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mips: mtmips: add CPU reset support for MT7628

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Allow the system to reset the CPU without calling the reset
controller. This patch also removed the default SYSRESET controller
for MT7628, as it is now optional.

Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
This commit is contained in:
Shiji Yang 2025-07-27 13:55:20 +08:00 committed by Tom Rini
parent 00618f7212
commit 80a3572f9b
3 changed files with 9 additions and 3 deletions
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3
arch/mips/mach-mtmips/Kconfig
View File

@ -104,8 +104,6 @@ config SOC_MT7628
select PINCTRL_MT7628
select PINCONF
select MTK_SERIAL
select SYSRESET
select SYSRESET_RESETCTL
select SPL_SEPARATE_BSS if SPL
select SPL_INIT_STACK_WITHOUT_MALLOC_F if SPL
select SPL_LOADER_SUPPORT if SPL
@ -113,7 +111,6 @@ config SOC_MT7628
select SPL_SIMPLE_BUS if SPL_DM
select SPL_DM_SERIAL if SPL_DM
select SPL_CLK if SPL_DM && SPL_SERIAL
select SPL_SYSRESET if SPL_DM
select SPL_OF_LIBFDT if SPL_OF_CONTROL
help
This supports MediaTek MT7628/MT7688.

8
arch/mips/mach-mtmips/mt7628/init.c
View File

@ -110,3 +110,11 @@ ulong notrace get_tbclk(void)
{
return gd->arch.timer_freq;
}
void _machine_restart(void)
{
void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
while (1)
writel(SYS_RST, sysc + SYSCTL_RSTCTL_REG);
}

1
arch/mips/mach-mtmips/mt7628/mt7628.h
View File

@ -49,6 +49,7 @@
#define SYSCTL_RSTCTL_REG 0x34
#define MC_RST 0x400
#define SYS_RST 0x01
#define SYSCTL_AGPIO_CFG_REG 0x3c
#define EPHY_GPIO_AIO_EN_S 17