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video: stm32: ltdc: add .of_to_plat callback
Drivers should extract device-tree data before probing via the .of_to_plat hook. Implement it for stm32_ltdc driver. No functional change. Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
This commit is contained in:
Raphael Gallais-Pou
Patrice Chotard
parent
a6e550b57a
commit
7f637df3db
@ -23,8 +23,17 @@
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#include <linux/printk.h>
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#include <linux/sizes.h>
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struct stm32_ltdc_priv {
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struct stm32_ltdc_plat {
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void __iomem *regs;
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struct udevice *bridge;
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struct udevice *panel;
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struct reset_ctl rst;
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struct clk pclk;
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struct clk bclk;
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};
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struct stm32_ltdc_priv {
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struct display_timing timings;
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enum video_log2_bpp l2bpp;
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u32 bg_col_argb;
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const u32 *layer_regs;
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@ -365,18 +374,20 @@ static bool has_alpha(u32 fmt)
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}
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}
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static void stm32_ltdc_enable(struct stm32_ltdc_priv *priv)
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static void stm32_ltdc_enable(void __iomem *regs)
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{
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/* Reload configuration immediately & enable LTDC */
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setbits_le32(priv->regs + LTDC_SRCR, SRCR_IMR);
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setbits_le32(priv->regs + LTDC_GCR, GCR_LTDCEN);
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setbits_le32(regs + LTDC_SRCR, SRCR_IMR);
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setbits_le32(regs + LTDC_GCR, GCR_LTDCEN);
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}
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static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv,
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struct display_timing *timings)
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static void stm32_ltdc_set_mode(struct udevice *dev)
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{
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void __iomem *regs = priv->regs;
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struct stm32_ltdc_plat *plat = dev_get_plat(dev);
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struct stm32_ltdc_priv *priv = dev_get_priv(dev);
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struct display_timing *timings = &priv->timings;
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u32 hsync, vsync, acc_hbp, acc_vbp, acc_act_w, acc_act_h;
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void __iomem *regs = plat->regs;
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u32 total_w, total_h;
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u32 val;
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@ -423,12 +434,14 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv,
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GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
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/* Overall background color */
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writel(priv->bg_col_argb, priv->regs + LTDC_BCCR);
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writel(priv->bg_col_argb, regs + LTDC_BCCR);
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}
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static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr)
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static void stm32_ltdc_set_layer1(struct udevice *dev, ulong fb_addr)
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{
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void __iomem *regs = priv->regs;
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struct stm32_ltdc_plat *plat = dev_get_plat(dev);
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struct stm32_ltdc_priv *priv = dev_get_priv(dev);
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void __iomem *regs = plat->regs;
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u32 x0, x1, y0, y1;
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u32 pitch_in_bytes;
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u32 line_length;
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@ -494,7 +507,7 @@ static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr)
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writel(fb_addr, regs + LTDC_L1CFBAR);
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/* Enable layer 1 */
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setbits_le32(priv->regs + LTDC_L1CR, LXCR_LEN);
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setbits_le32(regs + LTDC_L1CR, LXCR_LEN);
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}
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static int stm32_ltdc_get_remote_device(struct udevice *dev, ofnode ep_node,
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@ -619,53 +632,99 @@ static inline int stm32_ltdc_alloc_fb(struct udevice *dev)
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}
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#endif
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static int stm32_ltdc_probe(struct udevice *dev)
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static int stm32_ltdc_of_to_plat(struct udevice *dev)
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{
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struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
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struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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struct stm32_ltdc_plat *plat = dev_get_plat(dev);
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struct stm32_ltdc_priv *priv = dev_get_priv(dev);
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struct udevice *bridge = NULL;
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struct udevice *panel = NULL;
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struct display_timing timings;
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struct clk pclk, bclk;
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struct reset_ctl rst;
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ofnode node, port;
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ulong rate;
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int ret;
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priv->regs = dev_read_addr_ptr(dev);
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if (!priv->regs) {
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plat->regs = dev_read_addr_ptr(dev);
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if (!plat->regs) {
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dev_err(dev, "ltdc dt register address error\n");
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return -EINVAL;
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}
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ret = clk_get_by_name(dev, "bus", &bclk);
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if (ret) {
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if (ret != -ENODATA) {
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dev_err(dev, "bus clock get error %d\n", ret);
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return ret;
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}
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} else {
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ret = clk_enable(&bclk);
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if (ret) {
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dev_err(dev, "bus clock enable error %d\n", ret);
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return ret;
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}
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ret = clk_get_by_name(dev, "bus", &plat->bclk);
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if (ret && ret != -ENODATA) {
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dev_err(dev, "bus clock get error %d\n", ret);
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return ret;
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}
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ret = clk_get_by_name(dev, "lcd", &pclk);
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ret = clk_get_by_name(dev, "lcd", &plat->pclk);
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if (ret) {
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dev_err(dev, "peripheral clock get error %d\n", ret);
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return ret;
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}
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ret = clk_enable(&pclk);
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/*
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* Try all the ports until one working.
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*
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* This is done in two times. First is checks for the
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* UCLASS_VIDEO_BRIDGE available, and then for this bridge
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* it scans for a UCLASS_PANEL.
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*/
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port = dev_read_subnode(dev, "port");
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if (!ofnode_valid(port)) {
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dev_err(dev, "%s(%s): 'port' subnode not found\n",
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__func__, dev_read_name(dev));
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return -EINVAL;
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}
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for (node = ofnode_first_subnode(port);
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ofnode_valid(node);
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node = dev_read_next_subnode(node)) {
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ret = stm32_ltdc_display_init(dev, &node, &plat->panel, &plat->bridge);
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if (ret)
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dev_dbg(dev, "Device failed ret=%d\n", ret);
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else
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break;
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}
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/* Sanity check */
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if (ret)
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return ret;
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ret = panel_get_display_timing(plat->panel, &priv->timings);
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if (ret) {
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ret = ofnode_decode_display_timing(dev_ofnode(plat->panel),
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0, &priv->timings);
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if (ret) {
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dev_err(dev, "decode display timing error %d\n", ret);
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return ret;
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}
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}
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ret = reset_get_by_index(dev, 0, &plat->rst);
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if (ret)
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dev_err(dev, "missing ltdc hardware reset\n");
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return ret;
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}
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static int stm32_ltdc_probe(struct udevice *dev)
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{
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struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
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struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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struct stm32_ltdc_plat *plat = dev_get_plat(dev);
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struct stm32_ltdc_priv *priv = dev_get_priv(dev);
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struct display_timing *timings = &priv->timings;
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ulong rate;
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int ret;
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ret = clk_enable(&plat->bclk);
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if (ret) {
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dev_err(dev, "bus clock enable error %d\n", ret);
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return ret;
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}
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ret = clk_enable(&plat->pclk);
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if (ret) {
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dev_err(dev, "peripheral clock enable error %d\n", ret);
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return ret;
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}
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priv->hw_version = readl(priv->regs + LTDC_IDR);
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priv->hw_version = readl(plat->regs + LTDC_IDR);
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dev_dbg(dev, "%s: LTDC hardware 0x%x\n", __func__, priv->hw_version);
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switch (priv->hw_version) {
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@ -687,67 +746,22 @@ static int stm32_ltdc_probe(struct udevice *dev)
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return -ENODEV;
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}
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/*
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* Try all the ports until one working.
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*
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* This is done in two times. First is checks for the
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* UCLASS_VIDEO_BRIDGE available, and then for this bridge
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* it scans for a UCLASS_PANEL.
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*/
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port = dev_read_subnode(dev, "port");
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if (!ofnode_valid(port)) {
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dev_err(dev, "%s(%s): 'port' subnode not found\n",
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__func__, dev_read_name(dev));
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return -EINVAL;
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}
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for (node = ofnode_first_subnode(port);
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ofnode_valid(node);
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node = dev_read_next_subnode(node)) {
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ret = stm32_ltdc_display_init(dev, &node, &panel, &bridge);
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if (ret)
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dev_dbg(dev, "Device failed ret=%d\n", ret);
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else
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break;
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}
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/* Sanity check */
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if (ret)
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return ret;
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ret = panel_get_display_timing(panel, &timings);
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if (ret) {
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ret = ofnode_decode_display_timing(dev_ofnode(panel),
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0, &timings);
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if (ret) {
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dev_err(dev, "decode display timing error %d\n", ret);
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return ret;
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}
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}
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rate = clk_set_rate(&pclk, timings.pixelclock.typ);
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rate = clk_set_rate(&plat->pclk, timings->pixelclock.typ);
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if (IS_ERR_VALUE(rate))
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dev_warn(dev, "fail to set pixel clock %d hz, ret=%ld\n",
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timings.pixelclock.typ, rate);
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timings->pixelclock.typ, rate);
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dev_dbg(dev, "Set pixel clock req %d hz get %ld hz\n",
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timings.pixelclock.typ, rate);
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ret = reset_get_by_index(dev, 0, &rst);
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if (ret) {
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dev_err(dev, "missing ltdc hardware reset\n");
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return ret;
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}
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timings->pixelclock.typ, rate);
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/* Reset */
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reset_deassert(&rst);
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reset_deassert(&plat->rst);
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if (IS_ENABLED(CONFIG_VIDEO_BRIDGE)) {
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if (bridge) {
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ret = video_bridge_attach(bridge);
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if (plat->bridge) {
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ret = video_bridge_attach(plat->bridge);
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if (ret) {
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dev_err(bridge, "fail to attach bridge\n");
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dev_err(plat->bridge, "fail to attach bridge\n");
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return ret;
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}
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}
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@ -758,8 +772,8 @@ static int stm32_ltdc_probe(struct udevice *dev)
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priv->bg_col_argb = 0xFFFFFFFF; /* white no transparency */
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priv->crop_x = 0;
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priv->crop_y = 0;
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priv->crop_w = timings.hactive.typ;
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priv->crop_h = timings.vactive.typ;
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priv->crop_w = timings->hactive.typ;
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priv->crop_h = timings->vactive.typ;
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priv->alpha = 0xFF;
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ret = stm32_ltdc_alloc_fb(dev);
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@ -767,30 +781,30 @@ static int stm32_ltdc_probe(struct udevice *dev)
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return ret;
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dev_dbg(dev, "%dx%d %dbpp frame buffer at 0x%lx\n",
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timings.hactive.typ, timings.vactive.typ,
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timings->hactive.typ, timings->vactive.typ,
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VNBITS(priv->l2bpp), uc_plat->base);
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dev_dbg(dev, "crop %d,%d %dx%d bg 0x%08x alpha %d\n",
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priv->crop_x, priv->crop_y, priv->crop_w, priv->crop_h,
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priv->bg_col_argb, priv->alpha);
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/* Configure & start LTDC */
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stm32_ltdc_set_mode(priv, &timings);
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stm32_ltdc_set_layer1(priv, uc_plat->base);
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stm32_ltdc_enable(priv);
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stm32_ltdc_set_mode(dev);
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stm32_ltdc_set_layer1(dev, uc_plat->base);
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stm32_ltdc_enable(plat->regs);
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uc_priv->xsize = timings.hactive.typ;
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uc_priv->ysize = timings.vactive.typ;
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uc_priv->xsize = timings->hactive.typ;
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uc_priv->ysize = timings->vactive.typ;
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uc_priv->bpix = priv->l2bpp;
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if (!bridge) {
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ret = panel_enable_backlight(panel);
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if (!plat->bridge) {
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ret = panel_enable_backlight(plat->panel);
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if (ret) {
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dev_err(dev, "panel %s enable backlight error %d\n",
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panel->name, ret);
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plat->panel->name, ret);
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return ret;
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}
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} else if (IS_ENABLED(CONFIG_VIDEO_BRIDGE)) {
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ret = video_bridge_set_backlight(bridge, 80);
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ret = video_bridge_set_backlight(plat->bridge, 80);
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if (ret) {
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dev_err(dev, "fail to set backlight\n");
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return ret;
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@ -828,7 +842,9 @@ U_BOOT_DRIVER(stm32_ltdc) = {
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.name = "stm32_display",
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.id = UCLASS_VIDEO,
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.of_match = stm32_ltdc_ids,
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.of_to_plat = stm32_ltdc_of_to_plat,
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.probe = stm32_ltdc_probe,
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.bind = stm32_ltdc_bind,
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.plat_auto = sizeof(struct stm32_ltdc_plat),
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.priv_auto = sizeof(struct stm32_ltdc_priv),
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};
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