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arm: socfpga: fix comment about SPL memory layout

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The comment about SPL memory layout for socfpga gen5 is outdated: the
initial malloc memory is now at the end of the SRAM, gd is below it
(see board_init_f_alloc_reserve).

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Simon Goldschmidt 2019-04-09 21:02:03 +02:00 committed by Marek Vasut
parent ac1ec53e26
commit 798baf7ca3
1 changed files with 3 additions and 3 deletions
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6
include/configs/socfpga_common.h
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@ -236,9 +236,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
* *
* 0xFFFF_0000 ...... Start of SRAM * 0xFFFF_0000 ...... Start of SRAM
* 0xFFFF_xxxx ...... Top of stack (grows down) * 0xFFFF_xxxx ...... Top of stack (grows down)
* 0xFFFF_yyyy ...... Malloc area * 0xFFFF_yyyy ...... Global Data
* 0xFFFF_zzzz ...... Global Data * 0xFFFF_zzzz ...... Malloc area
* 0xFFFF_FF00 ...... End of SRAM * 0xFFFF_FFFF ...... End of SRAM
* *
* SRAM Memory layout for Arria 10: * SRAM Memory layout for Arria 10:
* 0xFFE0_0000 ...... Start of SRAM (bottom) * 0xFFE0_0000 ...... Start of SRAM (bottom)