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STM32 update:

Browse Source 
_ Add STM32MP21 support (board, machine, cmd_stm32key, cmd_stboard, rifsc)
 _ pinctrl: stm32 : various update
 _ stm32prog: clean stm32prog_data struct
 _ stm32mp2: Fix array bound check in setup_boot_mode()
 _ stm32mp2: Update dynamically DDR size in MMU table
 _ rifsc: various fixes
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Merge tag 'u-boot-stm32-20260224' of https://source.denx.de/u-boot/custodians/u-boot-stm

STM32 update:
_ Add STM32MP21 support (board, machine, cmd_stm32key, cmd_stboard, rifsc)
_ pinctrl: stm32 : various update
_ stm32prog: clean stm32prog_data struct
_ stm32mp2: Fix array bound check in setup_boot_mode()
_ stm32mp2: Update dynamically DDR size in MMU table
_ rifsc: various fixes
This commit is contained in:
Tom Rini 2026-02-25 08:48:54 -06:00
commit 78ea226ddb
38 changed files with 2447 additions and 194 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
arch/arm/dts/stm32mp215f-dk-u-boot.dtsi Normal file
View File

@ -0,0 +1,19 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
/*
* Copyright (C) STMicroelectronics 2026 - All Rights Reserved
*/
/ {
config {
u-boot,boot-led = "led-blue";
u-boot,mmc-env-partition = "u-boot-env";
};
};
&syscfg {
bootph-all;
};
&usart2 {
bootph-all;
};

27
arch/arm/mach-stm32mp/Kconfig
View File

@ -84,6 +84,32 @@ config STM32MP15X
STMicroelectronics MPU with core ARMv7
dual core A7 for STM32MP157/3, monocore for STM32MP151
config STM32MP21X
bool "Support STMicroelectronics STM32MP21x Soc"
select ARM64
select CLK_STM32MP21
select OF_BOARD
select PINCTRL_STM32
select STM32_RCC
select STM32_RESET
select STM32_SERIAL
select STM32MP_TAMP_NVMEM
select SYS_ARCH_TIMER
select TFABOOT
imply CLK_SCMI
imply CMD_NVEDIT_INFO
imply DM_REGULATOR
imply DM_REGULATOR_SCMI
imply OF_UPSTREAM
imply OPTEE
imply RESET_SCMI
imply SYSRESET_PSCI
imply TEE
imply VERSION_VARIABLE
help
Support of STMicroelectronics SOC STM32MP21X family
STMicroelectronics MPU with 1 A35 core and 1 M33 core
config STM32MP23X
bool "Support STMicroelectronics STM32MP23x Soc"
select ARM64
@ -195,6 +221,7 @@ config MFD_STM32_TIMERS
source "arch/arm/mach-stm32mp/Kconfig.13x"
source "arch/arm/mach-stm32mp/Kconfig.15x"
source "arch/arm/mach-stm32mp/Kconfig.21x"
source "arch/arm/mach-stm32mp/Kconfig.23x"
source "arch/arm/mach-stm32mp/Kconfig.25x"
source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"

37
arch/arm/mach-stm32mp/Kconfig.21x Normal file
View File

@ -0,0 +1,37 @@
if STM32MP21X
choice
prompt "STM32MP21X board select"
optional
config TARGET_ST_STM32MP21X
bool "STMicroelectronics STM32MP21X boards"
imply BOOTSTAGE
imply CMD_BOOTSTAGE
help
target the STMicroelectronics board with SOC STM32MP21X
managed by board/st/stm32mp2
The difference between board are managed with devicetree
endchoice
config TEXT_BASE
default 0x84000000
config PRE_CON_BUF_ADDR
default 0x84800000
config PRE_CON_BUF_SZ
default 4096
if DEBUG_UART
# debug on USART2 by default
config DEBUG_UART_BASE
default 0x400e0000
endif
source "board/st/stm32mp2/Kconfig"
endif

3
arch/arm/mach-stm32mp/Makefile
View File

@ -8,8 +8,9 @@ obj-y += syscon.o
obj-y += bsec.o
obj-y += soc.o
obj-$(CONFIG_STM32MP15X) += stm32mp1/
obj-$(CONFIG_STM32MP13X) += stm32mp1/
obj-$(CONFIG_STM32MP15X) += stm32mp1/
obj-$(CONFIG_STM32MP21X) += stm32mp2/
obj-$(CONFIG_STM32MP23X) += stm32mp2/
obj-$(CONFIG_STM32MP25X) += stm32mp2/

225
arch/arm/mach-stm32mp/cmd_stm32key.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
* Copyright (C) 2019-2024, STMicroelectronics - All Rights Reserved
*/
#include <command.h>
@ -16,21 +16,21 @@
* Closed device: OTP0
* STM32MP15x: bit 6 of OTP0
* STM32MP13x: 0b111111 = 0x3F for OTP_SECURED closed device
* STM32MP25x: bit 0 of OTP18
* STM32MP2xx: bit 0 of OTP18
*/
#define STM32MP1_OTP_CLOSE_ID 0
#define STM32_OTP_STM32MP13X_CLOSE_MASK GENMASK(5, 0)
#define STM32_OTP_STM32MP15X_CLOSE_MASK BIT(6)
#define STM32MP25_OTP_WORD8 8
#define STM32_OTP_STM32MP25X_BOOTROM_CLOSE_MASK GENMASK(7, 0)
#define STM32MP25_OTP_CLOSE_ID 18
#define STM32_OTP_STM32MP25X_CLOSE_MASK GENMASK(3, 0)
#define STM32_OTP_STM32MP25X_PROVISIONING_DONE_MASK GENMASK(7, 4)
#define STM32MP25_OTP_HWCONFIG 124
#define STM32_OTP_STM32MP25X_DISABLE_SCAN_MASK BIT(20)
#define STM32MP2X_OTP_WORD8 8
#define STM32_OTP_STM32MP2X_BOOTROM_CLOSE_MASK GENMASK(7, 0)
#define STM32MP2X_OTP_CLOSE_ID 18
#define STM32_OTP_STM32MP2X_CLOSE_MASK GENMASK(3, 0)
#define STM32_OTP_STM32MP2X_PROVISIONING_DONE_MASK GENMASK(7, 4)
#define STM32MP2X_OTP_HWCONFIG 124
#define STM32_OTP_STM32MP2X_DISABLE_SCAN_MASK BIT(20)
#define STM32MP25_OTP_BOOTROM_CONF8 17
#define STM32_OTP_STM32MP25X_OEM_KEY2_EN BIT(8)
#define STM32MP2X_OTP_BOOTROM_CONF8 17
#define STM32_OTP_STM32MP2X_OEM_KEY2_EN BIT(8)
/* PKH is the first element of the key list */
#define STM32KEY_PKH 0
@ -40,7 +40,8 @@ struct stm32key {
char *desc;
u16 start;
u8 size;
int (*post_process)(struct udevice *dev);
int (*post_process)(struct udevice *dev, const struct stm32key *key);
u32 (*key_format)(u32 value);
};
const struct stm32key stm32mp13_list[] = {
@ -67,9 +68,81 @@ const struct stm32key stm32mp15_list[] = {
}
};
static int post_process_oem_key2(struct udevice *dev);
static int post_process_oem_key2(struct udevice *dev, const struct stm32key *key);
static int post_process_edmk_128b(struct udevice *dev, const struct stm32key *key);
static u32 format1(u32 value);
static u32 format2(u32 value);
const struct stm32key stm32mp25_list[] = {
const struct stm32key stm32mp21_list[] = {
[STM32KEY_PKH] = {
.name = "OEM-KEY1",
.desc = "Hash of the 8 ECC Public Keys Hashes Table (ECDSA is the authentication algorithm) for FSBLA or M",
.start = 152,
.size = 8,
},
{
.name = "OEM-KEY2",
.desc = "Hash of the 8 ECC Public Keys Hashes Table (ECDSA is the authentication algorithm) for FSBLM",
.start = 160,
.size = 8,
.post_process = post_process_oem_key2,
},
{
.name = "RPROC-FW-PKH",
.desc = "Hash of the Public Key for remote processor firmware",
.start = 180,
.size = 8,
.key_format = format2,
},
{
.name = "ADAC-ROTPKH",
.desc = "Authenticated Debug Access Control Root Of Trust Public Key Hash",
.start = 238,
.size = 8,
.key_format = format2,
},
{
.name = "FIP-EDMK",
.desc = "Encryption/Decryption Master Key for FIP",
.start = 260,
.size = 8,
},
{
.name = "RPROC-FW-ENC-KEY",
.desc = "Encryption/Decryption Key for remote processor firmware",
.start = 332,
.size = 8,
.key_format = format2,
},
{
.name = "EDMK1-128b",
.desc = "Encryption/Decryption Master 128b Key for FSBLA or M",
.start = 356,
.size = 4,
.post_process = post_process_edmk_128b,
},
{
.name = "EDMK1-256b",
.desc = "Encryption/Decryption Master 256b Key for FSBLA or M",
.start = 356,
.size = 8,
},
{
.name = "EDMK2-128b",
.desc = "Encryption/Decryption Master 128b Key for FSBLM",
.start = 348,
.size = 4,
.post_process = post_process_edmk_128b,
},
{
.name = "EDMK2-256b",
.desc = "Encryption/Decryption Master 256b Key for FSBLM",
.start = 348,
.size = 8,
},
};
const struct stm32key stm32mp2x_list[] = {
[STM32KEY_PKH] = {
.name = "OEM-KEY1",
.desc = "Hash of the 8 ECC Public Keys Hashes Table (ECDSA is the authentication algorithm) for FSBLA or M",
@ -83,12 +156,26 @@ const struct stm32key stm32mp25_list[] = {
.size = 8,
.post_process = post_process_oem_key2,
},
{
.name = "RPROC-FW-PKH",
.desc = "Hash of the Public Key for remote processor firmware",
.start = 176,
.size = 8,
.key_format = format2,
},
{
.name = "FIP-EDMK",
.desc = "Encryption/Decryption Master Key for FIP",
.start = 260,
.size = 8,
},
{
.name = "RPROC-FW-ENC-KEY",
.desc = "Encryption/Decryption Key for remote processor firmware",
.start = 336,
.size = 8,
.key_format = format2,
},
{
.name = "EDMK1",
.desc = "Encryption/Decryption Master Key for FSBLA or M",
@ -138,23 +225,23 @@ const struct otp_close stm32mp15_close_state_otp[] = {
}
};
const struct otp_close stm32mp25_close_state_otp[] = {
const struct otp_close stm32mp2x_close_state_otp[] = {
{
.word = STM32MP25_OTP_WORD8,
.mask_wr = STM32_OTP_STM32MP25X_BOOTROM_CLOSE_MASK,
.word = STM32MP2X_OTP_WORD8,
.mask_wr = STM32_OTP_STM32MP2X_BOOTROM_CLOSE_MASK,
.mask_rd = 0,
.close_status_ops = NULL
},
{
.word = STM32MP25_OTP_CLOSE_ID,
.mask_wr = STM32_OTP_STM32MP25X_CLOSE_MASK |
STM32_OTP_STM32MP25X_PROVISIONING_DONE_MASK,
.mask_rd = STM32_OTP_STM32MP25X_CLOSE_MASK,
.word = STM32MP2X_OTP_CLOSE_ID,
.mask_wr = STM32_OTP_STM32MP2X_CLOSE_MASK |
STM32_OTP_STM32MP2X_PROVISIONING_DONE_MASK,
.mask_rd = STM32_OTP_STM32MP2X_CLOSE_MASK,
.close_status_ops = compare_any_bits
},
{
.word = STM32MP25_OTP_HWCONFIG,
.mask_wr = STM32_OTP_STM32MP25X_DISABLE_SCAN_MASK,
.word = STM32MP2X_OTP_HWCONFIG,
.mask_wr = STM32_OTP_STM32MP2X_DISABLE_SCAN_MASK,
.mask_rd = 0,
.close_status_ops = NULL
},
@ -171,8 +258,11 @@ static u8 get_key_nb(void)
if (IS_ENABLED(CONFIG_STM32MP15X))
return ARRAY_SIZE(stm32mp15_list);
if (IS_ENABLED(CONFIG_STM32MP21X))
return ARRAY_SIZE(stm32mp21_list);
if (IS_ENABLED(CONFIG_STM32MP23X) || IS_ENABLED(CONFIG_STM32MP25X))
return ARRAY_SIZE(stm32mp25_list);
return ARRAY_SIZE(stm32mp2x_list);
}
static const struct stm32key *get_key(u8 index)
@ -183,8 +273,11 @@ static const struct stm32key *get_key(u8 index)
if (IS_ENABLED(CONFIG_STM32MP15X))
return &stm32mp15_list[index];
if (IS_ENABLED(CONFIG_STM32MP21X))
return &stm32mp21_list[index];
if (IS_ENABLED(CONFIG_STM32MP23X) || IS_ENABLED(CONFIG_STM32MP25X))
return &stm32mp25_list[index];
return &stm32mp2x_list[index];
}
static u8 get_otp_close_state_nb(void)
@ -195,8 +288,9 @@ static u8 get_otp_close_state_nb(void)
if (IS_ENABLED(CONFIG_STM32MP15X))
return ARRAY_SIZE(stm32mp15_close_state_otp);
if (IS_ENABLED(CONFIG_STM32MP23X) || IS_ENABLED(CONFIG_STM32MP25X))
return ARRAY_SIZE(stm32mp25_close_state_otp);
if (IS_ENABLED(CONFIG_STM32MP21X) || IS_ENABLED(CONFIG_STM32MP23X) ||
IS_ENABLED(CONFIG_STM32MP25X))
return ARRAY_SIZE(stm32mp2x_close_state_otp);
}
static const struct otp_close *get_otp_close_state(u8 index)
@ -207,8 +301,27 @@ static const struct otp_close *get_otp_close_state(u8 index)
if (IS_ENABLED(CONFIG_STM32MP15X))
return &stm32mp15_close_state_otp[index];
if (IS_ENABLED(CONFIG_STM32MP23X) || IS_ENABLED(CONFIG_STM32MP25X))
return &stm32mp25_close_state_otp[index];
if (IS_ENABLED(CONFIG_STM32MP21X) || IS_ENABLED(CONFIG_STM32MP23X) ||
IS_ENABLED(CONFIG_STM32MP25X))
return &stm32mp2x_close_state_otp[index];
}
/*
* Define format wrappers based on reference manual formats
* ex for key from NIST vector AES_ECB_256b_test0:
* key (bytes) : f9 e8 38 9f ... ef 94 4b e0
* format 1 (le32) : 0xf9e8389f ... 0xef944be0
* format 2 (le32) : 0x9f38e8f9 ... 0xe04b94ef
*/
static u32 format1(u32 value)
{
return __be32_to_cpu(value);
}
static u32 format2(u32 value)
{
return __le32_to_cpu(value);
}
static int get_misc_dev(struct udevice **dev)
@ -225,15 +338,21 @@ static int get_misc_dev(struct udevice **dev)
static void read_key_value(const struct stm32key *key, unsigned long addr)
{
int i;
u32 (*format)(u32) = format1;
/* Use key_format function pointer if defined */
if (key->key_format)
format = key->key_format;
for (i = 0; i < key->size; i++) {
printf("%s OTP %i: [%08x] %08x\n", key->name, key->start + i,
(u32)addr, __be32_to_cpu(*(u32 *)addr));
(u32)addr, format(*(u32 *)addr));
addr += 4;
}
}
static int read_key_otp(struct udevice *dev, const struct stm32key *key, bool print, bool *locked)
static int read_key_otp(struct udevice *dev, const struct stm32key *key,
bool print, bool *locked)
{
int i, word, ret;
int nb_invalid = 0, nb_zero = 0, nb_lock = 0, nb_lock_err = 0;
@ -347,19 +466,19 @@ static int write_close_status(struct udevice *dev)
return 0;
}
static int post_process_oem_key2(struct udevice *dev)
static int post_process_oem_key2(struct udevice *dev, const struct stm32key *key)
{
int ret;
u32 val;
ret = misc_read(dev, STM32_BSEC_OTP(STM32MP25_OTP_BOOTROM_CONF8), &val, 4);
ret = misc_read(dev, STM32_BSEC_OTP(STM32MP2X_OTP_BOOTROM_CONF8), &val, 4);
if (ret != 4) {
log_err("Error %d failed to read STM32MP25_OTP_BOOTROM_CONF8\n", ret);
log_err("Error %d failed to read STM32MP2X_OTP_BOOTROM_CONF8\n", ret);
return -EIO;
}
val |= STM32_OTP_STM32MP25X_OEM_KEY2_EN;
ret = misc_write(dev, STM32_BSEC_OTP(STM32MP25_OTP_BOOTROM_CONF8), &val, 4);
val |= STM32_OTP_STM32MP2X_OEM_KEY2_EN;
ret = misc_write(dev, STM32_BSEC_OTP(STM32MP2X_OTP_BOOTROM_CONF8), &val, 4);
if (ret != 4) {
log_err("Error %d failed to write OEM_KEY2_ENABLE\n", ret);
return -EIO;
@ -368,14 +487,44 @@ static int post_process_oem_key2(struct udevice *dev)
return 0;
}
static int post_process_edmk_128b(struct udevice *dev, const struct stm32key *key)
{
int ret, word, start_otp;
u32 val;
start_otp = key->start + key->size;
/* On MP21, when using a 128bit key, program 0xffffffff and lock the unused OTPs. */
for (word = start_otp; word < (start_otp + 4); word++) {
val = GENMASK(31, 0);
ret = misc_write(dev, STM32_BSEC_OTP(word), &val, 4);
if (ret != 4)
log_warning("Fuse %s OTP padding %i failed, continue\n", key->name, word);
val = BSEC_LOCK_PERM;
ret = misc_write(dev, STM32_BSEC_LOCK(word), &val, 4);
if (ret != 4) {
log_err("Failed to lock unused OTP : %d\n", word);
return ret;
}
}
return 0;
}
static int fuse_key_value(struct udevice *dev, const struct stm32key *key, unsigned long addr,
bool print)
{
u32 word, val;
int i, ret;
u32 (*format)(u32) = format1;
/* Use key_format function pointer if defined */
if (key->key_format)
format = key->key_format;
for (i = 0, word = key->start; i < key->size; i++, word++, addr += 4) {
val = __be32_to_cpu(*(u32 *)addr);
val = format(*(u32 *)addr);
if (print)
printf("Fuse %s OTP %i : %08x\n", key->name, word, val);
@ -546,7 +695,7 @@ static int do_stm32key_fuse(struct cmd_tbl *cmdtp, int flag, int argc, char *con
return CMD_RET_FAILURE;
if (key->post_process) {
if (key->post_process(dev)) {
if (key->post_process(dev, key)) {
printf("Error: %s for post process\n", key->name);
return CMD_RET_FAILURE;
}

8
arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
View File

@ -187,11 +187,3 @@ U_BOOT_CMD(stm32prog, 5, 0, do_stm32prog,
" <addr> = address of flashlayout\n"
" <size> = size of flashlayout (optional for image with STM32 header)\n"
);
bool stm32prog_get_fsbl_nor(void)
{
if (stm32prog_data)
return stm32prog_data->fsbl_nor_detected;
return false;
}

10
arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
View File

@ -1010,7 +1010,6 @@ static int treat_partition_list(struct stm32prog_data *data)
INIT_LIST_HEAD(&data->dev[j].part_list);
}
data->fsbl_nor_detected = false;
for (i = 0; i < data->part_nb; i++) {
part = &data->part_array[i];
part->alt_id = -1;
@ -1055,15 +1054,6 @@ static int treat_partition_list(struct stm32prog_data *data)
stm32prog_err("Layout: too many device");
return -EINVAL;
}
switch (part->target) {
case STM32PROG_NOR:
if (!data->fsbl_nor_detected &&
!strncmp(part->name, "fsbl", 4))
data->fsbl_nor_detected = true;
/* fallthrough */
default:
break;
}
part->dev = &data->dev[j];
if (!IS_SELECT(part))
part->dev->full_update = false;

1
arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
View File

@ -167,7 +167,6 @@ struct stm32prog_data {
struct stm32prog_dev_t dev[STM32PROG_MAX_DEV]; /* array of device */
int part_nb; /* nb of partition */
struct stm32prog_part_t *part_array; /* array of partition */
bool fsbl_nor_detected;
/* command internal information */
unsigned int phase;

12
arch/arm/mach-stm32mp/include/mach/stm32.h
View File

@ -165,16 +165,20 @@ enum forced_boot_mode {
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_STM32MP15X || CONFIG_STM32MP13X */
#if defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X)
#if defined(CONFIG_STM32MP21X) || defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X)
#define STM32_USART2_BASE 0x400E0000
#define STM32_USART3_BASE 0x400F0000
#define STM32_UART4_BASE 0x40100000
#define STM32_UART5_BASE 0x40110000
#define STM32_USART6_BASE 0x40220000
#ifdef CONFIG_STM32MP25X
#define STM32_UART9_BASE 0x402C0000
#endif
#define STM32_USART1_BASE 0x40330000
#define STM32_UART7_BASE 0x40370000
#ifdef CONFIG_STM32MP25X
#define STM32_UART8_BASE 0x40380000
#endif
#define STM32_RCC_BASE 0x44200000
#define STM32_TAMP_BASE 0x46010000
#define STM32_SDMMC1_BASE 0x48220000
@ -194,7 +198,7 @@ enum forced_boot_mode {
#define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0)
#define TAMP_FWU_BOOT_IDX_OFFSET 0
#endif /* defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X) */
#endif /* defined(CONFIG_STM32MP21X) || defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X) */
/* offset used for BSEC driver: misc_read and misc_write */
#define STM32_BSEC_SHADOW_OFFSET 0x0
@ -218,14 +222,14 @@ enum forced_boot_mode {
#define BSEC_OTP_MAC 57
#define BSEC_OTP_BOARD 60
#endif
#if defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X)
#if defined(CONFIG_STM32MP21X) || defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X)
#define BSEC_OTP_SERIAL 5
#define BSEC_OTP_RPN 9
#define BSEC_OTP_REVID 102
#define BSEC_OTP_PKG 122
#define BSEC_OTP_BOARD 246
#define BSEC_OTP_MAC 247
#endif /* defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X) */
#endif /* defined(CONFIG_STM32MP21X) || defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X) */
#ifndef __ASSEMBLY__
#include <asm/types.h>

2
arch/arm/mach-stm32mp/include/mach/stm32prog.h
View File

@ -10,5 +10,3 @@ int stm32prog_write_medium_virt(struct dfu_entity *dfu, u64 offset,
int stm32prog_read_medium_virt(struct dfu_entity *dfu, u64 offset,
void *buf, long *len);
int stm32prog_get_medium_size_virt(struct dfu_entity *dfu, u64 *size);
bool stm32prog_get_fsbl_nor(void);

22
arch/arm/mach-stm32mp/include/mach/sys_proto.h
View File

@ -30,6 +30,20 @@
#define CPU_STM32MP131Fxx 0x05010EC8
#define CPU_STM32MP131Dxx 0x05010EC9
/* ID for STM32MP21x = Device Part Number (RPN) (bit31:0) */
#define CPU_STM32MP211Axx 0x40073E7D
#define CPU_STM32MP211Cxx 0x0007307D
#define CPU_STM32MP211Dxx 0xC0073E7D
#define CPU_STM32MP211Fxx 0x8007307D
#define CPU_STM32MP213Axx 0x40073E1D
#define CPU_STM32MP213Cxx 0x0007301D
#define CPU_STM32MP213Dxx 0xC0073E1D
#define CPU_STM32MP213Fxx 0x8007301D
#define CPU_STM32MP215Axx 0x40033E0D
#define CPU_STM32MP215Cxx 0x0003300D
#define CPU_STM32MP215Dxx 0xC0033E0D
#define CPU_STM32MP215Fxx 0x8003300D
/* ID for STM32MP23x = Device Part Number (RPN) (bit31:0) */
#define CPU_STM32MP235Cxx 0x00082182
#define CPU_STM32MP233Cxx 0x000B318E
@ -67,6 +81,7 @@ u32 get_cpu_type(void);
#define CPU_DEV_STM32MP15 0x500
#define CPU_DEV_STM32MP13 0x501
#define CPU_DEV_STM32MP21 0x503
#define CPU_DEV_STM32MP23 0x505
#define CPU_DEV_STM32MP25 0x505
@ -102,6 +117,13 @@ u32 get_cpu_package(void);
#define STM32MP15_PKG_AD_TFBGA257 1
#define STM32MP15_PKG_UNKNOWN 0
/* package used for STM32MP21x */
#define STM32MP21_PKG_CUSTOM 0
#define STM32MP21_PKG_AL_VFBGA361 1
#define STM32MP21_PKG_AN_VFBGA273 3
#define STM32MP21_PKG_AO_VFBGA225 4
#define STM32MP21_PKG_AM_TFBGA289 5
/* package used for STM32MP23x */
#define STM32MP23_PKG_CUSTOM 0
#define STM32MP23_PKG_AL_VFBGA361 1

7
arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c
View File

@ -17,6 +17,7 @@
#include <dm/device.h>
#include <dm/uclass.h>
#include <linux/bitfield.h>
#include <linux/err.h>
#include <malloc.h>
/* RCC register */
@ -231,6 +232,12 @@ static u32 read_idc(void)
{
void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
if (IS_ERR(syscfg)) {
pr_err("Error, can't get SYSCON range (%ld)\n", PTR_ERR(syscfg));
return PTR_ERR(syscfg);
}
return readl(syscfg + SYSCFG_IDC_OFFSET);
}

2
arch/arm/mach-stm32mp/stm32mp2/Makefile
View File

@ -6,6 +6,8 @@
obj-y += cpu.o
obj-y += arm64-mmu.o
obj-y += rifsc.o
obj-y += stm32mp2x.o
obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
obj-$(CONFIG_STM32MP21X) += stm32mp21x.o
obj-$(CONFIG_STM32MP23X) += stm32mp23x.o
obj-$(CONFIG_STM32MP25X) += stm32mp25x.o

2
arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c
View File

@ -16,6 +16,7 @@
struct mm_region stm32mp2_mem_map[MP2_MEM_MAP_MAX] = {
{
#if defined(CONFIG_STM32MP25X)
/* PCIe */
.virt = 0x10000000UL,
.phys = 0x10000000UL,
@ -24,6 +25,7 @@ struct mm_region stm32mp2_mem_map[MP2_MEM_MAP_MAX] = {
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
#endif
/* LPSRAMs, VDERAM, RETRAM, SRAMs, SYSRAM: alias1 */
.virt = 0x20000000UL,
.phys = 0x20000000UL,

20
arch/arm/mach-stm32mp/stm32mp2/cpu.c
View File

@ -15,6 +15,7 @@
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <asm/arch/sys_proto.h>
#include <asm/armv8/mmu.h>
#include <asm/system.h>
#include <dm/device.h>
#include <dm/lists.h>
@ -70,8 +71,21 @@ int mach_cpu_init(void)
void enable_caches(void)
{
struct mm_region *mem = mem_map;
/* deactivate the data cache, early enabled in arch_cpu_init() */
dcache_disable();
/* Parse mem_map and find DDR entry */
while (mem->size) {
if (mem->phys == CONFIG_TEXT_BASE) {
/* update DDR entry with real DDR size */
mem->size = gd->ram_size;
break;
}
mem++;
}
/*
* Force the call of setup_all_pgtables() in mmu_setup() by clearing tlb_fillptr
* to update the TLB location udpated in board_f.c::reserve_mmu
@ -128,8 +142,10 @@ static void setup_boot_mode(void)
STM32_UART5_BASE,
STM32_USART6_BASE,
STM32_UART7_BASE,
#ifdef CONFIG_STM32MP25X
STM32_UART8_BASE,
STM32_UART9_BASE
#endif
};
const u32 sdmmc_addr[] = {
STM32_SDMMC1_BASE,
@ -148,7 +164,7 @@ static void setup_boot_mode(void)
__func__, boot_ctx, boot_mode, instance, forced_mode);
switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
case BOOT_SERIAL_UART:
if (instance > ARRAY_SIZE(serial_addr))
if (instance >= ARRAY_SIZE(serial_addr))
break;
/* serial : search associated node in devicetree */
sprintf(cmd, "serial@%x", serial_addr[instance]);
@ -178,7 +194,7 @@ static void setup_boot_mode(void)
break;
case BOOT_FLASH_SD:
case BOOT_FLASH_EMMC:
if (instance > ARRAY_SIZE(sdmmc_addr))
if (instance >= ARRAY_SIZE(sdmmc_addr))
break;
/* search associated sdmmc node in devicetree */
sprintf(cmd, "mmc@%x", sdmmc_addr[instance]);

37
arch/arm/mach-stm32mp/stm32mp2/rifsc.c
View File

@ -141,27 +141,16 @@ static int rifsc_check_access(void *base, u32 id)
cid_reg_value = readl(base + RIFSC_RISC_PER0_CIDCFGR(id));
sem_reg_value = readl(base + RIFSC_RISC_PER0_SEMCR(id));
/*
* First check conditions for semaphore mode, which doesn't take into
* account static CID.
*/
if (cid_reg_value & CIDCFGR_SEMEN)
goto skip_cid_check;
/*
* Skip cid check if CID filtering isn't enabled or filtering is enabled on CID0, which
* corresponds to whatever CID.
*/
if (!(cid_reg_value & CIDCFGR_CFEN) ||
FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) == RIF_CID0)
goto skip_cid_check;
/* Coherency check with the CID configuration */
if (FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) != RIF_CID1) {
log_debug("Invalid CID configuration for peripheral %d\n", id);
/* Check security configuration */
if (sec_reg_value & BIT(reg_offset)) {
log_debug("Invalid security configuration for peripheral %d\n", id);
return -EACCES;
}
/* Skip cid check if CID filtering isn't enabled */
if (!(cid_reg_value & CIDCFGR_CFEN))
goto skip_cid_check;
/* Check semaphore accesses */
if (cid_reg_value & CIDCFGR_SEMEN) {
if (!(FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) {
@ -173,15 +162,12 @@ static int rifsc_check_access(void *base, u32 id)
log_debug("Semaphore unavailable for peripheral %d\n", id);
return -EACCES;
}
}
skip_cid_check:
/* Check security configuration */
if (sec_reg_value & BIT(reg_offset)) {
log_debug("Invalid security configuration for peripheral %d\n", id);
} else if (FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) != RIF_CID1) {
log_debug("Invalid CID configuration for peripheral %d\n", id);
return -EACCES;
}
skip_cid_check:
return 0;
}
@ -208,7 +194,7 @@ int stm32_rifsc_grant_access_by_id(ofnode device_node, u32 id)
* If the peripheral is in semaphore mode, take the semaphore so that
* the CID1 has the ownership.
*/
if (cid_reg_value & CIDCFGR_SEMEN &&
if (cid_reg_value & CIDCFGR_CFEN && cid_reg_value & CIDCFGR_SEMEN &&
(FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) {
err = stm32_rifsc_acquire_semaphore(rifsc_base, id);
if (err) {
@ -367,6 +353,7 @@ static int stm32_rifsc_remove(struct udevice *bus)
}
static const struct udevice_id stm32_rifsc_ids[] = {
{ .compatible = "st,stm32mp21-rifsc" },
{ .compatible = "st,stm32mp25-rifsc" },
{},
};

148
arch/arm/mach-stm32mp/stm32mp2/stm32mp21x.c Normal file
View File

@ -0,0 +1,148 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
/*
* Copyright (C) 2026, STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY LOGC_ARCH
#include <log.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <asm/arch/sys_proto.h>
/* Package = bit 0:2 of OTP122 => STM32MP21_PKG defines
* - 000: Custom package
* - 001: VFBGA361 => AL = 10x10, 361 balls pith 0.5mm
* - 011: VFBGA273 => AN = 11x11, 273 balls pith 0.5mm
* - 100: VFBGA225 => AO = 8x8, 225 balls pith 0.5mm
* - 101: TFBGA289 => AM = 14x14, 289 balls pith 0.8mm
* - others: Reserved
*/
int get_eth_nb(void)
{
int nb_eth;
switch (get_cpu_type()) {
case CPU_STM32MP215Axx:
fallthrough;
case CPU_STM32MP215Cxx:
fallthrough;
case CPU_STM32MP215Dxx:
fallthrough;
case CPU_STM32MP215Fxx:
fallthrough;
case CPU_STM32MP213Axx:
fallthrough;
case CPU_STM32MP213Cxx:
fallthrough;
case CPU_STM32MP213Dxx:
fallthrough;
case CPU_STM32MP213Fxx:
nb_eth = 2; /* dual ETH */
break;
case CPU_STM32MP211Axx:
fallthrough;
case CPU_STM32MP211Cxx:
fallthrough;
case CPU_STM32MP211Dxx:
fallthrough;
case CPU_STM32MP211Fxx:
nb_eth = 1; /* single ETH */
break;
default:
nb_eth = 0;
break;
}
return nb_eth;
}
void get_soc_name(char name[SOC_NAME_SIZE])
{
char *cpu_s, *cpu_r, *package;
cpu_s = "????";
cpu_r = "?";
package = "??";
if (get_cpu_dev() == CPU_DEV_STM32MP21) {
switch (get_cpu_type()) {
case CPU_STM32MP215Fxx:
cpu_s = "215F";
break;
case CPU_STM32MP215Dxx:
cpu_s = "215D";
break;
case CPU_STM32MP215Cxx:
cpu_s = "215C";
break;
case CPU_STM32MP215Axx:
cpu_s = "215A";
break;
case CPU_STM32MP213Fxx:
cpu_s = "213F";
break;
case CPU_STM32MP213Dxx:
cpu_s = "213D";
break;
case CPU_STM32MP213Cxx:
cpu_s = "213C";
break;
case CPU_STM32MP213Axx:
cpu_s = "213A";
break;
case CPU_STM32MP211Fxx:
cpu_s = "211F";
break;
case CPU_STM32MP211Dxx:
cpu_s = "211D";
break;
case CPU_STM32MP211Cxx:
cpu_s = "211C";
break;
case CPU_STM32MP211Axx:
cpu_s = "211A";
break;
default:
cpu_s = "21??";
break;
}
/* REVISION */
switch (get_cpu_rev()) {
case OTP_REVID_1:
cpu_r = "A";
break;
case OTP_REVID_1_1:
cpu_r = "Z";
break;
case OTP_REVID_2:
cpu_r = "B";
break;
default:
break;
}
/* PACKAGE */
switch (get_cpu_package()) {
case STM32MP25_PKG_CUSTOM:
package = "XX";
break;
case STM32MP21_PKG_AL_VFBGA361:
package = "AL";
break;
case STM32MP21_PKG_AN_VFBGA273:
package = "AN";
break;
case STM32MP21_PKG_AO_VFBGA225:
package = "AO";
break;
case STM32MP21_PKG_AM_TFBGA289:
package = "AM";
break;
default:
break;
}
}
snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, package, cpu_r);
}

44
arch/arm/mach-stm32mp/stm32mp2/stm32mp23x.c
View File

@ -11,19 +11,6 @@
#include <asm/arch/stm32.h>
#include <asm/arch/sys_proto.h>
/* SYSCFG register */
#define SYSCFG_DEVICEID_OFFSET 0x6400
#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0)
#define SYSCFG_DEVICEID_DEV_ID_SHIFT 0
/* Revision ID = OTP102[5:0] 6 bits : 3 for Major / 3 for Minor*/
#define REVID_SHIFT 0
#define REVID_MASK GENMASK(5, 0)
/* Device Part Number (RPN) = OTP9 */
#define RPN_SHIFT 0
#define RPN_MASK GENMASK(31, 0)
/* Package = bit 0:2 of OTP122 => STM32MP23_PKG defines
* - 000: Custom package
* - 011: TFBGA361 => AL = 10x10, 361 balls pith 0.5mm
@ -31,37 +18,6 @@
* - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm
* - others: Reserved
*/
#define PKG_SHIFT 0
#define PKG_MASK GENMASK(2, 0)
static u32 read_deviceid(void)
{
void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
return readl(syscfg + SYSCFG_DEVICEID_OFFSET);
}
u32 get_cpu_dev(void)
{
return (read_deviceid() & SYSCFG_DEVICEID_DEV_ID_MASK) >> SYSCFG_DEVICEID_DEV_ID_SHIFT;
}
u32 get_cpu_rev(void)
{
return get_otp(BSEC_OTP_REVID, REVID_SHIFT, REVID_MASK);
}
/* Get Device Part Number (RPN) from OTP */
u32 get_cpu_type(void)
{
return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
}
/* Get Package options from OTP */
u32 get_cpu_package(void)
{
return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
}
int get_eth_nb(void)
{

46
arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c
View File

@ -6,24 +6,9 @@
#define LOG_CATEGORY LOGC_ARCH
#include <log.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <asm/arch/sys_proto.h>
/* SYSCFG register */
#define SYSCFG_DEVICEID_OFFSET 0x6400
#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0)
#define SYSCFG_DEVICEID_DEV_ID_SHIFT 0
/* Revision ID = OTP102[5:0] 6 bits : 3 for Major / 3 for Minor*/
#define REVID_SHIFT 0
#define REVID_MASK GENMASK(5, 0)
/* Device Part Number (RPN) = OTP9 */
#define RPN_SHIFT 0
#define RPN_MASK GENMASK(31, 0)
/* Package = bit 0:2 of OTP122 => STM32MP25_PKG defines
* - 000: Custom package
* - 001: VFBGA361 => AL = 10x10, 361 balls pith 0.5mm
@ -31,37 +16,6 @@
* - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm
* - others: Reserved
*/
#define PKG_SHIFT 0
#define PKG_MASK GENMASK(2, 0)
static u32 read_deviceid(void)
{
void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
return readl(syscfg + SYSCFG_DEVICEID_OFFSET);
}
u32 get_cpu_dev(void)
{
return (read_deviceid() & SYSCFG_DEVICEID_DEV_ID_MASK) >> SYSCFG_DEVICEID_DEV_ID_SHIFT;
}
u32 get_cpu_rev(void)
{
return get_otp(BSEC_OTP_REVID, REVID_SHIFT, REVID_MASK);
}
/* Get Device Part Number (RPN) from OTP */
u32 get_cpu_type(void)
{
return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
}
/* Get Package options from OTP */
u32 get_cpu_package(void)
{
return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
}
int get_eth_nb(void)
{

63
arch/arm/mach-stm32mp/stm32mp2/stm32mp2x.c Normal file
View File

@ -0,0 +1,63 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
/*
* Copyright (C) 2026, STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY LOGC_ARCH
#include <log.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <linux/err.h>
/* SYSCFG register */
#define SYSCFG_DEVICEID_OFFSET 0x6400
#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0)
#define SYSCFG_DEVICEID_DEV_ID_SHIFT 0
/* Revision ID = OTP102[5:0] 6 bits : 3 for Major / 3 for Minor*/
#define REVID_SHIFT 0
#define REVID_MASK GENMASK(5, 0)
/* Device Part Number (RPN) = OTP9 */
#define RPN_SHIFT 0
#define RPN_MASK GENMASK(31, 0)
#define PKG_SHIFT 0
#define PKG_MASK GENMASK(2, 0)
static u32 read_deviceid(void)
{
void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
if (IS_ERR(syscfg)) {
pr_err("Error, can't get SYSCON range (%ld)\n", PTR_ERR(syscfg));
return PTR_ERR(syscfg);
}
return readl(syscfg + SYSCFG_DEVICEID_OFFSET);
}
u32 get_cpu_dev(void)
{
return (read_deviceid() & SYSCFG_DEVICEID_DEV_ID_MASK) >> SYSCFG_DEVICEID_DEV_ID_SHIFT;
}
u32 get_cpu_rev(void)
{
return get_otp(BSEC_OTP_REVID, REVID_SHIFT, REVID_MASK);
}
/* Get Device Part Number (RPN) from OTP */
u32 get_cpu_type(void)
{
return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
}
/* Get Package options from OTP */
u32 get_cpu_package(void)
{
return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
}

1
arch/arm/mach-stm32mp/syscon.c
View File

@ -10,6 +10,7 @@
static const struct udevice_id stm32mp_syscon_ids[] = {
{ .compatible = "st,stm32mp157-syscfg", .data = STM32MP_SYSCON_SYSCFG },
{ .compatible = "st,stm32mp21-syscfg", .data = STM32MP_SYSCON_SYSCFG},
{ .compatible = "st,stm32mp23-syscfg", .data = STM32MP_SYSCON_SYSCFG},
{ .compatible = "st,stm32mp25-syscfg", .data = STM32MP_SYSCON_SYSCFG},
{ }

2
board/st/common/Kconfig
View File

@ -1,7 +1,7 @@
config CMD_STBOARD
bool "stboard - command for OTP board information"
depends on ARCH_STM32MP
default y if TARGET_ST_STM32MP13X || TARGET_ST_STM32MP15X || TARGET_ST_STM32MP23X || TARGET_ST_STM32MP25X
default y if TARGET_ST_STM32MP13X || TARGET_ST_STM32MP15X || TARGET_ST_STM32MP21X || TARGET_ST_STM32MP23X || TARGET_ST_STM32MP25X
help
This compile the stboard command to
read and write the board in the OTP.

6
board/st/common/cmd_stboard.c
View File

@ -51,6 +51,7 @@ static bool check_stboard(u16 board)
0x1605, /* stm32mp25xx-dk */
0x1635,
0x1936, /* stm32mp25xx-ev1 */
0x2059, /* stm32mp21xx-dk */
};
for (i = 0; i < ARRAY_SIZE(st_board_id); i++)
@ -91,6 +92,11 @@ static int do_stboard(struct cmd_tbl *cmdtp, int flag, int argc,
DM_DRIVER_GET(stm32mp_bsec),
&dev);
if (ret) {
puts("Can't get BSEC device\n");
return CMD_RET_FAILURE;
}
ret = misc_read(dev, STM32_BSEC_OTP(BSEC_OTP_BOARD),
&otp, sizeof(otp));

14
board/st/stm32mp2/Kconfig
View File

@ -1,3 +1,17 @@
if TARGET_ST_STM32MP21X
config SYS_BOARD
default "stm32mp2"
config SYS_VENDOR
default "st"
config SYS_CONFIG_NAME
default "stm32mp21_st_common"
source "board/st/common/Kconfig"
endif
if TARGET_ST_STM32MP23X
config SYS_BOARD

78
configs/stm32mp21_defconfig Normal file
View File

@ -0,0 +1,78 @@
CONFIG_ARM=y
CONFIG_ARCH_STM32MP=y
CONFIG_SYS_MALLOC_F_LEN=0x600000
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x90000000
CONFIG_ENV_OFFSET=0x900000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp215f-dk"
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_SYS_LOAD_ADDR=0x84000000
CONFIG_STM32MP21X=y
CONFIG_DDR_CACHEABLE_SIZE=0x10000000
CONFIG_CMD_STM32KEY=y
CONFIG_TARGET_ST_STM32MP21X=y
CONFIG_SYS_MEMTEST_START=0x84000000
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_API=y
CONFIG_SYS_MMC_MAX_DEVICE=3
CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SYS_PROMPT="STM32MP> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ADTIMG=y
# CONFIG_CMD_ELF is not set
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADB is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_RNG=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_LOG=y
CONFIG_CMD_UBI=y
CONFIG_OF_LIVE=y
CONFIG_OF_UPSTREAM_BUILD_VENDOR=y
CONFIG_OF_UPSTREAM_VENDOR="st"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_IS_IN_UBI=y
CONFIG_ENV_UBI_PART="UBI"
CONFIG_ENV_UBI_VOLUME="uboot_config"
CONFIG_NO_NET=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_BUTTON=y
CONFIG_BUTTON_GPIO=y
CONFIG_GPIO_HOG=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_STM32F7=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_MTD=y
CONFIG_USE_SYS_MAX_FLASH_BANKS=y
CONFIG_SPI_FLASH=y
CONFIG_PINCONF=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_RAM=y
# CONFIG_STM32MP1_DDR is not set
CONFIG_DM_RNG=y
CONFIG_SERIAL_RX_BUFFER=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
# CONFIG_OPTEE_TA_AVB is not set
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
CONFIG_WDT_ARM_SMC=y
# CONFIG_UBIFS_SILENCE_DEBUG_DUMP is not set
CONFIG_ERRNO_STR=y

1
configs/stm32mp25_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_SYS_LOAD_ADDR=0x84000000
CONFIG_STM32MP25X=y
CONFIG_DDR_CACHEABLE_SIZE=0x10000000
CONFIG_CMD_STM32KEY=y
CONFIG_MFD_STM32_TIMERS=y
CONFIG_ENV_OFFSET_REDUND=0x940000
CONFIG_TARGET_ST_STM32MP25X=y

9
drivers/clk/stm32/Kconfig
View File

@ -37,6 +37,15 @@ config CLK_STM32MP13
Enable the STM32 clock (RCC) driver. Enable support for
manipulating STM32MP13's on-SoC clocks.
config CLK_STM32MP21
bool "Enable RCC clock driver for STM32MP21"
depends on ARCH_STM32MP && CLK
default y if STM32MP21X
select CLK_STM32_CORE
help
Enable the STM32 clock (RCC) driver. Enable support for
manipulating STM32MP21's on-SoC clocks.
config CLK_STM32MP25
bool "Enable RCC clock driver for STM32MP25"
depends on ARCH_STM32MP && CLK

1
drivers/clk/stm32/Makefile
View File

@ -7,4 +7,5 @@ obj-$(CONFIG_CLK_STM32F) += clk-stm32f.o
obj-$(CONFIG_CLK_STM32H7) += clk-stm32h7.o
obj-$(CONFIG_CLK_STM32MP1) += clk-stm32mp1.o
obj-$(CONFIG_CLK_STM32MP13) += clk-stm32mp13.o
obj-$(CONFIG_CLK_STM32MP21) += clk-stm32mp21.o
obj-$(CONFIG_CLK_STM32MP25) += clk-stm32mp25.o

709
drivers/clk/stm32/clk-stm32mp21.c Normal file
View File

@ -0,0 +1,709 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
/*
* Copyright (C) 2026, STMicroelectronics - All Rights Reserved
*/
#include <clk-uclass.h>
#include <dm.h>
#include <dt-bindings/clock/st,stm32mp21-rcc.h>
#include <linux/bitfield.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <mach/rif.h>
#include "clk-stm32-core.h"
#include "stm32mp21_rcc.h"
/* Clock security definition */
#define SECF_NONE -1
#define RCC_REG_SIZE 32
#define RCC_SECCFGR(x) (((x) / RCC_REG_SIZE) * 0x4 + RCC_SECCFGR0)
#define RCC_CIDCFGR(x) ((x) * 0x8 + RCC_R0CIDCFGR)
#define RCC_SEMCR(x) ((x) * 0x8 + RCC_R0SEMCR)
#define RCC_CID1 1
/* Register: RIFSC_CIDCFGR */
#define RCC_CIDCFGR_CFEN BIT(0)
#define RCC_CIDCFGR_SEM_EN BIT(1)
#define RCC_CIDCFGR_SEMWLC1_EN BIT(17)
#define RCC_CIDCFGR_SCID_MASK GENMASK(6, 4)
/* Register: RIFSC_SEMCR */
#define RCC_SEMCR_SEMCID_MASK GENMASK(6, 4)
#define STM32MP21_RIFRCC_DBG_ID 73
#define STM32MP21_RIFRCC_MCO1_ID 108
#define STM32MP21_RIFRCC_MCO2_ID 109
#define STM32MP21_RIFRCC_OSPI1_ID 110
#define SEC_RIFSC_FLAG BIT(31)
#define SEC_RIFRCC(_id) (STM32MP21_RIFRCC_##_id##_ID)
#define SEC_RIFSC(_id) ((_id) | SEC_RIFSC_FLAG)
/* must match scmi clock order found in DT */
enum {
IDX_HSE,
IDX_HSI,
IDX_MSI,
IDX_LSE,
IDX_LSI,
IDX_HSE_DIV2,
IDX_ICN_HS_MCU,
IDX_ICN_LS_MCU,
IDX_ICN_SDMMC,
IDX_ICN_DDR,
IDX_ICN_DISPLAY,
IDX_ICN_HSL,
IDX_ICN_NIC,
IDX_FLEXGEN_07,
IDX_FLEXGEN_08,
IDX_FLEXGEN_09,
IDX_FLEXGEN_10,
IDX_FLEXGEN_11,
IDX_FLEXGEN_12,
IDX_FLEXGEN_13,
IDX_FLEXGEN_14,
IDX_FLEXGEN_16,
IDX_FLEXGEN_17,
IDX_FLEXGEN_18,
IDX_FLEXGEN_19,
IDX_FLEXGEN_20,
IDX_FLEXGEN_21,
IDX_FLEXGEN_22,
IDX_FLEXGEN_23,
IDX_FLEXGEN_24,
IDX_FLEXGEN_25,
IDX_FLEXGEN_26,
IDX_FLEXGEN_27,
IDX_FLEXGEN_28,
IDX_FLEXGEN_29,
IDX_FLEXGEN_30,
IDX_FLEXGEN_31,
IDX_FLEXGEN_33,
IDX_FLEXGEN_36,
IDX_FLEXGEN_37,
IDX_FLEXGEN_38,
IDX_FLEXGEN_39,
IDX_FLEXGEN_40,
IDX_FLEXGEN_41,
IDX_FLEXGEN_42,
IDX_FLEXGEN_43,
IDX_FLEXGEN_44,
IDX_FLEXGEN_45,
IDX_FLEXGEN_46,
IDX_FLEXGEN_47,
IDX_FLEXGEN_48,
IDX_FLEXGEN_50,
IDX_FLEXGEN_51,
IDX_FLEXGEN_52,
IDX_FLEXGEN_53,
IDX_FLEXGEN_54,
IDX_FLEXGEN_55,
IDX_FLEXGEN_56,
IDX_FLEXGEN_57,
IDX_FLEXGEN_58,
IDX_FLEXGEN_61,
IDX_FLEXGEN_62,
IDX_FLEXGEN_63,
IDX_ICN_APB1,
IDX_ICN_APB2,
IDX_ICN_APB3,
IDX_ICN_APB4,
IDX_ICN_APB5,
IDX_ICN_APBDBG,
IDX_TIMG1,
IDX_TIMG2,
};
static const struct clk_parent_data adc1_src[] = {
{ .index = IDX_FLEXGEN_46 },
{ .index = IDX_ICN_LS_MCU },
};
static const struct clk_parent_data adc2_src[] = {
{ .index = IDX_FLEXGEN_47 },
{ .index = IDX_ICN_LS_MCU },
{ .index = IDX_FLEXGEN_46 },
};
static const struct clk_parent_data usb2phy1_src[] = {
{ .index = IDX_FLEXGEN_57 },
{ .index = IDX_HSE_DIV2 },
};
static const struct clk_parent_data usb2phy2_src[] = {
{ .index = IDX_FLEXGEN_58 },
{ .index = IDX_HSE_DIV2 },
};
static const struct clk_parent_data dts_src[] = {
{ .index = IDX_HSI },
{ .index = IDX_HSE },
{ .index = IDX_MSI },
};
static const struct clk_parent_data mco1_src[] = {
{ .index = IDX_FLEXGEN_61 },
{ .name = "ck_obs0" },
};
static const struct clk_parent_data mco2_src[] = {
{ .index = IDX_FLEXGEN_62 },
{ .name = "ck_obs1" },
};
enum enum_mux_cfg {
MUX_MCO1,
MUX_MCO2,
MUX_ADC1,
MUX_ADC2,
MUX_USB2PHY1,
MUX_USB2PHY2,
MUX_DTS,
MUX_NB
};
#define MUX_CFG(id, src, _offset, _shift, _witdh)[id] = {\
.num_parents = ARRAY_SIZE(src),\
.parent_data = src,\
.reg_off = (_offset),\
.shift = (_shift),\
.width = (_witdh),\
}
static const struct stm32_mux_cfg stm32mp21_muxes[MUX_NB] = {
MUX_CFG(MUX_ADC1, adc1_src, RCC_ADC1CFGR, 12, 1),
MUX_CFG(MUX_ADC2, adc2_src, RCC_ADC2CFGR, 12, 2),
MUX_CFG(MUX_DTS, dts_src, RCC_DTSCFGR, 12, 2),
MUX_CFG(MUX_MCO1, mco1_src, RCC_MCO1CFGR, 0, 1),
MUX_CFG(MUX_MCO2, mco2_src, RCC_MCO2CFGR, 0, 1),
MUX_CFG(MUX_USB2PHY1, usb2phy1_src, RCC_USB2PHY1CFGR, 15, 1),
MUX_CFG(MUX_USB2PHY2, usb2phy2_src, RCC_USB2PHY2CFGR, 15, 1),
};
enum enum_gate_cfg {
GATE_ADC1,
GATE_ADC2,
GATE_CRC,
GATE_CRYP1,
GATE_CRYP2,
GATE_CSI,
GATE_DBG,
GATE_DCMIPP,
GATE_DTS,
GATE_ETH1,
GATE_ETH1MAC,
GATE_ETH1RX,
GATE_ETH1STP,
GATE_ETH1TX,
GATE_ETH2,
GATE_ETH2MAC,
GATE_ETH2RX,
GATE_ETH2STP,
GATE_ETH2TX,
GATE_ETR,
GATE_FDCAN,
GATE_HASH1,
GATE_HASH2,
GATE_HDP,
GATE_I2C1,
GATE_I2C2,
GATE_I2C3,
GATE_I3C1,
GATE_I3C2,
GATE_I3C3,
GATE_IWDG1,
GATE_IWDG2,
GATE_IWDG3,
GATE_IWDG4,
GATE_LPTIM1,
GATE_LPTIM2,
GATE_LPTIM3,
GATE_LPTIM4,
GATE_LPTIM5,
GATE_LPUART1,
GATE_LTDC,
GATE_MCO1,
GATE_MCO2,
GATE_MDF1,
GATE_OSPI1,
GATE_PKA,
GATE_RNG1,
GATE_RNG2,
GATE_SAES,
GATE_SAI1,
GATE_SAI2,
GATE_SAI3,
GATE_SAI4,
GATE_SDMMC1,
GATE_SDMMC2,
GATE_SDMMC3,
GATE_SERC,
GATE_SPDIFRX,
GATE_SPI1,
GATE_SPI2,
GATE_SPI3,
GATE_SPI4,
GATE_SPI5,
GATE_SPI6,
GATE_STGEN,
GATE_STM,
GATE_TIM1,
GATE_TIM2,
GATE_TIM3,
GATE_TIM4,
GATE_TIM5,
GATE_TIM6,
GATE_TIM7,
GATE_TIM8,
GATE_TIM10,
GATE_TIM11,
GATE_TIM12,
GATE_TIM13,
GATE_TIM14,
GATE_TIM15,
GATE_TIM16,
GATE_TIM17,
GATE_TRACE,
GATE_UART4,
GATE_UART5,
GATE_UART7,
GATE_USART1,
GATE_USART2,
GATE_USART3,
GATE_USART6,
GATE_USBH,
GATE_USBOTG,
GATE_USB2PHY1,
GATE_USB2PHY2,
GATE_VREF,
GATE_WWDG1,
GATE_NB
};
#define GATE_CFG(id, _offset, _bit_idx, _offset_clr)[id] = {\
.reg_off = (_offset),\
.bit_idx = (_bit_idx),\
.set_clr = (_offset_clr),\
}
static const struct stm32_gate_cfg stm32mp21_gates[GATE_NB] = {
GATE_CFG(GATE_MCO1, RCC_MCO1CFGR, 8, 0),
GATE_CFG(GATE_MCO2, RCC_MCO2CFGR, 8, 0),
GATE_CFG(GATE_OSPI1, RCC_OSPI1CFGR, 1, 0),
GATE_CFG(GATE_DBG, RCC_DBGCFGR, 8, 0),
GATE_CFG(GATE_TRACE, RCC_DBGCFGR, 9, 0),
GATE_CFG(GATE_STM, RCC_STMCFGR, 1, 0),
GATE_CFG(GATE_ETR, RCC_ETRCFGR, 1, 0),
GATE_CFG(GATE_TIM1, RCC_TIM1CFGR, 1, 0),
GATE_CFG(GATE_TIM2, RCC_TIM2CFGR, 1, 0),
GATE_CFG(GATE_TIM3, RCC_TIM3CFGR, 1, 0),
GATE_CFG(GATE_TIM4, RCC_TIM4CFGR, 1, 0),
GATE_CFG(GATE_TIM5, RCC_TIM5CFGR, 1, 0),
GATE_CFG(GATE_TIM6, RCC_TIM6CFGR, 1, 0),
GATE_CFG(GATE_TIM7, RCC_TIM7CFGR, 1, 0),
GATE_CFG(GATE_TIM8, RCC_TIM8CFGR, 1, 0),
GATE_CFG(GATE_TIM10, RCC_TIM10CFGR, 1, 0),
GATE_CFG(GATE_TIM11, RCC_TIM11CFGR, 1, 0),
GATE_CFG(GATE_TIM12, RCC_TIM12CFGR, 1, 0),
GATE_CFG(GATE_TIM13, RCC_TIM13CFGR, 1, 0),
GATE_CFG(GATE_TIM14, RCC_TIM14CFGR, 1, 0),
GATE_CFG(GATE_TIM15, RCC_TIM15CFGR, 1, 0),
GATE_CFG(GATE_TIM16, RCC_TIM16CFGR, 1, 0),
GATE_CFG(GATE_TIM17, RCC_TIM17CFGR, 1, 0),
GATE_CFG(GATE_LPTIM1, RCC_LPTIM1CFGR, 1, 0),
GATE_CFG(GATE_LPTIM2, RCC_LPTIM2CFGR, 1, 0),
GATE_CFG(GATE_LPTIM3, RCC_LPTIM3CFGR, 1, 0),
GATE_CFG(GATE_LPTIM4, RCC_LPTIM4CFGR, 1, 0),
GATE_CFG(GATE_LPTIM5, RCC_LPTIM5CFGR, 1, 0),
GATE_CFG(GATE_SPI1, RCC_SPI1CFGR, 1, 0),
GATE_CFG(GATE_SPI2, RCC_SPI2CFGR, 1, 0),
GATE_CFG(GATE_SPI3, RCC_SPI3CFGR, 1, 0),
GATE_CFG(GATE_SPI4, RCC_SPI4CFGR, 1, 0),
GATE_CFG(GATE_SPI5, RCC_SPI5CFGR, 1, 0),
GATE_CFG(GATE_SPI6, RCC_SPI6CFGR, 1, 0),
GATE_CFG(GATE_SPDIFRX, RCC_SPDIFRXCFGR, 1, 0),
GATE_CFG(GATE_USART1, RCC_USART1CFGR, 1, 0),
GATE_CFG(GATE_USART2, RCC_USART2CFGR, 1, 0),
GATE_CFG(GATE_USART3, RCC_USART3CFGR, 1, 0),
GATE_CFG(GATE_UART4, RCC_UART4CFGR, 1, 0),
GATE_CFG(GATE_UART5, RCC_UART5CFGR, 1, 0),
GATE_CFG(GATE_USART6, RCC_USART6CFGR, 1, 0),
GATE_CFG(GATE_UART7, RCC_UART7CFGR, 1, 0),
GATE_CFG(GATE_LPUART1, RCC_LPUART1CFGR, 1, 0),
GATE_CFG(GATE_I2C1, RCC_I2C1CFGR, 1, 0),
GATE_CFG(GATE_I2C2, RCC_I2C2CFGR, 1, 0),
GATE_CFG(GATE_I2C3, RCC_I2C3CFGR, 1, 0),
GATE_CFG(GATE_SAI1, RCC_SAI1CFGR, 1, 0),
GATE_CFG(GATE_SAI2, RCC_SAI2CFGR, 1, 0),
GATE_CFG(GATE_SAI3, RCC_SAI3CFGR, 1, 0),
GATE_CFG(GATE_SAI4, RCC_SAI4CFGR, 1, 0),
GATE_CFG(GATE_MDF1, RCC_MDF1CFGR, 1, 0),
GATE_CFG(GATE_FDCAN, RCC_FDCANCFGR, 1, 0),
GATE_CFG(GATE_HDP, RCC_HDPCFGR, 1, 0),
GATE_CFG(GATE_ADC1, RCC_ADC1CFGR, 1, 0),
GATE_CFG(GATE_ADC2, RCC_ADC2CFGR, 1, 0),
GATE_CFG(GATE_ETH1MAC, RCC_ETH1CFGR, 1, 0),
GATE_CFG(GATE_ETH1STP, RCC_ETH1CFGR, 4, 0),
GATE_CFG(GATE_ETH1, RCC_ETH1CFGR, 5, 0),
GATE_CFG(GATE_ETH1TX, RCC_ETH1CFGR, 8, 0),
GATE_CFG(GATE_ETH1RX, RCC_ETH1CFGR, 10, 0),
GATE_CFG(GATE_ETH2MAC, RCC_ETH2CFGR, 1, 0),
GATE_CFG(GATE_ETH2STP, RCC_ETH2CFGR, 4, 0),
GATE_CFG(GATE_ETH2, RCC_ETH2CFGR, 5, 0),
GATE_CFG(GATE_ETH2TX, RCC_ETH2CFGR, 8, 0),
GATE_CFG(GATE_ETH2RX, RCC_ETH2CFGR, 10, 0),
GATE_CFG(GATE_USBH, RCC_USBHCFGR, 1, 0),
GATE_CFG(GATE_USB2PHY1, RCC_USB2PHY1CFGR, 1, 0),
GATE_CFG(GATE_USBOTG, RCC_OTGCFGR, 1, 0),
GATE_CFG(GATE_USB2PHY2, RCC_USB2PHY2CFGR, 1, 0),
GATE_CFG(GATE_STGEN, RCC_STGENCFGR, 1, 0),
GATE_CFG(GATE_SDMMC1, RCC_SDMMC1CFGR, 1, 0),
GATE_CFG(GATE_SDMMC2, RCC_SDMMC2CFGR, 1, 0),
GATE_CFG(GATE_SDMMC3, RCC_SDMMC3CFGR, 1, 0),
GATE_CFG(GATE_LTDC, RCC_LTDCCFGR, 1, 0),
GATE_CFG(GATE_CSI, RCC_CSICFGR, 1, 0),
GATE_CFG(GATE_DCMIPP, RCC_DCMIPPCFGR, 1, 0),
GATE_CFG(GATE_RNG1, RCC_RNG1CFGR, 1, 0),
GATE_CFG(GATE_RNG2, RCC_RNG2CFGR, 1, 0),
GATE_CFG(GATE_PKA, RCC_PKACFGR, 1, 0),
GATE_CFG(GATE_SAES, RCC_SAESCFGR, 1, 0),
GATE_CFG(GATE_HASH1, RCC_HASH1CFGR, 1, 0),
GATE_CFG(GATE_HASH2, RCC_HASH2CFGR, 1, 0),
GATE_CFG(GATE_CRYP1, RCC_CRYP1CFGR, 1, 0),
GATE_CFG(GATE_CRYP2, RCC_CRYP2CFGR, 1, 0),
GATE_CFG(GATE_IWDG1, RCC_IWDG1CFGR, 1, 0),
GATE_CFG(GATE_IWDG2, RCC_IWDG2CFGR, 1, 0),
GATE_CFG(GATE_IWDG3, RCC_IWDG3CFGR, 1, 0),
GATE_CFG(GATE_IWDG4, RCC_IWDG4CFGR, 1, 0),
GATE_CFG(GATE_WWDG1, RCC_WWDG1CFGR, 1, 0),
GATE_CFG(GATE_VREF, RCC_VREFCFGR, 1, 0),
GATE_CFG(GATE_DTS, RCC_DTSCFGR, 1, 0),
GATE_CFG(GATE_CRC, RCC_CRCCFGR, 1, 0),
GATE_CFG(GATE_SERC, RCC_SERCCFGR, 1, 0),
GATE_CFG(GATE_I3C1, RCC_I3C1CFGR, 1, 0),
GATE_CFG(GATE_I3C2, RCC_I3C2CFGR, 1, 0),
GATE_CFG(GATE_I3C3, RCC_I3C3CFGR, 1, 0),
};
static int stm32_rcc_get_access(struct udevice *dev, u32 index)
{
fdt_addr_t rcc_base = dev_read_addr(dev->parent);
u32 seccfgr, cidcfgr, semcr;
int bit, cid;
bit = index % RCC_REG_SIZE;
seccfgr = readl(rcc_base + RCC_SECCFGR(index));
if (seccfgr & BIT(bit))
return -EACCES;
cidcfgr = readl(rcc_base + RCC_CIDCFGR(index));
if (!(cidcfgr & RCC_CIDCFGR_CFEN))
/* CID filtering is turned off: access granted */
return 0;
if (!(cidcfgr & RCC_CIDCFGR_SEM_EN)) {
/* Static CID mode */
cid = FIELD_GET(RCC_CIDCFGR_SCID_MASK, cidcfgr);
if (cid != RCC_CID1)
return -EACCES;
return 0;
}
/* Pass-list with semaphore mode */
if (!(cidcfgr & RCC_CIDCFGR_SEMWLC1_EN))
return -EACCES;
semcr = readl(rcc_base + RCC_SEMCR(index));
cid = FIELD_GET(RCC_SEMCR_SEMCID_MASK, semcr);
if (cid != RCC_CID1)
return -EACCES;
return 0;
}
static int stm32mp21_check_security(struct udevice *dev, void __iomem *base,
const struct clock_config *cfg)
{
int ret = 0;
if (cfg->sec_id != SECF_NONE) {
u32 index = (u32)cfg->sec_id;
if (index & SEC_RIFSC_FLAG)
ret = stm32_rifsc_grant_access_by_id(dev_ofnode(dev),
index & ~SEC_RIFSC_FLAG);
else
ret = stm32_rcc_get_access(dev, index);
}
return ret;
}
#define STM32_COMPOSITE_NODIV(_id, _name, _flags, _sec_id, _gate_id, _mux_id)\
STM32_COMPOSITE(_id, _name, _flags, _sec_id, _gate_id, _mux_id, NO_STM32_DIV)
static const struct clock_config stm32mp21_clock_cfg[] = {
/* ADC */
STM32_GATE(CK_BUS_ADC1, "ck_icn_p_adc1", IDX_ICN_LS_MCU, 0, GATE_ADC1,
SEC_RIFSC(58)),
STM32_COMPOSITE_NODIV(CK_KER_ADC1, "ck_ker_adc12", 0, SEC_RIFSC(58),
GATE_ADC1, MUX_ADC1),
STM32_GATE(CK_BUS_ADC2, "ck_icn_p_adc2", IDX_ICN_LS_MCU, 0, GATE_ADC2, SEC_RIFSC(59)),
STM32_COMPOSITE_NODIV(CK_KER_ADC2, "ck_ker_adc2", 0, SEC_RIFSC(59), GATE_ADC2, MUX_ADC2),
/* CSI-HOST */
STM32_GATE(CK_BUS_CSI, "ck_icn_p_csi", IDX_ICN_APB4, 0, GATE_CSI, SEC_RIFSC(86)),
STM32_GATE(CK_KER_CSI, "ck_ker_csi", IDX_FLEXGEN_29, 0, GATE_CSI, SEC_RIFSC(86)),
STM32_GATE(CK_KER_CSITXESC, "ck_ker_csitxesc", IDX_FLEXGEN_30, 0, GATE_CSI,
SEC_RIFSC(86)),
/* CSI-PHY */
STM32_GATE(CK_KER_CSIPHY, "ck_ker_csiphy", IDX_FLEXGEN_31, 0, GATE_CSI,
SEC_RIFSC(86)),
/* DCMIPP */
STM32_GATE(CK_BUS_DCMIPP, "ck_icn_p_dcmipp", IDX_ICN_APB4, 0, GATE_DCMIPP,
SEC_RIFSC(87)),
/* CRC */
STM32_GATE(CK_BUS_CRC, "ck_icn_p_crc", IDX_ICN_LS_MCU, 0, GATE_CRC, SEC_RIFSC(109)),
/* CRYP */
STM32_GATE(CK_BUS_CRYP1, "ck_icn_p_cryp1", IDX_ICN_LS_MCU, 0, GATE_CRYP1,
SEC_RIFSC(98)),
STM32_GATE(CK_BUS_CRYP2, "ck_icn_p_cryp2", IDX_ICN_LS_MCU, 0, GATE_CRYP2,
SEC_RIFSC(99)),
/* DBG & TRACE*/
/* Trace and debug clocks are managed by SCMI */
/* Display subsystem */
/* LTDC */
STM32_GATE(CK_BUS_LTDC, "ck_icn_p_ltdc", IDX_ICN_APB4, 0, GATE_LTDC, SEC_RIFSC(80)),
STM32_GATE(CK_KER_LTDC, "ck_ker_ltdc", IDX_FLEXGEN_27, CLK_SET_RATE_PARENT, GATE_LTDC,
SEC_RIFSC(80)),
/* DTS */
STM32_COMPOSITE_NODIV(CK_KER_DTS, "ck_ker_dts", 0, SEC_RIFSC(107), GATE_DTS, MUX_DTS),
/* ETHERNET */
STM32_GATE(CK_BUS_ETH1, "ck_icn_p_eth1", IDX_ICN_LS_MCU, 0, GATE_ETH1, SEC_RIFSC(60)),
STM32_GATE(CK_ETH1_STP, "ck_ker_eth1stp", IDX_ICN_LS_MCU, 0, GATE_ETH1STP,
SEC_RIFSC(60)),
STM32_GATE(CK_KER_ETH1, "ck_ker_eth1", IDX_FLEXGEN_54, 0, GATE_ETH1, SEC_RIFSC(60)),
STM32_GATE(CK_KER_ETH1, "ck_ker_eth1ptp", IDX_FLEXGEN_56, 0, GATE_ETH1, SEC_RIFSC(60)),
STM32_GATE(CK_ETH1_MAC, "ck_ker_eth1mac", IDX_ICN_LS_MCU, 0, GATE_ETH1MAC,
SEC_RIFSC(60)),
STM32_GATE(CK_ETH1_TX, "ck_ker_eth1tx", IDX_ICN_LS_MCU, 0, GATE_ETH1TX, SEC_RIFSC(60)),
STM32_GATE(CK_ETH1_RX, "ck_ker_eth1rx", IDX_ICN_LS_MCU, 0, GATE_ETH1RX, SEC_RIFSC(60)),
STM32_GATE(CK_BUS_ETH2, "ck_icn_p_eth2", IDX_ICN_LS_MCU, 0, GATE_ETH2, SEC_RIFSC(61)),
STM32_GATE(CK_ETH2_STP, "ck_ker_eth2stp", IDX_ICN_LS_MCU, 0, GATE_ETH2STP,
SEC_RIFSC(61)),
STM32_GATE(CK_KER_ETH2, "ck_ker_eth2", IDX_FLEXGEN_54, 0, GATE_ETH2, SEC_RIFSC(61)),
STM32_GATE(CK_KER_ETH2, "ck_ker_eth2ptp", IDX_FLEXGEN_56, 0, GATE_ETH2, SEC_RIFSC(61)),
STM32_GATE(CK_ETH2_MAC, "ck_ker_eth2mac", IDX_ICN_LS_MCU, 0, GATE_ETH2MAC,
SEC_RIFSC(61)),
STM32_GATE(CK_ETH2_TX, "ck_ker_eth2tx", IDX_ICN_LS_MCU, 0, GATE_ETH2TX, SEC_RIFSC(61)),
STM32_GATE(CK_ETH2_RX, "ck_ker_eth2rx", IDX_ICN_LS_MCU, 0, GATE_ETH2RX, SEC_RIFSC(61)),
/* FDCAN */
STM32_GATE(CK_BUS_FDCAN, "ck_icn_p_fdcan", IDX_ICN_APB2, 0, GATE_FDCAN, SEC_RIFSC(56)),
STM32_GATE(CK_KER_FDCAN, "ck_ker_fdcan", IDX_FLEXGEN_26, 0, GATE_FDCAN, SEC_RIFSC(56)),
/* HASH */
STM32_GATE(CK_BUS_HASH1, "ck_icn_p_hash1", IDX_ICN_LS_MCU, 0, GATE_HASH1, SEC_RIFSC(96)),
STM32_GATE(CK_BUS_HASH2, "ck_icn_p_hash2", IDX_ICN_LS_MCU, 0, GATE_HASH2, SEC_RIFSC(97)),
/* HDP */
STM32_GATE(CK_BUS_HDP, "ck_icn_p_hdp", IDX_ICN_APB3, 0, GATE_HDP, SEC_RIFSC(57)),
/* I2C */
STM32_GATE(CK_KER_I2C1, "ck_ker_i2c1", IDX_FLEXGEN_13, 0, GATE_I2C1, SEC_RIFSC(41)),
STM32_GATE(CK_KER_I2C2, "ck_ker_i2c2", IDX_FLEXGEN_13, 0, GATE_I2C2, SEC_RIFSC(42)),
STM32_GATE(CK_KER_I2C3, "ck_ker_i2c3", IDX_FLEXGEN_38, 0, GATE_I2C3, SEC_RIFSC(43)),
/* I3C */
STM32_GATE(CK_KER_I3C1, "ck_ker_i3c1", IDX_FLEXGEN_14, 0, GATE_I3C1, SEC_RIFSC(114)),
STM32_GATE(CK_KER_I3C2, "ck_ker_i3c2", IDX_FLEXGEN_14, 0, GATE_I3C2, SEC_RIFSC(115)),
STM32_GATE(CK_KER_I3C3, "ck_ker_i3c3", IDX_FLEXGEN_36, 0, GATE_I3C3, SEC_RIFSC(116)),
/* IWDG */
STM32_GATE(CK_BUS_IWDG1, "ck_icn_p_iwdg1", IDX_ICN_APB3, 0, GATE_IWDG1, SEC_RIFSC(100)),
STM32_GATE(CK_BUS_IWDG2, "ck_icn_p_iwdg2", IDX_ICN_APB3, 0, GATE_IWDG2, SEC_RIFSC(101)),
STM32_GATE(CK_BUS_IWDG3, "ck_icn_p_iwdg3", IDX_ICN_APB3, 0, GATE_IWDG3, SEC_RIFSC(102)),
STM32_GATE(CK_BUS_IWDG4, "ck_icn_p_iwdg4", IDX_ICN_APB3, 0, GATE_IWDG4, SEC_RIFSC(103)),
/* LPTIM */
STM32_GATE(CK_KER_LPTIM1, "ck_ker_lptim1", IDX_FLEXGEN_07, 0, GATE_LPTIM1,
SEC_RIFSC(17)),
STM32_GATE(CK_KER_LPTIM2, "ck_ker_lptim2", IDX_FLEXGEN_07, 0, GATE_LPTIM2,
SEC_RIFSC(18)),
STM32_GATE(CK_KER_LPTIM3, "ck_ker_lptim3", IDX_FLEXGEN_40, 0, GATE_LPTIM3,
SEC_RIFSC(19)),
STM32_GATE(CK_KER_LPTIM4, "ck_ker_lptim4", IDX_FLEXGEN_41, 0, GATE_LPTIM4,
SEC_RIFSC(20)),
STM32_GATE(CK_KER_LPTIM5, "ck_ker_lptim5", IDX_FLEXGEN_42, 0, GATE_LPTIM5,
SEC_RIFSC(21)),
/* LPUART */
STM32_GATE(CK_KER_LPUART1, "ck_ker_lpuart1", IDX_FLEXGEN_39, 0, GATE_LPUART1,
SEC_RIFSC(40)),
/* MCO1 & MCO2 */
STM32_COMPOSITE_NODIV(CK_MCO1, "ck_mco1", 0, SEC_RIFRCC(MCO1), GATE_MCO1, MUX_MCO1),
STM32_COMPOSITE_NODIV(CK_MCO2, "ck_mco2", 0, SEC_RIFRCC(MCO2), GATE_MCO2, MUX_MCO2),
/* MDF */
STM32_GATE(CK_KER_MDF1, "ck_ker_mdf1", IDX_FLEXGEN_21, 0, GATE_MDF1, SEC_RIFSC(54)),
/* PKA */
STM32_GATE(CK_BUS_PKA, "ck_icn_p_pka", IDX_ICN_LS_MCU, 0, GATE_PKA, SEC_RIFSC(94)),
/* RNG */
STM32_GATE(CK_BUS_RNG1, "ck_icn_p_rng1", IDX_ICN_LS_MCU, CLK_IGNORE_UNUSED, GATE_RNG1,
SEC_RIFSC(92)),
STM32_GATE(CK_BUS_RNG2, "ck_icn_p_rng2", IDX_ICN_LS_MCU, CLK_IGNORE_UNUSED, GATE_RNG2,
SEC_RIFSC(93)),
/* SAES */
STM32_GATE(CK_BUS_SAES, "ck_icn_p_saes", IDX_ICN_LS_MCU, 0, GATE_SAES, SEC_RIFSC(95)),
/* SAI [1..4] */
STM32_GATE(CK_BUS_SAI1, "ck_icn_p_sai1", IDX_ICN_APB2, 0, GATE_SAI1, SEC_RIFSC(49)),
STM32_GATE(CK_BUS_SAI2, "ck_icn_p_sai2", IDX_ICN_APB2, 0, GATE_SAI2, SEC_RIFSC(50)),
STM32_GATE(CK_BUS_SAI3, "ck_icn_p_sai3", IDX_ICN_APB2, 0, GATE_SAI3, SEC_RIFSC(51)),
STM32_GATE(CK_BUS_SAI4, "ck_icn_p_sai4", IDX_ICN_APB2, 0, GATE_SAI4, SEC_RIFSC(52)),
STM32_GATE(CK_KER_SAI1, "ck_ker_sai1", IDX_FLEXGEN_22, 0, GATE_SAI1, SEC_RIFSC(49)),
STM32_GATE(CK_KER_SAI2, "ck_ker_sai2", IDX_FLEXGEN_23, 0, GATE_SAI2, SEC_RIFSC(50)),
STM32_GATE(CK_KER_SAI3, "ck_ker_sai3", IDX_FLEXGEN_24, 0, GATE_SAI3, SEC_RIFSC(51)),
STM32_GATE(CK_KER_SAI4, "ck_ker_sai4", IDX_FLEXGEN_25, 0, GATE_SAI4, SEC_RIFSC(52)),
/* SDMMC */
STM32_GATE(CK_KER_SDMMC1, "ck_ker_sdmmc1", IDX_FLEXGEN_51, 0, GATE_SDMMC1,
SEC_RIFSC(76)),
STM32_GATE(CK_KER_SDMMC2, "ck_ker_sdmmc2", IDX_FLEXGEN_52, 0, GATE_SDMMC2,
SEC_RIFSC(77)),
STM32_GATE(CK_KER_SDMMC3, "ck_ker_sdmmc3", IDX_FLEXGEN_53, 0, GATE_SDMMC3,
SEC_RIFSC(78)),
/* SERC */
STM32_GATE(CK_BUS_SERC, "ck_icn_p_serc", IDX_ICN_APB3, 0, GATE_SERC, SEC_RIFSC(110)),
/* SPDIF */
STM32_GATE(CK_KER_SPDIFRX, "ck_ker_spdifrx", IDX_FLEXGEN_12, 0, GATE_SPDIFRX,
SEC_RIFSC(30)),
/* SPI */
STM32_GATE(CK_KER_SPI1, "ck_ker_spi1", IDX_FLEXGEN_16, 0, GATE_SPI1, SEC_RIFSC(22)),
STM32_GATE(CK_KER_SPI2, "ck_ker_spi2", IDX_FLEXGEN_10, 0, GATE_SPI2, SEC_RIFSC(23)),
STM32_GATE(CK_KER_SPI3, "ck_ker_spi3", IDX_FLEXGEN_11, 0, GATE_SPI3, SEC_RIFSC(24)),
STM32_GATE(CK_KER_SPI4, "ck_ker_spi4", IDX_FLEXGEN_17, 0, GATE_SPI4, SEC_RIFSC(25)),
STM32_GATE(CK_KER_SPI5, "ck_ker_spi5", IDX_FLEXGEN_17, 0, GATE_SPI5, SEC_RIFSC(26)),
STM32_GATE(CK_KER_SPI6, "ck_ker_spi6", IDX_FLEXGEN_37, 0, GATE_SPI6, SEC_RIFSC(27)),
/* STGEN */
STM32_GATE(CK_KER_STGEN, "ck_ker_stgen", IDX_FLEXGEN_33, CLK_IGNORE_UNUSED, GATE_STGEN,
SEC_RIFSC(73)),
/* Timers */
STM32_GATE(CK_KER_TIM2, "ck_ker_tim2", IDX_TIMG1, 0, GATE_TIM2, SEC_RIFSC(1)),
STM32_GATE(CK_KER_TIM3, "ck_ker_tim3", IDX_TIMG1, 0, GATE_TIM3, SEC_RIFSC(2)),
STM32_GATE(CK_KER_TIM4, "ck_ker_tim4", IDX_TIMG1, 0, GATE_TIM4, SEC_RIFSC(3)),
STM32_GATE(CK_KER_TIM5, "ck_ker_tim5", IDX_TIMG1, 0, GATE_TIM5, SEC_RIFSC(4)),
STM32_GATE(CK_KER_TIM6, "ck_ker_tim6", IDX_TIMG1, 0, GATE_TIM6, SEC_RIFSC(5)),
STM32_GATE(CK_KER_TIM7, "ck_ker_tim7", IDX_TIMG1, 0, GATE_TIM7, SEC_RIFSC(6)),
STM32_GATE(CK_KER_TIM10, "ck_ker_tim10", IDX_TIMG1, 0, GATE_TIM10, SEC_RIFSC(8)),
STM32_GATE(CK_KER_TIM11, "ck_ker_tim11", IDX_TIMG1, 0, GATE_TIM11, SEC_RIFSC(9)),
STM32_GATE(CK_KER_TIM12, "ck_ker_tim12", IDX_TIMG1, 0, GATE_TIM12, SEC_RIFSC(10)),
STM32_GATE(CK_KER_TIM13, "ck_ker_tim13", IDX_TIMG1, 0, GATE_TIM13, SEC_RIFSC(11)),
STM32_GATE(CK_KER_TIM14, "ck_ker_tim14", IDX_TIMG1, 0, GATE_TIM14, SEC_RIFSC(12)),
STM32_GATE(CK_KER_TIM1, "ck_ker_tim1", IDX_TIMG2, 0, GATE_TIM1, SEC_RIFSC(0)),
STM32_GATE(CK_KER_TIM8, "ck_ker_tim8", IDX_TIMG2, 0, GATE_TIM8, SEC_RIFSC(7)),
STM32_GATE(CK_KER_TIM15, "ck_ker_tim15", IDX_TIMG2, 0, GATE_TIM15, SEC_RIFSC(13)),
STM32_GATE(CK_KER_TIM16, "ck_ker_tim16", IDX_TIMG2, 0, GATE_TIM16, SEC_RIFSC(14)),
STM32_GATE(CK_KER_TIM17, "ck_ker_tim17", IDX_TIMG2, 0, GATE_TIM17, SEC_RIFSC(15)),
/* UART/USART */
STM32_GATE(CK_KER_USART2, "ck_ker_usart2", IDX_FLEXGEN_08, 0, GATE_USART2,
SEC_RIFSC(32)),
STM32_GATE(CK_KER_UART4, "ck_ker_uart4", IDX_FLEXGEN_08, 0, GATE_UART4,
SEC_RIFSC(34)),
STM32_GATE(CK_KER_USART3, "ck_ker_usart3", IDX_FLEXGEN_09, 0, GATE_USART3,
SEC_RIFSC(33)),
STM32_GATE(CK_KER_UART5, "ck_ker_uart5", IDX_FLEXGEN_09, 0, GATE_UART5,
SEC_RIFSC(35)),
STM32_GATE(CK_KER_USART1, "ck_ker_usart1", IDX_FLEXGEN_18, 0, GATE_USART1,
SEC_RIFSC(31)),
STM32_GATE(CK_KER_USART6, "ck_ker_usart6", IDX_FLEXGEN_19, 0, GATE_USART6,
SEC_RIFSC(36)),
STM32_GATE(CK_KER_UART7, "ck_ker_uart7", IDX_FLEXGEN_20, 0, GATE_UART7,
SEC_RIFSC(37)),
/* USB2PHY1 */
STM32_COMPOSITE_NODIV(CK_KER_USB2PHY1, "ck_ker_usb2phy1", 0, SEC_RIFSC(63),
GATE_USB2PHY1, MUX_USB2PHY1),
/* USB2H */
STM32_GATE(CK_BUS_USBHOHCI, "ck_icn_m_usbhohci", IDX_ICN_HSL, 0, GATE_USBH,
SEC_RIFSC(63)),
STM32_GATE(CK_BUS_USBHEHCI, "ck_icn_m_usbhehci", IDX_ICN_HSL, 0, GATE_USBH,
SEC_RIFSC(63)),
/* USBOTG */
STM32_GATE(CK_BUS_OTG, "ck_icn_m_otg", IDX_ICN_HSL, 0, GATE_USBOTG,
SEC_RIFSC(66)),
/* USB2PHY2 */
STM32_COMPOSITE_NODIV(CK_KER_USB2PHY2EN, "ck_ker_usb2phy2_en", 0, SEC_RIFSC(66),
GATE_USB2PHY2, MUX_USB2PHY2),
/* VREF */
STM32_GATE(CK_BUS_VREF, "ck_icn_p_vref", IDX_ICN_APB3, 0, RCC_VREFCFGR,
SEC_RIFSC(106)),
/* WWDG */
STM32_GATE(CK_BUS_WWDG1, "ck_icn_p_wwdg1", IDX_ICN_APB3, 0, GATE_WWDG1,
SEC_RIFSC(104)),
};
static const struct stm32_clock_match_data stm32mp21_data = {
.tab_clocks = stm32mp21_clock_cfg,
.num_clocks = ARRAY_SIZE(stm32mp21_clock_cfg),
.clock_data = &(const struct clk_stm32_clock_data) {
.num_gates = ARRAY_SIZE(stm32mp21_gates),
.gates = stm32mp21_gates,
.muxes = stm32mp21_muxes,
},
.check_security = stm32mp21_check_security,
};
static int stm32mp21_clk_probe(struct udevice *dev)
{
fdt_addr_t base = dev_read_addr(dev->parent);
struct udevice *scmi;
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
/* force SCMI probe to register all SCMI clocks */
uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(scmi_clock), &scmi);
stm32_rcc_init(dev, &stm32mp21_data);
return 0;
}
U_BOOT_DRIVER(stm32mp21_clock) = {
.name = "stm32mp21_clk",
.id = UCLASS_CLK,
.ops = &stm32_clk_ops,
.priv_auto = sizeof(struct stm32mp_rcc_priv),
.probe = stm32mp21_clk_probe,
};

25
drivers/gpio/stm32_gpio.c
View File

@ -32,6 +32,9 @@
#define OTYPE_BITS(gpio_pin) (gpio_pin)
#define OTYPE_MSK 1
#define SECCFG_BITS(gpio_pin) (gpio_pin)
#define SECCFG_MSK 1
static void stm32_gpio_set_moder(struct stm32_gpio_regs *regs,
int idx,
int mode)
@ -89,6 +92,27 @@ static bool stm32_gpio_is_mapped(struct udevice *dev, int offset)
return !!(priv->gpio_range & BIT(offset));
}
static int stm32_gpio_request(struct udevice *dev, unsigned int offset, const char *label)
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct stm32_gpio_regs *regs = priv->regs;
ulong drv_data = dev_get_driver_data(dev);
if (!stm32_gpio_is_mapped(dev, offset))
return -ENXIO;
/* Deny request access if IO is secured */
if ((drv_data & STM32_GPIO_FLAG_SEC_CTRL) &&
((readl(&regs->seccfgr) >> SECCFG_BITS(offset)) & SECCFG_MSK)) {
dev_err(dev, "Failed to get secure IO %s %d @ %p\n",
uc_priv->bank_name, offset, regs);
return -EACCES;
}
return 0;
}
static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
@ -238,6 +262,7 @@ static int stm32_gpio_get_flags(struct udevice *dev, unsigned int offset,
}
static const struct dm_gpio_ops gpio_stm32_ops = {
.request = stm32_gpio_request,
.direction_input = stm32_gpio_direction_input,
.direction_output = stm32_gpio_direction_output,
.get_value = stm32_gpio_get_value,

5
drivers/gpio/stm32_gpio_priv.h
View File

@ -51,6 +51,8 @@ enum stm32_gpio_af {
STM32_GPIO_AF15
};
#define STM32_GPIO_FLAG_SEC_CTRL BIT(0)
struct stm32_gpio_dsc {
u8 port;
u8 pin;
@ -74,6 +76,9 @@ struct stm32_gpio_regs {
u32 bsrr; /* GPIO port bit set/reset */
u32 lckr; /* GPIO port configuration lock */
u32 afr[2]; /* GPIO alternate function */
u32 brr; /* GPIO port bit reset */
u32 rfu; /* Reserved */
u32 seccfgr; /* GPIO secure configuration */
};
struct stm32_gpio_priv {

83
drivers/pinctrl/pinctrl_stm32.c
View File

@ -11,6 +11,7 @@
#include <malloc.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <dm/device-internal.h>
#include <dm/device_compat.h>
#include <dm/lists.h>
#include <dm/pinctrl.h>
@ -27,6 +28,7 @@
#define PUPD_MASK 3
#define OTYPE_MSK 1
#define AFR_MASK 0xF
#define SECCFG_MSK 1
struct stm32_pinctrl_priv {
struct hwspinlock hws;
@ -39,7 +41,12 @@ struct stm32_gpio_bank {
struct list_head list;
};
struct stm32_pinctrl_data {
bool secure_control;
};
#ifndef CONFIG_XPL_BUILD
static int stm32_pinctrl_get_access(struct udevice *gpio_dev, unsigned int gpio_idx);
static char pin_name[PINNAME_SIZE];
static const char * const pinmux_mode[GPIOF_COUNT] = {
@ -216,6 +223,12 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
if (!gpio_dev)
return -ENODEV;
/* Check access protection */
if (stm32_pinctrl_get_access(gpio_dev, gpio_idx)) {
snprintf(buf, size, "NO ACCESS");
return 0;
}
mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
selector, gpio_idx, mode);
@ -252,6 +265,20 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
#endif
static int stm32_pinctrl_get_access(struct udevice *gpio_dev, unsigned int gpio_idx)
{
struct stm32_gpio_priv *priv = dev_get_priv(gpio_dev);
struct stm32_gpio_regs *regs = priv->regs;
ulong drv_data = dev_get_driver_data(gpio_dev);
/* Deny request access if IO is secured */
if ((drv_data & STM32_GPIO_FLAG_SEC_CTRL) &&
((readl(&regs->seccfgr) >> gpio_idx) & SECCFG_MSK))
return -EACCES;
return 0;
}
static int stm32_pinctrl_probe(struct udevice *dev)
{
struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
@ -279,6 +306,14 @@ static int stm32_gpio_config(ofnode node,
int ret;
u32 index;
/* Check access protection */
ret = stm32_pinctrl_get_access(desc->dev, desc->offset);
if (ret) {
dev_err(desc->dev, "Failed to get secure IO %s %d @ %p\n",
uc_priv->bank_name, desc->offset, regs);
return ret;
}
if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
ctl->pupd > 2 || ctl->speed > 3)
return -EINVAL;
@ -414,8 +449,25 @@ static int stm32_pinctrl_bind(struct udevice *dev)
{
ofnode node;
const char *name;
struct driver *drv;
const struct stm32_pinctrl_data *drv_data;
ulong gpio_data = 0;
int ret;
drv = lists_driver_lookup_name("gpio_stm32");
if (!drv) {
debug("Cannot find driver 'gpio_stm32'\n");
return -ENOENT;
}
drv_data = (const struct stm32_pinctrl_data *)dev_get_driver_data(dev);
if (!drv_data) {
debug("Cannot find driver data\n");
return -EINVAL;
}
if (drv_data->secure_control)
gpio_data = STM32_GPIO_FLAG_SEC_CTRL;
dev_for_each_subnode(node, dev) {
dev_dbg(dev, "bind %s\n", ofnode_get_name(node));
@ -431,8 +483,7 @@ static int stm32_pinctrl_bind(struct udevice *dev)
return -EINVAL;
/* Bind each gpio node */
ret = device_bind_driver_to_node(dev, "gpio_stm32",
name, node, NULL);
ret = device_bind_with_driver_data(dev, drv, name, gpio_data, node, NULL);
if (ret)
return ret;
@ -495,17 +546,25 @@ static struct pinctrl_ops stm32_pinctrl_ops = {
#endif
};
static const struct stm32_pinctrl_data stm32_pinctrl_no_sec = {
.secure_control = false,
};
static const struct stm32_pinctrl_data stm32_pinctrl_with_sec = {
.secure_control = true,
};
static const struct udevice_id stm32_pinctrl_ids[] = {
{ .compatible = "st,stm32f429-pinctrl" },
{ .compatible = "st,stm32f469-pinctrl" },
{ .compatible = "st,stm32f746-pinctrl" },
{ .compatible = "st,stm32f769-pinctrl" },
{ .compatible = "st,stm32h743-pinctrl" },
{ .compatible = "st,stm32mp157-pinctrl" },
{ .compatible = "st,stm32mp157-z-pinctrl" },
{ .compatible = "st,stm32mp135-pinctrl" },
{ .compatible = "st,stm32mp257-pinctrl" },
{ .compatible = "st,stm32mp257-z-pinctrl" },
{ .compatible = "st,stm32f429-pinctrl", .data = (ulong)&stm32_pinctrl_no_sec },
{ .compatible = "st,stm32f469-pinctrl", .data = (ulong)&stm32_pinctrl_no_sec },
{ .compatible = "st,stm32f746-pinctrl", .data = (ulong)&stm32_pinctrl_no_sec },
{ .compatible = "st,stm32f769-pinctrl", .data = (ulong)&stm32_pinctrl_no_sec },
{ .compatible = "st,stm32h743-pinctrl", .data = (ulong)&stm32_pinctrl_no_sec },
{ .compatible = "st,stm32mp157-pinctrl", .data = (ulong)&stm32_pinctrl_no_sec },
{ .compatible = "st,stm32mp157-z-pinctrl", .data = (ulong)&stm32_pinctrl_no_sec },
{ .compatible = "st,stm32mp135-pinctrl", .data = (ulong)&stm32_pinctrl_with_sec },
{ .compatible = "st,stm32mp257-pinctrl", .data = (ulong)&stm32_pinctrl_with_sec },
{ .compatible = "st,stm32mp257-z-pinctrl", .data = (ulong)&stm32_pinctrl_with_sec },
{ }
};

7
drivers/reset/stm32/Kconfig
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@ -14,6 +14,13 @@ config RESET_STM32MP1
Support for reset controllers on STMicroelectronics STM32MP1 family SoCs.
This reset driver is compatible with STM32MP13 and STM32MP15 SoCs.
config RESET_STM32MP21
bool "Enable the STM32MP21 reset"
default y if STM32MP21X
help
Support for reset controllers on STMicroelectronics STM32MP21 family SoCs.
This reset driver is compatible with STM32MP21 SoCs.
config RESET_STM32MP25
bool "Enable the STM32MP25 reset"
depends on STM32MP23X || STM32MP25X

1
drivers/reset/stm32/Makefile
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@ -6,4 +6,5 @@ obj-y += stm32-reset-core.o
obj-$(CONFIG_RESET_STM32) += stm32-reset.o
obj-$(CONFIG_RESET_STM32MP1) += stm32-reset-mp1.o
obj-$(CONFIG_RESET_STM32MP21) += stm32-reset-mp21.o
obj-$(CONFIG_RESET_STM32MP25) += stm32-reset-mp25.o

136
drivers/reset/stm32/stm32-reset-mp21.c Normal file
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@ -0,0 +1,136 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
/*
* Copyright (C) 2026, STMicroelectronics - All Rights Reserved
* Author(s): Gabriel Fernandez, <gabriel.fernandez@foss.st.com> for STMicroelectronics.
*/
#include <dm.h>
#include <stm32-reset-core.h>
#include <stm32mp21_rcc.h>
#include <dt-bindings/reset/st,stm32mp21-rcc.h>
/* Reset clear offset for STM32MP RCC */
#define RCC_CLR_OFFSET 0x4
/* Timeout for deassert */
#define STM32_DEASSERT_TIMEOUT_US 10000
#define RESET(id, _offset, _bit_idx, _set_clr) \
[id] = &(struct stm32_reset_cfg){ \
.offset = (_offset), \
.bit_idx = (_bit_idx), \
.set_clr = (_set_clr), \
}
static const struct stm32_reset_cfg *stm32mp21_reset[] = {
RESET(TIM1_R, RCC_TIM1CFGR, 0, 0),
RESET(TIM2_R, RCC_TIM2CFGR, 0, 0),
RESET(TIM3_R, RCC_TIM3CFGR, 0, 0),
RESET(TIM4_R, RCC_TIM4CFGR, 0, 0),
RESET(TIM5_R, RCC_TIM5CFGR, 0, 0),
RESET(TIM6_R, RCC_TIM6CFGR, 0, 0),
RESET(TIM7_R, RCC_TIM7CFGR, 0, 0),
RESET(TIM8_R, RCC_TIM8CFGR, 0, 0),
RESET(TIM10_R, RCC_TIM10CFGR, 0, 0),
RESET(TIM11_R, RCC_TIM11CFGR, 0, 0),
RESET(TIM12_R, RCC_TIM12CFGR, 0, 0),
RESET(TIM13_R, RCC_TIM13CFGR, 0, 0),
RESET(TIM14_R, RCC_TIM14CFGR, 0, 0),
RESET(TIM15_R, RCC_TIM15CFGR, 0, 0),
RESET(TIM16_R, RCC_TIM16CFGR, 0, 0),
RESET(TIM17_R, RCC_TIM17CFGR, 0, 0),
RESET(LPTIM1_R, RCC_LPTIM1CFGR, 0, 0),
RESET(LPTIM2_R, RCC_LPTIM2CFGR, 0, 0),
RESET(LPTIM3_R, RCC_LPTIM3CFGR, 0, 0),
RESET(LPTIM4_R, RCC_LPTIM4CFGR, 0, 0),
RESET(LPTIM5_R, RCC_LPTIM5CFGR, 0, 0),
RESET(SPI1_R, RCC_SPI1CFGR, 0, 0),
RESET(SPI2_R, RCC_SPI2CFGR, 0, 0),
RESET(SPI3_R, RCC_SPI3CFGR, 0, 0),
RESET(SPI4_R, RCC_SPI4CFGR, 0, 0),
RESET(SPI5_R, RCC_SPI5CFGR, 0, 0),
RESET(SPI6_R, RCC_SPI6CFGR, 0, 0),
RESET(SPDIFRX_R, RCC_SPDIFRXCFGR, 0, 0),
RESET(USART1_R, RCC_USART1CFGR, 0, 0),
RESET(USART2_R, RCC_USART2CFGR, 0, 0),
RESET(USART3_R, RCC_USART3CFGR, 0, 0),
RESET(UART4_R, RCC_UART4CFGR, 0, 0),
RESET(UART5_R, RCC_UART5CFGR, 0, 0),
RESET(USART6_R, RCC_USART6CFGR, 0, 0),
RESET(UART7_R, RCC_UART7CFGR, 0, 0),
RESET(LPUART1_R, RCC_LPUART1CFGR, 0, 0),
RESET(I2C1_R, RCC_I2C1CFGR, 0, 0),
RESET(I2C2_R, RCC_I2C2CFGR, 0, 0),
RESET(I2C3_R, RCC_I2C3CFGR, 0, 0),
RESET(SAI1_R, RCC_SAI1CFGR, 0, 0),
RESET(SAI2_R, RCC_SAI2CFGR, 0, 0),
RESET(SAI3_R, RCC_SAI3CFGR, 0, 0),
RESET(SAI4_R, RCC_SAI4CFGR, 0, 0),
RESET(MDF1_R, RCC_MDF1CFGR, 0, 0),
RESET(FDCAN_R, RCC_FDCANCFGR, 0, 0),
RESET(HDP_R, RCC_HDPCFGR, 0, 0),
RESET(ADC1_R, RCC_ADC1CFGR, 0, 0),
RESET(ADC2_R, RCC_ADC2CFGR, 0, 0),
RESET(ETH1_R, RCC_ETH1CFGR, 0, 0),
RESET(ETH2_R, RCC_ETH2CFGR, 0, 0),
RESET(USBH_R, RCC_USBHCFGR, 0, 0),
RESET(USB2PHY1_R, RCC_USB2PHY1CFGR, 0, 0),
RESET(USB2PHY2_R, RCC_USB2PHY2CFGR, 0, 0),
RESET(SDMMC1_R, RCC_SDMMC1CFGR, 0, 0),
RESET(SDMMC1DLL_R, RCC_SDMMC1CFGR, 16, 0),
RESET(SDMMC2_R, RCC_SDMMC2CFGR, 0, 0),
RESET(SDMMC2DLL_R, RCC_SDMMC2CFGR, 16, 0),
RESET(SDMMC3_R, RCC_SDMMC3CFGR, 0, 0),
RESET(SDMMC3DLL_R, RCC_SDMMC3CFGR, 16, 0),
RESET(LTDC_R, RCC_LTDCCFGR, 0, 0),
RESET(CSI_R, RCC_CSICFGR, 0, 0),
RESET(DCMIPP_R, RCC_DCMIPPCFGR, 0, 0),
RESET(DCMIPSSI_R, RCC_DCMIPSSICFGR, 0, 0),
RESET(WWDG1_R, RCC_WWDG1CFGR, 0, 0),
RESET(VREF_R, RCC_VREFCFGR, 0, 0),
RESET(DTS_R, RCC_DTSCFGR, 0, 0),
RESET(CRC_R, RCC_CRCCFGR, 0, 0),
RESET(SERC_R, RCC_SERCCFGR, 0, 0),
RESET(I3C1_R, RCC_I3C1CFGR, 0, 0),
RESET(I3C2_R, RCC_I3C2CFGR, 0, 0),
RESET(IWDG2_KER_R, RCC_IWDGC1CFGSETR, 18, 1),
RESET(IWDG4_KER_R, RCC_IWDGC2CFGSETR, 18, 1),
RESET(RNG1_R, RCC_RNG1CFGR, 0, 0),
RESET(RNG2_R, RCC_RNG2CFGR, 0, 0),
RESET(PKA_R, RCC_PKACFGR, 0, 0),
RESET(SAES_R, RCC_SAESCFGR, 0, 0),
RESET(HASH1_R, RCC_HASH1CFGR, 0, 0),
RESET(HASH2_R, RCC_HASH2CFGR, 0, 0),
RESET(CRYP1_R, RCC_CRYP1CFGR, 0, 0),
RESET(CRYP2_R, RCC_CRYP2CFGR, 0, 0),
RESET(OTG_R, RCC_OTGCFGR, 0, 0),
};
static const struct stm32_reset_cfg *stm32_get_reset_line(struct reset_ctl *reset_ctl)
{
unsigned long id = reset_ctl->id;
if (id < ARRAY_SIZE(stm32mp21_reset))
return stm32mp21_reset[id];
return NULL;
}
static const struct stm32_reset_data stm32mp21_reset_data = {
.get_reset_line = stm32_get_reset_line,
.clear_offset = RCC_CLR_OFFSET,
.reset_us = STM32_DEASSERT_TIMEOUT_US,
};
static int stm32_reset_probe(struct udevice *dev)
{
return stm32_reset_core_probe(dev, &stm32mp21_reset_data);
}
U_BOOT_DRIVER(stm32mp21_rcc_reset) = {
.name = "stm32mp21_reset",
.id = UCLASS_RESET,
.probe = stm32_reset_probe,
.priv_auto = sizeof(struct stm32_reset_priv),
.ops = &stm32_reset_ops,
};

126
include/configs/stm32mp21_common.h Normal file
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@ -0,0 +1,126 @@
/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
/*
* Copyright (C) 2026, STMicroelectronics - All Rights Reserved
*
* Configuration settings for the STM32MP21x CPU
*/
#ifndef __CONFIG_STM32MP21_COMMMON_H
#define __CONFIG_STM32MP21_COMMMON_H
#include <linux/sizes.h>
#include <asm/arch/stm32.h>
/*
* Configuration of the external SRAM memory used by U-Boot
*/
#define CFG_SYS_SDRAM_BASE STM32_DDR_BASE
/*
* For booting Linux, use the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_SYS_BOOTMAPSZ SZ_256M
/*****************************************************************************/
#ifdef CONFIG_DISTRO_DEFAULTS
/*****************************************************************************/
#ifdef CONFIG_NET
#define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
#else
#define BOOT_TARGET_PXE(func)
#endif
#ifdef CONFIG_CMD_MMC
#define BOOT_TARGET_MMC0(func) func(MMC, mmc, 0)
#define BOOT_TARGET_MMC1(func) func(MMC, mmc, 1)
#define BOOT_TARGET_MMC2(func) func(MMC, mmc, 2)
#else
#define BOOT_TARGET_MMC0(func)
#define BOOT_TARGET_MMC1(func)
#define BOOT_TARGET_MMC2(func)
#endif
#ifdef CONFIG_CMD_UBIFS
#define BOOT_TARGET_UBIFS(func) func(UBIFS, ubifs, 0, UBI, boot)
#else
#define BOOT_TARGET_UBIFS(func)
#endif
#ifdef CONFIG_CMD_USB
#define BOOT_TARGET_USB(func) func(USB, usb, 0)
#else
#define BOOT_TARGET_USB(func)
#endif
#define BOOT_TARGET_DEVICES(func) \
BOOT_TARGET_MMC1(func) \
BOOT_TARGET_UBIFS(func) \
BOOT_TARGET_MMC0(func) \
BOOT_TARGET_MMC2(func) \
BOOT_TARGET_USB(func) \
BOOT_TARGET_PXE(func)
/*
* default bootcmd for stm32mp21:
* for serial/usb: execute the stm32prog command
* for mmc boot (eMMC, SD card), distro boot on the same mmc device
* for NAND or SPI-NAND boot, distro boot with UBIFS on UBI partition
* for other boot, use the default distro order in ${boot_targets}
*/
#define STM32MP_BOOTCMD "bootcmd_stm32mp=" \
"echo \"Boot over ${boot_device}${boot_instance}!\";" \
"if test ${boot_device} = serial || test ${boot_device} = usb;" \
"then stm32prog ${boot_device} ${boot_instance}; " \
"else " \
"run env_check;" \
"if test ${boot_device} = mmc;" \
"then env set boot_targets \"mmc${boot_instance}\"; fi;" \
"if test ${boot_device} = nand ||" \
" test ${boot_device} = spi-nand ;" \
"then env set boot_targets ubifs0; fi;" \
"run distro_bootcmd;" \
"fi;\0"
#ifndef STM32MP_BOARD_EXTRA_ENV
#define STM32MP_BOARD_EXTRA_ENV
#endif
#define STM32MP_EXTRA \
"env_check=if env info -p -d -q; then env save; fi\0" \
"boot_net_usb_start=true\0"
/*
* memory layout for 96MB uncompressed/compressed kernel,
* 1M fdt, 1M script, 1M pxe and 1M for overlay
* and the ramdisk at the end.
*/
#define __KERNEL_COMP_ADDR_R __stringify(0x84000000)
#define __KERNEL_COMP_SIZE_R __stringify(0x04000000)
#define __KERNEL_ADDR_R __stringify(0x8a000000)
#define __FDT_ADDR_R __stringify(0x90000000)
#define __SCRIPT_ADDR_R __stringify(0x90100000)
#define __PXEFILE_ADDR_R __stringify(0x90200000)
#define __FDTOVERLAY_ADDR_R __stringify(0x90300000)
#define __RAMDISK_ADDR_R __stringify(0x90400000)
#define STM32MP_MEM_LAYOUT \
"kernel_addr_r=" __KERNEL_ADDR_R "\0" \
"fdt_addr_r=" __FDT_ADDR_R "\0" \
"scriptaddr=" __SCRIPT_ADDR_R "\0" \
"pxefile_addr_r=" __PXEFILE_ADDR_R "\0" \
"fdtoverlay_addr_r=" __FDTOVERLAY_ADDR_R "\0" \
"ramdisk_addr_r=" __RAMDISK_ADDR_R "\0" \
"kernel_comp_addr_r=" __KERNEL_COMP_ADDR_R "\0" \
"kernel_comp_size=" __KERNEL_COMP_SIZE_R "\0"
#include <config_distro_bootcmd.h>
#define CFG_EXTRA_ENV_SETTINGS \
STM32MP_MEM_LAYOUT \
STM32MP_BOOTCMD \
BOOTENV \
STM32MP_EXTRA \
STM32MP_BOARD_EXTRA_ENV
#endif
#endif /* __CONFIG_STM32MP21_COMMMON_H */

51
include/configs/stm32mp21_st_common.h Normal file
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@ -0,0 +1,51 @@
/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
/*
* Copyright (C) 2026, STMicroelectronics - All Rights Reserved
*
* Configuration settings for the STMicroelectonics STM32MP21x boards
*/
#ifndef __CONFIG_STM32MP21_ST_COMMON_H__
#define __CONFIG_STM32MP21_ST_COMMON_H__
#define STM32MP_BOARD_EXTRA_ENV \
"usb_pgood_delay=2000\0" \
"console=ttySTM0\0"
#include <configs/stm32mp21_common.h>
#ifdef CFG_EXTRA_ENV_SETTINGS
/*
* default bootcmd for stm32mp21 STMicroelectronics boards:
* for serial/usb: execute the stm32prog command
* for mmc boot (eMMC, SD card), distro boot on the same mmc device
* for nand or spi-nand boot, distro boot with ubifs on UBI partition or
* sdcard
* for nor boot, distro boot on SD card = mmc0 ONLY !
*/
#define ST_STM32MP21_BOOTCMD "bootcmd_stm32mp=" \
"echo \"Boot over ${boot_device}${boot_instance}!\";" \
"if test ${boot_device} = serial || test ${boot_device} = usb;" \
"then stm32prog ${boot_device} ${boot_instance}; " \
"else " \
"run env_check;" \
"if test ${boot_device} = mmc;" \
"then env set boot_targets \"mmc${boot_instance}\"; fi;" \
"if test ${boot_device} = nand ||" \
" test ${boot_device} = spi-nand ;" \
"then env set boot_targets ubifs0 mmc0; fi;" \
"if test ${boot_device} = nor;" \
"then env set boot_targets mmc0; fi;" \
"run distro_bootcmd;" \
"fi;\0"
#undef CFG_EXTRA_ENV_SETTINGS
#define CFG_EXTRA_ENV_SETTINGS \
STM32MP_MEM_LAYOUT \
ST_STM32MP21_BOOTCMD \
BOOTENV \
STM32MP_EXTRA \
STM32MP_BOARD_EXTRA_ENV
#endif
#endif

651
include/stm32mp21_rcc.h Normal file
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@ -0,0 +1,651 @@
/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
*/
#ifndef STM32MP21_RCC_H
#define STM32MP21_RCC_H
#define RCC_SECCFGR0 0x0
#define RCC_SECCFGR1 0x4
#define RCC_SECCFGR2 0x8
#define RCC_SECCFGR3 0xC
#define RCC_PRIVCFGR0 0x10
#define RCC_PRIVCFGR1 0x14
#define RCC_PRIVCFGR2 0x18
#define RCC_PRIVCFGR3 0x1C
#define RCC_RCFGLOCKR0 0x20
#define RCC_RCFGLOCKR1 0x24
#define RCC_RCFGLOCKR2 0x28
#define RCC_RCFGLOCKR3 0x2C
#define RCC_R0CIDCFGR 0x30
#define RCC_R0SEMCR 0x34
#define RCC_R1CIDCFGR 0x38
#define RCC_R1SEMCR 0x3C
#define RCC_R2CIDCFGR 0x40
#define RCC_R2SEMCR 0x44
#define RCC_R3CIDCFGR 0x48
#define RCC_R3SEMCR 0x4C
#define RCC_R4CIDCFGR 0x50
#define RCC_R4SEMCR 0x54
#define RCC_R5CIDCFGR 0x58
#define RCC_R5SEMCR 0x5C
#define RCC_R6CIDCFGR 0x60
#define RCC_R6SEMCR 0x64
#define RCC_R7CIDCFGR 0x68
#define RCC_R7SEMCR 0x6C
#define RCC_R8CIDCFGR 0x70
#define RCC_R8SEMCR 0x74
#define RCC_R9CIDCFGR 0x78
#define RCC_R9SEMCR 0x7C
#define RCC_R10CIDCFGR 0x80
#define RCC_R10SEMCR 0x84
#define RCC_R11CIDCFGR 0x88
#define RCC_R11SEMCR 0x8C
#define RCC_R12CIDCFGR 0x90
#define RCC_R12SEMCR 0x94
#define RCC_R13CIDCFGR 0x98
#define RCC_R13SEMCR 0x9C
#define RCC_R14CIDCFGR 0xA0
#define RCC_R14SEMCR 0xA4
#define RCC_R15CIDCFGR 0xA8
#define RCC_R15SEMCR 0xAC
#define RCC_R16CIDCFGR 0xB0
#define RCC_R16SEMCR 0xB4
#define RCC_R17CIDCFGR 0xB8
#define RCC_R17SEMCR 0xBC
#define RCC_R18CIDCFGR 0xC0
#define RCC_R18SEMCR 0xC4
#define RCC_R19CIDCFGR 0xC8
#define RCC_R19SEMCR 0xCC
#define RCC_R20CIDCFGR 0xD0
#define RCC_R20SEMCR 0xD4
#define RCC_R21CIDCFGR 0xD8
#define RCC_R21SEMCR 0xDC
#define RCC_R22CIDCFGR 0xE0
#define RCC_R22SEMCR 0xE4
#define RCC_R23CIDCFGR 0xE8
#define RCC_R23SEMCR 0xEC
#define RCC_R24CIDCFGR 0xF0
#define RCC_R24SEMCR 0xF4
#define RCC_R25CIDCFGR 0xF8
#define RCC_R25SEMCR 0xFC
#define RCC_R26CIDCFGR 0x100
#define RCC_R26SEMCR 0x104
#define RCC_R27CIDCFGR 0x108
#define RCC_R27SEMCR 0x10C
#define RCC_R28CIDCFGR 0x110
#define RCC_R28SEMCR 0x114
#define RCC_R29CIDCFGR 0x118
#define RCC_R29SEMCR 0x11C
#define RCC_R30CIDCFGR 0x120
#define RCC_R30SEMCR 0x124
#define RCC_R31CIDCFGR 0x128
#define RCC_R31SEMCR 0x12C
#define RCC_R32CIDCFGR 0x130
#define RCC_R32SEMCR 0x134
#define RCC_R33CIDCFGR 0x138
#define RCC_R33SEMCR 0x13C
#define RCC_R34CIDCFGR 0x140
#define RCC_R34SEMCR 0x144
#define RCC_R35CIDCFGR 0x148
#define RCC_R35SEMCR 0x14C
#define RCC_R36CIDCFGR 0x150
#define RCC_R36SEMCR 0x154
#define RCC_R37CIDCFGR 0x158
#define RCC_R37SEMCR 0x15C
#define RCC_R38CIDCFGR 0x160
#define RCC_R38SEMCR 0x164
#define RCC_R39CIDCFGR 0x168
#define RCC_R39SEMCR 0x16C
#define RCC_R40CIDCFGR 0x170
#define RCC_R40SEMCR 0x174
#define RCC_R41CIDCFGR 0x178
#define RCC_R41SEMCR 0x17C
#define RCC_R42CIDCFGR 0x180
#define RCC_R42SEMCR 0x184
#define RCC_R43CIDCFGR 0x188
#define RCC_R43SEMCR 0x18C
#define RCC_R44CIDCFGR 0x190
#define RCC_R44SEMCR 0x194
#define RCC_R45CIDCFGR 0x198
#define RCC_R45SEMCR 0x19C
#define RCC_R46CIDCFGR 0x1A0
#define RCC_R46SEMCR 0x1A4
#define RCC_R47CIDCFGR 0x1A8
#define RCC_R47SEMCR 0x1AC
#define RCC_R48CIDCFGR 0x1B0
#define RCC_R48SEMCR 0x1B4
#define RCC_R49CIDCFGR 0x1B8
#define RCC_R49SEMCR 0x1BC
#define RCC_R50CIDCFGR 0x1C0
#define RCC_R50SEMCR 0x1C4
#define RCC_R51CIDCFGR 0x1C8
#define RCC_R51SEMCR 0x1CC
#define RCC_R52CIDCFGR 0x1D0
#define RCC_R52SEMCR 0x1D4
#define RCC_R53CIDCFGR 0x1D8
#define RCC_R53SEMCR 0x1DC
#define RCC_R54CIDCFGR 0x1E0
#define RCC_R54SEMCR 0x1E4
#define RCC_R55CIDCFGR 0x1E8
#define RCC_R55SEMCR 0x1EC
#define RCC_R56CIDCFGR 0x1F0
#define RCC_R56SEMCR 0x1F4
#define RCC_R57CIDCFGR 0x1F8
#define RCC_R57SEMCR 0x1FC
#define RCC_R58CIDCFGR 0x200
#define RCC_R58SEMCR 0x204
#define RCC_R59CIDCFGR 0x208
#define RCC_R59SEMCR 0x20C
#define RCC_R60CIDCFGR 0x210
#define RCC_R60SEMCR 0x214
#define RCC_R61CIDCFGR 0x218
#define RCC_R61SEMCR 0x21C
#define RCC_R62CIDCFGR 0x220
#define RCC_R62SEMCR 0x224
#define RCC_R63CIDCFGR 0x228
#define RCC_R63SEMCR 0x22C
#define RCC_R64CIDCFGR 0x230
#define RCC_R64SEMCR 0x234
#define RCC_R65CIDCFGR 0x238
#define RCC_R65SEMCR 0x23C
#define RCC_R66CIDCFGR 0x240
#define RCC_R66SEMCR 0x244
#define RCC_R67CIDCFGR 0x248
#define RCC_R67SEMCR 0x24C
#define RCC_R68CIDCFGR 0x250
#define RCC_R68SEMCR 0x254
#define RCC_R69CIDCFGR 0x258
#define RCC_R69SEMCR 0x25C
#define RCC_R70CIDCFGR 0x260
#define RCC_R70SEMCR 0x264
#define RCC_R71CIDCFGR 0x268
#define RCC_R71SEMCR 0x26C
#define RCC_R73CIDCFGR 0x278
#define RCC_R73SEMCR 0x27C
#define RCC_R74CIDCFGR 0x280
#define RCC_R74SEMCR 0x284
#define RCC_R75CIDCFGR 0x288
#define RCC_R75SEMCR 0x28C
#define RCC_R76CIDCFGR 0x290
#define RCC_R76SEMCR 0x294
#define RCC_R77CIDCFGR 0x298
#define RCC_R77SEMCR 0x29C
#define RCC_R78CIDCFGR 0x2A0
#define RCC_R78SEMCR 0x2A4
#define RCC_R79CIDCFGR 0x2A8
#define RCC_R79SEMCR 0x2AC
#define RCC_R83CIDCFGR 0x2C8
#define RCC_R83SEMCR 0x2CC
#define RCC_R84CIDCFGR 0x2D0
#define RCC_R84SEMCR 0x2D4
#define RCC_R85CIDCFGR 0x2D8
#define RCC_R85SEMCR 0x2DC
#define RCC_R86CIDCFGR 0x2E0
#define RCC_R86SEMCR 0x2E4
#define RCC_R87CIDCFGR 0x2E8
#define RCC_R87SEMCR 0x2EC
#define RCC_R88CIDCFGR 0x2F0
#define RCC_R88SEMCR 0x2F4
#define RCC_R90CIDCFGR 0x300
#define RCC_R90SEMCR 0x304
#define RCC_R91CIDCFGR 0x308
#define RCC_R91SEMCR 0x30C
#define RCC_R92CIDCFGR 0x310
#define RCC_R92SEMCR 0x314
#define RCC_R93CIDCFGR 0x318
#define RCC_R93SEMCR 0x31C
#define RCC_R94CIDCFGR 0x320
#define RCC_R94SEMCR 0x324
#define RCC_R95CIDCFGR 0x328
#define RCC_R95SEMCR 0x32C
#define RCC_R96CIDCFGR 0x330
#define RCC_R96SEMCR 0x334
#define RCC_R97CIDCFGR 0x338
#define RCC_R97SEMCR 0x33C
#define RCC_R98CIDCFGR 0x340
#define RCC_R98SEMCR 0x344
#define RCC_R101CIDCFGR 0x358
#define RCC_R101SEMCR 0x35C
#define RCC_R102CIDCFGR 0x360
#define RCC_R102SEMCR 0x364
#define RCC_R103CIDCFGR 0x368
#define RCC_R103SEMCR 0x36C
#define RCC_R104CIDCFGR 0x370
#define RCC_R104SEMCR 0x374
#define RCC_R105CIDCFGR 0x378
#define RCC_R105SEMCR 0x37C
#define RCC_R106CIDCFGR 0x380
#define RCC_R106SEMCR 0x384
#define RCC_R108CIDCFGR 0x390
#define RCC_R108SEMCR 0x394
#define RCC_R109CIDCFGR 0x398
#define RCC_R109SEMCR 0x39C
#define RCC_R110CIDCFGR 0x3A0
#define RCC_R110SEMCR 0x3A4
#define RCC_R111CIDCFGR 0x3A8
#define RCC_R111SEMCR 0x3AC
#define RCC_R112CIDCFGR 0x3B0
#define RCC_R112SEMCR 0x3B4
#define RCC_R113CIDCFGR 0x3B8
#define RCC_R113SEMCR 0x3BC
#define RCC_GRSTCSETR 0x400
#define RCC_C1RSTCSETR 0x404
#define RCC_C2RSTCSETR 0x40C
#define RCC_HWRSTSCLRR 0x410
#define RCC_C1HWRSTSCLRR 0x414
#define RCC_C2HWRSTSCLRR 0x418
#define RCC_C1BOOTRSTSSETR 0x41C
#define RCC_C1BOOTRSTSCLRR 0x420
#define RCC_C2BOOTRSTSSETR 0x424
#define RCC_C2BOOTRSTSCLRR 0x428
#define RCC_C1SREQSETR 0x42C
#define RCC_C1SREQCLRR 0x430
#define RCC_CPUBOOTCR 0x434
#define RCC_STBYBOOTCR 0x438
#define RCC_LEGBOOTCR 0x43C
#define RCC_BDCR 0x440
#define RCC_RDCR 0x44C
#define RCC_C1MSRDCR 0x450
#define RCC_PWRLPDLYCR 0x454
#define RCC_C1CIESETR 0x458
#define RCC_C1CIFCLRR 0x45C
#define RCC_C2CIESETR 0x460
#define RCC_C2CIFCLRR 0x464
#define RCC_IWDGC1FZSETR 0x468
#define RCC_IWDGC1FZCLRR 0x46C
#define RCC_IWDGC1CFGSETR 0x470
#define RCC_IWDGC1CFGCLRR 0x474
#define RCC_IWDGC2FZSETR 0x478
#define RCC_IWDGC2FZCLRR 0x47C
#define RCC_IWDGC2CFGSETR 0x480
#define RCC_IWDGC2CFGCLRR 0x484
#define RCC_MCO1CFGR 0x488
#define RCC_MCO2CFGR 0x48C
#define RCC_OCENSETR 0x490
#define RCC_OCENCLRR 0x494
#define RCC_OCRDYR 0x498
#define RCC_HSICFGR 0x49C
#define RCC_MSICFGR 0x4A0
#define RCC_LSICR 0x4A4
#define RCC_RTCDIVR 0x4A8
#define RCC_APB1DIVR 0x4AC
#define RCC_APB2DIVR 0x4B0
#define RCC_APB3DIVR 0x4B4
#define RCC_APB4DIVR 0x4B8
#define RCC_APB5DIVR 0x4BC
#define RCC_APBDBGDIVR 0x4C0
#define RCC_TIMG1PRER 0x4C8
#define RCC_TIMG2PRER 0x4CC
#define RCC_LSMCUDIVR 0x4D0
#define RCC_DDRCPCFGR 0x4D4
#define RCC_DDRCAPBCFGR 0x4D8
#define RCC_DDRPHYCAPBCFGR 0x4DC
#define RCC_DDRPHYCCFGR 0x4E0
#define RCC_DDRCFGR 0x4E4
#define RCC_DDRITFCFGR 0x4E8
#define RCC_SYSRAMCFGR 0x4F0
#define RCC_SRAM1CFGR 0x4F8
#define RCC_RETRAMCFGR 0x500
#define RCC_BKPSRAMCFGR 0x504
#define RCC_OSPI1CFGR 0x514
#define RCC_FMCCFGR 0x51C
#define RCC_DBGCFGR 0x520
#define RCC_STMCFGR 0x524
#define RCC_ETRCFGR 0x528
#define RCC_GPIOACFGR 0x52C
#define RCC_GPIOBCFGR 0x530
#define RCC_GPIOCCFGR 0x534
#define RCC_GPIODCFGR 0x538
#define RCC_GPIOECFGR 0x53C
#define RCC_GPIOFCFGR 0x540
#define RCC_GPIOGCFGR 0x544
#define RCC_GPIOHCFGR 0x548
#define RCC_GPIOICFGR 0x54C
#define RCC_GPIOZCFGR 0x558
#define RCC_HPDMA1CFGR 0x55C
#define RCC_HPDMA2CFGR 0x560
#define RCC_HPDMA3CFGR 0x564
#define RCC_IPCC1CFGR 0x570
#define RCC_RTCCFGR 0x578
#define RCC_SYSCPU1CFGR 0x580
#define RCC_BSECCFGR 0x584
#define RCC_PLL2CFGR1 0x590
#define RCC_PLL2CFGR2 0x594
#define RCC_PLL2CFGR3 0x598
#define RCC_PLL2CFGR4 0x59C
#define RCC_PLL2CFGR5 0x5A0
#define RCC_PLL2CFGR6 0x5A8
#define RCC_PLL2CFGR7 0x5AC
#define RCC_HSIFMONCR 0x5E0
#define RCC_HSIFVALR 0x5E4
#define RCC_MSIFMONCR 0x5E8
#define RCC_MSIFVALR 0x5EC
#define RCC_TIM1CFGR 0x700
#define RCC_TIM2CFGR 0x704
#define RCC_TIM3CFGR 0x708
#define RCC_TIM4CFGR 0x70C
#define RCC_TIM5CFGR 0x710
#define RCC_TIM6CFGR 0x714
#define RCC_TIM7CFGR 0x718
#define RCC_TIM8CFGR 0x71C
#define RCC_TIM10CFGR 0x720
#define RCC_TIM11CFGR 0x724
#define RCC_TIM12CFGR 0x728
#define RCC_TIM13CFGR 0x72C
#define RCC_TIM14CFGR 0x730
#define RCC_TIM15CFGR 0x734
#define RCC_TIM16CFGR 0x738
#define RCC_TIM17CFGR 0x73C
#define RCC_LPTIM1CFGR 0x744
#define RCC_LPTIM2CFGR 0x748
#define RCC_LPTIM3CFGR 0x74C
#define RCC_LPTIM4CFGR 0x750
#define RCC_LPTIM5CFGR 0x754
#define RCC_SPI1CFGR 0x758
#define RCC_SPI2CFGR 0x75C
#define RCC_SPI3CFGR 0x760
#define RCC_SPI4CFGR 0x764
#define RCC_SPI5CFGR 0x768
#define RCC_SPI6CFGR 0x76C
#define RCC_SPDIFRXCFGR 0x778
#define RCC_USART1CFGR 0x77C
#define RCC_USART2CFGR 0x780
#define RCC_USART3CFGR 0x784
#define RCC_UART4CFGR 0x788
#define RCC_UART5CFGR 0x78C
#define RCC_USART6CFGR 0x790
#define RCC_UART7CFGR 0x794
#define RCC_LPUART1CFGR 0x7A0
#define RCC_I2C1CFGR 0x7A4
#define RCC_I2C2CFGR 0x7A8
#define RCC_I2C3CFGR 0x7AC
#define RCC_SAI1CFGR 0x7C4
#define RCC_SAI2CFGR 0x7C8
#define RCC_SAI3CFGR 0x7CC
#define RCC_SAI4CFGR 0x7D0
#define RCC_MDF1CFGR 0x7D8
#define RCC_FDCANCFGR 0x7E0
#define RCC_HDPCFGR 0x7E4
#define RCC_ADC1CFGR 0x7E8
#define RCC_ADC2CFGR 0x7EC
#define RCC_ETH1CFGR 0x7F0
#define RCC_ETH2CFGR 0x7F4
#define RCC_USBHCFGR 0x7FC
#define RCC_USB2PHY1CFGR 0x800
#define RCC_OTGCFGR 0x808
#define RCC_USB2PHY2CFGR 0x80C
#define RCC_STGENCFGR 0x824
#define RCC_SDMMC1CFGR 0x830
#define RCC_SDMMC2CFGR 0x834
#define RCC_SDMMC3CFGR 0x838
#define RCC_LTDCCFGR 0x840
#define RCC_CSICFGR 0x858
#define RCC_DCMIPPCFGR 0x85C
#define RCC_DCMIPSSICFGR 0x860
#define RCC_RNG1CFGR 0x870
#define RCC_RNG2CFGR 0x874
#define RCC_PKACFGR 0x878
#define RCC_SAESCFGR 0x87C
#define RCC_HASH1CFGR 0x880
#define RCC_HASH2CFGR 0x884
#define RCC_CRYP1CFGR 0x888
#define RCC_CRYP2CFGR 0x88C
#define RCC_IWDG1CFGR 0x894
#define RCC_IWDG2CFGR 0x898
#define RCC_IWDG3CFGR 0x89C
#define RCC_IWDG4CFGR 0x8A0
#define RCC_WWDG1CFGR 0x8A4
#define RCC_VREFCFGR 0x8AC
#define RCC_DTSCFGR 0x8B0
#define RCC_CRCCFGR 0x8B4
#define RCC_SERCCFGR 0x8B8
#define RCC_DDRPERFMCFGR 0x8C0
#define RCC_I3C1CFGR 0x8C8
#define RCC_I3C2CFGR 0x8CC
#define RCC_I3C3CFGR 0x8D0
#define RCC_MUXSELCFGR 0x1000
#define RCC_XBAR0CFGR 0x1018
#define RCC_XBAR1CFGR 0x101C
#define RCC_XBAR2CFGR 0x1020
#define RCC_XBAR3CFGR 0x1024
#define RCC_XBAR4CFGR 0x1028
#define RCC_XBAR5CFGR 0x102C
#define RCC_XBAR6CFGR 0x1030
#define RCC_XBAR7CFGR 0x1034
#define RCC_XBAR8CFGR 0x1038
#define RCC_XBAR9CFGR 0x103C
#define RCC_XBAR10CFGR 0x1040
#define RCC_XBAR11CFGR 0x1044
#define RCC_XBAR12CFGR 0x1048
#define RCC_XBAR13CFGR 0x104C
#define RCC_XBAR14CFGR 0x1050
#define RCC_XBAR15CFGR 0x1054
#define RCC_XBAR16CFGR 0x1058
#define RCC_XBAR17CFGR 0x105C
#define RCC_XBAR18CFGR 0x1060
#define RCC_XBAR19CFGR 0x1064
#define RCC_XBAR20CFGR 0x1068
#define RCC_XBAR21CFGR 0x106C
#define RCC_XBAR22CFGR 0x1070
#define RCC_XBAR23CFGR 0x1074
#define RCC_XBAR24CFGR 0x1078
#define RCC_XBAR25CFGR 0x107C
#define RCC_XBAR26CFGR 0x1080
#define RCC_XBAR27CFGR 0x1084
#define RCC_XBAR28CFGR 0x1088
#define RCC_XBAR29CFGR 0x108C
#define RCC_XBAR30CFGR 0x1090
#define RCC_XBAR31CFGR 0x1094
#define RCC_XBAR32CFGR 0x1098
#define RCC_XBAR33CFGR 0x109C
#define RCC_XBAR34CFGR 0x10A0
#define RCC_XBAR35CFGR 0x10A4
#define RCC_XBAR36CFGR 0x10A8
#define RCC_XBAR37CFGR 0x10AC
#define RCC_XBAR38CFGR 0x10B0
#define RCC_XBAR39CFGR 0x10B4
#define RCC_XBAR40CFGR 0x10B8
#define RCC_XBAR41CFGR 0x10BC
#define RCC_XBAR42CFGR 0x10C0
#define RCC_XBAR43CFGR 0x10C4
#define RCC_XBAR44CFGR 0x10C8
#define RCC_XBAR45CFGR 0x10CC
#define RCC_XBAR46CFGR 0x10D0
#define RCC_XBAR47CFGR 0x10D4
#define RCC_XBAR48CFGR 0x10D8
#define RCC_XBAR49CFGR 0x10DC
#define RCC_XBAR50CFGR 0x10E0
#define RCC_XBAR51CFGR 0x10E4
#define RCC_XBAR52CFGR 0x10E8
#define RCC_XBAR53CFGR 0x10EC
#define RCC_XBAR54CFGR 0x10F0
#define RCC_XBAR55CFGR 0x10F4
#define RCC_XBAR56CFGR 0x10F8
#define RCC_XBAR57CFGR 0x10FC
#define RCC_XBAR58CFGR 0x1100
#define RCC_XBAR59CFGR 0x1104
#define RCC_XBAR60CFGR 0x1108
#define RCC_XBAR61CFGR 0x110C
#define RCC_XBAR62CFGR 0x1110
#define RCC_XBAR63CFGR 0x1114
#define RCC_PREDIV0CFGR 0x1118
#define RCC_PREDIV1CFGR 0x111C
#define RCC_PREDIV2CFGR 0x1120
#define RCC_PREDIV3CFGR 0x1124
#define RCC_PREDIV4CFGR 0x1128
#define RCC_PREDIV5CFGR 0x112C
#define RCC_PREDIV6CFGR 0x1130
#define RCC_PREDIV7CFGR 0x1134
#define RCC_PREDIV8CFGR 0x1138
#define RCC_PREDIV9CFGR 0x113C
#define RCC_PREDIV10CFGR 0x1140
#define RCC_PREDIV11CFGR 0x1144
#define RCC_PREDIV12CFGR 0x1148
#define RCC_PREDIV13CFGR 0x114C
#define RCC_PREDIV14CFGR 0x1150
#define RCC_PREDIV15CFGR 0x1154
#define RCC_PREDIV16CFGR 0x1158
#define RCC_PREDIV17CFGR 0x115C
#define RCC_PREDIV18CFGR 0x1160
#define RCC_PREDIV19CFGR 0x1164
#define RCC_PREDIV20CFGR 0x1168
#define RCC_PREDIV21CFGR 0x116C
#define RCC_PREDIV22CFGR 0x1170
#define RCC_PREDIV23CFGR 0x1174
#define RCC_PREDIV24CFGR 0x1178
#define RCC_PREDIV25CFGR 0x117C
#define RCC_PREDIV26CFGR 0x1180
#define RCC_PREDIV27CFGR 0x1184
#define RCC_PREDIV28CFGR 0x1188
#define RCC_PREDIV29CFGR 0x118C
#define RCC_PREDIV30CFGR 0x1190
#define RCC_PREDIV31CFGR 0x1194
#define RCC_PREDIV32CFGR 0x1198
#define RCC_PREDIV33CFGR 0x119C
#define RCC_PREDIV34CFGR 0x11A0
#define RCC_PREDIV35CFGR 0x11A4
#define RCC_PREDIV36CFGR 0x11A8
#define RCC_PREDIV37CFGR 0x11AC
#define RCC_PREDIV38CFGR 0x11B0
#define RCC_PREDIV39CFGR 0x11B4
#define RCC_PREDIV40CFGR 0x11B8
#define RCC_PREDIV41CFGR 0x11BC
#define RCC_PREDIV42CFGR 0x11C0
#define RCC_PREDIV43CFGR 0x11C4
#define RCC_PREDIV44CFGR 0x11C8
#define RCC_PREDIV45CFGR 0x11CC
#define RCC_PREDIV46CFGR 0x11D0
#define RCC_PREDIV47CFGR 0x11D4
#define RCC_PREDIV48CFGR 0x11D8
#define RCC_PREDIV49CFGR 0x11DC
#define RCC_PREDIV50CFGR 0x11E0
#define RCC_PREDIV51CFGR 0x11E4
#define RCC_PREDIV52CFGR 0x11E8
#define RCC_PREDIV53CFGR 0x11EC
#define RCC_PREDIV54CFGR 0x11F0
#define RCC_PREDIV55CFGR 0x11F4
#define RCC_PREDIV56CFGR 0x11F8
#define RCC_PREDIV57CFGR 0x11FC
#define RCC_PREDIV58CFGR 0x1200
#define RCC_PREDIV59CFGR 0x1204
#define RCC_PREDIV60CFGR 0x1208
#define RCC_PREDIV61CFGR 0x120C
#define RCC_PREDIV62CFGR 0x1210
#define RCC_PREDIV63CFGR 0x1214
#define RCC_PREDIVSR1 0x1218
#define RCC_PREDIVSR2 0x121C
#define RCC_FINDIV0CFGR 0x1224
#define RCC_FINDIV1CFGR 0x1228
#define RCC_FINDIV2CFGR 0x122C
#define RCC_FINDIV3CFGR 0x1230
#define RCC_FINDIV4CFGR 0x1234
#define RCC_FINDIV5CFGR 0x1238
#define RCC_FINDIV6CFGR 0x123C
#define RCC_FINDIV7CFGR 0x1240
#define RCC_FINDIV8CFGR 0x1244
#define RCC_FINDIV9CFGR 0x1248
#define RCC_FINDIV10CFGR 0x124C
#define RCC_FINDIV11CFGR 0x1250
#define RCC_FINDIV12CFGR 0x1254
#define RCC_FINDIV13CFGR 0x1258
#define RCC_FINDIV14CFGR 0x125C
#define RCC_FINDIV15CFGR 0x1260
#define RCC_FINDIV16CFGR 0x1264
#define RCC_FINDIV17CFGR 0x1268
#define RCC_FINDIV18CFGR 0x126C
#define RCC_FINDIV19CFGR 0x1270
#define RCC_FINDIV20CFGR 0x1274
#define RCC_FINDIV21CFGR 0x1278
#define RCC_FINDIV22CFGR 0x127C
#define RCC_FINDIV23CFGR 0x1280
#define RCC_FINDIV24CFGR 0x1284
#define RCC_FINDIV25CFGR 0x1288
#define RCC_FINDIV26CFGR 0x128C
#define RCC_FINDIV27CFGR 0x1290
#define RCC_FINDIV28CFGR 0x1294
#define RCC_FINDIV29CFGR 0x1298
#define RCC_FINDIV30CFGR 0x129C
#define RCC_FINDIV31CFGR 0x12A0
#define RCC_FINDIV32CFGR 0x12A4
#define RCC_FINDIV33CFGR 0x12A8
#define RCC_FINDIV34CFGR 0x12AC
#define RCC_FINDIV35CFGR 0x12B0
#define RCC_FINDIV36CFGR 0x12B4
#define RCC_FINDIV37CFGR 0x12B8
#define RCC_FINDIV38CFGR 0x12BC
#define RCC_FINDIV39CFGR 0x12C0
#define RCC_FINDIV40CFGR 0x12C4
#define RCC_FINDIV41CFGR 0x12C8
#define RCC_FINDIV42CFGR 0x12CC
#define RCC_FINDIV43CFGR 0x12D0
#define RCC_FINDIV44CFGR 0x12D4
#define RCC_FINDIV45CFGR 0x12D8
#define RCC_FINDIV46CFGR 0x12DC
#define RCC_FINDIV47CFGR 0x12E0
#define RCC_FINDIV48CFGR 0x12E4
#define RCC_FINDIV49CFGR 0x12E8
#define RCC_FINDIV50CFGR 0x12EC
#define RCC_FINDIV51CFGR 0x12F0
#define RCC_FINDIV52CFGR 0x12F4
#define RCC_FINDIV53CFGR 0x12F8
#define RCC_FINDIV54CFGR 0x12FC
#define RCC_FINDIV55CFGR 0x1300
#define RCC_FINDIV56CFGR 0x1304
#define RCC_FINDIV57CFGR 0x1308
#define RCC_FINDIV58CFGR 0x130C
#define RCC_FINDIV59CFGR 0x1310
#define RCC_FINDIV60CFGR 0x1314
#define RCC_FINDIV61CFGR 0x1318
#define RCC_FINDIV62CFGR 0x131C
#define RCC_FINDIV63CFGR 0x1320
#define RCC_FINDIVSR1 0x1324
#define RCC_FINDIVSR2 0x1328
#define RCC_FCALCOBS0CFGR 0x1340
#define RCC_FCALCOBS1CFGR 0x1344
#define RCC_FCALCREFCFGR 0x1348
#define RCC_FCALCCR1 0x134C
#define RCC_FCALCCR2 0x1354
#define RCC_FCALCSR 0x1358
#define RCC_PLL4CFGR1 0x1360
#define RCC_PLL4CFGR2 0x1364
#define RCC_PLL4CFGR3 0x1368
#define RCC_PLL4CFGR4 0x136C
#define RCC_PLL4CFGR5 0x1370
#define RCC_PLL4CFGR6 0x1378
#define RCC_PLL4CFGR7 0x137C
#define RCC_PLL5CFGR1 0x1388
#define RCC_PLL5CFGR2 0x138C
#define RCC_PLL5CFGR3 0x1390
#define RCC_PLL5CFGR4 0x1394
#define RCC_PLL5CFGR5 0x1398
#define RCC_PLL5CFGR6 0x13A0
#define RCC_PLL5CFGR7 0x13A4
#define RCC_PLL6CFGR1 0x13B0
#define RCC_PLL6CFGR2 0x13B4
#define RCC_PLL6CFGR3 0x13B8
#define RCC_PLL6CFGR4 0x13BC
#define RCC_PLL6CFGR5 0x13C0
#define RCC_PLL6CFGR6 0x13C8
#define RCC_PLL6CFGR7 0x13CC
#define RCC_PLL7CFGR1 0x13D8
#define RCC_PLL7CFGR2 0x13DC
#define RCC_PLL7CFGR3 0x13E0
#define RCC_PLL7CFGR4 0x13E4
#define RCC_PLL7CFGR5 0x13E8
#define RCC_PLL7CFGR6 0x13F0
#define RCC_PLL7CFGR7 0x13F4
#define RCC_PLL8CFGR1 0x1400
#define RCC_PLL8CFGR2 0x1404
#define RCC_PLL8CFGR3 0x1408
#define RCC_PLL8CFGR4 0x140C
#define RCC_PLL8CFGR5 0x1410
#define RCC_PLL8CFGR6 0x1418
#define RCC_PLL8CFGR7 0x141C
#define RCC_VERR 0xFFF4
#define RCC_IDR 0xFFF8
#define RCC_SIDR 0xFFFC
#endif /* STM32MP21_RCC_H */