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Blackfin: support boards with no external memory
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
dbda2c65e5
commit
7527feef06
@ -538,10 +538,18 @@ program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
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* self-refresh. So we have to pull it out before programming.
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*/
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#ifdef EBIU_RSTCTL
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# ifdef CONFIG_EBIU_RSTCTL_VAL
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bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
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# endif
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# ifdef CONFIG_EBIU_DDRCTL0_VAL
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bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
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# endif
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# ifdef CONFIG_EBIU_DDRCTL1_VAL
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bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
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# endif
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# ifdef CONFIG_EBIU_DDRCTL2_VAL
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bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
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# endif
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# ifdef CONFIG_EBIU_DDRCTL3_VAL
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/* default is disable, so don't need to force this */
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bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
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@ -611,11 +619,17 @@ program_async_controller(ADI_BOOT_DATA *bs)
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serial_putc('b');
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#ifdef EBIU_MODE
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/* Not all parts have these additional MMRs. */
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#ifdef EBIU_MODE
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# ifdef CONFIG_EBIU_MBSCTL_VAL
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bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
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# endif
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# ifdef CONFIG_EBIU_MODE_VAL
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bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
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# endif
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# ifdef CONFIG_EBIU_FCTL_VAL
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bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
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# endif
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#endif
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serial_putc('c');
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@ -95,6 +95,7 @@ ENTRY(_start)
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/* Save RETX so we can pass it while booting Linux */
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r7 = RETX;
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#if CONFIG_MEM_SIZE
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/* Figure out where we are currently executing so that we can decide
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* how to best reprogram and relocate things. We'll pass below:
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* R4: load address of _start
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@ -131,6 +132,9 @@ ENTRY(_start)
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r3.h = 0x2000;
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cc = r5 < r3 (iu);
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if cc jump .Ldma_and_reprogram;
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#else
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r6 = 1 (x); /* fake loaded_from_ldr = 1 */
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#endif
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r0 = 0 (x); /* set bootstruct to NULL */
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call _initcode;
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jump .Lprogrammed;
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@ -154,6 +158,7 @@ ENTRY(_start)
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.Lprogrammed:
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serial_early_set_baud
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#if CONFIG_MEM_SIZE
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/* Relocate from wherever we are (FLASH/RAM/etc...) to the hardcoded
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* monitor location in the end of RAM. We know that memcpy() only
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* uses registers, so it is safe to call here. Note that this only
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@ -166,6 +171,7 @@ ENTRY(_start)
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r2.l = LO(CONFIG_SYS_MONITOR_LEN);
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r2.h = HI(CONFIG_SYS_MONITOR_LEN);
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call _memcpy_ASM;
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#endif
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/* Initialize BSS section ... we know that memset() does not
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* use the BSS, so it is safe to call here. The bootrom LDR
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@ -92,7 +92,11 @@
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# define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024)
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#endif
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#ifndef CONFIG_SYS_MONITOR_BASE
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# if CONFIG_SYS_MAX_RAM_SIZE
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# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
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# else
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# define CONFIG_SYS_MONITOR_BASE 0
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# endif
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#endif
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#ifndef CONFIG_SYS_MALLOC_BASE
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# define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
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@ -114,7 +118,8 @@
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#endif
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/* Check to make sure everything fits in external RAM */
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#if ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE)
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#if CONFIG_SYS_MAX_RAM_SIZE && \
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((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE)
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# error Memory Map does not fit into configuration
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#endif
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@ -130,18 +130,27 @@ void init_cplbtables(void)
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dcplb_add(0xFF800000, L1_DMEMORY);
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++i;
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icplb_add(CONFIG_SYS_MONITOR_BASE & CPLB_PAGE_MASK, SDRAM_IKERNEL);
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dcplb_add(CONFIG_SYS_MONITOR_BASE & CPLB_PAGE_MASK, SDRAM_DKERNEL);
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if (CONFIG_MEM_SIZE) {
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uint32_t mbase = CONFIG_SYS_MONITOR_BASE;
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uint32_t mend = mbase + CONFIG_SYS_MONITOR_LEN;
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mbase &= CPLB_PAGE_MASK;
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mend &= CPLB_PAGE_MASK;
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icplb_add(mbase, SDRAM_IKERNEL);
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dcplb_add(mbase, SDRAM_DKERNEL);
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++i;
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/* If the monitor crosses a 4 meg boundary, we'll need
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* to lock two entries for it.
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/*
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* If the monitor crosses a 4 meg boundary, we'll need
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* to lock two entries for it. We assume it doesn't
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* cross two 4 meg boundaries ...
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*/
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if ((CONFIG_SYS_MONITOR_BASE & CPLB_PAGE_MASK) != ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) & CPLB_PAGE_MASK)) {
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icplb_add((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) & CPLB_PAGE_MASK, SDRAM_IKERNEL);
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dcplb_add((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) & CPLB_PAGE_MASK, SDRAM_DKERNEL);
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if (mbase != mend) {
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icplb_add(mend, SDRAM_IKERNEL);
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dcplb_add(mend, SDRAM_DKERNEL);
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++i;
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}
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}
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icplb_add(0x20000000, SDRAM_INON_CHBL);
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dcplb_add(0x20000000, SDRAM_EBIU);
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@ -57,7 +57,14 @@ OUTPUT_ARCH(bfin)
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MEMORY
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{
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#if CONFIG_MEM_SIZE
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ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
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# define ram_code ram
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# define ram_data ram
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#else
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# define ram_code l1_code
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# define ram_data l1_data
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#endif
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l1_code : ORIGIN = L1_CODE_ORIGIN, LENGTH = L1_INST_SRAM_SIZE
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l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
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}
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@ -82,7 +89,7 @@ SECTIONS
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.text :
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{
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*(.text .text.*)
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} >ram
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} >ram_code
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.rodata :
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{
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@ -91,7 +98,7 @@ SECTIONS
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*(.rodata1)
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*(.eh_frame)
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. = ALIGN(4);
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} >ram
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} >ram_data
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.data :
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{
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@ -102,14 +109,14 @@ SECTIONS
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*(.sdata2)
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*(.dynamic)
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CONSTRUCTORS
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} >ram
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} >ram_data
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.u_boot_cmd :
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{
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___u_boot_cmd_start = .;
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*(.u_boot_cmd)
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___u_boot_cmd_end = .;
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} >ram
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} >ram_data
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.text_l1 :
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{
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@ -118,7 +125,7 @@ SECTIONS
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*(.l1.text)
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. = ALIGN(4);
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__etext_l1 = .;
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} >l1_code AT>ram
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} >l1_code AT>ram_code
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__text_l1_lma = LOADADDR(.text_l1);
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__text_l1_len = SIZEOF(.text_l1);
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ASSERT (__text_l1_len <= L1_INST_SRAM_SIZE, "L1 text overflow!")
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@ -131,7 +138,7 @@ SECTIONS
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*(.l1.bss)
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. = ALIGN(4);
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__edata_l1 = .;
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} >l1_data AT>ram
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} >l1_data AT>ram_data
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__data_l1_lma = LOADADDR(.data_l1);
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__data_l1_len = SIZEOF(.data_l1);
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ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data B overflow!")
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@ -143,7 +150,7 @@ SECTIONS
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*(.dynbss)
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*(.bss .bss.*)
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*(COMMON)
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} >ram
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} >ram_data
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__bss_vma = ADDR(.bss);
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__bss_len = SIZEOF(.bss);
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}
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