mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-09-25 15:51:27 +02:00
ARM: dts: sun9i: Sync from Linux v5.18-rc1
Copy the devicetree source for the A80 SoC and all existing boards verbatim from the Linux v5.18-rc1 tag. This update should not impact any existing U-Boot functionality. Signed-off-by: Samuel Holland <samuel@sholland.org>
This commit is contained in:
Samuel Holland
Andre Przywara
parent
70f24fa02b
commit
6f97e028ef
@ -63,12 +63,12 @@
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leds {
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compatible = "gpio-leds";
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green {
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led-0 {
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label = "cubieboard4:green:usr";
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gpios = <&pio 7 17 GPIO_ACTIVE_HIGH>; /* PH17 */
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};
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red {
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led-1 {
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label = "cubieboard4:red:usr";
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gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
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};
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@ -87,33 +87,25 @@
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};
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vga-dac {
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compatible = "corpro,gm7123", "adi,adv7123", "dumb-vga-dac";
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compatible = "corpro,gm7123", "adi,adv7123";
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vdd-supply = <®_dcdc1>;
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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vga_dac_in: endpoint@0 {
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reg = <0>;
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vga_dac_in: endpoint {
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remote-endpoint = <&tcon0_out_vga>;
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};
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};
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port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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vga_dac_out: endpoint@0 {
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reg = <0>;
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vga_dac_out: endpoint {
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remote-endpoint = <&vga_con_in>;
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};
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};
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@ -133,12 +125,27 @@
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status = "okay";
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};
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&gmac {
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pinctrl-names = "default";
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pinctrl-0 = <&gmac_rgmii_pins>;
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phy-handle = <&phy1>;
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phy-mode = "rgmii-id";
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phy-supply = <®_cldo1>;
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status = "okay";
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};
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_pins>;
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status = "okay";
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};
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&mdio {
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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@ -183,10 +190,26 @@
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clocks = <&ac100_rtc 0>;
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};
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&pio {
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vcc-pa-supply = <®_ldo_io1>;
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vcc-pb-supply = <®_aldo2>;
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vcc-pc-supply = <®_dcdc1>;
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vcc-pd-supply = <®_dc1sw>;
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vcc-pe-supply = <®_eldo2>;
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vcc-pf-supply = <®_dcdc1>;
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vcc-pg-supply = <®_ldo_io0>;
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vcc-ph-supply = <®_dcdc1>;
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};
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&r_ir {
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status = "okay";
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};
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&r_pio {
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vcc-pl-supply = <®_dldo2>;
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vcc-pm-supply = <®_eldo3>;
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};
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&r_rsb {
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status = "okay";
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@ -217,6 +240,10 @@
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/* unused */
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};
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reg_dc1sw: dc1sw {
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regulator-name = "vcc-pd";
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};
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reg_dc5ldo: dc5ldo {
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regulator-always-on;
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regulator-min-microvolt = <800000>;
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@ -271,7 +298,6 @@
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};
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reg_dldo2: dldo2 {
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regulator-always-on;
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-name = "vcc-pl";
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@ -290,14 +316,12 @@
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};
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reg_eldo3: eldo3 {
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regulator-always-on;
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-name = "vcc-pm-codec-io1";
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};
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reg_ldo_io0: ldo_io0 {
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regulator-always-on;
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-name = "vcc-pg";
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@ -385,6 +409,14 @@
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*/
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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/*
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* The PHY requires 20ms after all voltages
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* are applied until core logic is ready and
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* 30ms after the reset pin is de-asserted.
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* Set a 100ms delay to account for PMIC
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* ramp time and board traces.
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*/
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regulator-enable-ramp-delay = <100000>;
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regulator-name = "vcc-gmac-phy";
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};
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@ -464,8 +496,7 @@
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};
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&tcon0_out {
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tcon0_out_vga: endpoint@0 {
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reg = <0>;
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tcon0_out_vga: endpoint {
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remote-endpoint = <&vga_dac_in>;
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};
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};
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@ -82,7 +82,7 @@
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reg_usb1_vbus: usb1-vbus {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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regulator-name = "usb1-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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@ -91,7 +91,7 @@
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reg_usb3_vbus: usb3-vbus {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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regulator-name = "usb3-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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@ -120,6 +120,21 @@
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status = "okay";
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};
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&gmac {
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pinctrl-names = "default";
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pinctrl-0 = <&gmac_rgmii_pins>;
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phy-handle = <&phy1>;
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phy-mode = "rgmii-id";
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phy-supply = <®_cldo1>;
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status = "okay";
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};
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&mdio {
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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@ -172,10 +187,26 @@
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clocks = <&ac100_rtc 0>;
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};
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&pio {
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vcc-pa-supply = <®_ldo_io1>;
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vcc-pb-supply = <®_aldo2>;
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vcc-pc-supply = <®_dcdc1>;
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vcc-pd-supply = <®_dcdc1>;
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vcc-pe-supply = <®_eldo2>;
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vcc-pf-supply = <®_dcdc1>;
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vcc-pg-supply = <®_ldo_io0>;
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vcc-ph-supply = <®_dcdc1>;
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};
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&r_ir {
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status = "okay";
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};
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&r_pio {
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vcc-pl-supply = <®_dldo2>;
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vcc-pm-supply = <®_eldo3>;
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};
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&r_rsb {
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status = "okay";
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@ -213,6 +244,10 @@
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regulator-name = "vdd-cpus-09-usbh";
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};
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dc1sw {
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/* unused */
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};
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reg_dcdc1: dcdc1 {
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regulator-always-on;
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regulator-min-microvolt = <3000000>;
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@ -260,7 +295,6 @@
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};
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reg_dldo2: dldo2 {
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regulator-always-on;
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-name = "vcc-pl";
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@ -279,14 +313,12 @@
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};
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reg_eldo3: eldo3 {
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regulator-always-on;
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-name = "vcc-pm-codec-io1";
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};
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reg_ldo_io0: ldo_io0 {
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regulator-always-on;
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-name = "vcc-pg";
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@ -374,6 +406,14 @@
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*/
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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/*
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* The PHY requires 20ms after all voltages
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* are applied until core logic is ready and
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* 30ms after the reset pin is de-asserted.
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* Set a 100ms delay to account for PMIC
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* ramp time and board traces.
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*/
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regulator-enable-ramp-delay = <100000>;
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regulator-name = "vcc-gmac-phy";
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};
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@ -56,6 +56,10 @@
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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aliases {
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ethernet0 = &gmac;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -183,6 +187,37 @@
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clock-output-names = "osc32k";
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};
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/*
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* The following two are dummy clocks, placeholders
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* used in the gmac_tx clock. The gmac driver will
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* choose one parent depending on the PHY interface
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* mode, using clk_set_rate auto-reparenting.
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*
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* The actual TX clock rate is not controlled by the
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* gmac_tx clock.
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*/
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mii_phy_tx_clk: mii_phy_tx_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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clock-output-names = "mii_phy_tx";
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};
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gmac_int_tx_clk: gmac_int_tx_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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clock-output-names = "gmac_int_tx";
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};
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gmac_tx_clk: clk@800030 {
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#clock-cells = <0>;
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compatible = "allwinner,sun7i-a20-gmac-clk";
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reg = <0x00800030 0x4>;
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clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
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clock-output-names = "gmac_tx";
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};
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cpus_clk: clk@8001410 {
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compatible = "allwinner,sun9i-a80-cpus-clk";
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reg = <0x08001410 0x4>;
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@ -254,7 +289,7 @@
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status = "disabled";
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};
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soc {
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soc@20000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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@ -283,6 +318,27 @@
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};
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};
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gmac: ethernet@830000 {
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compatible = "allwinner,sun7i-a20-gmac";
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reg = <0x00830000 0x1054>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>;
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clock-names = "stmmaceth", "allwinner_gmac_tx";
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resets = <&ccu RST_BUS_GMAC>;
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reset-names = "stmmaceth";
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snps,pbl = <2>;
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snps,fixed-burst;
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snps,force_sf_dma_mode;
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status = "disabled";
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mdio: mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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ehci0: usb@a00000 {
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compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
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reg = <0x00a00000 0x100>;
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@ -331,16 +387,16 @@
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usbphy2: phy@a01800 {
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compatible = "allwinner,sun9i-a80-usb-phy";
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reg = <0x00a01800 0x4>;
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clocks = <&usb_clocks CLK_USB1_HSIC>,
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clocks = <&usb_clocks CLK_USB1_PHY>,
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<&usb_clocks CLK_USB_HSIC>,
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<&usb_clocks CLK_USB1_PHY>;
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clock-names = "hsic_480M",
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<&usb_clocks CLK_USB1_HSIC>;
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clock-names = "phy",
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"hsic_12M",
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"phy";
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resets = <&usb_clocks RST_USB1_HSIC>,
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<&usb_clocks RST_USB1_PHY>;
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reset-names = "hsic",
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"phy";
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"hsic_480M";
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resets = <&usb_clocks RST_USB1_PHY>,
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<&usb_clocks RST_USB1_HSIC>;
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reset-names = "phy",
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"hsic";
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status = "disabled";
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#phy-cells = <0>;
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/* usb1 is always used with HSIC */
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@ -373,16 +429,16 @@
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usbphy3: phy@a02800 {
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compatible = "allwinner,sun9i-a80-usb-phy";
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reg = <0x00a02800 0x4>;
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clocks = <&usb_clocks CLK_USB2_HSIC>,
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clocks = <&usb_clocks CLK_USB2_PHY>,
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<&usb_clocks CLK_USB_HSIC>,
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<&usb_clocks CLK_USB2_PHY>;
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clock-names = "hsic_480M",
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<&usb_clocks CLK_USB2_HSIC>;
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clock-names = "phy",
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"hsic_12M",
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"phy";
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resets = <&usb_clocks RST_USB2_HSIC>,
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<&usb_clocks RST_USB2_PHY>;
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reset-names = "hsic",
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"phy";
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"hsic_480M";
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resets = <&usb_clocks RST_USB2_PHY>,
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<&usb_clocks RST_USB2_HSIC>;
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reset-names = "phy",
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"hsic";
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status = "disabled";
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#phy-cells = <0>;
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};
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@ -401,6 +457,15 @@
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reg = <0x01700000 0x100>;
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};
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crypto: crypto@1c02000 {
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compatible = "allwinner,sun9i-a80-crypto";
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reg = <0x01c02000 0x1000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&ccu RST_BUS_SS>;
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clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
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clock-names = "bus", "mod";
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};
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mmc0: mmc@1c0f000 {
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compatible = "allwinner,sun9i-a80-mmc";
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reg = <0x01c0f000 0x1000>;
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@ -465,9 +530,7 @@
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compatible = "allwinner,sun9i-a80-mmc-config-clk";
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reg = <0x01c13000 0x10>;
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clocks = <&ccu CLK_BUS_MMC>;
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clock-names = "ahb";
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resets = <&ccu RST_BUS_MMC>;
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reset-names = "ahb";
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#clock-cells = <1>;
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#reset-cells = <1>;
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clock-output-names = "mmc0_config", "mmc1_config",
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@ -475,7 +538,7 @@
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};
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gic: interrupt-controller@1c41000 {
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compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
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compatible = "arm,gic-400";
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reg = <0x01c41000 0x1000>,
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<0x01c42000 0x2000>,
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<0x01c44000 0x2000>,
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@ -544,12 +607,9 @@
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#size-cells = <0>;
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fe0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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fe0_out_deu0: endpoint@0 {
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reg = <0>;
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fe0_out_deu0: endpoint {
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remote-endpoint = <&deu0_in_fe0>;
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};
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};
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@ -571,12 +631,9 @@
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#size-cells = <0>;
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fe1_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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||||
fe1_out_deu1: endpoint@0 {
|
||||
reg = <0>;
|
||||
fe1_out_deu1: endpoint {
|
||||
remote-endpoint = <&deu1_in_fe1>;
|
||||
};
|
||||
};
|
||||
@ -614,12 +671,9 @@
|
||||
};
|
||||
|
||||
be0_out: port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
be0_out_drc0: endpoint@0 {
|
||||
reg = <0>;
|
||||
be0_out_drc0: endpoint {
|
||||
remote-endpoint = <&drc0_in_be0>;
|
||||
};
|
||||
};
|
||||
@ -657,12 +711,9 @@
|
||||
};
|
||||
|
||||
be1_out: port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
be1_out_drc1: endpoint@0 {
|
||||
reg = <0>;
|
||||
be1_out_drc1: endpoint {
|
||||
remote-endpoint = <&drc1_in_be1>;
|
||||
};
|
||||
};
|
||||
@ -686,12 +737,9 @@
|
||||
#size-cells = <0>;
|
||||
|
||||
deu0_in: port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
deu0_in_fe0: endpoint@0 {
|
||||
reg = <0>;
|
||||
deu0_in_fe0: endpoint {
|
||||
remote-endpoint = <&fe0_out_deu0>;
|
||||
};
|
||||
};
|
||||
@ -731,12 +779,9 @@
|
||||
#size-cells = <0>;
|
||||
|
||||
deu1_in: port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
deu1_in_fe1: endpoint@0 {
|
||||
reg = <0>;
|
||||
deu1_in_fe1: endpoint {
|
||||
remote-endpoint = <&fe1_out_deu1>;
|
||||
};
|
||||
};
|
||||
@ -776,23 +821,17 @@
|
||||
#size-cells = <0>;
|
||||
|
||||
drc0_in: port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
drc0_in_be0: endpoint@0 {
|
||||
reg = <0>;
|
||||
drc0_in_be0: endpoint {
|
||||
remote-endpoint = <&be0_out_drc0>;
|
||||
};
|
||||
};
|
||||
|
||||
drc0_out: port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
drc0_out_tcon0: endpoint@0 {
|
||||
reg = <0>;
|
||||
drc0_out_tcon0: endpoint {
|
||||
remote-endpoint = <&tcon0_in_drc0>;
|
||||
};
|
||||
};
|
||||
@ -816,23 +855,17 @@
|
||||
#size-cells = <0>;
|
||||
|
||||
drc1_in: port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
drc1_in_be1: endpoint@0 {
|
||||
reg = <0>;
|
||||
drc1_in_be1: endpoint {
|
||||
remote-endpoint = <&be1_out_drc1>;
|
||||
};
|
||||
};
|
||||
|
||||
drc1_out: port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
drc1_out_tcon1: endpoint@0 {
|
||||
reg = <0>;
|
||||
drc1_out_tcon1: endpoint {
|
||||
remote-endpoint = <&tcon1_in_drc1>;
|
||||
};
|
||||
};
|
||||
@ -845,28 +878,28 @@
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;
|
||||
clock-names = "ahb", "tcon-ch0";
|
||||
resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>;
|
||||
reset-names = "lcd", "edp";
|
||||
resets = <&ccu RST_BUS_LCD0>,
|
||||
<&ccu RST_BUS_EDP>,
|
||||
<&ccu RST_BUS_LVDS>;
|
||||
reset-names = "lcd",
|
||||
"edp",
|
||||
"lvds";
|
||||
clock-output-names = "tcon0-pixel-clock";
|
||||
#clock-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon0_in: port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
tcon0_in_drc0: endpoint@0 {
|
||||
reg = <0>;
|
||||
tcon0_in_drc0: endpoint {
|
||||
remote-endpoint = <&drc0_out_tcon0>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon0_out: port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
@ -886,19 +919,14 @@
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon1_in: port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
tcon1_in_drc1: endpoint@0 {
|
||||
reg = <0>;
|
||||
tcon1_in_drc1: endpoint {
|
||||
remote-endpoint = <&drc1_out_tcon1>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon1_out: port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
@ -930,6 +958,7 @@
|
||||
compatible = "allwinner,sun6i-a31-wdt";
|
||||
reg = <0x06000ca0 0x20>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&osc24M>;
|
||||
};
|
||||
|
||||
pio: pinctrl@6000800 {
|
||||
@ -945,9 +974,20 @@
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
#gpio-cells = <3>;
|
||||
|
||||
gmac_rgmii_pins: gmac-rgmii-pins {
|
||||
pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5",
|
||||
"PA7", "PA8", "PA9", "PA10", "PA12",
|
||||
"PA13", "PA15", "PA16", "PA17";
|
||||
function = "gmac";
|
||||
/*
|
||||
* data lines in RGMII mode use DDR mode
|
||||
* and need a higher signal drive strength
|
||||
*/
|
||||
drive-strength = <40>;
|
||||
};
|
||||
|
||||
i2c3_pins: i2c3-pins {
|
||||
pins = "PG10", "PG11";
|
||||
function = "i2c3";
|
||||
@ -1126,6 +1166,7 @@
|
||||
compatible = "allwinner,sun6i-a31-wdt";
|
||||
reg = <0x08001000 0x20>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&osc24M>;
|
||||
};
|
||||
|
||||
prcm@8001400 {
|
||||
@ -1148,7 +1189,7 @@
|
||||
};
|
||||
|
||||
r_ir: ir@8002000 {
|
||||
compatible = "allwinner,sun5i-a13-ir";
|
||||
compatible = "allwinner,sun6i-a31-ir";
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&r_ir_pins>;
|
||||
@ -1196,7 +1237,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
r_rsb: i2c@8003400 {
|
||||
r_rsb: rsb@8003400 {
|
||||
compatible = "allwinner,sun8i-a23-rsb";
|
||||
reg = <0x08003400 0x400>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user