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ARM: renesas: Put common r7s72100 code in board/renesas/common

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Break out SoC specific code from the GR-Peach board and put it into the
board/renesas/common directory so it can be easily shared between the
GR-Peach and Genmai boards.

Signed-off-by: Magnus Damm <damm@opensource.se>
This commit is contained in:
Magnus Damm 2025-07-02 19:13:46 +02:00 committed by Marek Vasut
parent 74fc581374
commit 6e20aa243d
5 changed files with 35 additions and 23 deletions
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8
board/renesas/common/Makefile
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@ -5,6 +5,7 @@
# #
# R-Car SoCs # R-Car SoCs
ifndef CONFIG_RZA1
ifndef CONFIG_RZG2L ifndef CONFIG_RZG2L
# 32 bit SoCs # 32 bit SoCs
@ -45,3 +46,10 @@ endif
endif endif
endif endif
endif
# RZ/A1 SoCs
ifdef CONFIG_RZA1
obj-y += rza1-common.o
obj-y += rza1-lowlevel_init.o
endif

27
board/renesas/common/rza1-common.c Normal file
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@ -0,0 +1,27 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Renesas Electronics
* Copyright (C) Chris Brandt
*/
#include <init.h>
#include <asm/io.h>
#define RZA1_WDT_BASE 0xfcfe0000
#define WTCSR 0x00
#define WTCNT 0x02
#define WRCSR 0x04
void __weak reset_cpu(void)
{
/* Dummy read (must read WRCSR:WOVF at least once before clearing) */
readb(RZA1_WDT_BASE + WRCSR);
writew(0xa500, RZA1_WDT_BASE + WRCSR);
writew(0x5a5f, RZA1_WDT_BASE + WRCSR);
writew(0x5a00, RZA1_WDT_BASE + WTCNT);
writew(0xa578, RZA1_WDT_BASE + WTCSR);
for (;;)
asm volatile("wfi");
}

0
board/renesas/grpeach/lowlevel_init.S → board/renesas/common/rza1-lowlevel_init.S
View File

1
board/renesas/grpeach/Makefile
View File

@ -5,4 +5,3 @@
# SPDX-License-Identifier: GPL-2.0+ # SPDX-License-Identifier: GPL-2.0+
obj-y := grpeach.o obj-y := grpeach.o
obj-y += lowlevel_init.o

22
board/renesas/grpeach/grpeach.c
View File

@ -4,17 +4,9 @@
* Copyright (C) Chris Brandt * Copyright (C) Chris Brandt
*/ */
#include <cpu_func.h>
#include <errno.h> #include <errno.h>
#include <init.h> #include <init.h>
#include <asm/global_data.h> #include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#define RZA1_WDT_BASE 0xfcfe0000
#define WTCSR 0x00
#define WTCNT 0x02
#define WRCSR 0x04
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -39,17 +31,3 @@ int dram_init_banksize(void)
return 0; return 0;
} }
void reset_cpu(void)
{
/* Dummy read (must read WRCSR:WOVF at least once before clearing) */
readb(RZA1_WDT_BASE + WRCSR);
writew(0xa500, RZA1_WDT_BASE + WRCSR);
writew(0x5a5f, RZA1_WDT_BASE + WRCSR);
writew(0x5a00, RZA1_WDT_BASE + WTCNT);
writew(0xa578, RZA1_WDT_BASE + WTCSR);
for (;;)
asm volatile("wfi");
}