From 6de333b5caf035c38d7af9fa7596aeffcc49db42 Mon Sep 17 00:00:00 2001 From: Balaji Selvanathan Date: Wed, 3 Dec 2025 16:37:31 +0530 Subject: [PATCH] drivers: usb: dwc3: Add delay after core soft reset Add a 100 ms delay after clearing the core soft reset bit to ensure the DWC3 controller has sufficient time to complete its reset sequence before subsequent register accesses. Without this delay, USB initialization can fail on some Qualcomm platforms, particularly when using super-speed capable PHYs like the QMP USB3-DP Combo PHY on SC7280/QCM6490. Taken from Linux commit f88359e1588b ("usb: dwc3: core: Do core softreset when switch mode") Signed-off-by: Balaji Selvanathan Reviewed-by: Varadarajan Narayanan Link: https://patch.msgid.link/20251203110735.1959862-3-balaji.selvanathan@oss.qualcomm.com Signed-off-by: Casey Connolly --- drivers/usb/dwc3/core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 65c4d1a4e6f..0dee14c8b59 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -106,6 +106,8 @@ done: if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) mdelay(50); + mdelay(100); + return 0; }