From eacf07e631dc97cef0ae903cea7a3655355d9941 Mon Sep 17 00:00:00 2001 From: Karsten Merker Date: Sun, 5 May 2019 23:36:29 +0200 Subject: [PATCH 1/4] riscv: increase the environment size for the qemu-riscv platform to 128kB The existing default size of 4kB is too small as the default environment has already nearly that size and defining a single additional environment variable can exceed the available space. Signed-off-by: Karsten Merker Reviewed-by: Bin Meng --- include/configs/qemu-riscv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index b7110edebcb..df22f780b09 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -20,7 +20,7 @@ #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 /* Environment options */ -#define CONFIG_ENV_SIZE SZ_4K +#define CONFIG_ENV_SIZE SZ_128K #define BOOT_TARGET_DEVICES(func) \ func(QEMU, qemu, na) \ From cd6b6199eab1229547ac896f916b7735f77fa554 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 15 May 2019 08:42:58 -0700 Subject: [PATCH 2/4] riscv: qemu: Enable PCI host ECAM generic driver QEMU 4.0.0 'virt' target integrates a generic ECAM PCI host. Enable the driver for it. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Tested-by: Lukas Auer --- board/emulation/qemu-riscv/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 20ea6dc59b7..2a03e43b4c2 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -36,5 +36,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply OF_BOARD_SETUP imply SIFIVE_SERIAL imply SMP + imply PCI + imply DM_PCI + imply PCIE_ECAM_GENERIC + imply CMD_PCI endif From e64db0d92e320beec3214b78a4fb5cb81b8652dc Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 15 May 2019 08:42:59 -0700 Subject: [PATCH 3/4] riscv: qemu: Enable e1000 and nvme support Since we have added the PCI support to the 'virt' target, enable e1000 and NVME as alternate network and storage devices for these virtio based devices. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Tested-by: Lukas Auer --- board/emulation/qemu-riscv/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 2a03e43b4c2..7f9a74dd48e 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -40,5 +40,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply DM_PCI imply PCIE_ECAM_GENERIC imply CMD_PCI + imply E1000 + imply NVME endif From 39494822e3a639c8b5d60538d1dcae17bcf3c5f6 Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Tue, 28 May 2019 15:47:51 +0530 Subject: [PATCH 4/4] riscv: Add Microchip MPFS Icicle board support This patch adds Microchip MPFS Icicle board support. For now, NS16550 serial driver is only enabled. The Microchip MPFS Icicle defconfig by default builds U-Boot for M-Mode with SMP support. Signed-off-by: Padmarao Begari Reviewed-by: Bin Meng Reviewed-by: Lukas Auer --- arch/riscv/Kconfig | 4 ++ board/microchip/mpfs_icicle/Kconfig | 26 ++++++++++ board/microchip/mpfs_icicle/MAINTAINERS | 7 +++ board/microchip/mpfs_icicle/Makefile | 7 +++ board/microchip/mpfs_icicle/mpfs_icicle.c | 30 +++++++++++ configs/microchip_mpfs_icicle_defconfig | 8 +++ include/configs/microchip_mpfs_icicle.h | 63 +++++++++++++++++++++++ 7 files changed, 145 insertions(+) create mode 100644 board/microchip/mpfs_icicle/Kconfig create mode 100644 board/microchip/mpfs_icicle/MAINTAINERS create mode 100644 board/microchip/mpfs_icicle/Makefile create mode 100644 board/microchip/mpfs_icicle/mpfs_icicle.c create mode 100644 configs/microchip_mpfs_icicle_defconfig create mode 100644 include/configs/microchip_mpfs_icicle.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 0d04d91ad49..8cfc7d0faaa 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -11,6 +11,9 @@ choice config TARGET_AX25_AE350 bool "Support ax25-ae350" +config TARGET_MICROCHIP_ICICLE + bool "Support Microchip PolarFire-SoC Icicle Board" + config TARGET_QEMU_VIRT bool "Support QEMU Virt Board" @@ -48,6 +51,7 @@ config SPL_SYS_DCACHE_OFF # board-specific options below source "board/AndesTech/ax25-ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" +source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/fu540/Kconfig" # platform-specific options below diff --git a/board/microchip/mpfs_icicle/Kconfig b/board/microchip/mpfs_icicle/Kconfig new file mode 100644 index 00000000000..bf8e1a13ece --- /dev/null +++ b/board/microchip/mpfs_icicle/Kconfig @@ -0,0 +1,26 @@ +if TARGET_MICROCHIP_ICICLE + +config SYS_BOARD + default "mpfs_icicle" + +config SYS_VENDOR + default "microchip" + +config SYS_CPU + default "generic" + +config SYS_CONFIG_NAME + default "microchip_mpfs_icicle" + +config SYS_TEXT_BASE + default 0x80000000 if !RISCV_SMODE + default 0x80200000 if RISCV_SMODE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select GENERIC_RISCV + select BOARD_EARLY_INIT_F + imply SMP + imply SYS_NS16550 + +endif diff --git a/board/microchip/mpfs_icicle/MAINTAINERS b/board/microchip/mpfs_icicle/MAINTAINERS new file mode 100644 index 00000000000..22f3b97d8b1 --- /dev/null +++ b/board/microchip/mpfs_icicle/MAINTAINERS @@ -0,0 +1,7 @@ +Microchip MPFS icicle +M: Padmarao Begari +M: Cyril Jean +S: Maintained +F: board/microchip/mpfs_icicle/ +F: include/configs/microchip_mpfs_icicle.h +F: configs/microchip_mpfs_icicle_defconfig diff --git a/board/microchip/mpfs_icicle/Makefile b/board/microchip/mpfs_icicle/Makefile new file mode 100644 index 00000000000..72b0410dda8 --- /dev/null +++ b/board/microchip/mpfs_icicle/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Microchip Technology Inc. +# Padmarao Begari +# + +obj-y += mpfs_icicle.o diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c new file mode 100644 index 00000000000..0ef243186d4 --- /dev/null +++ b/board/microchip/mpfs_icicle/mpfs_icicle.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Microchip Technology Inc. + * Padmarao Begari + */ + +#include +#include +#include + +#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088) + +int board_init(void) +{ + /* For now nothing to do here. */ + + return 0; +} + +int board_early_init_f(void) +{ + unsigned int val; + + /* Reset uart peripheral */ + val = readl(MPFS_SYSREG_SOFT_RESET); + val = (val & ~(1u << 5u)); + writel(val, MPFS_SYSREG_SOFT_RESET); + + return 0; +} diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig new file mode 100644 index 00000000000..a375546a751 --- /dev/null +++ b/configs/microchip_mpfs_icicle_defconfig @@ -0,0 +1,8 @@ +CONFIG_RISCV=y +CONFIG_ARCH_RV64I=y +CONFIG_NR_CPUS=5 +CONFIG_TARGET_MICROCHIP_ICICLE=y +CONFIG_BOOTDELAY=3 +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_FIT=y +CONFIG_OF_PRIOR_STAGE=y diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h new file mode 100644 index 00000000000..82c7fbbdf22 --- /dev/null +++ b/include/configs/microchip_mpfs_icicle.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Microchip Technology Inc. + * Padmarao Begari + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * CPU and Board Configuration Options + */ +#define CONFIG_BOOTP_SEND_HOSTNAME + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +/* + * Print Buffer Size + */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* + * max number of command args + */ +#define CONFIG_SYS_MAXARGS 16 + +/* + * Boot Argument Buffer Size + */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * Size of malloc() pool + * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough + */ +#define CONFIG_SYS_MALLOC_LEN (512 << 10) + +/* + * Physical Memory Map + */ +#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_0_SIZE 0x40000000 /* 1 GB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 + +/* Init Stack Pointer */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x200000) + +#define CONFIG_SYS_LOAD_ADDR 0x80000000 /* SDRAM */ + +/* + * memtest works on DRAM + */ +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) + +/* When we use RAM as ENV */ +#define CONFIG_ENV_SIZE 0x2000 + +#endif /* __CONFIG_H */