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clk: rockchip: rk3588: Fix clk_aux16m in clock driver
The rate and error value is not returned for aux16m clocks, fix this. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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@ -1558,7 +1558,7 @@ static ulong rk3588_clk_get_rate(struct clk *clk)
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#ifndef CONFIG_SPL_BUILD
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#ifndef CONFIG_SPL_BUILD
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case CLK_AUX16M_0:
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case CLK_AUX16M_0:
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case CLK_AUX16M_1:
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case CLK_AUX16M_1:
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rk3588_aux16m_get_clk(priv, clk->id);
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rate = rk3588_aux16m_get_clk(priv, clk->id);
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break;
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break;
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case ACLK_VOP_ROOT:
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case ACLK_VOP_ROOT:
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case ACLK_VOP:
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case ACLK_VOP:
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@ -1707,7 +1707,7 @@ static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate)
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#ifndef CONFIG_SPL_BUILD
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#ifndef CONFIG_SPL_BUILD
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case CLK_AUX16M_0:
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case CLK_AUX16M_0:
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case CLK_AUX16M_1:
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case CLK_AUX16M_1:
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rk3588_aux16m_set_clk(priv, clk->id, rate);
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ret = rk3588_aux16m_set_clk(priv, clk->id, rate);
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break;
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break;
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case ACLK_VOP_ROOT:
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case ACLK_VOP_ROOT:
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case ACLK_VOP:
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case ACLK_VOP:
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