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board: venice: move soc-specific dram config into soc-specific files
Move the determination of the dram timings into the soc-specific files. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Tim Harvey
Fabio Estevam
parent
2f1c3e1f9e
commit
66e8b17eee
@ -6,18 +6,6 @@
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#ifndef __LPDDR4_TIMING_H__
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#define __LPDDR4_TIMING_H__
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#ifdef CONFIG_IMX8MM
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extern struct dram_timing_info dram_timing_512mb;
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extern struct dram_timing_info dram_timing_1gb;
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extern struct dram_timing_info dram_timing_2gb;
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extern struct dram_timing_info dram_timing_4gb;
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#elif CONFIG_IMX8MN
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extern struct dram_timing_info dram_timing_1gb_single_die;
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extern struct dram_timing_info dram_timing_2gb_single_die;
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extern struct dram_timing_info dram_timing_2gb_dual_die;
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#elif CONFIG_IMX8MP
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extern struct dram_timing_info dram_timing_1gb_single_die;
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extern struct dram_timing_info dram_timing_4gb_dual_die;
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#endif
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extern struct dram_timing_info *spl_dram_init(const char *model, int sizemb);
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#endif /* __LPDDR4_TIMING_H__ */
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@ -1830,7 +1830,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg_512mb[] = {
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};
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/* ddr timing config params */
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struct dram_timing_info dram_timing_512mb = {
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static struct dram_timing_info dram_timing_512mb = {
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.ddrc_cfg = ddr_ddrc_cfg_512mb,
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.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_512mb),
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.ddrphy_cfg = ddr_ddrphy_cfg_512mb,
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@ -2489,7 +2489,7 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg_1gb[] = {
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};
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/* lpddr4 timing config params */
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struct dram_timing_info dram_timing_1gb = {
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static struct dram_timing_info dram_timing_1gb = {
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.ddrc_cfg = lpddr4_ddrc_cfg_1gb,
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.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg_1gb),
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.ddrphy_cfg = lpddr4_ddrphy_cfg_1gb,
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@ -3005,7 +3005,7 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg_4gb[] = {
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};
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/* lpddr4 timing config params */
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struct dram_timing_info dram_timing_4gb = {
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static struct dram_timing_info dram_timing_4gb = {
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.ddrc_cfg = lpddr4_ddrc_cfg_4gb,
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.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg_4gb),
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.ddrphy_cfg = lpddr4_ddrphy_cfg_4gb,
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@ -3140,12 +3140,12 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg_2gb[] = {
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{ 0x100a7, 0x7 },
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{ 0x110a0, 0x0 },
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{ 0x110a1, 0x1 },
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{ 0x110a2, 0x2 },
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{ 0x110a3, 0x3 },
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{ 0x110a4, 0x4 },
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{ 0x110a5, 0x5 },
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{ 0x110a6, 0x6 },
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{ 0x110a7, 0x7 },
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{ 0x110a2, 0x3 },
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{ 0x110a3, 0x4 },
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{ 0x110a4, 0x5 },
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{ 0x110a5, 0x2 },
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{ 0x110a6, 0x7 },
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{ 0x110a7, 0x6 },
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{ 0x120a0, 0x0 },
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{ 0x120a1, 0x1 },
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{ 0x120a2, 0x3 },
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@ -3156,12 +3156,12 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg_2gb[] = {
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{ 0x120a7, 0x6 },
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{ 0x130a0, 0x0 },
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{ 0x130a1, 0x1 },
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{ 0x130a2, 0x5 },
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{ 0x130a3, 0x2 },
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{ 0x130a4, 0x3 },
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{ 0x130a5, 0x4 },
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{ 0x130a6, 0x7 },
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{ 0x130a7, 0x6 },
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{ 0x130a2, 0x2 },
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{ 0x130a3, 0x3 },
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{ 0x130a4, 0x4 },
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{ 0x130a5, 0x5 },
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{ 0x130a6, 0x6 },
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{ 0x130a7, 0x7 },
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{ 0x1005f, 0x1ff },
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{ 0x1015f, 0x1ff },
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{ 0x1105f, 0x1ff },
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@ -3521,7 +3521,7 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg_2gb[] = {
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};
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/* lpddr4 timing config params */
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struct dram_timing_info dram_timing_2gb = {
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static struct dram_timing_info dram_timing_2gb = {
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.ddrc_cfg = lpddr4_ddrc_cfg_2gb,
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.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg_2gb),
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.ddrphy_cfg = lpddr4_ddrphy_cfg_2gb,
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@ -3534,3 +3534,28 @@ struct dram_timing_info dram_timing_2gb = {
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.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
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.fsp_table = { 3000, 400, 100, },
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};
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struct dram_timing_info *spl_dram_init(const char *model, int sizemb)
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{
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struct dram_timing_info *dram_timing;
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switch (sizemb) {
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case 512:
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dram_timing = &dram_timing_512mb;
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break;
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case 1024:
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dram_timing = &dram_timing_1gb;
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break;
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case 2048:
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dram_timing = &dram_timing_2gb;
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break;
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case 4096:
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dram_timing = &dram_timing_4gb;
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break;
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default:
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printf("unsupported");
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dram_timing = &dram_timing_1gb;
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}
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return dram_timing;
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}
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@ -1,6 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0+
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#include <linux/kernel.h>
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#include <string.h>
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#include <asm/arch/ddr.h>
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/*
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@ -1425,7 +1426,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg_1gb_single_die[] = {
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};
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/* ddr timing config params */
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struct dram_timing_info dram_timing_1gb_single_die = {
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static struct dram_timing_info dram_timing_1gb_single_die = {
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.ddrc_cfg = ddr_ddrc_cfg_1gb_single_die,
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.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_1gb_single_die),
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.ddrphy_cfg = ddr_ddrphy_cfg_1gb_single_die,
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@ -1890,7 +1891,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg_2gb_single_die[] = {
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};
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/* ddr timing config params */
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struct dram_timing_info dram_timing_2gb_single_die = {
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static struct dram_timing_info dram_timing_2gb_single_die = {
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.ddrc_cfg = ddr_ddrc_cfg_2gb_single_die,
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.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_2gb_single_die),
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.ddrphy_cfg = ddr_ddrphy_cfg_2gb_single_die,
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@ -2354,7 +2355,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg_2gb_dual_die[] = {
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};
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/* ddr timing config params */
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struct dram_timing_info dram_timing_2gb_dual_die = {
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static struct dram_timing_info dram_timing_2gb_dual_die = {
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.ddrc_cfg = ddr_ddrc_cfg_2gb_dual_die,
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.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_2gb_dual_die),
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.ddrphy_cfg = ddr_ddrphy_cfg_2gb_dual_die,
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@ -2367,3 +2368,27 @@ struct dram_timing_info dram_timing_2gb_dual_die = {
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.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
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.fsp_table = { 3200, 400, 100, },
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};
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struct dram_timing_info *spl_dram_init(const char *model, int sizemb)
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{
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struct dram_timing_info *dram_timing;
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switch (sizemb) {
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case 1024:
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dram_timing = &dram_timing_1gb_single_die;
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break;
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case 2048:
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if (!strcmp(model, "GW7902-SP466-A") ||
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!strcmp(model, "GW7902-SP466-B")) {
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dram_timing = &dram_timing_2gb_dual_die;
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} else {
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dram_timing = &dram_timing_2gb_single_die;
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}
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break;
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default:
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printf("unsupported");
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dram_timing = &dram_timing_2gb_dual_die;
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}
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return dram_timing;
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}
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@ -1832,7 +1832,7 @@ struct dram_fsp_msg ddr_dram_fsp_msg_1gb_single_die[] = {
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};
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/* ddr timing config params */
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struct dram_timing_info dram_timing_1gb_single_die = {
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static struct dram_timing_info dram_timing_1gb_single_die = {
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.ddrc_cfg = ddr_ddrc_cfg_1gb_single_die,
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.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_1gb_single_die),
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.ddrphy_cfg = ddr_ddrphy_cfg_1gb_single_die,
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@ -2364,7 +2364,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg_4gb_dual_die[] = {
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};
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/* ddr timing config params */
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struct dram_timing_info dram_timing_4gb_dual_die = {
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static struct dram_timing_info dram_timing_4gb_dual_die = {
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.ddrc_cfg = ddr_ddrc_cfg_4gb_dual_die,
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.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_4gb_dual_die),
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.ddrphy_cfg = ddr_ddrphy_cfg_4gb_dual_die,
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@ -2377,3 +2377,22 @@ struct dram_timing_info dram_timing_4gb_dual_die = {
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.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
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.fsp_table = { 4000, 400, 100, },
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};
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struct dram_timing_info *spl_dram_init(const char *model, int sizemb)
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{
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struct dram_timing_info *dram_timing;
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switch (sizemb) {
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case 1024:
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dram_timing = &dram_timing_1gb_single_die;
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break;
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case 4096:
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dram_timing = &dram_timing_4gb_dual_die;
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break;
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default:
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printf("unsupported");
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dram_timing = &dram_timing_4gb_dual_die;
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}
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return dram_timing;
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}
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@ -32,69 +32,6 @@
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#define PCIE_RSTN IMX_GPIO_NR(4, 6)
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static void spl_dram_init(int size)
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{
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struct dram_timing_info *dram_timing;
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switch (size) {
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#ifdef CONFIG_IMX8MM
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case 512:
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dram_timing = &dram_timing_512mb;
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break;
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case 1024:
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dram_timing = &dram_timing_1gb;
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break;
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case 2048:
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dram_timing = &dram_timing_2gb;
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break;
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case 4096:
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dram_timing = &dram_timing_4gb;
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break;
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default:
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printf("Unknown DDR configuration: %d MiB\n", size);
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dram_timing = &dram_timing_1gb;
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size = 1024;
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#elif CONFIG_IMX8MN
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case 1024:
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dram_timing = &dram_timing_1gb_single_die;
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break;
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case 2048:
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if (!strcmp(eeprom_get_model(), "GW7902-SP466-A") ||
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!strcmp(eeprom_get_model(), "GW7902-SP466-B")) {
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dram_timing = &dram_timing_2gb_dual_die;
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} else {
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dram_timing = &dram_timing_2gb_single_die;
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}
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break;
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default:
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printf("Unknown DDR configuration: %d MiB\n", size);
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dram_timing = &dram_timing_2gb_dual_die;
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size = 2048;
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#elif CONFIG_IMX8MP
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case 1024:
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dram_timing = &dram_timing_1gb_single_die;
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break;
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case 4096:
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dram_timing = &dram_timing_4gb_dual_die;
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break;
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default:
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printf("Unknown DDR configuration: %d GiB\n", size);
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dram_timing = &dram_timing_4gb_dual_die;
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size = 4096;
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#endif
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}
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printf("DRAM : LPDDR4 ");
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if (size > 512)
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printf("%d GiB", size / 1024);
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else
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printf("%d MiB", size);
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printf(" %dMT/s %dMHz\n",
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dram_timing->fsp_msg[0].drate,
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dram_timing->fsp_msg[0].drate / 2);
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ddr_init(dram_timing);
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}
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/*
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* Model specific PMIC adjustments necessary prior to DRAM init
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*
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@ -118,9 +55,8 @@ static int dm_i2c_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set)
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return dm_i2c_write(dev, reg, &val, 1);
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}
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static int power_init_board(struct udevice *gsc)
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static int power_init_board(const char *model, struct udevice *gsc)
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{
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const char *model = eeprom_get_model();
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struct udevice *bus;
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struct udevice *dev;
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int ret;
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@ -251,9 +187,11 @@ static int power_init_board(struct udevice *gsc)
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void board_init_f(ulong dummy)
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{
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struct dram_timing_info *dram_timing;
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struct udevice *bus, *dev;
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const char *model;
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int dram_szmb;
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int i, ret;
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int dram_sz;
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arch_cpu_init();
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@ -311,13 +249,23 @@ void board_init_f(ulong dummy)
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break;
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mdelay(1);
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}
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dram_sz = venice_eeprom_init(0);
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dram_szmb = venice_eeprom_init(0);
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model = eeprom_get_model();
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/* PMIC */
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power_init_board(dev);
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power_init_board(model, dev);
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/* DDR initialization */
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spl_dram_init(dram_sz);
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printf("DRAM : LPDDR4 ");
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if (dram_szmb > 512)
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printf("%d GiB", dram_szmb / 1024);
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else
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printf("%d MiB", dram_szmb);
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dram_timing = spl_dram_init(model, dram_szmb);
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printf(" %dMT/s %dMHz\n",
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dram_timing->fsp_msg[0].drate,
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dram_timing->fsp_msg[0].drate / 2);
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ddr_init(dram_timing);
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board_init_r(NULL, 0);
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}
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