From 9b31e109b2dab0e696659f77c057e620bfb62b5b Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Sat, 16 Apr 2022 20:15:30 +0200 Subject: [PATCH 01/24] soc: xilinx: versal: fix out of bounds array access The call to xilinx_pm_request requires an array of a larger size. Signed-off-by: Jorge Ramirez-Ortiz Link: https://lore.kernel.org/r/20220416181530.2311155-1-jorge@foundries.io Signed-off-by: Michal Simek --- drivers/soc/soc_xilinx_versal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/soc_xilinx_versal.c b/drivers/soc/soc_xilinx_versal.c index f8bcd9ab404..3d8c25c19bb 100644 --- a/drivers/soc/soc_xilinx_versal.c +++ b/drivers/soc/soc_xilinx_versal.c @@ -45,7 +45,7 @@ static const struct soc_ops soc_xilinx_versal_ops = { static int soc_xilinx_versal_probe(struct udevice *dev) { struct soc_xilinx_versal_priv *priv = dev_get_priv(dev); - u32 ret_payload[4]; + u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; priv->family = versal_family; From 303198e26dd455aafd23d25e9f4d99d9fee1caec Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 20 Apr 2022 09:39:04 +0200 Subject: [PATCH 02/24] soc: xilinx: zynqmp: fix out of bounds array access The call to xilinx_pm_request requires an array of a larger size. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/5f1409de285d7454af171a54e5f115da9d82c44e.1650440343.git.michal.simek@xilinx.com --- drivers/soc/soc_xilinx_zynqmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c index 7d33ce2163d..a71115b17cc 100644 --- a/drivers/soc/soc_xilinx_zynqmp.c +++ b/drivers/soc/soc_xilinx_zynqmp.c @@ -49,7 +49,7 @@ static const struct soc_ops soc_xilinx_zynqmp_ops = { static int soc_xilinx_zynqmp_probe(struct udevice *dev) { struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev); - u32 ret_payload[4]; + u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; priv->family = zynqmp_family; From 9c563e916c91f8ad093e832fbe00ab12dd18ea61 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 29 Apr 2022 11:52:27 +0200 Subject: [PATCH 03/24] xilinx: Handle board_get_usable_ram_top(0) properly board_get_usable_ram_top() was designed for getting the top most location for U-Boot allocation that's why function itself supports via total_size parameter to find out where the right location for U-Boot is. But function itself is also reused by different (EFI) which is passing total_size as 0 to find out where the usable ram top is. For this case doesn't make sense (a waste time) to call any lmb functions. That's why simply return gd->ram_top. And gd->ram_top is filled already based on previous call for U-Boot iself. The same solution is also used by stm32mp by commit 92b611e8b003 ("stm32mp: correctly handle board_get_usable_ram_top(0)") and commit c8510e397fad ("stm32mp: Fix board_get_usable_ram_top()"). Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/44470619e74f3e480b70deac24578e3e0d5c907e.1651225945.git.michal.simek@amd.com --- board/xilinx/versal/board.c | 3 +++ board/xilinx/zynqmp/zynqmp.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 2e2807eee46..a88f5bb177e 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -256,6 +256,9 @@ ulong board_get_usable_ram_top(ulong total_size) phys_addr_t reg; struct lmb lmb; + if (!total_size) + return gd->ram_top; + /* found enough not-reserved memory to relocated U-Boot */ lmb_init(&lmb); lmb_add(&lmb, gd->ram_base, gd->ram_size); diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 41ecc9559c4..e311aa772cc 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -516,6 +516,9 @@ ulong board_get_usable_ram_top(ulong total_size) phys_addr_t reg; struct lmb lmb; + if (!total_size) + return gd->ram_top; + if (!IS_ALIGNED((ulong)gd->fdt_blob, 0x8)) panic("Not 64bit aligned DT location: %p\n", gd->fdt_blob); From 1720336d3cc5a7e24faee915e0441c57df6e2cab Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Wed, 27 Apr 2022 10:30:45 +0200 Subject: [PATCH 04/24] Revert "arm64: xilinx: Set CONFIG_ZYNQMP_FIRMWARE config for mini emmc" This reverts commit 122ca834f2f4a9d70abeece3d1ff200a3556ab24. Disable CONFIG_ZYNQMP_FIRMWARE config from zynqmp & versal mini emmc defconfig files, as mini emmc does not use any firmware. Signed-off-by: T Karthik Reddy Acked-by: Ashok Reddy Soma Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/f73a50980d3af894f1e86cfc98742dbdec573760.1651048242.git.michal.simek@xilinx.com --- configs/xilinx_versal_mini_emmc0_defconfig | 1 - configs/xilinx_versal_mini_emmc1_defconfig | 1 - configs/xilinx_zynqmp_mini_emmc0_defconfig | 1 - configs/xilinx_zynqmp_mini_emmc1_defconfig | 1 - 4 files changed, 4 deletions(-) diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig index ab14118fdcd..9d2f97576bb 100644 --- a/configs/xilinx_versal_mini_emmc0_defconfig +++ b/configs/xilinx_versal_mini_emmc0_defconfig @@ -56,7 +56,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_NET is not set # CONFIG_DM_WARN is not set # CONFIG_DM_DEVICE_REMOVE is not set -CONFIG_ZYNQMP_FIRMWARE=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_ARM_DCC=y diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig index cab3d21cb71..7efb9287561 100644 --- a/configs/xilinx_versal_mini_emmc1_defconfig +++ b/configs/xilinx_versal_mini_emmc1_defconfig @@ -56,7 +56,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_NET is not set # CONFIG_DM_WARN is not set # CONFIG_DM_DEVICE_REMOVE is not set -CONFIG_ZYNQMP_FIRMWARE=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_ARM_DCC=y diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index e176175251f..b4052771566 100644 --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -58,7 +58,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_DM_WARN is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_ZYNQMP_FIRMWARE=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig index f5b35fbb71c..5fa1337d761 100644 --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -58,7 +58,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_DM_WARN is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_ZYNQMP_FIRMWARE=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y From 155353234ec2259efae88c9973f81a53a2b9afb5 Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Wed, 27 Apr 2022 10:27:12 +0200 Subject: [PATCH 05/24] mmc: zynq_sdhci: Add weak function prototype zynqmp_pm_is_function_supported() which checks feature support on som, which is implemented in firmware_zynqmp.c driver. As mini configuration does not use firmware driver, so create a weak function to avoid compilation error on zynqmp mini configuration. Signed-off-by: T Karthik Reddy Acked-by: Ashok Reddy Soma Reviewed-by: Jaehoon Chung Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/c60655a509956b8fc3a81671a7dc51157f3973db.1651048030.git.michal.simek@xilinx.com --- drivers/mmc/zynq_sdhci.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index a59d96c6bda..e978b679885 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -79,6 +79,11 @@ __weak int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2, return 0; } +__weak int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id) +{ + return 1; +} + #if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) /* Default settings for ZynqMP Clock Phases */ static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0, From 80b8bbbf98fcb062d7bbc7bff10ef51086d3c422 Mon Sep 17 00:00:00 2001 From: Neal Frager Date: Tue, 10 May 2022 16:18:42 +0200 Subject: [PATCH 06/24] arm64: zynqmp: zynqmp-zcu106-rev1.0: Fix DP PLL configuration This patch fixes the DP audio and video PLL configurations for the zynqmp-zcu106-rev1.0 evaluation board. The Linux DP driver expects the DP to be using the following PLL config: - DP video PLL should use the VPLL (0x0) - DP audio PLL should use the RPLL (0x3) Register 0xFD1A0070 configures the DP video PLL. Register 0xFD1A0074 configures the DP audio PLL. Signed-off-by: Neal Frager Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/ae42ad6185418713a473660c8d15903299af7764.1652192319.git.michal.simek@amd.com --- board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c index 2ac4e035d88..3dc9bf8f3a8 100644 --- a/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c @@ -81,8 +81,8 @@ static unsigned long psu_clock_init_data(void) psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010203U); - psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C00U); + psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U); psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011303U); psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); From a3659640e03aacb21171eb54e35df79f18174603 Mon Sep 17 00:00:00 2001 From: Neal Frager Date: Thu, 5 May 2022 10:56:29 +0200 Subject: [PATCH 07/24] arm64: zynqmp: zynqmp-zcu106-revA: Fix DP PLL configuration This patch fixes the DP audio and video PLL configurations for the zynqmp-zcu106-revA evaluation board. The Linux DP driver expects the DP to be using the following PLL config: - DP video PLL should use the VPLL (0x0) - DP audio PLL should use the RPLL (0x3) Register 0xFD1A0070 configures the DP video PLL. Register 0xFD1A0074 configures the DP audio PLL. Signed-off-by: Neal Frager Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/62538b4a04dee28a6fc8ac5b85f8c845a5a76aa4.1651740988.git.michal.simek@amd.com --- board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c index 15f0be1a43a..cbc436289f5 100644 --- a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c @@ -81,8 +81,8 @@ static unsigned long psu_clock_init_data(void) psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010203U); - psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C00U); + psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U); psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011303U); psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); From 2946c551f1d873f40187c042d0c9306e7fef27c5 Mon Sep 17 00:00:00 2001 From: Neal Frager Date: Thu, 5 May 2022 10:55:51 +0200 Subject: [PATCH 08/24] arm64: zynqmp: zynqmp-zcu102-revA: Fix DP PLL configuration This patch fixes the DP audio and video PLL configurations for the zynqmp-zcu102-revA evaluation board. The Linux DP driver expects the DP to be using the following PLL config: - DP video PLL should use the VPLL (0x0) - DP audio PLL should use the RPLL (0x3) Register 0xFD1A0070 configures the DP video PLL. Register 0xFD1A0074 configures the DP audio PLL. Signed-off-by: Neal Frager Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/b2eb87758e0cd4844e1754da8c58fce58d9cf683.1651740949.git.michal.simek@amd.com --- board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c index 8ecd9ee90b5..f99e06acf6e 100644 --- a/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c @@ -85,8 +85,8 @@ static unsigned long psu_clock_init_data(void) psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010303U); - psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01012700U); + psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U); psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011103U); psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); psu_mask_write(0xFD1A0064, 0x01003F07U, 0x01000200U); From 67bdaa016514f020b717a3ba350696ded44a10a3 Mon Sep 17 00:00:00 2001 From: Neal Frager Date: Wed, 4 May 2022 09:12:26 +0200 Subject: [PATCH 09/24] arm64: zynqmp: Fix split mode reset functionality This patch fixes two issues in the set_r5_reset function. 1. When in split mode, the lpd_amba_rst bit should only be set when both r5 cpu cores are in reset. Otherwise, if one r5 core is still running, setting the lpd_amba_rst bit will cause an error for the running core. The set_r5_reset function has been modified to check if the other r5 core is still running before setting the lpd_amba_rst bit. 2. The cpu_disable function was always assuming that the r5 cores are in split mode when resetting either core 4 or 5. This is incorrect for lockstep functionality. This patch adds a function check_r5_mode to handle the cpu_disable function correctly for the r5 cores by checking the mode and handling the reset appropriately. Signed-off-by: Neal Frager Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/d99cbd7f2394ac055ef27457298f554ff0747ba7.1651648344.git.michal.simek@amd.com --- arch/arm/mach-zynqmp/mp.c | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c index 704520e7a3c..4f1ed44afb6 100644 --- a/arch/arm/mach-zynqmp/mp.c +++ b/arch/arm/mach-zynqmp/mp.c @@ -102,13 +102,21 @@ static void set_r5_reset(u32 nr, u8 mode) u32 tmp; tmp = readl(&crlapb_base->rst_lpd_top); - if (mode == LOCK || nr == ZYNQMP_CORE_RPU0) - tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | - ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK); - - if (mode == LOCK || nr == ZYNQMP_CORE_RPU1) + if (mode == LOCK) { tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | + ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK | ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK); + } else { + if (nr == ZYNQMP_CORE_RPU0) { + tmp |= ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK; + if (tmp & ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK) + tmp |= ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK; + } else { + tmp |= ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK; + if (tmp & ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK) + tmp |= ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK; + } + } writel(tmp, &crlapb_base->rst_lpd_top); } @@ -142,6 +150,17 @@ static void enable_clock_r5(void) udelay(0x500); } +static int check_r5_mode(void) +{ + u32 tmp; + + tmp = readl(&rpu_base->rpu_glbl_ctrl); + if (tmp & ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK) + return SPLIT; + + return LOCK; +} + int cpu_disable(u32 nr) { if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) { @@ -149,7 +168,7 @@ int cpu_disable(u32 nr) val |= 1 << nr; writel(val, &crfapb_base->rst_fpd_apu); } else { - set_r5_reset(nr, SPLIT); + set_r5_reset(nr, check_r5_mode()); } return 0; From 10c29fa1cc77bc4dbf620fa5a212ae78a1cb0a73 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 10 May 2022 16:23:02 +0200 Subject: [PATCH 10/24] xilinx: zynqmp: Do not guard SPL_FS_LOAD_PAYLOAD_NAME by SDHCI driver CONFIG_SPL_FS_LOAD_PAYLOAD_NAME is used by set_dfu_alt_info() for string generation. It doesn't depend on SDHCI because the same file can be stored to other non volatile memories like qspi. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/97434e122c6f8f042330b60d3e8de4c31f3e3f93.1652192580.git.michal.simek@amd.com Link: https://lore.kernel.org/r/718de136c68c9a76fc7b4e536a727f401b05bfb9.1652702625.git.michal.simek@amd.com --- include/configs/xilinx_zynqmp.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 8eb44b18d20..f25d796a1e7 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -226,7 +226,6 @@ #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "atf-uboot.ub" /* MMC support */ -#ifdef CONFIG_MMC_SDHCI_ZYNQ # define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* unused */ # define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* unused */ # if defined(CONFIG_SPL_LOAD_FIT) @@ -234,7 +233,6 @@ # else # define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" # endif -#endif #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU) # define CONFIG_SPL_HASH From 6e38e2ea795e7e36abe8755f536747b76a29094f Mon Sep 17 00:00:00 2001 From: Amit Kumar Mahapatra Date: Tue, 10 May 2022 16:33:01 +0200 Subject: [PATCH 11/24] arm64: zynqmp: Set qspi tx-buswidth to 4 In all the ZynqMP boards dts files tx-buswidth is by default set to 1. Due to this the framework only issues 1-1-1 write commands to the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4 write commands, so updated the tx-buswidth to 4 in ZynqMP boards dts files. This would enable the spi-nor framework to issue 1-4-4 write commands instead of 1-1-1. This will increase the tx data transfer rate, as now the tx data will be transferred on four lines instead on single line. Signed-off-by: Amit Kumar Mahapatra Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/ad61199f55e5e00f29de6206d9d1872a52a7657e.1652193179.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 2 +- arch/arm/dts/zynqmp-mini-qspi.dts | 2 +- arch/arm/dts/zynqmp-sm-k26-revA.dts | 2 +- arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts | 2 +- arch/arm/dts/zynqmp-zc1232-revA.dts | 2 +- arch/arm/dts/zynqmp-zc1254-revA.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 2 +- arch/arm/dts/zynqmp-zcu102-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu104-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu104-revC.dts | 2 +- arch/arm/dts/zynqmp-zcu106-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu111-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu1275-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu208-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu216-revA.dts | 2 +- 18 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index 86f2ccf4d95..7b3722f0808 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -77,7 +77,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index e980fb07fc3..11b2a58a0f0 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -73,7 +73,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index c8c5100672f..db199c467b0 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -73,7 +73,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts index 9b4320fe6e2..20c21deb667 100644 --- a/arch/arm/dts/zynqmp-mini-qspi.dts +++ b/arch/arm/dts/zynqmp-mini-qspi.dts @@ -68,7 +68,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; }; diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index 14ab31685df..e904cd8ea09 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -117,7 +117,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { diff --git a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts index 300e2ebe96e..3750bb38b58 100644 --- a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts +++ b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts @@ -61,7 +61,7 @@ compatible = "st,m25p80", "n25q256a", "jedec,spi-nor"; m25p,fast-read; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <166000000>; #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts index 7543855c9fd..63c553f7724 100644 --- a/arch/arm/dts/zynqmp-zc1232-revA.dts +++ b/arch/arm/dts/zynqmp-zc1232-revA.dts @@ -44,7 +44,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts index 9cc1c0c6c5a..343033cc7e8 100644 --- a/arch/arm/dts/zynqmp-zc1254-revA.dts +++ b/arch/arm/dts/zynqmp-zc1254-revA.dts @@ -45,7 +45,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 4a87bd6a6aa..d20f6675687 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -351,7 +351,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index f420f83ad20..e153a64f4fb 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -173,7 +173,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 1b1cabb004f..aac798d6e74 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -948,7 +948,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 9cd30447eb3..50bf4790891 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -434,7 +434,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 45191569c10..752a9e38f3d 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -446,7 +446,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 50cc72eb924..03624648cd7 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -942,7 +942,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 2b15ce1ea84..021fe88670f 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -784,7 +784,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts index 10d8bc8f9a1..e88fc23b1f1 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts @@ -50,7 +50,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 32a6e6fb55e..c5cdd58af6e 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -642,7 +642,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index 1e347036d0a..caae16965d6 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -653,7 +653,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; From e9869f474c35b81577066441dce6960c03089023 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Tue, 10 May 2022 07:12:34 -0600 Subject: [PATCH 12/24] phy: zynqmp: Increase timeout value to 10ms Observing psgtr pll timeouts with some usb hubs and devices behind it. Increase timeout to 10ms to take care of it. Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20220510131234.2650-1-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek --- drivers/phy/phy-zynqmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/phy-zynqmp.c b/drivers/phy/phy-zynqmp.c index 08c1b6efcfd..d1288bb17f3 100644 --- a/drivers/phy/phy-zynqmp.c +++ b/drivers/phy/phy-zynqmp.c @@ -168,7 +168,7 @@ enum { }; /* Timeout values */ -#define TIMEOUT_US 1000 +#define TIMEOUT_US 10000 #define IOU_SLCR_GEM_CLK_CTRL 0x308 #define GEM_CTRL_GEM_SGMII_MODE BIT(2) From 6be41ea4e6ff5aceff152a8480ce1c93427b1247 Mon Sep 17 00:00:00 2001 From: Neal Frager Date: Mon, 16 May 2022 16:02:19 +0200 Subject: [PATCH 13/24] arm64: zynqmp: zynqmp-sm-k26-revA: Fix DP PLL configuration This patch fixes the DP audio and video PLL configurations for the zynqmp-sm-k26-revA som. The Linux DP driver expects the DP to be using the following PLL config: - DP video PLL should use the VPLL (0x0) - DP audio PLL should use the RPLL (0x3) - DP system time clock PLL should use RPLL (0x3) Register 0xFD1A0070 configures the DP video PLL. Register 0xFD1A0074 configures the DP audio PLL. Register 0xFD1A007C configures the DP system time clock PLL. Signed-off-by: Neal Frager Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/fa7e9abc419c9d7648405d1c62367dbe701d09b8.1652709736.git.michal.simek@amd.com --- board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c index ed025790bc3..e5598807e8c 100644 --- a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c @@ -74,6 +74,9 @@ static unsigned long psu_clock_init_data(void) psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000A00U); psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U); + psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01013803U); psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U); From a4180c369607b262779b77c1a9cd2f68e993eead Mon Sep 17 00:00:00 2001 From: Piyush Mehta Date: Wed, 11 May 2022 11:52:45 +0200 Subject: [PATCH 14/24] arm64: zynqmp: Add mode-pin GPIO controller DT node Add mode-pin GPIO controller DT node in zynqmp.dtsi and also setup default reset-gpios property for usb which is default Xilinx setup. Signed-off-by: Piyush Mehta Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/f2a1f6f541c41075ea36062857031bfc28d6d303.1652262769.git.michal.simek@amd.com --- arch/arm/dts/zynqmp.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index c4426088502..6b711c810e6 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -13,6 +13,7 @@ */ #include +#include #include #include @@ -189,6 +190,12 @@ compatible = "xlnx,zynqmp-pinctrl"; status = "disabled"; }; + + modepin_gpio: gpio { + compatible = "xlnx,zynqmp-gpio-modepin"; + gpio-controller; + #gpio-cells = <2>; + }; }; }; @@ -874,6 +881,7 @@ <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; + reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; ranges; dwc3_0: usb@fe200000 { From e7b390024c2437a6f43dc9d9d03e8c9d470ce811 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 11 May 2022 11:52:46 +0200 Subject: [PATCH 15/24] arm64: zynqmp: Add gpio labels for modepin Using labels helps with better identifications of chips. Signed-off-by: Michal Simek Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/15b0f68077fb3c86d438caf8562de87367361c60.1652262769.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sm-k26-revA.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index e904cd8ea09..a2c88dc34c6 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -89,6 +89,10 @@ }; }; +&modepin_gpio { + label = "modepin"; +}; + &uart1 { /* MIO36/MIO37 */ status = "okay"; }; From 234f8be5683d6e9cd5ed83deb8d3e48acc839779 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 11 May 2022 11:52:47 +0200 Subject: [PATCH 16/24] arm64: zynqmp: Fix opp-table-cpu OPP table name now should start with "opp-table" and OPP entries shouldn't contain commas and @ signs in accordance to the new schema requirement. The same change was done in Linux by commit c6d4a8977598 ("ARM: tegra: Rename CPU and EMC OPP table device-tree nodes"), commit ffbe853a3f5a ("ARM: dts: sunxi: Fix OPPs node name") or commit b7072cc5704d ("arm64: dts: qcom: qcs404: Rename CPU and CPR OPP tables"). Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/a1176349448df35127dbac15c1eeb2229505bae7.1652262769.git.michal.simek@amd.com --- arch/arm/dts/zynqmp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 6b711c810e6..a0f664a59db 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -76,7 +76,7 @@ }; }; - cpu_opp_table: cpu-opp-table { + cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2"; opp-shared; opp00 { From d59fac2f3f247470708a1aed1af96802a05e0e61 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 11 May 2022 11:52:48 +0200 Subject: [PATCH 17/24] arm64: zynqmp: Add power domain description for PL PL has own power domain which is not described in DT. That's why add it there by default. Signed-off-by: Michal Simek Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/b38e2ea95dab434bc007f9ed6c438c68149744bf.1652262769.git.michal.simek@amd.com --- arch/arm/dts/zynqmp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index a0f664a59db..dae8f0669df 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -218,6 +218,7 @@ #address-cells = <2>; #size-cells = <2>; ranges; + power-domains = <&zynqmp_firmware PD_PL>; }; amba: axi { From 07f8e78af0637204e5ae33067d6ca17d34b181f6 Mon Sep 17 00:00:00 2001 From: Vishal Patel Date: Wed, 11 May 2022 11:52:49 +0200 Subject: [PATCH 18/24] arm64: zynqmp: Add pwm-fan node and fix ttc0 pwm-cells property Add pwm-fan node to control fan through hwmon and change pwm-cells property to 3 to allow fancontrol utility to function correctly. Signed-off-by: Vishal Patel Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/21b4dfce3e45136a468974ea3dedca03320e27b8.1652262769.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sm-k26-revA.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index a2c88dc34c6..8b2cd512da5 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -87,12 +87,23 @@ <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; }; + + pwm-fan { + compatible = "pwm-fan"; + status = "okay"; + pwms = <&ttc0 2 40000 0>; + }; }; &modepin_gpio { label = "modepin"; }; +&ttc0 { + status = "okay"; + #pwm-cells = <3>; +}; + &uart1 { /* MIO36/MIO37 */ status = "okay"; }; From dda356db648ba3ee6f52efe790b0fa925868258b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 11 May 2022 11:52:50 +0200 Subject: [PATCH 19/24] arm64: zynqmp: Add dmas, gpu, rtc, watchdogs and opp nodes for SOM There are couple of IPs which are enabled in origin HW design which are missing in SOM dt. Add them to match default setup. Signed-off-by: Michal Simek Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/901401beacbea5931fc18cde20c157e5978a7023.1652262769.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sm-k26-revA.dts | 95 +++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index 8b2cd512da5..35fab915172 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -356,3 +356,98 @@ &zynqmp_dpsub { status = "okay"; }; + +&rtc { + status = "okay"; +}; + +&lpd_dma_chan1 { + status = "okay"; +}; + +&lpd_dma_chan2 { + status = "okay"; +}; + +&lpd_dma_chan3 { + status = "okay"; +}; + +&lpd_dma_chan4 { + status = "okay"; +}; + +&lpd_dma_chan5 { + status = "okay"; +}; + +&lpd_dma_chan6 { + status = "okay"; +}; + +&lpd_dma_chan7 { + status = "okay"; +}; + +&lpd_dma_chan8 { + status = "okay"; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&lpd_watchdog { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; + +&cpu_opp_table { + opp00 { + opp-hz = /bits/ 64 <1333333333>; + }; + opp01 { + opp-hz = /bits/ 64 <666666666>; + }; + opp02 { + opp-hz = /bits/ 64 <444444444>; + }; + opp03 { + opp-hz = /bits/ 64 <333333333>; + }; +}; From 725badc5a2e25ec4cdb163ddd78a669a7065e7fb Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Wed, 11 May 2022 11:52:51 +0200 Subject: [PATCH 20/24] Revert "arm64: zynqmp: Add zynqmp firmware specific DT nodes" This reverts commit 50a6bd000f94832658f42fb01b9aaf9e39a52004. As zynqmp mini emmc does not rely on firmware, remove firmware related device tree modes from zynqmp mini emmc dts files. Signed-off-by: T Karthik Reddy Acked-by: Ashok Reddy Soma Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/e69b30d82b0307c563fe72630d9172e53964aeda.1652262769.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-mini-emmc0.dts | 40 ------------------------------ arch/arm/dts/zynqmp-mini-emmc1.dts | 40 ------------------------------ 2 files changed, 80 deletions(-) diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts index 8d9f9ca3725..8467dd8e1cc 100644 --- a/arch/arm/dts/zynqmp-mini-emmc0.dts +++ b/arch/arm/dts/zynqmp-mini-emmc0.dts @@ -41,46 +41,6 @@ clock-frequency = <200000000>; }; - firmware { - zynqmp_firmware: zynqmp-firmware { - compatible = "xlnx,zynqmp-firmware"; - #power-domain-cells = <1>; - method = "smc"; - u-boot,dm-pre-reloc; - - zynqmp_power: zynqmp-power { - u-boot,dm-pre-reloc; - compatible = "xlnx,zynqmp-power"; - mboxes = <&ipi_mailbox_pmu1 0>, - <&ipi_mailbox_pmu1 1>; - mbox-names = "tx", "rx"; - }; - }; - }; - - zynqmp_ipi: zynqmp_ipi { - u-boot,dm-pre-reloc; - compatible = "xlnx,zynqmp-ipi-mailbox"; - xlnx,ipi-id = <0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ipi_mailbox_pmu1: mailbox@ff990400 { - u-boot,dm-pre-reloc; - reg = <0x0 0xff9905c0 0x0 0x20>, - <0x0 0xff9905e0 0x0 0x20>, - <0x0 0xff990e80 0x0 0x20>, - <0x0 0xff990ea0 0x0 0x20>; - reg-names = "local_request_region", - "local_response_region", - "remote_request_region", - "remote_response_region"; - #mbox-cells = <1>; - xlnx,ipi-id = <4>; - }; - }; - amba: amba { compatible = "simple-bus"; #address-cells = <2>; diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts index 5722b762d67..2afcc7751b9 100644 --- a/arch/arm/dts/zynqmp-mini-emmc1.dts +++ b/arch/arm/dts/zynqmp-mini-emmc1.dts @@ -41,46 +41,6 @@ clock-frequency = <200000000>; }; - firmware { - zynqmp_firmware: zynqmp-firmware { - compatible = "xlnx,zynqmp-firmware"; - #power-domain-cells = <1>; - method = "smc"; - u-boot,dm-pre-reloc; - - zynqmp_power: zynqmp-power { - u-boot,dm-pre-reloc; - compatible = "xlnx,zynqmp-power"; - mboxes = <&ipi_mailbox_pmu1 0>, - <&ipi_mailbox_pmu1 1>; - mbox-names = "tx", "rx"; - }; - }; - }; - - zynqmp_ipi: zynqmp_ipi { - u-boot,dm-pre-reloc; - compatible = "xlnx,zynqmp-ipi-mailbox"; - xlnx,ipi-id = <0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ipi_mailbox_pmu1: mailbox@ff990400 { - u-boot,dm-pre-reloc; - reg = <0x0 0xff9905c0 0x0 0x20>, - <0x0 0xff9905e0 0x0 0x20>, - <0x0 0xff990e80 0x0 0x20>, - <0x0 0xff990ea0 0x0 0x20>; - reg-names = "local_request_region", - "local_response_region", - "remote_request_region", - "remote_response_region"; - #mbox-cells = <1>; - xlnx,ipi-id = <4>; - }; - }; - amba: amba { compatible = "simple-bus"; #address-cells = <2>; From e4f1d2881e14145c29d5d8c05896e5bc73a15038 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 11 May 2022 11:52:52 +0200 Subject: [PATCH 21/24] arm64: zynqmp: Add PHY description for SGMII on vck190 SC SGMII requires phy to be configured. The support for this has been added to Linux and U-Boot already that's why also describe the phy via DT. Clock is coming from si5332 chip (output 1) 125MHz which is only one GT line use on this board. Signed-off-by: Michal Simek Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/8ad8d0c2fc9690cc90f95feddf87b0e94a685a43.1652262769.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index f229880a702..72618378230 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -42,6 +42,12 @@ reg = <0x0 0x0 0x0 0x80000000>; }; + si5332_1: si5332_1 { /* u142 - GEM0 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; @@ -135,8 +141,17 @@ xlnx,mio-bank = <1>; }; +/* GEM SGMII */ +&psgtr { + status = "okay"; + /* gem0 */ + clocks = <&si5332_1>; + clock-names = "ref0"; +}; + &gem0 { status = "okay"; + phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; From d5b9b22f7b070a422b630421fdcefade5bf577a5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 11 May 2022 11:52:53 +0200 Subject: [PATCH 22/24] arm64: zynqmp: Add linux,code for fwuen button BTN_MISC looks like the most reasonable option for this button. Button is used by firmware to indicate (after reset, power up) that user wants to do firmware upgrade via firmware update utility. For bootloader or OS is this just user button which is worth to have it mapped. Also button can be used as a wakeup source and pressing it for more time can generate more chars that's why also adding wakeup-source and autorepeat properties. Signed-off-by: Michal Simek Reviewed-by: Radhey Shyam Pandey Link: https://lore.kernel.org/r/7f6d627473632c3c3036ec9f6aaa36e00f4615e2.1652262769.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sm-k26-revA.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index 35fab915172..7c2bfa395da 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -56,6 +56,9 @@ fwuen { label = "fwuen"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + autorepeat; }; }; From 11ed38f5dc12afb581e0fdb2e617c6e25fa81af8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 11 May 2022 11:52:54 +0200 Subject: [PATCH 23/24] arm64: zynqmp: Add DT description for si5328 for zcu102/zcu106 Origin DT binding just specify driver but wasn't aligned with DT binding which came later. Extend description for zcu102 and zcu106 to cover latest binding. Signed-off-by: Michal Simek Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/db66a4bb501183ffbd033da4dd263afdb214f8ec.1652262769.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-zcu102-revA.dts | 21 ++++++++++++++++++++- arch/arm/dts/zynqmp-zcu106-revA.dts | 21 ++++++++++++++++++++- 2 files changed, 40 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index aac798d6e74..c13b52a6aea 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -604,7 +604,26 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - /* SI5328 - u20 */ + si5328: clock-generator@69 {/* SI5328 - u20 */ + compatible = "silabs,si5328"; + reg = <0x69>; + /* + * Chip has interrupt present connected to PL + * interrupt-parent = <&>; + * interrupts = <>; + */ + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + clocks = <&refhdmi>; + clock-names = "xtal"; + clock-output-names = "si5328"; + + si5328_clk: clk0@0 { + reg = <0>; + clock-frequency = <27000000>; + }; + }; }; /* 5 - 7 unconnected */ }; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 03624648cd7..6dfc8fe17bf 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -593,7 +593,26 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - /* SI5328 - u20 */ + si5328: clock-generator@69 {/* SI5328 - u20 */ + compatible = "silabs,si5328"; + reg = <0x69>; + /* + * Chip has interrupt present connected to PL + * interrupt-parent = <&>; + * interrupts = <>; + */ + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + clocks = <&refhdmi>; + clock-names = "xtal"; + clock-output-names = "si5328"; + + si5328_clk: clk0@0 { + reg = <0>; + clock-frequency = <27000000>; + }; + }; }; i2c@5 { #address-cells = <1>; From 594f692f491f0def6c4b6543e158a7f367b35dcc Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 18 May 2022 13:41:31 +0200 Subject: [PATCH 24/24] xilinx: zynqmp: Wire tee for Multi DTB use cases Fix TEE wiring when MULTI_DTB is selected. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/c8523a89d910ae6b8a9971b4e7b3bda89be3dc27.1652874088.git.michal.simek@amd.com --- arch/arm/mach-zynqmp/mkimage_fit_atf.sh | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh index 72a8a3eb771..40ed23b0ba6 100755 --- a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh +++ b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh @@ -140,6 +140,15 @@ cat << __CONF_SECTION1_EOF }; __CONF_SECTION1_EOF else +if [ -f $BL32 ]; then +cat << __CONF_SECTION1_EOF + config_1 { + description = "Multi DTB with TF-A and TEE"; + firmware = "atf"; + loadables = "uboot", "tee", "fdt_1"; + }; +__CONF_SECTION1_EOF +else cat << __CONF_SECTION1_EOF config_1 { description = "Multi DTB with TF-A"; @@ -148,6 +157,7 @@ cat << __CONF_SECTION1_EOF }; __CONF_SECTION1_EOF fi +fi cat << __ITS_EOF };