From 0adf10a87b1500c4d0970085ab102330721eb449 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 11 May 2022 23:09:33 +0200 Subject: [PATCH 1/3] ARM: dts: stm32: Configure Buck3 voltage per PMIC NVM on Avenger96 The Avenger96 board comes in multiple regulator configurations. - rev.100 or rev.200 have Buck3 preconfigured to 3V3 operation on boot and contains extra Enpirion EP53A8LQI DCDC converter which supplies the IO. Reduce Buck3 voltage to 2V9 to not waste power. - rev.200L have Buck3 preconfigured to 1V8 operation and have no Enpirion EP53A8LQI DCDC anymore, the IO is supplied from Buck3. Configure the Buck3 voltage on this board per PMIC NVM settings and update buck3 voltage limits in DT passed to OS before booting OS to prevent potential hardware damage. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi | 2 +- board/dhelectronics/dh_stm32mp1/board.c | 109 +++++++++++++++++++++- 2 files changed, 107 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi index 9937b28548c..e20917824bf 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi @@ -19,7 +19,7 @@ }; &vdd { - regulator-min-microvolt = <2900000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2900000>; }; diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index 67273f90992..d407f0bf592 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -594,14 +594,98 @@ static void board_init_fmc2(void) setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN); } +#ifdef CONFIG_DM_REGULATOR +#define STPMIC_NVM_BUCKS_VOUT_SHR 0xfc +#define STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_1V2 0 +#define STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_1V8 1 +#define STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_3V0 2 +#define STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_3V3 3 +#define STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_MASK GENMASK(1, 0) +#define STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_OFFSET(n) ((((n) - 1) & 3) * 2) +static int board_get_regulator_buck3_nvm_uv_av96(int *uv) +{ + const void *fdt = gd->fdt_blob; + struct udevice *dev; + u8 bucks_vout = 0; + const char *prop; + int len, ret; + + /* Check whether this is Avenger96 board. */ + prop = fdt_getprop(fdt, 0, "compatible", &len); + if (!prop || !len) + return -ENODEV; + + if (!strstr(prop, "avenger96")) + return -EINVAL; + + /* Read out STPMIC1 NVM and determine default Buck3 voltage. */ + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(stpmic1_nvm), + &dev); + if (ret) + return ret; + + ret = misc_read(dev, STPMIC_NVM_BUCKS_VOUT_SHR, &bucks_vout, 1); + if (ret != 1) + return -EINVAL; + + bucks_vout >>= STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_OFFSET(3); + bucks_vout &= STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_MASK; + + /* + * Avenger96 board comes in multiple regulator configurations: + * - rev.100 or rev.200 have Buck3 preconfigured to 3V3 operation on + * boot and contains extra Enpirion EP53A8LQI DCDC converter which + * supplies the IO. Reduce Buck3 voltage to 2V9 to not waste power. + * - rev.200L have Buck3 preconfigured to 1V8 operation and have no + * Enpirion EP53A8LQI DCDC anymore, the IO is supplied from Buck3. + */ + if (bucks_vout == STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_3V3) + *uv = 2900000; + else + *uv = 1800000; + + return 0; +} + +static void board_init_regulator_av96(void) +{ + struct udevice *rdev; + int ret, uv; + + ret = board_get_regulator_buck3_nvm_uv_av96(&uv); + if (ret) /* Not Avenger96 board. */ + return; + + ret = regulator_get_by_devname("buck3", &rdev); + if (ret) + return; + + /* Adjust Buck3 per preconfigured PMIC voltage from NVM. */ + regulator_set_value(rdev, uv); +} + +static void board_init_regulator(void) +{ + board_init_regulator_av96(); + + regulators_enable_boot_on(_DEBUG); +} +#else +static inline int board_get_regulator_buck3_nvm_uv_av96(int *uv) +{ + return -EINVAL; +} + +static inline void board_init_regulator(void) {} +#endif + /* board dependent setup after realloc */ int board_init(void) { board_key_check(); -#ifdef CONFIG_DM_REGULATOR - regulators_enable_boot_on(_DEBUG); -#endif + board_init_regulator(); sysconf_init(); @@ -721,6 +805,25 @@ int board_interface_eth_init(struct udevice *dev, #if defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { + const char *buck3path = "/soc/i2c@5c002000/stpmic@33/regulators/buck3"; + int buck3off, ret, uv; + + ret = board_get_regulator_buck3_nvm_uv_av96(&uv); + if (ret) /* Not Avenger96 board, do not patch Buck3 in DT. */ + return 0; + + buck3off = fdt_path_offset(blob, buck3path); + if (buck3off < 0) /* No Buck3 regulator found. */ + return 0; + + ret = fdt_setprop_u32(blob, buck3off, "regulator-min-microvolt", uv); + if (ret < 0) + return ret; + + ret = fdt_setprop_u32(blob, buck3off, "regulator-max-microvolt", uv); + if (ret < 0) + return ret; + return 0; } #endif From a6d7eeb66db720e77aba587fce6cc88a2003e8ab Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 12 May 2022 09:17:37 +0200 Subject: [PATCH 2/3] spi: stm32_qspi: Always check SR_TCF flags in stm32_qspi_wait_cmd() Currently, SR_TCF flag is checked in case there is data, this criteria is not correct. SR_TCF flags is set when programmed number of bytes have been transferred to the memory device ("bytes" comprised command and data send to the SPI device). So even if there is no data, we must check SR_TCF flag. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- drivers/spi/stm32_qspi.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c index 8f4aabc3d16..3c8faecb54a 100644 --- a/drivers/spi/stm32_qspi.c +++ b/drivers/spi/stm32_qspi.c @@ -150,20 +150,19 @@ static int _stm32_qspi_wait_cmd(struct stm32_qspi_priv *priv, u32 sr; int ret = 0; - if (op->data.nbytes) { - ret = readl_poll_timeout(&priv->regs->sr, sr, - sr & STM32_QSPI_SR_TCF, - STM32_QSPI_CMD_TIMEOUT_US); - if (ret) { - log_err("cmd timeout (stat:%#x)\n", sr); - } else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) { - log_err("transfer error (stat:%#x)\n", sr); - ret = -EIO; - } - /* clear flags */ - writel(STM32_QSPI_FCR_CTCF | STM32_QSPI_FCR_CTEF, &priv->regs->fcr); + ret = readl_poll_timeout(&priv->regs->sr, sr, + sr & STM32_QSPI_SR_TCF, + STM32_QSPI_CMD_TIMEOUT_US); + if (ret) { + log_err("cmd timeout (stat:%#x)\n", sr); + } else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) { + log_err("transfer error (stat:%#x)\n", sr); + ret = -EIO; } + /* clear flags */ + writel(STM32_QSPI_FCR_CTCF | STM32_QSPI_FCR_CTEF, &priv->regs->fcr); + if (!ret) ret = _stm32_qspi_wait_for_not_busy(priv); From b6a469360a0dec01dbbf087c5184a59dda494569 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 12 May 2022 09:17:38 +0200 Subject: [PATCH 3/3] spi: stm32_qspi: Remove SR_BUSY bit check before sending command Waiting for SR_BUSY bit when receiving a new command is not needed. SR_BUSY bit is already managed in the previous command treatment. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- drivers/spi/stm32_qspi.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c index 3c8faecb54a..ceba413727e 100644 --- a/drivers/spi/stm32_qspi.c +++ b/drivers/spi/stm32_qspi.c @@ -255,10 +255,6 @@ static int stm32_qspi_exec_op(struct spi_slave *slave, op->dummy.buswidth, op->data.buswidth, op->addr.val, op->data.nbytes); - ret = _stm32_qspi_wait_for_not_busy(priv); - if (ret) - return ret; - addr_max = op->addr.val + op->data.nbytes + 1; if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) {