From 64e8482f1c94ab6e1fb4837a8744ca8a156c507e Mon Sep 17 00:00:00 2001 From: Zong Li Date: Thu, 14 Dec 2023 14:09:36 +0000 Subject: [PATCH 1/9] cache: add sifive private L2 cache driver This driver is currently responsible for enabling the clock gating feature of SiFive pre core's private L2 cache. Signed-off-by: Zong Li Reviewed-by: Leo Yu-Chi Liang --- drivers/cache/Kconfig | 7 +++++ drivers/cache/Makefile | 1 + drivers/cache/cache-sifive-pl2.c | 44 ++++++++++++++++++++++++++++++++ 3 files changed, 52 insertions(+) create mode 100644 drivers/cache/cache-sifive-pl2.c diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index 6cb8c3e980c..26c2d80a1c5 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -45,4 +45,11 @@ config SIFIVE_CCACHE This driver is for SiFive Composable L2/L3 cache. It enables cache ways of composable cache. +config SIFIVE_PL2 + bool "SiFive private L2 cache" + select CACHE + help + This driver is for SiFive Private L2 cache. It configures registers + to enable the clock gating feature. + endmenu diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile index ad765774e32..78e673d09e5 100644 --- a/drivers/cache/Makefile +++ b/drivers/cache/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o +obj-$(CONFIG_SIFIVE_PL2) += cache-sifive-pl2.o diff --git a/drivers/cache/cache-sifive-pl2.c b/drivers/cache/cache-sifive-pl2.c new file mode 100644 index 00000000000..ae689e18ed5 --- /dev/null +++ b/drivers/cache/cache-sifive-pl2.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 SiFive + */ + +#include +#include +#include +#include +#include +#include + +#define SIFIVE_PL2CHICKENBIT_OFFSET 0x1000 +#define SIFIVE_PL2CHICKENBIT_REGIONCLOCKDISABLE_MASK BIT(3) + +static int sifive_pl2_probe(struct udevice *dev) +{ + fdt_addr_t base; + u32 val; + + base = dev_read_addr(dev); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + /* Enable regionClockDisable bit */ + val = readl((void __iomem *)(base + SIFIVE_PL2CHICKENBIT_OFFSET)); + writel(val & ~SIFIVE_PL2CHICKENBIT_REGIONCLOCKDISABLE_MASK, + (void __iomem *)(base + SIFIVE_PL2CHICKENBIT_OFFSET)); + + return 0; +} + +static const struct udevice_id sifive_pl2_ids[] = { + { .compatible = "sifive,pl2cache0" }, + { .compatible = "sifive,pl2cache1" }, + {} +}; + +U_BOOT_DRIVER(sifive_pl2) = { + .name = "sifive_pl2", + .id = UCLASS_CACHE, + .of_match = sifive_pl2_ids, + .probe = sifive_pl2_probe, +}; From 40c76dfed29ac2173bd32d730979ef2531029048 Mon Sep 17 00:00:00 2001 From: Zong Li Date: Thu, 14 Dec 2023 14:09:37 +0000 Subject: [PATCH 2/9] riscv: cache: support cache enable in SPL stage The power gating feature of pl2 should be enabled as early as possible, it would be better to put it in SPL stage. Signed-off-by: Zong Li Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/lib/sifive_cache.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c index 39b0248c323..d8fe1dfa958 100644 --- a/arch/riscv/lib/sifive_cache.c +++ b/arch/riscv/lib/sifive_cache.c @@ -7,7 +7,10 @@ #include #include #include +#include +#include +#ifndef CONFIG_SPL_BUILD void enable_caches(void) { struct udevice *dev; @@ -25,3 +28,21 @@ void enable_caches(void) log_debug("ccache enable failed"); } } +#else +static inline void probe_cache_device(struct driver *driver, struct udevice *dev) +{ + for (uclass_find_first_device(UCLASS_CACHE, &dev); + dev; + uclass_find_next_device(&dev)) { + if (dev->driver == driver) + device_probe(dev); + } +} + +void enable_caches(void) +{ + struct udevice *dev = NULL; + + probe_cache_device(DM_DRIVER_GET(sifive_pl2), dev); +} +#endif /* !CONFIG_SPL_BUILD */ From 670db88c79ce88ff6c053f6507404bd6752b664f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 20 Dec 2023 15:53:28 +0100 Subject: [PATCH 3/9] riscv: Extend board compatible string with "qemu,mbv" Extend compatible string to match the latest change in dt binding. Fixes: 7576ab2facae ("riscv: Add support for AMD/Xilinx MicroBlaze V") Signed-off-by: Michal Simek Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/xilinx-mbv32.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts index 6a6b8b694bd..94e42c26811 100644 --- a/arch/riscv/dts/xilinx-mbv32.dts +++ b/arch/riscv/dts/xilinx-mbv32.dts @@ -12,7 +12,7 @@ #address-cells = <1>; #size-cells = <1>; model = "AMD MicroBlaze V 32bit"; - compatible = "amd,mbv"; + compatible = "qemu,mbv", "amd,mbv"; cpus: cpus { #address-cells = <1>; From c36eb2f91766642e41ce2e5895cce928e68ddc1f Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Tue, 26 Dec 2023 14:17:32 +0800 Subject: [PATCH 4/9] andes: csr.h: Clean up CSR definition Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin --- arch/riscv/include/asm/arch-andes/csr.h | 18 +++++++----------- arch/riscv/include/asm/csr.h | 1 + 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h index 393d51c6dde..12d5eb6f6c2 100644 --- a/arch/riscv/include/asm/arch-andes/csr.h +++ b/arch/riscv/include/asm/arch-andes/csr.h @@ -12,20 +12,16 @@ #define CSR_MCACHE_CTL 0x7ca #define CSR_MMISC_CTL 0x7d0 -#define CSR_MARCHID 0xf12 #define CSR_MCCTLCOMMAND 0x7cc -#define MCACHE_CTL_IC_EN_OFFSET 0 -#define MCACHE_CTL_DC_EN_OFFSET 1 -#define MCACHE_CTL_CCTL_SUEN_OFFSET 8 -#define MCACHE_CTL_DC_COHEN_OFFSET 19 -#define MCACHE_CTL_DC_COHSTA_OFFSET 20 +/* mcache_ctl register */ + +#define MCACHE_CTL_IC_EN BIT(0) +#define MCACHE_CTL_DC_EN BIT(1) +#define MCACHE_CTL_CCTL_SUEN BIT(8) +#define MCACHE_CTL_DC_COHEN BIT(19) +#define MCACHE_CTL_DC_COHSTA BIT(20) -#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET) -#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET) -#define MCACHE_CTL_CCTL_SUEN BIT(MCACHE_CTL_CCTL_SUEN_OFFSET) -#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET) -#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET) #define CCTL_L1D_WBINVAL_ALL 6 diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 1a15089cae9..986f951c31a 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -142,6 +142,7 @@ #define CSR_CYCLEH 0xc80 #define CSR_TIMEH 0xc81 #define CSR_INSTRETH 0xc82 +#define CSR_MARCHID 0xf12 #define CSR_MHARTID 0xf14 #ifndef __ASSEMBLY__ From b0469041c09e80fdef56a6c8938f8fc74a385a24 Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Tue, 26 Dec 2023 14:17:33 +0800 Subject: [PATCH 5/9] andes: ae350: Implement cache switch via Kconfig Kconfig provides SYS_[I|D]CACHE_OFF config options to switch off caches. Provide the corresponding implementation to the options. Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin --- arch/riscv/cpu/andesv5/cpu.c | 25 ++++++++++++++++--------- board/AndesTech/ae350/ae350.c | 3 ++- 2 files changed, 18 insertions(+), 10 deletions(-) diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c index 63bc24cdfc7..e764f6c5c07 100644 --- a/arch/riscv/cpu/andesv5/cpu.c +++ b/arch/riscv/cpu/andesv5/cpu.c @@ -32,18 +32,25 @@ void harts_early_init(void) if (CONFIG_IS_ENABLED(RISCV_MMODE)) { unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL); - mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_IC_EN | - MCACHE_CTL_DC_EN | MCACHE_CTL_CCTL_SUEN); + mcache_ctl_val |= MCACHE_CTL_CCTL_SUEN; + + if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF)) + mcache_ctl_val |= MCACHE_CTL_IC_EN; + + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + mcache_ctl_val |= (MCACHE_CTL_DC_EN | MCACHE_CTL_DC_COHEN); csr_write(CSR_MCACHE_CTL, mcache_ctl_val); - /* - * Check mcache_ctl.DC_COHEN, we assume this platform does - * not support CM if the bit is hard-wired to 0. - */ - if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) { - /* Wait for DC_COHSTA bit to be set */ - while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA)); + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) { + /* + * Check mcache_ctl.DC_COHEN, we assume this platform does + * not support CM if the bit is hard-wired to 0. + */ + if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) { + /* Wait for DC_COHSTA bit to be set */ + while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA)); + } } } } diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c index 772c6bf1ee3..bef9e3149ee 100644 --- a/board/AndesTech/ae350/ae350.c +++ b/board/AndesTech/ae350/ae350.c @@ -102,7 +102,8 @@ void *board_fdt_blob_setup(int *err) void spl_board_init() { /* enable v5l2 cache */ - enable_caches(); + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + enable_caches(); } #endif From bf12bb99d870cccb666011c917cf3510f9b2d9a2 Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Tue, 26 Dec 2023 14:17:34 +0800 Subject: [PATCH 6/9] andes: cpu: Enable memboost feature Andes CPU has memboost feature including prefetch, write-around and non-blocking load. Enable them by default. Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin --- arch/riscv/cpu/andesv5/cpu.c | 9 ++++++++- arch/riscv/include/asm/arch-andes/csr.h | 6 ++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c index e764f6c5c07..a23b7948d92 100644 --- a/arch/riscv/cpu/andesv5/cpu.c +++ b/arch/riscv/cpu/andesv5/cpu.c @@ -31,8 +31,11 @@ void harts_early_init(void) /* Enable I/D-cache in SPL */ if (CONFIG_IS_ENABLED(RISCV_MMODE)) { unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL); + unsigned long mmisc_ctl_val = csr_read(CSR_MMISC_CTL); - mcache_ctl_val |= MCACHE_CTL_CCTL_SUEN; + mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \ + MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \ + MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN); if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF)) mcache_ctl_val |= MCACHE_CTL_IC_EN; @@ -52,5 +55,9 @@ void harts_early_init(void) while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA)); } } + + mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN; + + csr_write(CSR_MMISC_CTL, mmisc_ctl_val); } } diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h index 12d5eb6f6c2..3f3f05b348a 100644 --- a/arch/riscv/include/asm/arch-andes/csr.h +++ b/arch/riscv/include/asm/arch-andes/csr.h @@ -19,9 +19,15 @@ #define MCACHE_CTL_IC_EN BIT(0) #define MCACHE_CTL_DC_EN BIT(1) #define MCACHE_CTL_CCTL_SUEN BIT(8) +#define MCACHE_CTL_IC_PREFETCH_EN BIT(9) +#define MCACHE_CTL_DC_PREFETCH_EN BIT(10) +#define MCACHE_CTL_DC_WAROUND_EN BIT(13) +#define MCACHE_CTL_L2C_WAROUND_EN BIT(15) #define MCACHE_CTL_DC_COHEN BIT(19) #define MCACHE_CTL_DC_COHSTA BIT(20) +/* mmisc_ctl register */ +#define MMISC_CTL_NON_BLOCKING_EN BIT(8) #define CCTL_L1D_WBINVAL_ALL 6 From 61d5c543f330d660513e7d8c4d53c7db8a847bdc Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Tue, 26 Dec 2023 14:17:35 +0800 Subject: [PATCH 7/9] andes: cpu: Enable cache and TLB ECC support Andes CPU supports cache and TLB ECC. Enable them by default. Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin --- arch/riscv/cpu/andesv5/cpu.c | 3 ++- arch/riscv/include/asm/arch-andes/csr.h | 3 +++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c index a23b7948d92..d25ecba0e88 100644 --- a/arch/riscv/cpu/andesv5/cpu.c +++ b/arch/riscv/cpu/andesv5/cpu.c @@ -35,7 +35,8 @@ void harts_early_init(void) mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \ MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \ - MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN); + MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN | \ + MCACHE_CTL_IC_ECCEN | MCACHE_CTL_DC_ECCEN | MCACHE_CTL_TLB_ECCEN); if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF)) mcache_ctl_val |= MCACHE_CTL_IC_EN; diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h index 3f3f05b348a..028fd01c2f3 100644 --- a/arch/riscv/include/asm/arch-andes/csr.h +++ b/arch/riscv/include/asm/arch-andes/csr.h @@ -18,11 +18,14 @@ #define MCACHE_CTL_IC_EN BIT(0) #define MCACHE_CTL_DC_EN BIT(1) +#define MCACHE_CTL_IC_ECCEN BIT(3) +#define MCACHE_CTL_DC_ECCEN BIT(5) #define MCACHE_CTL_CCTL_SUEN BIT(8) #define MCACHE_CTL_IC_PREFETCH_EN BIT(9) #define MCACHE_CTL_DC_PREFETCH_EN BIT(10) #define MCACHE_CTL_DC_WAROUND_EN BIT(13) #define MCACHE_CTL_L2C_WAROUND_EN BIT(15) +#define MCACHE_CTL_TLB_ECCEN BIT(18) #define MCACHE_CTL_DC_COHEN BIT(19) #define MCACHE_CTL_DC_COHSTA BIT(20) From 936b5030306528c49cf531b1655f954e309ae6c0 Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Tue, 26 Dec 2023 14:54:27 +0800 Subject: [PATCH 8/9] andes: ae350: Save cpu name to env Detect CPU name through marchid and then save it to env. Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin --- board/AndesTech/ae350/ae350.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c index bef9e3149ee..4e53fee5d23 100644 --- a/board/AndesTech/ae350/ae350.c +++ b/board/AndesTech/ae350/ae350.c @@ -13,7 +13,9 @@ #if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH) #include #endif +#include #include +#include #include #include #include @@ -27,6 +29,27 @@ DECLARE_GLOBAL_DATA_PTR; /* * Miscellaneous platform dependent initializations */ +#if IS_ENABLED(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ + long csr_marchid = 0; + const long mask_64 = 0x8000; + const long mask_cpu = 0xff; + char cpu_name[10] = {}; + +#if CONFIG_IS_ENABLED(RISCV_SMODE) + sbi_get_marchid(&csr_marchid); +#elif CONFIG_IS_ENABLED(RISCV_MMODE) + csr_marchid = csr_read(CSR_MARCHID); +#endif + if (mask_64 & csr_marchid) + snprintf(cpu_name, sizeof(cpu_name), "ax%lx", (mask_cpu & csr_marchid)); + else + snprintf(cpu_name, sizeof(cpu_name), "a%lx", (mask_cpu & csr_marchid)); + + return env_set("cpu", cpu_name); +} +#endif #if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL) #define ANDES_SPL_FDT_ADDR (CONFIG_TEXT_BASE - 0x100000) From 9924d44dbcd47bd3664fa9f1f9f24044d83eaebf Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Tue, 26 Dec 2023 14:54:41 +0800 Subject: [PATCH 9/9] andes: ae350: Enable MISC_INIT_R for ae350 platform Enable MISC_INIT_R for ae350 to support CPU name detection and re-sync the configs via make savedefconfig. Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin --- configs/ae350_rv32_defconfig | 5 +++-- configs/ae350_rv32_spl_defconfig | 5 +++-- configs/ae350_rv32_spl_xip_defconfig | 5 +++-- configs/ae350_rv32_xip_defconfig | 5 +++-- configs/ae350_rv64_defconfig | 5 +++-- configs/ae350_rv64_spl_defconfig | 5 +++-- configs/ae350_rv64_spl_xip_defconfig | 5 +++-- configs/ae350_rv64_xip_defconfig | 5 +++-- 8 files changed, 24 insertions(+), 16 deletions(-) diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index 06cd972a0d6..3bfa3e9f8ed 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -11,14 +11,15 @@ CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_ANDES_AE350=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_FIT=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 +CONFIG_SYS_PBSIZE=1050 CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_SYS_PBSIZE=1050 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index f469d5bb2bb..aeb50206d2c 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -16,19 +16,20 @@ CONFIG_RISCV_SMODE=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 +CONFIG_SYS_PBSIZE=1050 CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_SYS_PBSIZE=1050 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index 9672a19c233..f15ec301ce7 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -17,19 +17,20 @@ CONFIG_SPL_XIP=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 +CONFIG_SYS_PBSIZE=1050 CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_SYS_PBSIZE=1050 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index b90200a97e8..c40eb043c5d 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -12,14 +12,15 @@ CONFIG_TARGET_ANDES_AE350=y CONFIG_XIP=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_FIT=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 +CONFIG_SYS_PBSIZE=1050 CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_SYS_PBSIZE=1050 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index a4b9ad6162d..7ae938aeb23 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -11,14 +11,15 @@ CONFIG_TARGET_ANDES_AE350=y CONFIG_ARCH_RV64I=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_FIT=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 +CONFIG_SYS_PBSIZE=1050 CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_SYS_PBSIZE=1050 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 834a0fbbdd5..68ac4325ab8 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -16,19 +16,20 @@ CONFIG_RISCV_SMODE=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 +CONFIG_SYS_PBSIZE=1050 CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_SYS_PBSIZE=1050 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index b52b8d78d71..839ca335d4d 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -17,19 +17,20 @@ CONFIG_SPL_XIP=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 +CONFIG_SYS_PBSIZE=1050 CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_SYS_PBSIZE=1050 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index cc5e751c9b6..5432b6d6d78 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -12,14 +12,15 @@ CONFIG_ARCH_RV64I=y CONFIG_XIP=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_FIT=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 +CONFIG_SYS_PBSIZE=1050 CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_SYS_PBSIZE=1050 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y