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Merge branch '2022-03-31-critical-fixes'

Browse Source 
- Fixes for 2 gateworks platforms, Edison platform, incorrectly showing
  2 logos on LCD screens, not cleaning a generated environment file and
  correct the CONFIG_SYS_IMMR Kconfig migration on a number of MPC85xx
  platforms.
This commit is contained in:
Tom Rini 2022-03-31 08:28:43 -04:00
commit 64b78f5721
53 changed files with 96 additions and 87 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Makefile
View File

@ -2187,8 +2187,8 @@ CLEAN_DIRS += $(MODVERDIR) \
$(filter-out include, $(shell ls -1 $d 2>/dev/null)))) $(filter-out include, $(shell ls -1 $d 2>/dev/null))))
CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \ CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
drivers/video/u_boot_logo.S tools/version.h \ include/generated/env.in drivers/video/u_boot_logo.S \
u-boot* MLO* SPL System.map fit-dtb.blob* \ tools/version.h u-boot* MLO* SPL System.map fit-dtb.blob* \
u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log \ u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log \
lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \ lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \
idbloader.img flash.bin flash.log defconfig keep-syms-lto.c \ idbloader.img flash.bin flash.log defconfig keep-syms-lto.c \

2
arch/Kconfig
View File

@ -363,7 +363,7 @@ config SYS_DISABLE_DCACHE_OPS
this functionality. this functionality.
config SYS_IMMR config SYS_IMMR
hex hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
default 0xFF000000 if MPC8xx default 0xFF000000 if MPC8xx
default 0xF0000000 if ARCH_MPC8313 default 0xF0000000 if ARCH_MPC8313

17
arch/x86/cpu/apollolake/acpi.c
View File

@ -146,25 +146,16 @@ void fill_fadt(struct acpi_fadt *fadt)
fadt->x_pm_tmr_blk.addrl = IOMAP_ACPI_BASE + PM1_TMR; fadt->x_pm_tmr_blk.addrl = IOMAP_ACPI_BASE + PM1_TMR;
} }
static int apl_write_fadt(struct acpi_ctx *ctx, const struct acpi_writer *entry) void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
void *dsdt)
{ {
struct acpi_table_header *header; struct acpi_table_header *header = &fadt->header;
struct acpi_fadt *fadt;
fadt = ctx->current; acpi_fadt_common(fadt, facs, dsdt);
acpi_fadt_common(fadt, ctx->facs, ctx->dsdt);
intel_acpi_fill_fadt(fadt); intel_acpi_fill_fadt(fadt);
fill_fadt(fadt); fill_fadt(fadt);
header = &fadt->header;
header->checksum = table_compute_checksum(fadt, header->length); header->checksum = table_compute_checksum(fadt, header->length);
acpi_add_table(ctx, fadt);
acpi_inc(ctx, sizeof(struct acpi_fadt));
return 0;
} }
ACPI_WRITER(5fadt, "FACS", apl_write_fadt, 0);
int apl_acpi_fill_dmar(struct acpi_ctx *ctx) int apl_acpi_fill_dmar(struct acpi_ctx *ctx)
{ {

27
arch/x86/cpu/baytrail/acpi.c
View File

@ -15,24 +15,20 @@
#include <asm/arch/iomap.h> #include <asm/arch/iomap.h>
#include <dm/uclass-internal.h> #include <dm/uclass-internal.h>
static int baytrail_write_fadt(struct acpi_ctx *ctx, void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
const struct acpi_writer *entry) void *dsdt)
{ {
struct acpi_table_header *header; struct acpi_table_header *header = &(fadt->header);
struct acpi_fadt *fadt;
fadt = ctx->current;
header = &fadt->header;
u16 pmbase = ACPI_BASE_ADDRESS; u16 pmbase = ACPI_BASE_ADDRESS;
memset(fadt, '\0', sizeof(struct acpi_fadt)); memset((void *)fadt, 0, sizeof(struct acpi_fadt));
acpi_fill_header(header, "FACP"); acpi_fill_header(header, "FACP");
header->length = sizeof(struct acpi_fadt); header->length = sizeof(struct acpi_fadt);
header->revision = 4; header->revision = 4;
fadt->firmware_ctrl = (u32)ctx->facs; fadt->firmware_ctrl = (u32)facs;
fadt->dsdt = (u32)ctx->dsdt; fadt->dsdt = (u32)dsdt;
fadt->preferred_pm_profile = ACPI_PM_MOBILE; fadt->preferred_pm_profile = ACPI_PM_MOBILE;
fadt->sci_int = 9; fadt->sci_int = 9;
fadt->smi_cmd = 0; fadt->smi_cmd = 0;
@ -79,9 +75,9 @@ static int baytrail_write_fadt(struct acpi_ctx *ctx,
fadt->reset_reg.addrh = 0; fadt->reset_reg.addrh = 0;
fadt->reset_value = SYS_RST | RST_CPU | FULL_RST; fadt->reset_value = SYS_RST | RST_CPU | FULL_RST;
fadt->x_firmware_ctl_l = (u32)ctx->facs; fadt->x_firmware_ctl_l = (u32)facs;
fadt->x_firmware_ctl_h = 0; fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = (u32)ctx->dsdt; fadt->x_dsdt_l = (u32)dsdt;
fadt->x_dsdt_h = 0; fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
@ -141,14 +137,7 @@ static int baytrail_write_fadt(struct acpi_ctx *ctx,
fadt->x_gpe1_blk.addrh = 0x0; fadt->x_gpe1_blk.addrh = 0x0;
header->checksum = table_compute_checksum(fadt, header->length); header->checksum = table_compute_checksum(fadt, header->length);
acpi_add_table(ctx, fadt);
acpi_inc(ctx, sizeof(struct acpi_fadt));
return 0;
} }
ACPI_WRITER(5fadt, "FACP", baytrail_write_fadt, 0);
int acpi_create_gnvs(struct acpi_global_nvs *gnvs) int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
{ {

27
arch/x86/cpu/quark/acpi.c
View File

@ -10,24 +10,20 @@
#include <asm/arch/global_nvs.h> #include <asm/arch/global_nvs.h>
#include <asm/arch/iomap.h> #include <asm/arch/iomap.h>
static int quark_write_fadt(struct acpi_ctx *ctx, void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
const struct acpi_writer *entry) void *dsdt)
{ {
struct acpi_table_header *header = &(fadt->header);
u16 pmbase = ACPI_PM1_BASE_ADDRESS; u16 pmbase = ACPI_PM1_BASE_ADDRESS;
struct acpi_table_header *header;
struct acpi_fadt *fadt;
fadt = ctx->current; memset((void *)fadt, 0, sizeof(struct acpi_fadt));
header = &fadt->header;
memset(fadt, '\0', sizeof(struct acpi_fadt));
acpi_fill_header(header, "FACP"); acpi_fill_header(header, "FACP");
header->length = sizeof(struct acpi_fadt); header->length = sizeof(struct acpi_fadt);
header->revision = 4; header->revision = 4;
fadt->firmware_ctrl = (u32)ctx->facs; fadt->firmware_ctrl = (u32)facs;
fadt->dsdt = (u32)ctx->dsdt; fadt->dsdt = (u32)dsdt;
fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED; fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED;
fadt->sci_int = 9; fadt->sci_int = 9;
fadt->smi_cmd = 0; fadt->smi_cmd = 0;
@ -74,9 +70,9 @@ static int quark_write_fadt(struct acpi_ctx *ctx,
fadt->reset_reg.addrh = 0; fadt->reset_reg.addrh = 0;
fadt->reset_value = SYS_RST | RST_CPU | FULL_RST; fadt->reset_value = SYS_RST | RST_CPU | FULL_RST;
fadt->x_firmware_ctl_l = (u32)ctx->facs; fadt->x_firmware_ctl_l = (u32)facs;
fadt->x_firmware_ctl_h = 0; fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = (u32)ctx->dsdt; fadt->x_dsdt_l = (u32)dsdt;
fadt->x_dsdt_h = 0; fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
@ -136,14 +132,7 @@ static int quark_write_fadt(struct acpi_ctx *ctx,
fadt->x_gpe1_blk.addrh = 0x0; fadt->x_gpe1_blk.addrh = 0x0;
header->checksum = table_compute_checksum(fadt, header->length); header->checksum = table_compute_checksum(fadt, header->length);
acpi_add_table(ctx, fadt);
acpi_inc(ctx, sizeof(struct acpi_fadt));
return 0;
} }
ACPI_WRITER(5fadt, "FACP", quark_write_fadt, 0);
int acpi_create_gnvs(struct acpi_global_nvs *gnvs) int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
{ {

25
arch/x86/cpu/tangier/acpi.c
View File

@ -16,23 +16,19 @@
#include <asm/arch/iomap.h> #include <asm/arch/iomap.h>
#include <dm/uclass-internal.h> #include <dm/uclass-internal.h>
static int tangier_write_fadt(struct acpi_ctx *ctx, void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
const struct acpi_writer *entry) void *dsdt)
{ {
struct acpi_table_header *header; struct acpi_table_header *header = &(fadt->header);
struct acpi_fadt *fadt;
fadt = ctx->current; memset((void *)fadt, 0, sizeof(struct acpi_fadt));
header = &fadt->header;
memset(fadt, '\0', sizeof(struct acpi_fadt));
acpi_fill_header(header, "FACP"); acpi_fill_header(header, "FACP");
header->length = sizeof(struct acpi_fadt); header->length = sizeof(struct acpi_fadt);
header->revision = 6; header->revision = 6;
fadt->firmware_ctrl = (u32)ctx->facs; fadt->firmware_ctrl = (u32)facs;
fadt->dsdt = (u32)ctx->dsdt; fadt->dsdt = (u32)dsdt;
fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED; fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED;
fadt->iapc_boot_arch = ACPI_FADT_VGA_NOT_PRESENT | fadt->iapc_boot_arch = ACPI_FADT_VGA_NOT_PRESENT |
@ -45,18 +41,13 @@ static int tangier_write_fadt(struct acpi_ctx *ctx,
fadt->minor_revision = 2; fadt->minor_revision = 2;
fadt->x_firmware_ctl_l = (u32)ctx->facs; fadt->x_firmware_ctl_l = (u32)facs;
fadt->x_firmware_ctl_h = 0; fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = (u32)ctx->dsdt; fadt->x_dsdt_l = (u32)dsdt;
fadt->x_dsdt_h = 0; fadt->x_dsdt_h = 0;
header->checksum = table_compute_checksum(fadt, header->length); header->checksum = table_compute_checksum(fadt, header->length);
acpi_inc(ctx, sizeof(struct acpi_fadt));
return 0;
} }
ACPI_WRITER(5fadt, "FACP", tangier_write_fadt, 0);
u32 acpi_fill_madt(u32 current) u32 acpi_fill_madt(u32 current)
{ {

2
arch/x86/include/asm/acpi_table.h
View File

@ -24,6 +24,8 @@ struct acpi_table_header;
/* These can be used by the target port */ /* These can be used by the target port */
void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
void *dsdt);
int acpi_create_madt_lapics(u32 current); int acpi_create_madt_lapics(u32 current);
int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
u32 addr, u32 gsi_base); u32 addr, u32 gsi_base);

15
arch/x86/lib/acpi_table.c
View File

@ -458,6 +458,21 @@ int acpi_write_gnvs(struct acpi_ctx *ctx, const struct acpi_writer *entry)
} }
ACPI_WRITER(4gnvs, "GNVS", acpi_write_gnvs, 0); ACPI_WRITER(4gnvs, "GNVS", acpi_write_gnvs, 0);
static int acpi_write_fadt(struct acpi_ctx *ctx,
const struct acpi_writer *entry)
{
struct acpi_fadt *fadt;
fadt = ctx->current;
acpi_create_fadt(fadt, ctx->facs, ctx->dsdt);
acpi_add_table(ctx, fadt);
acpi_inc(ctx, sizeof(struct acpi_fadt));
return 0;
}
ACPI_WRITER(5fact, "FADT", acpi_write_fadt, 0);
/** /**
* acpi_write_hpet() - Write out a HPET table * acpi_write_hpet() - Write out a HPET table
* *

4
board/gateworks/gw_ventana/gsc.c
View File

@ -41,7 +41,7 @@ int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
break; break;
debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr, debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
n, ret); n, ret);
if (ret != -ENODEV) if (ret != -EREMOTEIO)
break; break;
mdelay(10); mdelay(10);
} }
@ -60,7 +60,7 @@ int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
break; break;
debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr, debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
n, ret); n, ret);
if (ret != -ENODEV) if (ret != -EREMOTEIO)
break; break;
mdelay(10); mdelay(10);
} }

13
board/gateworks/venice/venice.c
View File

@ -21,19 +21,10 @@ DECLARE_GLOBAL_DATA_PTR;
int board_phys_sdram_size(phys_size_t *size) int board_phys_sdram_size(phys_size_t *size)
{ {
const fdt64_t *val; if (!size)
int offset;
int len;
/* get size from dt which SPL updated per EEPROM config */
offset = fdt_path_offset(gd->fdt_blob, "/memory");
if (offset < 0)
return -EINVAL; return -EINVAL;
val = fdt_getprop(gd->fdt_blob, offset, "reg", &len); *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
if (len < sizeof(*val) * 2)
return -EINVAL;
*size = get_unaligned_be64(&val[1]);
return 0; return 0;
} }

1
configs/MPC8548CDS_36BIT_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xE0000000
CONFIG_SYS_TEXT_BASE=0xFFF80000 CONFIG_SYS_TEXT_BASE=0xFFF80000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/MPC8548CDS_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xE0000000
CONFIG_SYS_TEXT_BASE=0xFFF80000 CONFIG_SYS_TEXT_BASE=0xFFF80000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/MPC8548CDS_legacy_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xE0000000
CONFIG_SYS_TEXT_BASE=0xFFF80000 CONFIG_SYS_TEXT_BASE=0xFFF80000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/P1010RDB-PA_36BIT_NAND_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SIZE=0x4000

1
configs/P1010RDB-PA_36BIT_NOR_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/P1010RDB-PA_36BIT_SDCARD_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y

1
configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y

1
configs/P1010RDB-PA_NAND_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SIZE=0x4000

1
configs/P1010RDB-PA_NOR_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/P1010RDB-PA_SDCARD_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y

1
configs/P1010RDB-PA_SPIFLASH_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y

1
configs/P1010RDB-PB_36BIT_NAND_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SIZE=0x4000

1
configs/P1010RDB-PB_36BIT_NOR_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/P1010RDB-PB_36BIT_SDCARD_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y

1
configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y

1
configs/P1010RDB-PB_NAND_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SIZE=0x4000

1
configs/P1010RDB-PB_NOR_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/P1010RDB-PB_SDCARD_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y

1
configs/P1010RDB-PB_SPIFLASH_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y

1
configs/P1020RDB-PC_36BIT_NAND_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SIZE=0x4000

1
configs/P1020RDB-PC_36BIT_SDCARD_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y

1
configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y

1
configs/P1020RDB-PC_36BIT_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/P1020RDB-PC_NAND_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SIZE=0x4000

1
configs/P1020RDB-PC_SDCARD_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y

1
configs/P1020RDB-PC_SPIFLASH_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y

1
configs/P1020RDB-PC_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/P1020RDB-PD_NAND_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SIZE=0x20000

1
configs/P1020RDB-PD_SDCARD_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y

1
configs/P1020RDB-PD_SPIFLASH_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y

1
configs/P1020RDB-PD_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/P2020RDB-PC_36BIT_NAND_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SIZE=0x4000

1
configs/P2020RDB-PC_36BIT_SDCARD_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y

1
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y

1
configs/P2020RDB-PC_36BIT_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/P2020RDB-PC_NAND_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SIZE=0x4000

1
configs/P2020RDB-PC_SDCARD_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y

1
configs/P2020RDB-PC_SPIFLASH_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y

1
configs/P2020RDB-PC_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xFFE00000
CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socrates_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_PPC=y CONFIG_PPC=y
CONFIG_SYS_IMMR=0xE0000000
CONFIG_SYS_TEXT_BASE=0xfff80000 CONFIG_SYS_TEXT_BASE=0xfff80000
CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000

3
drivers/video/video-uclass.c
View File

@ -407,7 +407,8 @@ static int video_post_probe(struct udevice *dev)
return ret; return ret;
} }
if (IS_ENABLED(CONFIG_VIDEO_LOGO) && !plat->hide_logo) { if (IS_ENABLED(CONFIG_VIDEO_LOGO) &&
!IS_ENABLED(CONFIG_SPLASH_SCREEN) && !plat->hide_logo) {
ret = show_splash(dev); ret = show_splash(dev);
if (ret) { if (ret) {
log_debug("Cannot show splash screen\n"); log_debug("Cannot show splash screen\n");

2
include/configs/imx8mm_venice.h
View File

@ -83,7 +83,7 @@
/* SDRAM configuration */ /* SDRAM configuration */
#define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */ #define PHYS_SDRAM_SIZE SZ_4G
#define CONFIG_SYS_BOOTM_LEN SZ_256M #define CONFIG_SYS_BOOTM_LEN SZ_256M
/* UART */ /* UART */

2
include/configs/imx8mn_venice.h
View File

@ -80,7 +80,7 @@
/* SDRAM configuration */ /* SDRAM configuration */
#define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE SZ_1G #define PHYS_SDRAM_SIZE SZ_4G
#define CONFIG_SYS_BOOTM_LEN SZ_256M #define CONFIG_SYS_BOOTM_LEN SZ_256M
/* UART */ /* UART */