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phy: marvell: a3700: Use reg_set16 instead of phy_write16

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The macro phy_write16 is not used by the rest of the code,
phy_read16 is not used at all.
We also change the macro SGMIIPHY_ADDR to a static inline function.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Marek Behún 2018-04-24 17:21:13 +02:00 committed by Stefan Roese
parent fae82c8f83
commit 63cfff9fde
2 changed files with 22 additions and 18 deletions
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25
drivers/phy/marvell/comphy_a3700.c
View File

@ -610,7 +610,7 @@ static void comphy_sgmii_phy_init(u32 lane, u32 speed)
val = sgmii_phy_init[addr]; val = sgmii_phy_init[addr];
} }
phy_write16(lane, addr, val, 0xFFFF); reg_set16(sgmiiphy_addr(lane, addr), val, 0xFFFF);
} }
} }
@ -673,26 +673,26 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
mdelay(10); mdelay(10);
/* 9. Program COMPHY register PHY_MODE */ /* 9. Program COMPHY register PHY_MODE */
phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR, reg_set16(sgmiiphy_addr(lane, PHY_PWR_PLL_CTRL_ADDR),
PHY_MODE_SGMII << rf_phy_mode_shift, rf_phy_mode_mask); PHY_MODE_SGMII << rf_phy_mode_shift, rf_phy_mode_mask);
/* /*
* 10. Set COMPHY register REFCLK_SEL to select the correct REFCLK * 10. Set COMPHY register REFCLK_SEL to select the correct REFCLK
* source * source
*/ */
phy_write16(lane, PHY_MISC_REG0_ADDR, 0, rb_ref_clk_sel); reg_set16(sgmiiphy_addr(lane, PHY_MISC_REG0_ADDR), 0, rb_ref_clk_sel);
/* /*
* 11. Set correct reference clock frequency in COMPHY register * 11. Set correct reference clock frequency in COMPHY register
* REF_FREF_SEL. * REF_FREF_SEL.
*/ */
if (get_ref_clk() == 40) { if (get_ref_clk() == 40) {
phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR, reg_set16(sgmiiphy_addr(lane, PHY_PWR_PLL_CTRL_ADDR),
0x4 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask); 0x4 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
} else { } else {
/* 25MHz */ /* 25MHz */
phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR, reg_set16(sgmiiphy_addr(lane, PHY_PWR_PLL_CTRL_ADDR),
0x1 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask); 0x1 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
} }
/* 12. Program COMPHY register PHY_GEN_MAX[1:0] */ /* 12. Program COMPHY register PHY_GEN_MAX[1:0] */
@ -708,7 +708,8 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
* bus width * bus width
*/ */
/* 10bit */ /* 10bit */
phy_write16(lane, PHY_DIG_LB_EN_ADDR, 0, rf_data_width_mask); reg_set16(sgmiiphy_addr(lane, PHY_DIG_LB_EN_ADDR), 0,
rf_data_width_mask);
/* /*
* 14. As long as DFE function needs to be enabled in any mode, * 14. As long as DFE function needs to be enabled in any mode,
@ -751,10 +752,12 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
* 18. Check the PHY Polarity invert bit * 18. Check the PHY Polarity invert bit
*/ */
if (invert & PHY_POLARITY_TXD_INVERT) if (invert & PHY_POLARITY_TXD_INVERT)
phy_write16(lane, PHY_SYNC_PATTERN_ADDR, phy_txd_inv, 0); reg_set16(sgmiiphy_addr(lane, PHY_SYNC_PATTERN_ADDR),
phy_txd_inv, 0);
if (invert & PHY_POLARITY_RXD_INVERT) if (invert & PHY_POLARITY_RXD_INVERT)
phy_write16(lane, PHY_SYNC_PATTERN_ADDR, phy_rxd_inv, 0); reg_set16(sgmiiphy_addr(lane, PHY_SYNC_PATTERN_ADDR),
phy_rxd_inv, 0);
/* /*
* 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 * 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1

15
drivers/phy/marvell/comphy_a3700.h
View File

@ -60,13 +60,14 @@
#define USB32_CTRL_BASE MVEBU_REG(0x05D800) #define USB32_CTRL_BASE MVEBU_REG(0x05D800)
#define USB3PHY_SHFT 2 #define USB3PHY_SHFT 2
#define SGMIIPHY_BASE(l) (l == 1 ? USB3PHY_BASE : PCIEPHY_BASE) static inline void __iomem *sgmiiphy_addr(u32 lane, u32 addr)
#define SGMIIPHY_ADDR(l, a) \ {
((void __iomem *)(((a & 0x00007FF) * 2) + SGMIIPHY_BASE(l))) addr = (addr & 0x00007FF) * 2;
if (lane == 1)
#define phy_read16(l, a) read16((void __iomem *)SGMIIPHY_ADDR(l, a)) return PCIEPHY_BASE + addr;
#define phy_write16(l, a, data, mask) \ else
reg_set16(SGMIIPHY_ADDR(l, a), data, mask) return USB3PHY_BASE + addr;
}
/* units */ /* units */
#define PCIE 1 #define PCIE 1