From 8fbcc0e0e839a8e25f636c76e59311033d3817b5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 13 Nov 2025 12:54:51 +0100 Subject: [PATCH 1/8] boot: Assure FDT is always at 8-byte aligned address The fitImage may contain FDT at 4-byte aligned address, because alignment of DT tags is 4 bytes. However, libfdt and also Linux expects DT to be at 8-byte aligned address. Make sure that the DTs embedded in fitImages are always used from 8-byte aligned addresses. In case the DT is decompressed, make sure the target buffer is 8-byte aligned. In case the DT is only loaded, make sure the target buffer is 8-byte aligned too. Signed-off-by: Marek Vasut --- boot/image-fit.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/boot/image-fit.c b/boot/image-fit.c index 2f2d3e9304d..cccaa48f683 100644 --- a/boot/image-fit.c +++ b/boot/image-fit.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #ifdef CONFIG_DM_HASH @@ -36,6 +35,7 @@ DECLARE_GLOBAL_DATA_PTR; #include #include #include +#include #include #include @@ -2279,7 +2279,7 @@ int fit_image_load(struct bootm_headers *images, ulong addr, log_debug("decompressing image\n"); if (load == data) { - loadbuf = malloc(max_decomp_len); + loadbuf = memalign(8, max_decomp_len); load = map_to_sysmem(loadbuf); } else { loadbuf = map_sysmem(load, max_decomp_len); @@ -2291,6 +2291,11 @@ int fit_image_load(struct bootm_headers *images, ulong addr, return -ENOEXEC; } len = load_end - load; + } else if (load_op != FIT_LOAD_IGNORED && image_type == IH_TYPE_FLATDT && + ((uintptr_t)buf & 7)) { + loadbuf = memalign(8, len); + load = map_to_sysmem(loadbuf); + memcpy(loadbuf, buf, len); } else if (load != data) { log_debug("copying\n"); loadbuf = map_sysmem(load, len); From eb726cf6ae0e202f36aabcce88e21358cd3a7c5b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 13 Nov 2025 12:55:28 +0100 Subject: [PATCH 2/8] arm: qemu: Eliminate fdt_high and initrd_high misuse The fdt_high and initrd_high have nasty side-effects , which may lead to DT placed at 4-byte aligned offset when used in place, which then prevents Linux on arm64 from booting. This is difficult to debug and inobvious, with little to no gain. Remove this to let U-Boot place the DT at correctly aligned address. Signed-off-by: Marek Vasut Reviewed-by: Tom Rini --- board/emulation/qemu-arm/qemu-arm.env | 2 -- 1 file changed, 2 deletions(-) diff --git a/board/emulation/qemu-arm/qemu-arm.env b/board/emulation/qemu-arm/qemu-arm.env index fb4adef281e..f74f251712a 100644 --- a/board/emulation/qemu-arm/qemu-arm.env +++ b/board/emulation/qemu-arm/qemu-arm.env @@ -5,8 +5,6 @@ stdin=serial,usbkbd stdout=serial,vidconsole stderr=serial,vidconsole -fdt_high=0xffffffff -initrd_high=0xffffffff fdt_addr=0x40000000 scriptaddr=0x40200000 pxefile_addr_r=0x40300000 From d9e183a04c92d96c8f8b145c0b789c62bdfc2605 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 13 Nov 2025 12:56:09 +0100 Subject: [PATCH 3/8] MIPS: Assure end of U-Boot is at 8-byte aligned offset Make sure the end of U-Boot is at 8-byte aligned offset, not 4-byte aligned offset. This allows safely appending DT at the end of U-Boot with the guarantee that the DT will be at 8-byte aligned offset. This 8-byte alignment is now checked by newer libfdt 1.7.2 . Signed-off-by: Marek Vasut --- arch/mips/cpu/u-boot.lds | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/cpu/u-boot.lds b/arch/mips/cpu/u-boot.lds index 9a4ebcd1515..133ea05df3d 100644 --- a/arch/mips/cpu/u-boot.lds +++ b/arch/mips/cpu/u-boot.lds @@ -37,7 +37,7 @@ SECTIONS KEEP(*(SORT(__u_boot_list*))); } - . = ALIGN(4); + . = ALIGN(8); __image_copy_end = .; __init_end = .; @@ -56,7 +56,7 @@ SECTIONS . += CONFIG_MIPS_RELOCATION_TABLE_SIZE - 4; } - . = ALIGN(4); + . = ALIGN(8); _end = .; .bss __rel_start (OVERLAY) : { @@ -64,7 +64,7 @@ SECTIONS *(.sbss.*) *(.bss.*) *(COMMON) - . = ALIGN(4); + . = ALIGN(8); __bss_end = .; } From 9bde0c1da52e9421c84fa622849d85dbb77603e6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 13 Nov 2025 12:56:29 +0100 Subject: [PATCH 4/8] sandbox: Fix DT compiler address warnings in sandbox DTs Trivially fix the following warnings in sandbox DTs, which show up with DTC 1.7.2. Fill in the missing address and adjust emulated I2C address to fit the 7bit address limit: " arch/sandbox/dts/sandbox.dtsi:138.30-140.5: Warning (i2c_bus_reg): /i2c@0/sandbox_pmic: I2C bus unit address format error, expected "40" arch/sandbox/dts/sandbox.dtsi:146.18-161.5: Warning (i2c_bus_reg): /i2c@0/emul: I2C bus unit address format error, expected "ff" arch/sandbox/dts/sandbox.dtsi:148.4-17: Warning (i2c_bus_reg): /i2c@0/emul:reg: I2C address must be less than 7-bits, got "0xff". Set I2C_TEN_BIT_ADDRESS for 10 bit addresses or fix the property " " arch/sandbox/dts/.test.dtb.pre.tmp:912.18-926.5: Warning (i2c_bus_reg): /i2c@0/emul: I2C bus unit address format error, expected "ff" arch/sandbox/dts/.test.dtb.pre.tmp:913.4-17: Warning (i2c_bus_reg): /i2c@0/emul:reg: I2C address must be less than 7-bits, got "0xff". Set I2C_TEN_BIT_ADDRESS for 10 bit addresses or fix the property arch/sandbox/dts/.test.dtb.pre.tmp:928.30-931.5: Warning (i2c_bus_reg): /i2c@0/sandbox_pmic: I2C bus unit address format error, expected "40" " Fix up pmic test to match. Signed-off-by: Marek Vasut Reviewed-by: Heiko Schocher Reviewed-by: Mattijs Korpershoek --- arch/sandbox/dts/sandbox.dtsi | 6 +++--- arch/sandbox/dts/test.dts | 6 +++--- test/dm/pmic.c | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi index 8a115c503dc..02b03894eaf 100644 --- a/arch/sandbox/dts/sandbox.dtsi +++ b/arch/sandbox/dts/sandbox.dtsi @@ -135,7 +135,7 @@ sandbox,emul = <&emul0>; bootph-pre-ram; }; - sandbox_pmic: sandbox_pmic { + sandbox_pmic: sandbox_pmic@40 { reg = <0x40>; }; @@ -143,9 +143,9 @@ reg = <0x41>; }; - i2c_emul: emul { + i2c_emul: emul@7f { bootph-pre-ram; - reg = <0xff>; + reg = <0x7f>; compatible = "sandbox,i2c-emul-parent"; emul_eeprom: emul-eeprom { compatible = "sandbox,i2c-eeprom"; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 0b3fc505e53..bb17a687862 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -947,8 +947,8 @@ sandbox,emul = <&emul1>; }; - i2c_emul: emul { - reg = <0xff>; + i2c_emul: emul@7f { + reg = <0x7f>; compatible = "sandbox,i2c-emul-parent"; emul_eeprom: emul-eeprom { compatible = "sandbox,i2c-eeprom"; @@ -963,7 +963,7 @@ }; }; - sandbox_pmic: sandbox_pmic { + sandbox_pmic: sandbox_pmic@40 { reg = <0x40>; sandbox,emul = <&emul_pmic0>; }; diff --git a/test/dm/pmic.c b/test/dm/pmic.c index 70dd18f5df0..b163b8e315d 100644 --- a/test/dm/pmic.c +++ b/test/dm/pmic.c @@ -39,7 +39,7 @@ static inline int power_pmic_get(struct unit_test_state *uts, char *name) /* Test PMIC get method */ static int dm_test_power_pmic_get(struct unit_test_state *uts) { - power_pmic_get(uts, "sandbox_pmic"); + power_pmic_get(uts, "sandbox_pmic@40"); return 0; } @@ -57,7 +57,7 @@ DM_TEST(dm_test_power_pmic_mc34708_get, UTF_SCAN_FDT); /* Test PMIC I/O */ static int dm_test_power_pmic_io(struct unit_test_state *uts) { - const char *name = "sandbox_pmic"; + const char *name = "sandbox_pmic@40"; uint8_t out_buffer, in_buffer; struct udevice *dev; int reg_count, i; From 416ceee82f7abe4065446a0b97252c8c1573438c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 13 Nov 2025 12:56:30 +0100 Subject: [PATCH 5/8] sandbox: Fix DT compiler pin warnings in sandbox DTs Trivially fix the following warnings in sandbox DTs, which show up with DTC 1.7.2. Assign pin groups less confusing node names with pins- prefix to avoid confusing DT compiler into thinking the node is really a bus node: " arch/sandbox/dts/.test.dtb.pre.tmp:1831.20-1841.5: Warning (i2c_bus_bridge): /pinctrl/i2c: incorrect #address-cells for I2C bus arch/sandbox/dts/.test.dtb.pre.tmp:1831.20-1841.5: Warning (i2c_bus_bridge): /pinctrl/i2c: incorrect #size-cells for I2C bus arch/sandbox/dts/test.dtb: Warning (i2c_bus_reg): Failed prerequisite 'i2c_bus_bridge' arch/sandbox/dts/.test.dtb.pre.tmp:1848.20-1856.5: Warning (spi_bus_bridge): /pinctrl/spi: incorrect #address-cells for SPI bus arch/sandbox/dts/.test.dtb.pre.tmp:1848.20-1856.5: Warning (spi_bus_bridge): /pinctrl/spi: incorrect #size-cells for SPI bus arch/sandbox/dts/test.dtb: Warning (spi_bus_reg): Failed prerequisite 'spi_bus_bridge' " Signed-off-by: Marek Vasut Reviewed-by: Mattijs Korpershoek Reviewed-by: Heiko Schocher --- arch/sandbox/dts/test.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index bb17a687862..cd53c170171 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -1842,7 +1842,7 @@ pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>; pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>; - pinctrl_gpios: gpios { + pinctrl_gpios: pins-gpios { gpio0 { pins = "P5"; function = "GPIO"; @@ -1866,7 +1866,7 @@ }; }; - pinctrl_i2c: i2c { + pinctrl_i2c: pins-i2c { groups { groups = "I2C_UART"; function = "I2C"; @@ -1878,12 +1878,12 @@ }; }; - pinctrl_i2s: i2s { + pinctrl_i2s: pins-i2s { groups = "SPI_I2S"; function = "I2S"; }; - pinctrl_spi: spi { + pinctrl_spi: pins-spi { groups = "SPI_I2S"; function = "SPI"; From f74353099016a22500830adda2bb0558322b414c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 13 Nov 2025 12:57:52 +0100 Subject: [PATCH 6/8] test/py: Use aligned address for overlays in 'extension' test The 'extension' test would set 'extension_overlay_addr' variable to decimal 4096 due to conversion in python. The 'extension_overlay_addr' is however sampled using env_get_hex("extension_overlay_addr", 0); which converts the 4096 to 0x4096 and uses that as DT overlay address, which is unaligned. Fix this by setting extension_overlay_addr to 0x1000 as intended, which is aligned. Signed-off-by: Marek Vasut Reviewed-by: Tom Rini Reviewed-by: Mattijs Korpershoek --- test/py/tests/test_extension.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/py/tests/test_extension.py b/test/py/tests/test_extension.py index 61223496054..6daab0c9782 100644 --- a/test/py/tests/test_extension.py +++ b/test/py/tests/test_extension.py @@ -38,7 +38,7 @@ def test_extension(ubman): assert('overlay1.dtbo' in output) ubman.run_command_list([ - 'setenv extension_overlay_addr %s' % (overlay_addr), + 'setenv extension_overlay_addr %x' % (overlay_addr), 'setenv extension_overlay_cmd \'host load hostfs - ${extension_overlay_addr} %s${extension_overlay_name}\'' % (os.path.join(ubman.config.build_dir, OVERLAY_DIR))]) output = ubman.run_command('extension apply 0') From 8c0d78ddc4989fe95337b20e392a76e796001eb6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 16 Nov 2025 01:14:32 +0100 Subject: [PATCH 7/8] xtensa: Assure end of U-Boot is at 8-byte aligned offset Make sure the end of U-Boot is at 8-byte aligned offset, not 4-byte aligned offset. This allows safely appending DT at the end of U-Boot with the guarantee that the DT will be at 8-byte aligned offset. This 8-byte alignment is now checked by newer libfdt 1.7.2 . Signed-off-by: Marek Vasut --- arch/xtensa/cpu/u-boot.lds | 2 +- arch/xtensa/include/asm/ldscript.h | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/xtensa/cpu/u-boot.lds b/arch/xtensa/cpu/u-boot.lds index 72e4b9a706e..6894d4c327b 100644 --- a/arch/xtensa/cpu/u-boot.lds +++ b/arch/xtensa/cpu/u-boot.lds @@ -78,7 +78,7 @@ SECTIONS SECTION_text(XTENSA_SYS_TEXT_ADDR, FOLLOWING(.DoubleExceptionVector.text)) SECTION_rodata(ALIGN(16), FOLLOWING(.text)) SECTION_u_boot_list(ALIGN(16), FOLLOWING(.rodata)) - SECTION_data(ALIGN(16), FOLLOWING(__u_boot_list)) + SECTION_data(ALIGN(16), FOLLOWINGDT(__u_boot_list)) __reloc_end = .; __init_end = .; diff --git a/arch/xtensa/include/asm/ldscript.h b/arch/xtensa/include/asm/ldscript.h index bcf0fd5a744..50d3b390405 100644 --- a/arch/xtensa/include/asm/ldscript.h +++ b/arch/xtensa/include/asm/ldscript.h @@ -21,6 +21,9 @@ #define FORCE_OUTPUT . = . #define FOLLOWING(sec) \ AT(((LOADADDR(sec) + SIZEOF(sec) + ALIGN_LMA-1)) & ~(ALIGN_LMA-1)) +#define ALIGN_LMA_DT 8 +#define FOLLOWINGDT(sec) \ + AT(((LOADADDR(sec) + SIZEOF(sec) + ALIGN_LMA_DT-1)) & ~(ALIGN_LMA_DT-1)) /* * Specify an output section that will be added to the ROM store table @@ -110,6 +113,7 @@ ___u_boot_list_start = ABSOLUTE(.); \ KEEP(*(SORT(__u_boot_list*))); \ ___u_boot_list_end = ABSOLUTE(.); \ + . = ALIGN(ALIGN_LMA_DT); \ } #define SECTION_data(_vma_, _lma_) \ @@ -130,6 +134,7 @@ *(.eh_frame) \ *(.dynamic) \ *(.gnu.version_d) \ + . = ALIGN(ALIGN_LMA_DT); \ _data_end = ABSOLUTE(.); \ } From 534eaa4d4dec9efed662189fd68f78b3b7b1e636 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 16 Nov 2025 01:19:01 +0100 Subject: [PATCH 8/8] xtensa: Fix big endian build Make sure the correct PLATFORM_...FLAGS are assigned in each case, consistently. Assign PLATFORM_ELFFLAGS for both LE and BE case. The previous PLATFORM_CPPFLAGS makes no sense for these particular parameters, which are passed to objcopy. Signed-off-by: Marek Vasut --- arch/xtensa/config.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/xtensa/config.mk b/arch/xtensa/config.mk index 200b66f8504..75888720d4a 100644 --- a/arch/xtensa/config.mk +++ b/arch/xtensa/config.mk @@ -9,7 +9,7 @@ PLATFORM_CPPFLAGS += -D__XTENSA__ -mlongcalls -mforce-no-pic \ LDFLAGS_FINAL += --gc-sections ifeq ($(CONFIG_SYS_BIG_ENDIAN),y) -PLATFORM_CPPFLAGS += -B xtensa -O elf32-xtensa-be +PLATFORM_ELFFLAGS += -B xtensa -O elf32-xtensa-be else PLATFORM_ELFFLAGS += -B xtensa -O elf32-xtensa-le endif