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pinctrl: rockchip: Add support for RK3506
Add pinctrl driver for RK3506. Imported from vendor U-Boot linux-6.1-stan-rkr6 tag with adjustments to use regmap_update_bits(). Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Tested-by: Aaron Griffith <aargri@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Ye Zhang
Tom Rini
parent
ea45ebafd8
commit
6225eeff57
@ -14,6 +14,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl-rk3308.o
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obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
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obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
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obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
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obj-$(CONFIG_ROCKCHIP_RK3506) += pinctrl-rk3506.o
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obj-$(CONFIG_ROCKCHIP_RK3528) += pinctrl-rk3528.o
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obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
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obj-$(CONFIG_ROCKCHIP_RK3576) += pinctrl-rk3576.o
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462
drivers/pinctrl/rockchip/pinctrl-rk3506.c
Normal file
462
drivers/pinctrl/rockchip/pinctrl-rk3506.c
Normal file
@ -0,0 +1,462 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
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*/
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include <regmap.h>
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#include <syscon.h>
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#include "pinctrl-rockchip.h"
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#include <dt-bindings/pinctrl/rockchip.h>
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static int rk3506_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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int iomux_num = (pin / 8);
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struct regmap *regmap;
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int reg, mask;
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u8 bit;
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u32 data, rmask;
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if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
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regmap = priv->regmap_pmu;
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else
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regmap = priv->regmap_base;
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if (bank->bank_num == 1)
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regmap = priv->regmap_ioc1;
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else if (bank->bank_num == 4)
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return 0;
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reg = bank->iomux[iomux_num].offset;
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if ((pin % 8) >= 4)
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reg += 0x4;
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bit = (pin % 4) * 4;
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mask = 0xf;
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if (bank->recalced_mask & BIT(pin))
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rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
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data = (mask << (bit + 16));
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rmask = data | (data >> 16);
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data |= (mux & mask) << bit;
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return regmap_update_bits(regmap, reg, rmask, data);
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}
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#define RK3506_DRV_BITS_PER_PIN 8
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#define RK3506_DRV_PINS_PER_REG 2
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#define RK3506_DRV_GPIO0_A_OFFSET 0x100
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#define RK3506_DRV_GPIO0_D_OFFSET 0x830
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#define RK3506_DRV_GPIO1_OFFSET 0x140
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#define RK3506_DRV_GPIO2_OFFSET 0x180
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#define RK3506_DRV_GPIO3_OFFSET 0x1c0
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#define RK3506_DRV_GPIO4_OFFSET 0x840
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static int rk3506_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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int ret = 0;
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switch (bank->bank_num) {
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case 0:
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*regmap = priv->regmap_pmu;
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if (pin_num > 24) {
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ret = -EINVAL;
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} else if (pin_num < 24) {
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*reg = RK3506_DRV_GPIO0_A_OFFSET;
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} else {
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*reg = RK3506_DRV_GPIO0_D_OFFSET;
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*bit = 3;
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return 0;
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}
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break;
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case 1:
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*regmap = priv->regmap_ioc1;
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if (pin_num < 28)
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*reg = RK3506_DRV_GPIO1_OFFSET;
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else
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ret = -EINVAL;
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break;
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case 2:
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*regmap = priv->regmap_base;
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if (pin_num < 17)
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*reg = RK3506_DRV_GPIO2_OFFSET;
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else
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ret = -EINVAL;
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break;
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case 3:
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*regmap = priv->regmap_base;
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if (pin_num < 15)
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*reg = RK3506_DRV_GPIO3_OFFSET;
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else
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ret = -EINVAL;
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break;
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case 4:
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*regmap = priv->regmap_base;
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if (pin_num < 8 || pin_num > 11) {
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ret = -EINVAL;
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} else {
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*reg = RK3506_DRV_GPIO4_OFFSET;
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*bit = 10;
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return 0;
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}
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break;
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default:
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ret = -EINVAL;
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break;
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}
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if (ret) {
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debug("unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
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return ret;
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}
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*reg += ((pin_num / RK3506_DRV_PINS_PER_REG) * 4);
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*bit = pin_num % RK3506_DRV_PINS_PER_REG;
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*bit *= RK3506_DRV_BITS_PER_PIN;
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return 0;
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}
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static int rk3506_set_drive(struct rockchip_pin_bank *bank,
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int pin_num, int strength)
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{
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struct regmap *regmap;
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int reg, ret, i;
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u32 data, rmask;
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u8 bit;
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int rmask_bits = RK3506_DRV_BITS_PER_PIN;
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ret = rk3506_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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if (ret)
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return ret;
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for (i = 0, ret = 1; i < strength; i++)
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ret = (ret << 1) | 1;
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if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) {
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rmask_bits = 2;
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ret = strength;
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}
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/* enable the write to the equivalent lower bits */
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data = ((1 << rmask_bits) - 1) << (bit + 16);
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rmask = data | (data >> 16);
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data |= (ret << bit);
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return regmap_update_bits(regmap, reg, rmask, data);
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}
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#define RK3506_PULL_BITS_PER_PIN 2
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#define RK3506_PULL_PINS_PER_REG 8
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#define RK3506_PULL_GPIO0_A_OFFSET 0x200
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#define RK3506_PULL_GPIO0_D_OFFSET 0x830
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#define RK3506_PULL_GPIO1_OFFSET 0x210
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#define RK3506_PULL_GPIO2_OFFSET 0x220
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#define RK3506_PULL_GPIO3_OFFSET 0x230
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#define RK3506_PULL_GPIO4_OFFSET 0x840
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static int rk3506_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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int ret = 0;
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switch (bank->bank_num) {
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case 0:
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*regmap = priv->regmap_pmu;
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if (pin_num > 24) {
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ret = -EINVAL;
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} else if (pin_num < 24) {
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*reg = RK3506_PULL_GPIO0_A_OFFSET;
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} else {
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*reg = RK3506_PULL_GPIO0_D_OFFSET;
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*bit = 5;
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return 0;
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}
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break;
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case 1:
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*regmap = priv->regmap_ioc1;
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if (pin_num < 28)
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*reg = RK3506_PULL_GPIO1_OFFSET;
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else
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ret = -EINVAL;
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break;
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case 2:
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*regmap = priv->regmap_base;
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if (pin_num < 17)
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*reg = RK3506_PULL_GPIO2_OFFSET;
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else
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ret = -EINVAL;
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break;
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case 3:
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*regmap = priv->regmap_base;
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if (pin_num < 15)
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*reg = RK3506_PULL_GPIO3_OFFSET;
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else
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ret = -EINVAL;
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break;
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case 4:
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*regmap = priv->regmap_base;
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if (pin_num < 8 || pin_num > 11) {
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ret = -EINVAL;
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} else {
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*reg = RK3506_PULL_GPIO4_OFFSET;
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*bit = 13;
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return 0;
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}
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break;
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default:
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ret = -EINVAL;
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break;
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}
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if (ret) {
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debug("unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
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return ret;
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}
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*reg += ((pin_num / RK3506_PULL_PINS_PER_REG) * 4);
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*bit = pin_num % RK3506_PULL_PINS_PER_REG;
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*bit *= RK3506_PULL_BITS_PER_PIN;
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return 0;
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}
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static int rk3506_set_pull(struct rockchip_pin_bank *bank,
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int pin_num, int pull)
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{
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struct regmap *regmap;
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int reg, ret;
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u8 bit, type;
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u32 data, rmask;
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if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
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return -EOPNOTSUPP;
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ret = rk3506_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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if (ret)
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return ret;
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type = bank->pull_type[pin_num / 8];
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if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4)
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type = 1;
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ret = rockchip_translate_pull_value(type, pull);
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if (ret < 0) {
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debug("unsupported pull setting %d\n", pull);
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return ret;
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}
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/* enable the write to the equivalent lower bits */
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data = ((1 << RK3506_PULL_BITS_PER_PIN) - 1) << (bit + 16);
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rmask = data | (data >> 16);
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data |= (ret << bit);
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return regmap_update_bits(regmap, reg, rmask, data);
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}
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#define RK3506_SMT_BITS_PER_PIN 1
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#define RK3506_SMT_PINS_PER_REG 8
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#define RK3506_SMT_GPIO0_A_OFFSET 0x400
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#define RK3506_SMT_GPIO0_D_OFFSET 0x830
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#define RK3506_SMT_GPIO1_OFFSET 0x410
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#define RK3506_SMT_GPIO2_OFFSET 0x420
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#define RK3506_SMT_GPIO3_OFFSET 0x430
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#define RK3506_SMT_GPIO4_OFFSET 0x840
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static int rk3506_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num,
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struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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int ret = 0;
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switch (bank->bank_num) {
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case 0:
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*regmap = priv->regmap_pmu;
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if (pin_num > 24) {
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ret = -EINVAL;
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} else if (pin_num < 24) {
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*reg = RK3506_SMT_GPIO0_A_OFFSET;
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} else {
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*reg = RK3506_SMT_GPIO0_D_OFFSET;
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*bit = 9;
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return 0;
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}
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break;
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case 1:
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*regmap = priv->regmap_ioc1;
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if (pin_num < 28)
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*reg = RK3506_SMT_GPIO1_OFFSET;
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else
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ret = -EINVAL;
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break;
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case 2:
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*regmap = priv->regmap_base;
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if (pin_num < 17)
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*reg = RK3506_SMT_GPIO2_OFFSET;
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else
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ret = -EINVAL;
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break;
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case 3:
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*regmap = priv->regmap_base;
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if (pin_num < 15)
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*reg = RK3506_SMT_GPIO3_OFFSET;
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else
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ret = -EINVAL;
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break;
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case 4:
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*regmap = priv->regmap_base;
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if (pin_num < 8 || pin_num > 11) {
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ret = -EINVAL;
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} else {
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*reg = RK3506_SMT_GPIO4_OFFSET;
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*bit = 8;
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return 0;
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}
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break;
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default:
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ret = -EINVAL;
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break;
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}
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if (ret) {
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debug("unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
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return ret;
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}
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*reg += ((pin_num / RK3506_SMT_PINS_PER_REG) * 4);
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*bit = pin_num % RK3506_SMT_PINS_PER_REG;
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*bit *= RK3506_SMT_BITS_PER_PIN;
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return 0;
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}
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static int rk3506_set_schmitt(struct rockchip_pin_bank *bank,
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int pin_num, int enable)
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{
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struct regmap *regmap;
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int reg, ret;
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u32 data, rmask;
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u8 bit;
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ret = rk3506_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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if (ret)
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return ret;
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/* enable the write to the equivalent lower bits */
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data = ((1 << RK3506_SMT_BITS_PER_PIN) - 1) << (bit + 16);
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rmask = data | (data >> 16);
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data |= (enable << bit);
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if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) {
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data = 0x3 << (bit + 16);
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rmask = data | (data >> 16);
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data |= ((enable ? 0x3 : 0) << bit);
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}
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return regmap_update_bits(regmap, reg, rmask, data);
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}
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static struct rockchip_mux_recalced_data rk3506_mux_recalced_data[] = {
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{
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.num = 0,
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.pin = 24,
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.reg = 0x830,
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.bit = 0,
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.mask = 0x3
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},
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};
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static struct rockchip_pin_bank rk3506_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
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IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
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IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
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IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
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IOMUX_8WIDTH_2BIT | IOMUX_SOURCE_PMU,
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0x0, 0x8, 0x10, 0x830),
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PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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0x20, 0x28, 0x30, 0x38),
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PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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0x40, 0x48, 0x50, 0x58),
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PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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0x60, 0x68, 0x70, 0x78),
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PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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0x80, 0x88, 0x90, 0x98),
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};
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static const struct rockchip_pin_ctrl rk3506_pin_ctrl = {
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.pin_banks = rk3506_pin_banks,
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.nr_banks = ARRAY_SIZE(rk3506_pin_banks),
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.iomux_recalced = rk3506_mux_recalced_data,
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.niomux_recalced = ARRAY_SIZE(rk3506_mux_recalced_data),
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.set_mux = rk3506_set_mux,
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.set_pull = rk3506_set_pull,
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.set_drive = rk3506_set_drive,
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.set_schmitt = rk3506_set_schmitt,
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};
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static const struct udevice_id rk3506_pinctrl_ids[] = {
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{
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.compatible = "rockchip,rk3506-pinctrl",
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.data = (ulong)&rk3506_pin_ctrl
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},
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{ }
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};
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||||
|
||||
U_BOOT_DRIVER(rockchip_rk3506_pinctrl) = {
|
||||
.name = "rockchip_rk3506_pinctrl",
|
||||
.id = UCLASS_PINCTRL,
|
||||
.of_match = rk3506_pinctrl_ids,
|
||||
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
|
||||
.ops = &rockchip_pinctrl_ops,
|
||||
#if CONFIG_IS_ENABLED(OF_REAL)
|
||||
.bind = dm_scan_fdt_dev,
|
||||
#endif
|
||||
.probe = rockchip_pinctrl_probe,
|
||||
};
|
||||
@ -659,6 +659,15 @@ int rockchip_pinctrl_probe(struct udevice *dev)
|
||||
}
|
||||
}
|
||||
|
||||
if (dev_read_bool(dev, "rockchip,ioc1")) {
|
||||
priv->regmap_ioc1 =
|
||||
syscon_regmap_lookup_by_phandle(dev, "rockchip,ioc1");
|
||||
if (IS_ERR(priv->regmap_ioc1)) {
|
||||
debug("unable to find rockchip,ioc1 regmap\n");
|
||||
return PTR_ERR(priv->regmap_ioc1);
|
||||
}
|
||||
}
|
||||
|
||||
ctrl = rockchip_pinctrl_get_soc_data(dev);
|
||||
if (!ctrl) {
|
||||
debug("driver data not available\n");
|
||||
|
||||
@ -528,6 +528,7 @@ struct rockchip_pinctrl_priv {
|
||||
struct rockchip_pin_ctrl *ctrl;
|
||||
struct regmap *regmap_base;
|
||||
struct regmap *regmap_pmu;
|
||||
struct regmap *regmap_ioc1;
|
||||
};
|
||||
|
||||
extern const struct pinctrl_ops rockchip_pinctrl_ops;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user