mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-05-04 12:21:03 +02:00
Subtree merge tag 'v7.0-dts' of dts repo [1] into dts/upstream
[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git - Remove netc_timerX nodes from arch/arm/dts/imx943-u-boot.dtsi as they are now upstream - Move dts/upstream/include/dt-bindings/reset/bcm6318-reset.h to include/dt-bindings/reset/bcm6318-reset.h as upstream has removed this file as unused (but we use it). Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
commit
5d401bfbdf
@ -339,12 +339,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
netc_timer0: ethernet@0,1 {
|
||||
compatible = "pci1131,ee02";
|
||||
reg = <0x100 0 0 0 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
netc_switch: ethernet-switch@0,2 {
|
||||
compatible = "pci1131,eef2", "nxp,imx943-netc-switch";
|
||||
reg = <0x200 0 0 0 0>;
|
||||
@ -408,12 +402,6 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
netc_timer1: ethernet@0,1 {
|
||||
compatible = "pci1131,ee02";
|
||||
reg = <0x10100 0 0 0 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enetc1: ethernet@8,0 {
|
||||
compatible = "pci1131,e101";
|
||||
reg = <0x14000 0 0 0 0>;
|
||||
@ -426,12 +414,6 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
netc_timer2: ethernet@10,1 {
|
||||
compatible = "pci1131,ee02";
|
||||
reg = <0x18100 0 0 0 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
netc_emdio: mdio@18,0 {
|
||||
compatible = "pci1131,ee00";
|
||||
reg = <0x1c000 0 0 0 0>;
|
||||
|
||||
@ -56,7 +56,6 @@ DT_DOCS = $(patsubst $(srctree)/%,%,$(shell $(find_all_cmd)))
|
||||
|
||||
override DTC_FLAGS := \
|
||||
-Wno-avoid_unnecessary_addr_size \
|
||||
-Wno-graph_child_address \
|
||||
-Wno-unique_unit_address \
|
||||
-Wunique_unit_address_if_enabled
|
||||
|
||||
@ -82,5 +81,8 @@ clean-files = $(shell find $(obj) \( -name '*.example.dts' -o \
|
||||
dt_compatible_check: $(obj)/processed-schema.json
|
||||
$(Q)$(srctree)/scripts/dtc/dt-extract-compatibles $(srctree) | xargs dt-check-compatible -v -s $<
|
||||
|
||||
PHONY += dt_binding_check_one
|
||||
dt_binding_check_one: $(obj)/.dt-binding.checked $(obj)/.yamllint.checked
|
||||
|
||||
PHONY += dt_binding_check
|
||||
dt_binding_check: $(obj)/.dt-binding.checked $(obj)/.yamllint.checked $(CHK_DT_EXAMPLES)
|
||||
dt_binding_check: dt_binding_check_one $(CHK_DT_EXAMPLES)
|
||||
|
||||
@ -9,6 +9,9 @@ title: Altera's SoCFPGA platform
|
||||
maintainers:
|
||||
- Dinh Nguyen <dinguyen@kernel.org>
|
||||
|
||||
description:
|
||||
Altera/Intel boards with ARM 32/64 bits cores
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: "/"
|
||||
@ -81,6 +84,30 @@ properties:
|
||||
- altr,socfpga-stratix10-swvp
|
||||
- const: altr,socfpga-stratix10
|
||||
|
||||
- description: AgileX boards
|
||||
items:
|
||||
- enum:
|
||||
- intel,n5x-socdk
|
||||
- intel,socfpga-agilex-n6000
|
||||
- intel,socfpga-agilex-socdk
|
||||
- intel,socfpga-agilex-socdk-emmc
|
||||
- const: intel,socfpga-agilex
|
||||
|
||||
- description: Agilex3 boards
|
||||
items:
|
||||
- enum:
|
||||
- intel,socfpga-agilex3-socdk
|
||||
- const: intel,socfpga-agilex3
|
||||
- const: intel,socfpga-agilex5
|
||||
|
||||
- description: Agilex5 boards
|
||||
items:
|
||||
- enum:
|
||||
- intel,socfpga-agilex5-socdk
|
||||
- intel,socfpga-agilex5-socdk-013b
|
||||
- intel,socfpga-agilex5-socdk-nand
|
||||
- const: intel,socfpga-agilex5
|
||||
|
||||
- description: SoCFPGA VT
|
||||
items:
|
||||
- const: altr,socfpga-vt
|
||||
|
||||
@ -245,6 +245,14 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- amlogic,aq222
|
||||
- const: amlogic,s805x2
|
||||
- const: amlogic,s4
|
||||
|
||||
- description: Boards with the Amlogic Meson S4 S905Y4 SoC
|
||||
items:
|
||||
- enum:
|
||||
- khadas,vim1s
|
||||
- const: amlogic,s905y4
|
||||
- const: amlogic,s4
|
||||
|
||||
- description: Boards with the Amlogic S6 S905X5 SoC
|
||||
|
||||
@ -31,7 +31,7 @@ maintainers:
|
||||
- Mike Leach <mike.leach@linaro.org>
|
||||
- Suzuki K Poulose <suzuki.poulose@arm.com>
|
||||
- James Clark <james.clark@linaro.org>
|
||||
- Mao Jinlong <quic_jinlmao@quicinc.com>
|
||||
- Mao Jinlong <jinlong.mao@oss.qualcomm.com>
|
||||
- Hao Zhang <quic_hazha@quicinc.com>
|
||||
|
||||
properties:
|
||||
|
||||
@ -30,7 +30,7 @@ maintainers:
|
||||
- Mike Leach <mike.leach@linaro.org>
|
||||
- Suzuki K Poulose <suzuki.poulose@arm.com>
|
||||
- James Clark <james.clark@linaro.org>
|
||||
- Mao Jinlong <quic_jinlmao@quicinc.com>
|
||||
- Mao Jinlong <jinlong.mao@oss.qualcomm.com>
|
||||
- Hao Zhang <quic_hazha@quicinc.com>
|
||||
|
||||
properties:
|
||||
|
||||
@ -157,6 +157,12 @@ patternProperties:
|
||||
- const: simple-bus
|
||||
- const: simple-bus
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 1
|
||||
|
||||
interrupt-map: true
|
||||
interrupt-map-mask: true
|
||||
|
||||
patternProperties:
|
||||
'^motherboard-bus@':
|
||||
type: object
|
||||
|
||||
@ -34,6 +34,7 @@ properties:
|
||||
- amd,ethanolx-bmc
|
||||
- ampere,mtjade-bmc
|
||||
- aspeed,ast2500-evb
|
||||
- asrock,altrad8-bmc
|
||||
- asrock,e3c246d4i-bmc
|
||||
- asrock,e3c256d4i-bmc
|
||||
- asrock,romed8hm3-bmc
|
||||
@ -80,6 +81,7 @@ properties:
|
||||
- aspeed,ast2600-evb
|
||||
- aspeed,ast2600-evb-a1
|
||||
- asus,x4tf-bmc
|
||||
- facebook,anacapa-bmc
|
||||
- facebook,bletchley-bmc
|
||||
- facebook,catalina-bmc
|
||||
- facebook,clemente-bmc
|
||||
@ -107,6 +109,7 @@ properties:
|
||||
- inventec,transformer-bmc
|
||||
- jabil,rbp-bmc
|
||||
- nvidia,gb200nvl-bmc
|
||||
- nvidia,msx4-bmc
|
||||
- qcom,dc-scm-v1-bmc
|
||||
- quanta,s6q-bmc
|
||||
- ufispace,ncplite-bmc
|
||||
|
||||
@ -235,9 +235,11 @@ properties:
|
||||
- const: microchip,lan9662
|
||||
- const: microchip,lan966
|
||||
|
||||
- description: Microchip LAN9668 PCB8290 Evaluation Board.
|
||||
- description: Microchip LAN9668 Evaluation Board.
|
||||
items:
|
||||
- const: microchip,lan9668-pcb8290
|
||||
- enum:
|
||||
- microchip,lan9668-pcb8290
|
||||
- microchip,lan9668-pcb8385
|
||||
- const: microchip,lan9668
|
||||
- const: microchip,lan966
|
||||
|
||||
|
||||
@ -1,24 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,vulcan-soc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Vulcan
|
||||
|
||||
maintainers:
|
||||
- Robert Richter <rrichter@marvell.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,vulcan-eval
|
||||
- cavium,thunderx2-cn9900
|
||||
- const: brcm,vulcan-soc
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
@ -65,6 +65,11 @@ properties:
|
||||
gpio-line-names:
|
||||
minItems: 8
|
||||
|
||||
patternProperties:
|
||||
'-hog$':
|
||||
required:
|
||||
- gpio-hog
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- gpio-controller
|
||||
@ -87,6 +92,9 @@ properties:
|
||||
- compatible
|
||||
- "#reset-cells"
|
||||
|
||||
power:
|
||||
$ref: /schemas/power/raspberrypi,bcm2835-power.yaml#
|
||||
|
||||
pwm:
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
@ -16,9 +16,11 @@ properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
|
||||
- description: Radxa Orion O6
|
||||
- description: Sky1 based boards
|
||||
items:
|
||||
- const: radxa,orion-o6
|
||||
- enum:
|
||||
- radxa,orion-o6 # Radxa Orion O6 board
|
||||
- xunlong,orangepi-6-plus # Xunlong orangepi 6 plus board
|
||||
- const: cix,sky1
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
@ -1071,6 +1071,15 @@ properties:
|
||||
- gw,imx8mn-gw7902 # i.MX8MM Gateworks Board
|
||||
- const: fsl,imx8mn
|
||||
|
||||
- description: ifm i.MX8MN VHIP4 based boards
|
||||
items:
|
||||
- enum:
|
||||
- ifm,imx8mn-vhip4-evalboard-v1
|
||||
- ifm,imx8mn-vhip4-evalboard-v2
|
||||
- const: ifm,imx8mn-vhip4-evalboard
|
||||
- const: ifm,imx8mn-vhip4
|
||||
- const: fsl,imx8mn
|
||||
|
||||
- description: Variscite VAR-SOM-MX8MN based boards
|
||||
items:
|
||||
- enum:
|
||||
@ -1099,6 +1108,7 @@ properties:
|
||||
- emcraft,imx8mp-navqp # i.MX8MP Emcraft Systems NavQ+ Kit
|
||||
- fsl,imx8mp-evk # i.MX8MP EVK Board
|
||||
- fsl,imx8mp-evk-revb4 # i.MX8MP EVK Rev B4 Board
|
||||
- fsl,imx8mp-frdm # i.MX8MP Freedom Board
|
||||
- gateworks,imx8mp-gw71xx-2x # i.MX8MP Gateworks Board
|
||||
- gateworks,imx8mp-gw72xx-2x # i.MX8MP Gateworks Board
|
||||
- gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board
|
||||
@ -1340,7 +1350,7 @@ properties:
|
||||
- const: toradex,apalis-imx8
|
||||
- const: fsl,imx8qm
|
||||
|
||||
- description: i.MX8QM Boards with Toradex Apalis iMX8 V1.1 Modules
|
||||
- description: i.MX8QM/i.MX8QP Boards with Toradex Apalis iMX8 V1.1 Modules
|
||||
items:
|
||||
- enum:
|
||||
- toradex,apalis-imx8-v1.1-eval # Apalis iMX8 V1.1 Module on Apalis Eval. V1.0/V1.1 Board
|
||||
@ -1348,7 +1358,9 @@ properties:
|
||||
- toradex,apalis-imx8-v1.1-ixora-v1.1 # Apalis iMX8 V1.1 Module on Ixora V1.1 C. Board
|
||||
- toradex,apalis-imx8-v1.1-ixora-v1.2 # Apalis iMX8 V1.1 Module on Ixora V1.2 C. Board
|
||||
- const: toradex,apalis-imx8-v1.1
|
||||
- const: fsl,imx8qm
|
||||
- enum:
|
||||
- fsl,imx8qm
|
||||
- fsl,imx8qp
|
||||
|
||||
- description: i.MX8QXP based Boards
|
||||
items:
|
||||
@ -1419,6 +1431,7 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx91-11x11-evk # i.MX91 11x11 EVK Board
|
||||
- fsl,imx91-11x11-frdm # FRDM i.MX91 Development Board
|
||||
- const: fsl,imx91
|
||||
|
||||
- description: i.MX93 based Boards
|
||||
@ -1426,6 +1439,7 @@ properties:
|
||||
- enum:
|
||||
- fsl,imx93-9x9-qsb # i.MX93 9x9 QSB Board
|
||||
- fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board
|
||||
- fsl,imx93-11x11-frdm # i.MX93 11x11 FRDM Board
|
||||
- fsl,imx93-14x14-evk # i.MX93 14x14 EVK Board
|
||||
- const: fsl,imx93
|
||||
|
||||
@ -1439,10 +1453,17 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx95-15x15-evk # i.MX95 15x15 EVK Board
|
||||
- fsl,imx95-15x15-frdm # i.MX95 15x15 FRDM Board
|
||||
- fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board
|
||||
- toradex,verdin-imx95-19x19-evk # i.MX95 Verdin Evaluation Kit (EVK)
|
||||
- const: fsl,imx95
|
||||
|
||||
- description: i.MX952 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx952-evk # i.MX952 EVK Board
|
||||
- const: fsl,imx952
|
||||
|
||||
- description: PHYTEC i.MX 95 FPSC based Boards
|
||||
items:
|
||||
- enum:
|
||||
@ -1679,6 +1700,15 @@ properties:
|
||||
- const: kontron,sl28
|
||||
- const: fsl,ls1028a
|
||||
|
||||
- description:
|
||||
TQ-Systems TQMLS1028A SoM on MBLS1028A/MBLS1028A-IND board
|
||||
items:
|
||||
- enum:
|
||||
- tq,ls1028a-tqmls1028a-mbls1028a
|
||||
- tq,ls1028a-tqmls1028a-mbls1028a-ind
|
||||
- const: tq,ls1028a-tqmls1028a
|
||||
- const: fsl,ls1028a
|
||||
|
||||
- description: LS1043A based Boards
|
||||
items:
|
||||
- enum:
|
||||
|
||||
@ -1,40 +0,0 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/intel,socfpga.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel SoCFPGA platform
|
||||
|
||||
maintainers:
|
||||
- Dinh Nguyen <dinguyen@kernel.org>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: "/"
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: AgileX boards
|
||||
items:
|
||||
- enum:
|
||||
- intel,n5x-socdk
|
||||
- intel,socfpga-agilex-n6000
|
||||
- intel,socfpga-agilex-socdk
|
||||
- const: intel,socfpga-agilex
|
||||
- description: Agilex3 boards
|
||||
items:
|
||||
- enum:
|
||||
- intel,socfpga-agilex3-socdk
|
||||
- const: intel,socfpga-agilex3
|
||||
- const: intel,socfpga-agilex5
|
||||
- description: Agilex5 boards
|
||||
items:
|
||||
- enum:
|
||||
- intel,socfpga-agilex5-socdk
|
||||
- intel,socfpga-agilex5-socdk-013b
|
||||
- intel,socfpga-agilex5-socdk-nand
|
||||
- const: intel,socfpga-agilex5
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
@ -438,12 +438,14 @@ properties:
|
||||
- const: mediatek,mt8365
|
||||
- items:
|
||||
- enum:
|
||||
- ezurio,mt8370-tungsten-smarc
|
||||
- grinn,genio-510-sbc
|
||||
- mediatek,mt8370-evk
|
||||
- const: mediatek,mt8370
|
||||
- const: mediatek,mt8188
|
||||
- items:
|
||||
- enum:
|
||||
- ezurio,mt8390-tungsten-smarc
|
||||
- grinn,genio-700-sbc
|
||||
- mediatek,mt8390-evk
|
||||
- const: mediatek,mt8390
|
||||
|
||||
@ -48,19 +48,39 @@ required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: mediatek,mt8183-audiosys
|
||||
then:
|
||||
properties:
|
||||
audio-controller:
|
||||
$ref: /schemas/sound/mediatek,mt8183-audio.yaml#
|
||||
else:
|
||||
properties:
|
||||
audio-controller:
|
||||
$ref: /schemas/sound/mediatek,mt2701-audio.yaml#
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- mediatek,mt2701-audsys
|
||||
- mediatek,mt7622-audsys
|
||||
then:
|
||||
properties:
|
||||
audio-controller:
|
||||
$ref: /schemas/sound/mediatek,mt2701-audio.yaml#
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: mediatek,mt8183-audiosys
|
||||
then:
|
||||
properties:
|
||||
audio-controller:
|
||||
$ref: /schemas/sound/mediatek,mt8183-audio.yaml#
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: mediatek,mt8192-audsys
|
||||
then:
|
||||
properties:
|
||||
audio-controller:
|
||||
$ref: /schemas/sound/mt8192-afe-pcm.yaml#
|
||||
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
||||
@ -1,31 +0,0 @@
|
||||
OMAP PRM instance bindings
|
||||
|
||||
Power and Reset Manager is an IP block on OMAP family of devices which
|
||||
handle the power domains and their current state, and provide reset
|
||||
handling for the domains and/or separate IP blocks under the power domain
|
||||
hierarchy.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must contain one of the following:
|
||||
"ti,am3-prm-inst"
|
||||
"ti,am4-prm-inst"
|
||||
"ti,omap4-prm-inst"
|
||||
"ti,omap5-prm-inst"
|
||||
"ti,dra7-prm-inst"
|
||||
and additionally must contain:
|
||||
"ti,omap-prm-inst"
|
||||
- reg: Contains PRM instance register address range
|
||||
(base address and length)
|
||||
|
||||
Optional properties:
|
||||
- #power-domain-cells: Should be 0 if the instance is a power domain provider.
|
||||
- #reset-cells: Should be 1 if the PRM instance in question supports resets.
|
||||
|
||||
Example:
|
||||
|
||||
prm_dsp2: prm@1b00 {
|
||||
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1b00 0x40>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -7,9 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: CoreSight TMC Control Unit
|
||||
|
||||
maintainers:
|
||||
- Yuanfang Zhang <quic_yuanfang@quicinc.com>
|
||||
- Mao Jinlong <quic_jinlmao@quicinc.com>
|
||||
- Jie Gan <quic_jiegan@quicinc.com>
|
||||
- Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
|
||||
- Mao Jinlong <jinlong.mao@oss.qualcomm.com>
|
||||
- Jie Gan <jie.gan@oss.qualcomm.com>
|
||||
|
||||
description: |
|
||||
The Trace Memory Controller(TMC) is used for Embedded Trace Buffer(ETB),
|
||||
@ -26,8 +26,13 @@ description: |
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sa8775p-ctcu
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,qcs8300-ctcu
|
||||
- const: qcom,sa8775p-ctcu
|
||||
- enum:
|
||||
- qcom,sa8775p-ctcu
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
90
dts/upstream/Bindings/arm/qcom,coresight-itnoc.yaml
Normal file
90
dts/upstream/Bindings/arm/qcom,coresight-itnoc.yaml
Normal file
@ -0,0 +1,90 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/qcom,coresight-itnoc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Interconnect Trace Network On Chip - ITNOC
|
||||
|
||||
maintainers:
|
||||
- Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
|
||||
|
||||
description:
|
||||
The Interconnect TNOC is a CoreSight graph link that forwards trace data
|
||||
from a subsystem to the Aggregator TNOC. Compared to Aggregator TNOC, it
|
||||
does not have aggregation and ATID functionality.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^itnoc(@[0-9a-f]+)?$"
|
||||
|
||||
compatible:
|
||||
const: qcom,coresight-itnoc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: apb
|
||||
|
||||
in-ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
patternProperties:
|
||||
'^port(@[0-9a-f]{1,2})?$':
|
||||
description: Input connections from CoreSight Trace Bus
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
|
||||
out-ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
port:
|
||||
description: out connections to aggregator TNOC
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- in-ports
|
||||
- out-ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
itnoc@109ac000 {
|
||||
compatible = "qcom,coresight-itnoc";
|
||||
reg = <0x109ac000 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb";
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
tn_ic_in_tpdm_dcc: endpoint {
|
||||
remote-endpoint = <&tpdm_dcc_out_tn_ic>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
tn_ic_out_tnoc_aggr: endpoint {
|
||||
/* to Aggregator TNOC input */
|
||||
remote-endpoint = <&tn_ag_in_tn_ic>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Qualcomm Coresight Remote ETM(Embedded Trace Macrocell)
|
||||
|
||||
maintainers:
|
||||
- Jinlong Mao <quic_jinlmao@quicinc.com>
|
||||
- Tao Zhang <quic_taozha@quicinc.com>
|
||||
- Jinlong Mao <jinlong.mao@oss.qualcomm.com>
|
||||
- Tao Zhang <tao.zhang@oss.qualcomm.com>
|
||||
|
||||
description:
|
||||
Support for ETM trace collection on remote processor using coresight
|
||||
|
||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Qualcomm Trace Network On Chip - TNOC
|
||||
|
||||
maintainers:
|
||||
- Yuanfang Zhang <quic_yuanfang@quicinc.com>
|
||||
- Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
|
||||
|
||||
description: >
|
||||
The Trace Network On Chip (TNOC) is an integration hierarchy hardware
|
||||
|
||||
@ -33,8 +33,8 @@ description: |
|
||||
to sink.
|
||||
|
||||
maintainers:
|
||||
- Mao Jinlong <quic_jinlmao@quicinc.com>
|
||||
- Tao Zhang <quic_taozha@quicinc.com>
|
||||
- Mao Jinlong <jinlong.mao@oss.qualcomm.com>
|
||||
- Tao Zhang <tao.zhang@oss.qualcomm.com>
|
||||
|
||||
# Need a custom select here or 'arm,primecell' will match on lots of nodes
|
||||
select:
|
||||
|
||||
@ -19,8 +19,8 @@ description: |
|
||||
sources and send it to a TPDA for packetization, timestamping, and funneling.
|
||||
|
||||
maintainers:
|
||||
- Mao Jinlong <quic_jinlmao@quicinc.com>
|
||||
- Tao Zhang <quic_taozha@quicinc.com>
|
||||
- Mao Jinlong <jinlong.mao@oss.qualcomm.com>
|
||||
- Tao Zhang <tao.zhang@oss.qualcomm.com>
|
||||
|
||||
# Need a custom select here or 'arm,primecell' will match on lots of nodes
|
||||
select:
|
||||
|
||||
@ -61,6 +61,11 @@ properties:
|
||||
- qcom,apq8084-sbc
|
||||
- const: qcom,apq8084
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- fairphone,fp6
|
||||
- const: qcom,milos
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- microsoft,dempsey
|
||||
@ -327,6 +332,12 @@ properties:
|
||||
- qcom,ipq9574-ap-al02-c9
|
||||
- const: qcom,ipq9574
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,kaanapali-mtp
|
||||
- qcom,kaanapali-qrd
|
||||
- const: qcom,kaanapali
|
||||
|
||||
- description: Sierra Wireless MangOH Green with WP8548 Module
|
||||
items:
|
||||
- const: swir,mangoh-green-wp8548
|
||||
@ -336,6 +347,7 @@ properties:
|
||||
- description: Qualcomm Technologies, Inc. Robotics RB1
|
||||
items:
|
||||
- enum:
|
||||
- arduino,imola
|
||||
- qcom,qrb2210-rb1
|
||||
- const: qcom,qrb2210
|
||||
- const: qcom,qcm2290
|
||||
@ -348,6 +360,7 @@ properties:
|
||||
- qcom,qcs6490-rb3gen2
|
||||
- radxa,dragon-q6a
|
||||
- shift,otter
|
||||
- thundercomm,rubikpi3
|
||||
- const: qcom,qcm6490
|
||||
|
||||
- description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform
|
||||
@ -900,6 +913,8 @@ properties:
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- google,blueline
|
||||
- google,crosshatch
|
||||
- huawei,planck
|
||||
- lenovo,yoga-c630
|
||||
- lg,judyln
|
||||
@ -1067,6 +1082,19 @@ properties:
|
||||
- const: qcom,x1e78100
|
||||
- const: qcom,x1e80100
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- medion,sprchrgd14s1
|
||||
- tuxedo,elite14gen1
|
||||
- const: qcom,x1e78100
|
||||
- const: qcom,x1e80100
|
||||
|
||||
- items:
|
||||
- const: microsoft,denali-lcd
|
||||
- const: microsoft,denali
|
||||
- const: qcom,x1p64100
|
||||
- const: qcom,x1e80100
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- asus,vivobook-s15
|
||||
@ -1089,6 +1117,11 @@ properties:
|
||||
- const: qcom,hamoa-iot-som
|
||||
- const: qcom,x1e80100
|
||||
|
||||
- items:
|
||||
- const: microsoft,denali-oled
|
||||
- const: microsoft,denali
|
||||
- const: qcom,x1e80100
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- asus,zenbook-a14-ux3407qa-lcd
|
||||
|
||||
@ -14,21 +14,21 @@ properties:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
# RTD1195 SoC based boards
|
||||
- items:
|
||||
- description: RTD1195 SoC based boards
|
||||
items:
|
||||
- enum:
|
||||
- mele,x1000 # MeLE X1000
|
||||
- realtek,horseradish # Realtek Horseradish EVB
|
||||
- const: realtek,rtd1195
|
||||
|
||||
# RTD1293 SoC based boards
|
||||
- items:
|
||||
- description: RTD1293 SoC based boards
|
||||
items:
|
||||
- enum:
|
||||
- synology,ds418j # Synology DiskStation DS418j
|
||||
- const: realtek,rtd1293
|
||||
|
||||
# RTD1295 SoC based boards
|
||||
- items:
|
||||
- description: RTD1295 SoC based boards
|
||||
items:
|
||||
- enum:
|
||||
- mele,v9 # MeLE V9
|
||||
- probox2,ava # ProBox2 AVA
|
||||
@ -36,25 +36,43 @@ properties:
|
||||
- zidoo,x9s # Zidoo X9S
|
||||
- const: realtek,rtd1295
|
||||
|
||||
# RTD1296 SoC based boards
|
||||
- items:
|
||||
- description: RTD1296 SoC based boards
|
||||
items:
|
||||
- enum:
|
||||
- synology,ds418 # Synology DiskStation DS418
|
||||
- const: realtek,rtd1296
|
||||
|
||||
# RTD1395 SoC based boards
|
||||
- items:
|
||||
- description: RTD1395 SoC based boards
|
||||
items:
|
||||
- enum:
|
||||
- bananapi,bpi-m4 # Banana Pi BPI-M4
|
||||
- realtek,lion-skin # Realtek Lion Skin EVB
|
||||
- const: realtek,rtd1395
|
||||
|
||||
# RTD1619 SoC based boards
|
||||
- items:
|
||||
- description: RTD1501s SoC based boards
|
||||
items:
|
||||
- enum:
|
||||
- realtek,phantom # Realtek Phantom EVB (8GB)
|
||||
- const: realtek,rtd1501s
|
||||
|
||||
- description: RTD1619 SoC based boards
|
||||
items:
|
||||
- enum:
|
||||
- realtek,mjolnir # Realtek Mjolnir EVB
|
||||
- const: realtek,rtd1619
|
||||
|
||||
- description: RTD1861b SoC based boards
|
||||
items:
|
||||
- enum:
|
||||
- realtek,krypton # Realtek Krypton EVB (8GB)
|
||||
- const: realtek,rtd1861b
|
||||
|
||||
- description: RTD1920s SoC based boards
|
||||
items:
|
||||
- enum:
|
||||
- realtek,smallville # Realtek Smallville EVB (4GB)
|
||||
- const: realtek,rtd1920s
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
|
||||
@ -60,6 +60,12 @@ properties:
|
||||
- anbernic,rg-arc-s
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Anbernic RK3568 Handheld Gaming Console
|
||||
items:
|
||||
- enum:
|
||||
- anbernic,rg-ds
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Ariaboard Photonicat
|
||||
items:
|
||||
- const: ariaboard,photonicat
|
||||
@ -894,11 +900,15 @@ properties:
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: QNAP TS-x33 NAS devices
|
||||
items:
|
||||
- enum:
|
||||
- qnap,ts233
|
||||
- qnap,ts433
|
||||
- const: rockchip,rk3568
|
||||
oneOf:
|
||||
- items:
|
||||
- const: qnap,ts133
|
||||
- const: rockchip,rk3566
|
||||
- items:
|
||||
- enum:
|
||||
- qnap,ts233
|
||||
- qnap,ts433
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Radxa Compute Module 3 (CM3)
|
||||
items:
|
||||
@ -907,13 +917,27 @@ properties:
|
||||
- const: radxa,cm3
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Radxa CM3 Industrial
|
||||
- description: Radxa CM3I
|
||||
items:
|
||||
- enum:
|
||||
- radxa,e25
|
||||
- const: radxa,cm3i
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Radxa CM3J
|
||||
items:
|
||||
- enum:
|
||||
- radxa,cm3j-rpi-cm4
|
||||
- const: radxa,cm3j
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Radxa CM5
|
||||
items:
|
||||
- enum:
|
||||
- radxa,cm5-io
|
||||
- const: radxa,cm5
|
||||
- const: rockchip,rk3588s
|
||||
|
||||
- description: Radxa E20C
|
||||
items:
|
||||
- const: radxa,e20c
|
||||
@ -1299,6 +1323,12 @@ properties:
|
||||
- xunlong,orangepi-5b
|
||||
- const: rockchip,rk3588s
|
||||
|
||||
- description: Xunlong Orange Pi CM5
|
||||
items:
|
||||
- const: xunlong,orangepi-cm5-base
|
||||
- const: xunlong,orangepi-cm5
|
||||
- const: rockchip,rk3588s
|
||||
|
||||
- description: Zkmagic A95X Z2
|
||||
items:
|
||||
- const: zkmagic,a95x-z2
|
||||
|
||||
@ -19,15 +19,15 @@ properties:
|
||||
- nvidia,tegra264-pmc
|
||||
|
||||
reg:
|
||||
minItems: 4
|
||||
minItems: 3
|
||||
maxItems: 5
|
||||
|
||||
reg-names:
|
||||
minItems: 4
|
||||
minItems: 3
|
||||
items:
|
||||
- const: pmc
|
||||
- const: wake
|
||||
- const: aotag
|
||||
- enum: [ aotag, scratch, misc ]
|
||||
- enum: [ scratch, misc ]
|
||||
- const: misc
|
||||
|
||||
@ -51,6 +51,7 @@ allOf:
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
reg-names:
|
||||
maxItems: 4
|
||||
@ -73,7 +74,9 @@ allOf:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: nvidia,tegra234-pmc
|
||||
enum:
|
||||
- nvidia,tegra234-pmc
|
||||
- nvidia,tegra264-pmc
|
||||
then:
|
||||
properties:
|
||||
reg-names:
|
||||
|
||||
55
dts/upstream/Bindings/arm/ti/ti,omap-prm-inst.yaml
Normal file
55
dts/upstream/Bindings/arm/ti/ti,omap-prm-inst.yaml
Normal file
@ -0,0 +1,55 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/ti/ti,omap-prm-inst.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: OMAP PRM instances
|
||||
|
||||
maintainers:
|
||||
- Aaro Koskinen <aaro.koskinen@iki.fi>
|
||||
- Andreas Kemnade <andreas@kemnade.info>
|
||||
- Kevin Hilman <khilman@baylibre.com>
|
||||
- Roger Quadros <rogerq@kernel.org>
|
||||
- Tony Lindgren <tony@atomide.com>
|
||||
|
||||
description:
|
||||
Power and Reset Manager is an IP block on OMAP family of devices which
|
||||
handle the power domains and their current state, and provide reset
|
||||
handling for the domains and/or separate IP blocks under the power domain
|
||||
hierarchy.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- ti,am3-prm-inst
|
||||
- ti,am4-prm-inst
|
||||
- ti,omap4-prm-inst
|
||||
- ti,omap5-prm-inst
|
||||
- ti,dra7-prm-inst
|
||||
- const: ti,omap-prm-inst
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#power-domain-cells":
|
||||
const: 0
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
reset-controller@1b00 {
|
||||
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1b00 0x40>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -103,7 +103,7 @@ required:
|
||||
- arm,vexpress,config-bridge
|
||||
|
||||
patternProperties:
|
||||
'clk[0-9]*$':
|
||||
'^clock-controller.*$':
|
||||
type: object
|
||||
description:
|
||||
clocks
|
||||
@ -137,7 +137,7 @@ patternProperties:
|
||||
- arm,vexpress-sysreg,func
|
||||
- "#clock-cells"
|
||||
|
||||
"^volt-.+$":
|
||||
"^regulator-.+$":
|
||||
$ref: /schemas/regulator/regulator.yaml#
|
||||
properties:
|
||||
compatible:
|
||||
@ -272,7 +272,7 @@ examples:
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
clk0 {
|
||||
clock-controller {
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 0>;
|
||||
#clock-cells = <0>;
|
||||
|
||||
@ -18,26 +18,6 @@ maintainers:
|
||||
- Hans de Goede <hdegoede@redhat.com>
|
||||
- Jens Axboe <axboe@kernel.dk>
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- brcm,iproc-ahci
|
||||
- cavium,octeon-7130-ahci
|
||||
- hisilicon,hisi-ahci
|
||||
- ibm,476gtr-ahci
|
||||
- marvell,armada-3700-ahci
|
||||
- marvell,armada-8k-ahci
|
||||
- marvell,berlin2q-ahci
|
||||
- qcom,apq8064-ahci
|
||||
- qcom,ipq806x-ahci
|
||||
- socionext,uniphier-pro4-ahci
|
||||
- socionext,uniphier-pxs2-ahci
|
||||
- socionext,uniphier-pxs3-ahci
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
|
||||
@ -54,4 +54,7 @@ $defs:
|
||||
each port can have a Port Multiplier attached thus allowing to
|
||||
access more than one drive by means of a single SATA port.
|
||||
|
||||
port:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
|
||||
...
|
||||
|
||||
@ -66,7 +66,7 @@ then:
|
||||
required:
|
||||
- refresh-rate-hz
|
||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -17,8 +17,10 @@ description: |
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- aspeed,ast2600-ahbc
|
||||
items:
|
||||
- enum:
|
||||
- aspeed,ast2600-ahbc
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@ -32,6 +34,6 @@ additionalProperties: false
|
||||
examples:
|
||||
- |
|
||||
ahbc@1e600000 {
|
||||
compatible = "aspeed,ast2600-ahbc";
|
||||
compatible = "aspeed,ast2600-ahbc", "syscon";
|
||||
reg = <0x1e600000 0x100>;
|
||||
};
|
||||
|
||||
@ -19,21 +19,29 @@ description: |
|
||||
the SDMA can access. There are no special clocks for the bus, because
|
||||
the SDMA controller itself has its interrupt and clock assignments.
|
||||
|
||||
EMI (External Memory Interface) for legacy i.MX35.
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: fsl,spba-bus
|
||||
enum:
|
||||
- fsl,aips
|
||||
- fsl,emi
|
||||
- fsl,spba-bus
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^spba-bus(@[0-9a-f]+)?$"
|
||||
pattern: "^((spba|emi)-bus|bus)(@[0-9a-f]+)?$"
|
||||
|
||||
compatible:
|
||||
items:
|
||||
- const: fsl,spba-bus
|
||||
- enum:
|
||||
- fsl,aips
|
||||
- fsl,emi
|
||||
- fsl,spba-bus
|
||||
- const: simple-bus
|
||||
|
||||
'#address-cells':
|
||||
|
||||
@ -54,7 +54,7 @@ properties:
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 1
|
||||
enum: [ 1, 2 ]
|
||||
|
||||
ranges: true
|
||||
|
||||
|
||||
46
dts/upstream/Bindings/cache/qcom,llcc.yaml
vendored
46
dts/upstream/Bindings/cache/qcom,llcc.yaml
vendored
@ -20,6 +20,7 @@ description: |
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,glymur-llcc
|
||||
- qcom,ipq5424-llcc
|
||||
- qcom,kaanapali-llcc
|
||||
- qcom,qcs615-llcc
|
||||
@ -46,11 +47,11 @@ properties:
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
maxItems: 10
|
||||
maxItems: 14
|
||||
|
||||
reg-names:
|
||||
minItems: 1
|
||||
maxItems: 10
|
||||
maxItems: 14
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
@ -84,6 +85,47 @@ allOf:
|
||||
items:
|
||||
- const: llcc0_base
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,glymur-llcc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
items:
|
||||
- description: LLCC0 base register region
|
||||
- description: LLCC1 base register region
|
||||
- description: LLCC2 base register region
|
||||
- description: LLCC3 base register region
|
||||
- description: LLCC4 base register region
|
||||
- description: LLCC5 base register region
|
||||
- description: LLCC6 base register region
|
||||
- description: LLCC7 base register region
|
||||
- description: LLCC8 base register region
|
||||
- description: LLCC9 base register region
|
||||
- description: LLCC10 base register region
|
||||
- description: LLCC11 base register region
|
||||
- description: LLCC broadcast base register region
|
||||
- description: LLCC broadcast AND register region
|
||||
reg-names:
|
||||
items:
|
||||
- const: llcc0_base
|
||||
- const: llcc1_base
|
||||
- const: llcc2_base
|
||||
- const: llcc3_base
|
||||
- const: llcc4_base
|
||||
- const: llcc5_base
|
||||
- const: llcc6_base
|
||||
- const: llcc7_base
|
||||
- const: llcc8_base
|
||||
- const: llcc9_base
|
||||
- const: llcc10_base
|
||||
- const: llcc11_base
|
||||
- const: llcc_broadcast_base
|
||||
- const: llcc_broadcast_and_base
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
116
dts/upstream/Bindings/clock/amlogic,t7-peripherals-clkc.yaml
Normal file
116
dts/upstream/Bindings/clock/amlogic,t7-peripherals-clkc.yaml
Normal file
@ -0,0 +1,116 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/amlogic,t7-peripherals-clkc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Amlogic T7 Peripherals Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
- Jerome Brunet <jbrunet@baylibre.com>
|
||||
- Xianwei Zhao <xianwei.zhao@amlogic.com>
|
||||
- Jian Hu <jian.hu@amlogic.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: amlogic,t7-peripherals-clkc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
minItems: 14
|
||||
items:
|
||||
- description: input oscillator
|
||||
- description: input sys clk
|
||||
- description: input fixed pll
|
||||
- description: input fclk div 2
|
||||
- description: input fclk div 2p5
|
||||
- description: input fclk div 3
|
||||
- description: input fclk div 4
|
||||
- description: input fclk div 5
|
||||
- description: input fclk div 7
|
||||
- description: input hifi pll
|
||||
- description: input gp0 pll
|
||||
- description: input gp1 pll
|
||||
- description: input mpll1
|
||||
- description: input mpll2
|
||||
- description: external input rmii oscillator (optional)
|
||||
- description: input video pll0 (optional)
|
||||
- description: external pad input for rtc (optional)
|
||||
|
||||
clock-names:
|
||||
minItems: 14
|
||||
items:
|
||||
- const: xtal
|
||||
- const: sys
|
||||
- const: fix
|
||||
- const: fdiv2
|
||||
- const: fdiv2p5
|
||||
- const: fdiv3
|
||||
- const: fdiv4
|
||||
- const: fdiv5
|
||||
- const: fdiv7
|
||||
- const: hifi
|
||||
- const: gp0
|
||||
- const: gp1
|
||||
- const: mpll1
|
||||
- const: mpll2
|
||||
- const: ext_rmii
|
||||
- const: vid_pll0
|
||||
- const: ext_rtc
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
apb {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clkc_periphs:clock-controller@0 {
|
||||
compatible = "amlogic,t7-peripherals-clkc";
|
||||
reg = <0 0x0 0 0x1c8>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&xtal>,
|
||||
<&scmi_clk 13>,
|
||||
<&scmi_clk 16>,
|
||||
<&scmi_clk 18>,
|
||||
<&scmi_clk 20>,
|
||||
<&scmi_clk 22>,
|
||||
<&scmi_clk 24>,
|
||||
<&scmi_clk 26>,
|
||||
<&scmi_clk 28>,
|
||||
<&hifi 1>,
|
||||
<&gp0 1>,
|
||||
<&gp1 1>,
|
||||
<&mpll 4>,
|
||||
<&mpll 6>;
|
||||
clock-names = "xtal",
|
||||
"sys",
|
||||
"fix",
|
||||
"fdiv2",
|
||||
"fdiv2p5",
|
||||
"fdiv3",
|
||||
"fdiv4",
|
||||
"fdiv5",
|
||||
"fdiv7",
|
||||
"hifi",
|
||||
"gp0",
|
||||
"gp1",
|
||||
"mpll1",
|
||||
"mpll2";
|
||||
};
|
||||
};
|
||||
114
dts/upstream/Bindings/clock/amlogic,t7-pll-clkc.yaml
Normal file
114
dts/upstream/Bindings/clock/amlogic,t7-pll-clkc.yaml
Normal file
@ -0,0 +1,114 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Amlogic T7 PLL Clock Control Controller
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
- Jerome Brunet <jbrunet@baylibre.com>
|
||||
- Jian Hu <jian.hu@amlogic.com>
|
||||
- Xianwei Zhao <xianwei.zhao@amlogic.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- amlogic,t7-gp0-pll
|
||||
- amlogic,t7-gp1-pll
|
||||
- amlogic,t7-hifi-pll
|
||||
- amlogic,t7-pcie-pll
|
||||
- amlogic,t7-mpll
|
||||
- amlogic,t7-hdmi-pll
|
||||
- amlogic,t7-mclk-pll
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: mclk pll input oscillator gate
|
||||
- description: oscillator input clock source for mclk_sel_0
|
||||
- description: fixed input clock source for mclk_sel_0
|
||||
minItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: in0
|
||||
- const: in1
|
||||
- const: in2
|
||||
minItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: amlogic,t7-mclk-pll
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
|
||||
clock-names:
|
||||
minItems: 3
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- amlogic,t7-gp0-pll
|
||||
- amlogic,t7-gp1--pll
|
||||
- amlogic,t7-hifi-pll
|
||||
- amlogic,t7-pcie-pll
|
||||
- amlogic,t7-mpll
|
||||
- amlogic,t7-hdmi-pll
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
maxItems: 1
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
apb {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clock-controller@8080 {
|
||||
compatible = "amlogic,t7-gp0-pll";
|
||||
reg = <0 0x8080 0 0x20>;
|
||||
clocks = <&scmi_clk 2>;
|
||||
clock-names = "in0";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock-controller@8300 {
|
||||
compatible = "amlogic,t7-mclk-pll";
|
||||
reg = <0 0x8300 0 0x18>;
|
||||
clocks = <&scmi_clk 2>,
|
||||
<&xtal>,
|
||||
<&scmi_clk 31>;
|
||||
clock-names = "in0", "in1", "in2";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
@ -29,9 +29,10 @@ properties:
|
||||
enum:
|
||||
- google,gs101-cmu-top
|
||||
- google,gs101-cmu-apm
|
||||
- google,gs101-cmu-misc
|
||||
- google,gs101-cmu-dpu
|
||||
- google,gs101-cmu-hsi0
|
||||
- google,gs101-cmu-hsi2
|
||||
- google,gs101-cmu-misc
|
||||
- google,gs101-cmu-peric0
|
||||
- google,gs101-cmu-peric1
|
||||
|
||||
@ -52,6 +53,11 @@ properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
samsung,sysreg:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to system registers interface.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
@ -77,6 +83,24 @@ allOf:
|
||||
items:
|
||||
- const: oscclk
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: google,gs101-cmu-dpu
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (24.576 MHz)
|
||||
- description: DPU bus clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
@ -166,6 +190,18 @@ allOf:
|
||||
- const: bus
|
||||
- const: ip
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: google,gs101-cmu-top
|
||||
then:
|
||||
properties:
|
||||
samsung,sysreg: false
|
||||
else:
|
||||
required:
|
||||
- samsung,sysreg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
@ -175,7 +211,7 @@ examples:
|
||||
|
||||
cmu_top: clock-controller@1e080000 {
|
||||
compatible = "google,gs101-cmu-top";
|
||||
reg = <0x1e080000 0x8000>;
|
||||
reg = <0x1e080000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&ext_24_5m>;
|
||||
clock-names = "oscclk";
|
||||
|
||||
@ -14,11 +14,9 @@ maintainers:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt7622-pciesys
|
||||
- const: syscon
|
||||
- const: mediatek,mt7629-pciesys
|
||||
enum:
|
||||
- mediatek,mt7622-pciesys
|
||||
- mediatek,mt7629-pciesys
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@ -40,7 +38,7 @@ additionalProperties: false
|
||||
examples:
|
||||
- |
|
||||
clock-controller@1a100800 {
|
||||
compatible = "mediatek,mt7622-pciesys", "syscon";
|
||||
compatible = "mediatek,mt7622-pciesys";
|
||||
reg = <0x1a100800 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
@ -17,7 +17,11 @@ description: |
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: microchip,mpfs-ccc
|
||||
oneOf:
|
||||
- items:
|
||||
- const: microchip,pic64gx-ccc
|
||||
- const: microchip,mpfs-ccc
|
||||
- const: microchip,mpfs-ccc
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
||||
@ -19,7 +19,11 @@ description: |
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: microchip,mpfs-clkcfg
|
||||
oneOf:
|
||||
- items:
|
||||
- const: microchip,pic64gx-clkcfg
|
||||
- const: microchip,mpfs-clkcfg
|
||||
- const: microchip,mpfs-clkcfg
|
||||
|
||||
reg:
|
||||
oneOf:
|
||||
@ -69,6 +73,16 @@ required:
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: microchip,pic64gx-clkcfg
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8953.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on MSM8953
|
||||
title: Qualcomm Global Clock & Reset Controller on MSM8937, MSM8940, MSM8953 and SDM439
|
||||
|
||||
maintainers:
|
||||
- Adam Skladowski <a_skl39@protonmail.com>
|
||||
@ -13,7 +13,7 @@ maintainers:
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on MSM8937 or MSM8953.
|
||||
domains on MSM8937, MSM8940, MSM8953 or SDM439.
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,gcc-msm8917.h
|
||||
@ -23,7 +23,9 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,gcc-msm8937
|
||||
- qcom,gcc-msm8940
|
||||
- qcom,gcc-msm8953
|
||||
- qcom,gcc-sdm439
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
||||
63
dts/upstream/Bindings/clock/qcom,kaanapali-gxclkctl.yaml
Normal file
63
dts/upstream/Bindings/clock/qcom,kaanapali-gxclkctl.yaml
Normal file
@ -0,0 +1,63 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,kaanapali-gxclkctl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics power domain Controller on Kaanapali
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <taniya.das@oss.qualcomm.com>
|
||||
|
||||
description: |
|
||||
Qualcomm GX(graphics) is a clock controller which has PLLs, clocks and
|
||||
Power domains (GDSC). This module provides the power domains control
|
||||
of gxclkctl on Qualcomm SoCs which helps the recovery of Graphics subsystem.
|
||||
|
||||
See also:
|
||||
include/dt-bindings/clock/qcom,kaanapali-gxclkctl.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,kaanapali-gxclkctl
|
||||
|
||||
power-domains:
|
||||
description:
|
||||
Power domains required for the clock controller to operate
|
||||
items:
|
||||
- description: GFX power domain
|
||||
- description: GMXC power domain
|
||||
- description: GPUCC(CX) power domain
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- power-domains
|
||||
- '#power-domain-cells'
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/power/qcom,rpmhpd.h>
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clock-controller@3d64000 {
|
||||
compatible = "qcom,kaanapali-gxclkctl";
|
||||
reg = <0x0 0x03d64000 0x0 0x6000>;
|
||||
power-domains = <&rpmhpd RPMHPD_GFX>,
|
||||
<&rpmhpd RPMHPD_GMXC>,
|
||||
<&gpucc 0>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -9,23 +9,32 @@ title: Qualcomm Camera Clock & Reset Controller on SM8450
|
||||
maintainers:
|
||||
- Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
|
||||
- Jagadeesh Kona <quic_jkona@quicinc.com>
|
||||
- Taniya Das <taniya.das@oss.qualcomm.com>
|
||||
|
||||
description: |
|
||||
Qualcomm camera clock control module provides the clocks, resets and power
|
||||
domains on SM8450.
|
||||
|
||||
See also:
|
||||
include/dt-bindings/clock/qcom,kaanapali-camcc.h
|
||||
include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h
|
||||
include/dt-bindings/clock/qcom,sm8450-camcc.h
|
||||
include/dt-bindings/clock/qcom,sm8550-camcc.h
|
||||
include/dt-bindings/clock/qcom,sm8650-camcc.h
|
||||
include/dt-bindings/clock/qcom,sm8750-cambistmclkcc.h
|
||||
include/dt-bindings/clock/qcom,sm8750-camcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,kaanapali-cambistmclkcc
|
||||
- qcom,kaanapali-camcc
|
||||
- qcom,sm8450-camcc
|
||||
- qcom,sm8475-camcc
|
||||
- qcom,sm8550-camcc
|
||||
- qcom,sm8650-camcc
|
||||
- qcom,sm8750-cambistmclkcc
|
||||
- qcom,sm8750-camcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
@ -63,6 +72,8 @@ allOf:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,kaanapali-cambistmclkcc
|
||||
- qcom,kaanapali-camcc
|
||||
- qcom,sc8280xp-camcc
|
||||
- qcom,sm8450-camcc
|
||||
- qcom,sm8550-camcc
|
||||
|
||||
@ -14,6 +14,7 @@ description: |
|
||||
domains on Qualcomm SoCs.
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,kaanapali-gpucc.h
|
||||
include/dt-bindings/clock/qcom,milos-gpucc.h
|
||||
include/dt-bindings/clock/qcom,sar2130p-gpucc.h
|
||||
include/dt-bindings/clock/qcom,sm4450-gpucc.h
|
||||
@ -26,6 +27,7 @@ description: |
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,kaanapali-gpucc
|
||||
- qcom,milos-gpucc
|
||||
- qcom,sar2130p-gpucc
|
||||
- qcom,sm4450-gpucc
|
||||
|
||||
@ -15,6 +15,7 @@ description: |
|
||||
domains on SM8450.
|
||||
|
||||
See also:
|
||||
include/dt-bindings/clock/qcom,kaanapali-videocc.h
|
||||
include/dt-bindings/clock/qcom,sm8450-videocc.h
|
||||
include/dt-bindings/clock/qcom,sm8650-videocc.h
|
||||
include/dt-bindings/clock/qcom,sm8750-videocc.h
|
||||
@ -22,6 +23,7 @@ description: |
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,kaanapali-videocc
|
||||
- qcom,sm8450-videocc
|
||||
- qcom,sm8475-videocc
|
||||
- qcom,sm8550-videocc
|
||||
@ -61,6 +63,7 @@ allOf:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,kaanapali-videocc
|
||||
- qcom,sm8450-videocc
|
||||
- qcom,sm8550-videocc
|
||||
- qcom,sm8750-videocc
|
||||
|
||||
@ -15,6 +15,7 @@ description: |
|
||||
domains on SM8550, SM8650, SM8750 and few other platforms.
|
||||
|
||||
See also:
|
||||
- include/dt-bindings/clock/qcom,kaanapali-dispcc.h
|
||||
- include/dt-bindings/clock/qcom,sm8550-dispcc.h
|
||||
- include/dt-bindings/clock/qcom,sm8650-dispcc.h
|
||||
- include/dt-bindings/clock/qcom,sm8750-dispcc.h
|
||||
@ -23,6 +24,7 @@ description: |
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,kaanapali-dispcc
|
||||
- qcom,sar2130p-dispcc
|
||||
- qcom,sm8550-dispcc
|
||||
- qcom,sm8650-dispcc
|
||||
|
||||
@ -62,6 +62,9 @@ properties:
|
||||
- description: USB4_1 PHY max PIPE clock source
|
||||
- description: USB4_2 PHY PCIE PIPE clock source
|
||||
- description: USB4_2 PHY max PIPE clock source
|
||||
- description: UFS PHY RX Symbol 0 clock source
|
||||
- description: UFS PHY RX Symbol 1 clock source
|
||||
- description: UFS PHY TX Symbol 0 clock source
|
||||
|
||||
power-domains:
|
||||
description:
|
||||
@ -121,7 +124,10 @@ examples:
|
||||
<&usb4_1_phy_pcie_pipe_clk>,
|
||||
<&usb4_1_phy_max_pipe_clk>,
|
||||
<&usb4_2_phy_pcie_pipe_clk>,
|
||||
<&usb4_2_phy_max_pipe_clk>;
|
||||
<&usb4_2_phy_max_pipe_clk>,
|
||||
<&ufs_phy_rx_symbol_0>,
|
||||
<&ufs_phy_rx_symbol_1>,
|
||||
<&ufs_phy_tx_symbol_0>;
|
||||
power-domains = <&rpmhpd RPMHPD_CX>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
@ -62,7 +62,7 @@ properties:
|
||||
description: Output clock down spread in pcm (1/1000 of percent)
|
||||
|
||||
patternProperties:
|
||||
"^DIF[0-19]$":
|
||||
"^DIF1?[0-9]$":
|
||||
type: object
|
||||
description:
|
||||
Description of one of the outputs (DIF0..DIF19).
|
||||
@ -107,6 +107,15 @@ examples:
|
||||
DIF0 {
|
||||
renesas,slew-rate = <3000000>;
|
||||
};
|
||||
|
||||
/* Not present on 9FGV0241, used for DT validation only */
|
||||
DIF2 {
|
||||
renesas,slew-rate = <2000000>;
|
||||
};
|
||||
|
||||
DIF19 {
|
||||
renesas,slew-rate = <3000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -40,6 +40,7 @@ properties:
|
||||
- samsung,exynosautov920-cmu-hsi2
|
||||
- samsung,exynosautov920-cmu-m2m
|
||||
- samsung,exynosautov920-cmu-mfc
|
||||
- samsung,exynosautov920-cmu-mfd
|
||||
- samsung,exynosautov920-cmu-misc
|
||||
- samsung,exynosautov920-cmu-peric0
|
||||
- samsung,exynosautov920-cmu-peric1
|
||||
@ -268,6 +269,24 @@ allOf:
|
||||
- const: mfc
|
||||
- const: wfd
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov920-cmu-mfd
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (38.4 MHz)
|
||||
- description: CMU_MFD NOC clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: noc
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
|
||||
@ -4,14 +4,16 @@
|
||||
$id: http://devicetree.org/schemas/clock/spacemit,k1-pll.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: SpacemiT K1 PLL
|
||||
title: SpacemiT K1/K3 PLL
|
||||
|
||||
maintainers:
|
||||
- Haylen Chu <heylenay@4d2.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: spacemit,k1-pll
|
||||
enum:
|
||||
- spacemit,k1-pll
|
||||
- spacemit,k3-pll
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@ -28,7 +30,8 @@ properties:
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
description:
|
||||
See <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
|
||||
For K1 SoC, check <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
|
||||
For K3 SoC, check <dt-bindings/clock/spacemit,k3-clocks.h> for valid indices.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
145
dts/upstream/Bindings/connector/pcie-m2-m-connector.yaml
Normal file
145
dts/upstream/Bindings/connector/pcie-m2-m-connector.yaml
Normal file
@ -0,0 +1,145 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/connector/pcie-m2-m-connector.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: PCIe M.2 Mechanical Key M Connector
|
||||
|
||||
maintainers:
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
|
||||
|
||||
description:
|
||||
A PCIe M.2 M connector node represents a physical PCIe M.2 Mechanical Key M
|
||||
connector. The Mechanical Key M connectors are used to connect SSDs to the
|
||||
host system over PCIe/SATA interfaces. These connectors also offer optional
|
||||
interfaces like USB, SMBus.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: pcie-m2-m-connector
|
||||
|
||||
vpcie3v3-supply:
|
||||
description: A phandle to the regulator for 3.3v supply.
|
||||
|
||||
vpcie1v8-supply:
|
||||
description: A phandle to the regulator for VIO 1.8v supply.
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description: OF graph bindings modeling the interfaces exposed on the
|
||||
connector. Since a single connector can have multiple interfaces, every
|
||||
interface has an assigned OF graph port number as described below.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: PCIe interface
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: SATA interface
|
||||
|
||||
port@2:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: USB 2.0 interface
|
||||
|
||||
anyOf:
|
||||
- required:
|
||||
- port@0
|
||||
- required:
|
||||
- port@1
|
||||
|
||||
i2c-parent:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: I2C interface
|
||||
|
||||
clocks:
|
||||
description: 32.768 KHz Suspend Clock (SUSCLK) input from the host system to
|
||||
the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.1 for
|
||||
more details.
|
||||
maxItems: 1
|
||||
|
||||
pedet-gpios:
|
||||
description: GPIO input to PEDET signal. This signal is used by the host
|
||||
systems to determine the communication protocol that the M.2 card uses;
|
||||
SATA signaling (low) or PCIe signaling (high). Refer, PCI Express M.2
|
||||
Specification r4.0, sec 3.3.4.2 for more details.
|
||||
maxItems: 1
|
||||
|
||||
viocfg-gpios:
|
||||
description: GPIO input to IO voltage configuration (VIO_CFG) signal. This
|
||||
signal is used by the host systems to determine whether the card supports
|
||||
an independent IO voltage domain for the sideband signals or not. Refer,
|
||||
PCI Express M.2 Specification r4.0, sec 3.1.15.1 for more details.
|
||||
maxItems: 1
|
||||
|
||||
pwrdis-gpios:
|
||||
description: GPIO output to Power Disable (PWRDIS) signal. This signal is
|
||||
used by the host system to disable power on the M.2 card. Refer, PCI
|
||||
Express M.2 Specification r4.0, sec 3.3.5.2 for more details.
|
||||
maxItems: 1
|
||||
|
||||
pln-gpios:
|
||||
description: GPIO output to Power Loss Notification (PLN#) signal. This
|
||||
signal is used by the host system to notify the M.2 card that the power
|
||||
loss event is about to occur. Refer, PCI Express M.2 Specification r4.0,
|
||||
sec 3.2.17.1 for more details.
|
||||
maxItems: 1
|
||||
|
||||
plas3-gpios:
|
||||
description: GPIO input to Power Loss Acknowledge (PLA_S3#) signal. This
|
||||
signal is used by the host system to receive the acknowledgment of the M.2
|
||||
card's preparation for power loss.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- vpcie3v3-supply
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# PCI M.2 Key M connector for SSDs with PCIe interface
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
connector {
|
||||
compatible = "pcie-m2-m-connector";
|
||||
vpcie3v3-supply = <&vreg_nvme>;
|
||||
i2c-parent = <&i2c0>;
|
||||
pedet-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>;
|
||||
viocfg-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
|
||||
pwrdis-gpios = <&tlmm 97 GPIO_ACTIVE_HIGH>;
|
||||
pln-gpios = <&tlmm 98 GPIO_ACTIVE_LOW>;
|
||||
plas3-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <0>;
|
||||
|
||||
endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&pcie6_port0_ep>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <2>;
|
||||
|
||||
endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&usb_hs_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -301,6 +301,7 @@ properties:
|
||||
maxItems: 4
|
||||
|
||||
dependencies:
|
||||
pd-disable: [typec-power-opmode]
|
||||
sink-vdos-v1: [ sink-vdos ]
|
||||
sink-vdos: [ sink-vdos-v1 ]
|
||||
|
||||
|
||||
@ -35,6 +35,7 @@ properties:
|
||||
- description: v2 of CPUFREQ HW (EPSS)
|
||||
items:
|
||||
- enum:
|
||||
- qcom,milos-cpufreq-epss
|
||||
- qcom,qcs8300-cpufreq-epss
|
||||
- qcom,qdu1000-cpufreq-epss
|
||||
- qcom,sa8255p-cpufreq-epss
|
||||
@ -169,6 +170,7 @@ allOf:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,milos-cpufreq-epss
|
||||
- qcom,qcs8300-cpufreq-epss
|
||||
- qcom,sc7280-cpufreq-epss
|
||||
- qcom,sm8250-cpufreq-epss
|
||||
|
||||
@ -30,11 +30,17 @@ properties:
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
aspeed,ahbc:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
A phandle to the AHB controller node, which must be a syscon
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- interrupts
|
||||
- aspeed,ahbc
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
@ -46,4 +52,5 @@ examples:
|
||||
reg = <0x1e6fa000 0x400>, <0x1e710000 0x1800>;
|
||||
interrupts = <160>;
|
||||
clocks = <&syscon ASPEED_CLK_GATE_RSACLK>;
|
||||
aspeed,ahbc = <&ahbc>;
|
||||
};
|
||||
|
||||
@ -16,6 +16,7 @@ properties:
|
||||
- const: atmel,at91sam9g46-aes
|
||||
- items:
|
||||
- enum:
|
||||
- microchip,lan9691-aes
|
||||
- microchip,sam9x7-aes
|
||||
- microchip,sama7d65-aes
|
||||
- const: atmel,at91sam9g46-aes
|
||||
|
||||
@ -16,6 +16,7 @@ properties:
|
||||
- const: atmel,at91sam9g46-sha
|
||||
- items:
|
||||
- enum:
|
||||
- microchip,lan9691-sha
|
||||
- microchip,sam9x7-sha
|
||||
- microchip,sama7d65-sha
|
||||
- const: atmel,at91sam9g46-sha
|
||||
|
||||
@ -12,6 +12,14 @@ maintainers:
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: marvell,armada-cp110-crypto
|
||||
- const: inside-secure,safexcel-eip197b
|
||||
- items:
|
||||
- enum:
|
||||
- marvell,armada-3700-crypto
|
||||
- mediatek,mt7986-crypto
|
||||
- const: inside-secure,safexcel-eip97ies
|
||||
- const: inside-secure,safexcel-eip197b
|
||||
- const: inside-secure,safexcel-eip197d
|
||||
- const: inside-secure,safexcel-eip97ies
|
||||
@ -26,9 +34,11 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
minItems: 4
|
||||
maxItems: 6
|
||||
|
||||
interrupt-names:
|
||||
minItems: 4
|
||||
items:
|
||||
- const: ring0
|
||||
- const: ring1
|
||||
@ -65,6 +75,18 @@ allOf:
|
||||
minItems: 2
|
||||
required:
|
||||
- clock-names
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
not:
|
||||
contains:
|
||||
const: mediatek,mt7986-crypto
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
minItems: 6
|
||||
interrupt-names:
|
||||
minItems: 6
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
||||
@ -14,6 +14,7 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- qcom,kaanapali-inline-crypto-engine
|
||||
- qcom,milos-inline-crypto-engine
|
||||
- qcom,qcs8300-inline-crypto-engine
|
||||
- qcom,sa8775p-inline-crypto-engine
|
||||
- qcom,sc7180-inline-crypto-engine
|
||||
|
||||
@ -21,6 +21,7 @@ properties:
|
||||
- qcom,ipq5424-trng
|
||||
- qcom,ipq9574-trng
|
||||
- qcom,kaanapali-trng
|
||||
- qcom,milos-trng
|
||||
- qcom,qcs615-trng
|
||||
- qcom,qcs8300-trng
|
||||
- qcom,sa8255p-trng
|
||||
@ -30,6 +31,7 @@ properties:
|
||||
- qcom,sm8550-trng
|
||||
- qcom,sm8650-trng
|
||||
- qcom,sm8750-trng
|
||||
- qcom,x1e80100-trng
|
||||
- const: qcom,trng
|
||||
|
||||
reg:
|
||||
|
||||
@ -14,6 +14,8 @@ description: |
|
||||
The ZynqMP AES-GCM hardened cryptographic accelerator is used to
|
||||
encrypt or decrypt the data with provided key and initialization vector.
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: xlnx,zynqmp-aes
|
||||
|
||||
@ -59,6 +59,7 @@ required:
|
||||
- compatible
|
||||
- clocks
|
||||
- ports
|
||||
- reg
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
@ -73,6 +74,15 @@ allOf:
|
||||
ports:
|
||||
properties:
|
||||
port@2: false
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: fsl,imx6sx-ldb
|
||||
then:
|
||||
required:
|
||||
- reg-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
||||
@ -79,7 +79,6 @@ properties:
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reset-gpios
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
@ -33,6 +33,7 @@ properties:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- onnn,fin3385 # OnSemi FIN3385
|
||||
- ti,ds90c185 # For the TI DS90C185 FPD-Link Serializer
|
||||
- ti,ds90c187 # For the TI DS90C187 FPD-Link Serializer
|
||||
- ti,sn75lvds83 # For the TI SN75LVDS83 FlatLink transmitter
|
||||
|
||||
@ -19,6 +19,9 @@ properties:
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
video-ports:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 0x230145
|
||||
|
||||
@ -14,16 +14,21 @@ description: |
|
||||
RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
|
||||
up to four data lanes.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/display/dsi-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
|
||||
- renesas,r9a07g054-mipi-dsi # RZ/V2L
|
||||
- const: renesas,rzg2l-mipi-dsi
|
||||
|
||||
- items:
|
||||
- const: renesas,r9a09g056-mipi-dsi # RZ/V2N
|
||||
- const: renesas,r9a09g057-mipi-dsi
|
||||
|
||||
- enum:
|
||||
- renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
|
||||
- renesas,r9a07g054-mipi-dsi # RZ/V2L
|
||||
- const: renesas,rzg2l-mipi-dsi
|
||||
- renesas,r9a09g057-mipi-dsi # RZ/V2H(P)
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@ -49,34 +54,56 @@ properties:
|
||||
- const: debug
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: DSI D-PHY PLL multiplied clock
|
||||
- description: DSI D-PHY system clock
|
||||
- description: DSI AXI bus clock
|
||||
- description: DSI Register access clock
|
||||
- description: DSI Video clock
|
||||
- description: DSI D-PHY Escape mode transmit clock
|
||||
oneOf:
|
||||
- items:
|
||||
- description: DSI D-PHY PLL multiplied clock
|
||||
- description: DSI D-PHY system clock
|
||||
- description: DSI AXI bus clock
|
||||
- description: DSI Register access clock
|
||||
- description: DSI Video clock
|
||||
- description: DSI D-PHY Escape mode transmit clock
|
||||
- items:
|
||||
- description: DSI D-PHY PLL reference clock
|
||||
- description: DSI AXI bus clock
|
||||
- description: DSI Register access clock
|
||||
- description: DSI Video clock
|
||||
- description: DSI D-PHY Escape mode transmit clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pllclk
|
||||
- const: sysclk
|
||||
- const: aclk
|
||||
- const: pclk
|
||||
- const: vclk
|
||||
- const: lpclk
|
||||
oneOf:
|
||||
- items:
|
||||
- const: pllclk
|
||||
- const: sysclk
|
||||
- const: aclk
|
||||
- const: pclk
|
||||
- const: vclk
|
||||
- const: lpclk
|
||||
- items:
|
||||
- const: pllrefclk
|
||||
- const: aclk
|
||||
- const: pclk
|
||||
- const: vclk
|
||||
- const: lpclk
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: MIPI_DSI_CMN_RSTB
|
||||
- description: MIPI_DSI_ARESET_N
|
||||
- description: MIPI_DSI_PRESET_N
|
||||
oneOf:
|
||||
- items:
|
||||
- description: MIPI_DSI_CMN_RSTB
|
||||
- description: MIPI_DSI_ARESET_N
|
||||
- description: MIPI_DSI_PRESET_N
|
||||
- items:
|
||||
- description: MIPI_DSI_ARESET_N
|
||||
- description: MIPI_DSI_PRESET_N
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: rst
|
||||
- const: arst
|
||||
- const: prst
|
||||
oneOf:
|
||||
- items:
|
||||
- const: rst
|
||||
- const: arst
|
||||
- const: prst
|
||||
- items:
|
||||
- const: arst
|
||||
- const: prst
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
@ -130,6 +157,41 @@ required:
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: ../dsi-controller.yaml#
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,r9a09g057-mipi-dsi
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 5
|
||||
|
||||
clock-names:
|
||||
maxItems: 5
|
||||
|
||||
resets:
|
||||
maxItems: 2
|
||||
|
||||
reset-names:
|
||||
maxItems: 2
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 6
|
||||
|
||||
clock-names:
|
||||
minItems: 6
|
||||
|
||||
resets:
|
||||
minItems: 3
|
||||
|
||||
reset-names:
|
||||
minItems: 3
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r9a07g044-cpg.h>
|
||||
|
||||
@ -27,6 +27,7 @@ properties:
|
||||
- const: adi,adv7123
|
||||
- enum:
|
||||
- adi,adv7123
|
||||
- algoltek,ag6311
|
||||
- asl-tek,cs5263
|
||||
- dumb-vga-dac
|
||||
- parade,ps185hdm
|
||||
|
||||
@ -117,7 +117,7 @@ properties:
|
||||
- 1 # 3.5dB pre-emphasis
|
||||
- 2 # 6dB pre-emphasis
|
||||
|
||||
oneOf:
|
||||
anyOf:
|
||||
- required:
|
||||
- port@0
|
||||
- required:
|
||||
|
||||
@ -1,17 +0,0 @@
|
||||
Android Goldfish framebuffer
|
||||
|
||||
Android Goldfish framebuffer device used by Android emulator.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should contain "google,goldfish-fb"
|
||||
- reg : <registers mapping>
|
||||
- interrupts : <interrupt mapping>
|
||||
|
||||
Example:
|
||||
|
||||
display-controller@1f008000 {
|
||||
compatible = "google,goldfish-fb";
|
||||
interrupts = <0x10>;
|
||||
reg = <0x1f008000 0x100>;
|
||||
};
|
||||
38
dts/upstream/Bindings/display/google,goldfish-fb.yaml
Normal file
38
dts/upstream/Bindings/display/google,goldfish-fb.yaml
Normal file
@ -0,0 +1,38 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/google,goldfish-fb.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Android Goldfish Framebuffer
|
||||
|
||||
maintainers:
|
||||
- Kuan-Wei Chiu <visitorckw@gmail.com>
|
||||
|
||||
description:
|
||||
Android Goldfish framebuffer device used by Android emulator.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: google,goldfish-fb
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
display@1f008000 {
|
||||
compatible = "google,goldfish-fb";
|
||||
reg = <0x1f008000 0x100>;
|
||||
interrupts = <16>;
|
||||
};
|
||||
@ -253,7 +253,6 @@ allOf:
|
||||
enum:
|
||||
# these platforms support 2 streams MST on some interfaces,
|
||||
# others are SST only
|
||||
- qcom,glymur-dp
|
||||
- qcom,sc8280xp-dp
|
||||
- qcom,x1e80100-dp
|
||||
then:
|
||||
@ -310,6 +309,26 @@ allOf:
|
||||
minItems: 6
|
||||
maxItems: 8
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
# these platforms support 2 streams MST on some interfaces,
|
||||
# others are SST only, but all controllers have 4 ports
|
||||
- qcom,glymur-dp
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 9
|
||||
maxItems: 9
|
||||
clocks:
|
||||
minItems: 5
|
||||
maxItems: 6
|
||||
clocks-names:
|
||||
minItems: 5
|
||||
maxItems: 6
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@ -15,6 +15,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,apq8064-dsi-ctrl
|
||||
- qcom,kaanapali-dsi-ctrl
|
||||
- qcom,msm8226-dsi-ctrl
|
||||
- qcom,msm8916-dsi-ctrl
|
||||
- qcom,msm8953-dsi-ctrl
|
||||
@ -45,6 +46,11 @@ properties:
|
||||
- qcom,sm8650-dsi-ctrl
|
||||
- qcom,sm8750-dsi-ctrl
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,qcs8300-dsi-ctrl
|
||||
- const: qcom,sa8775p-dsi-ctrl
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
- enum:
|
||||
- qcom,dsi-ctrl-6g-qcm2290
|
||||
- qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible
|
||||
@ -369,6 +375,7 @@ allOf:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,kaanapali-dsi-ctrl
|
||||
- qcom,sm8750-dsi-ctrl
|
||||
then:
|
||||
properties:
|
||||
|
||||
@ -14,18 +14,25 @@ allOf:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,dsi-phy-7nm
|
||||
- qcom,dsi-phy-7nm-8150
|
||||
- qcom,sa8775p-dsi-phy-5nm
|
||||
- qcom,sar2130p-dsi-phy-5nm
|
||||
- qcom,sc7280-dsi-phy-7nm
|
||||
- qcom,sm6375-dsi-phy-7nm
|
||||
- qcom,sm8350-dsi-phy-5nm
|
||||
- qcom,sm8450-dsi-phy-5nm
|
||||
- qcom,sm8550-dsi-phy-4nm
|
||||
- qcom,sm8650-dsi-phy-4nm
|
||||
- qcom,sm8750-dsi-phy-3nm
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,dsi-phy-7nm
|
||||
- qcom,dsi-phy-7nm-8150
|
||||
- qcom,kaanapali-dsi-phy-3nm
|
||||
- qcom,sa8775p-dsi-phy-5nm
|
||||
- qcom,sar2130p-dsi-phy-5nm
|
||||
- qcom,sc7280-dsi-phy-7nm
|
||||
- qcom,sm6375-dsi-phy-7nm
|
||||
- qcom,sm8350-dsi-phy-5nm
|
||||
- qcom,sm8450-dsi-phy-5nm
|
||||
- qcom,sm8550-dsi-phy-4nm
|
||||
- qcom,sm8650-dsi-phy-4nm
|
||||
- qcom,sm8750-dsi-phy-3nm
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,qcs8300-dsi-phy-5nm
|
||||
- const: qcom,sa8775p-dsi-phy-5nm
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
||||
@ -45,11 +45,11 @@ properties:
|
||||
- const: amd,imageon
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
minItems: 1
|
||||
maxItems: 7
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
minItems: 1
|
||||
maxItems: 7
|
||||
|
||||
reg:
|
||||
@ -378,35 +378,74 @@ allOf:
|
||||
- const: xo
|
||||
description: GPUCC clocksource clock
|
||||
|
||||
required:
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,adreno-612.0
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: GPU Core clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: core
|
||||
|
||||
reg:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
|
||||
reg-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: kgsl_3d0_reg_memory
|
||||
- const: cx_mem
|
||||
- const: cx_dbgc
|
||||
|
||||
required:
|
||||
- clocks
|
||||
- clock-names
|
||||
else:
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
oneOf:
|
||||
- pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$'
|
||||
- pattern: '^qcom,adreno-[0-9a-f]{8}$'
|
||||
|
||||
then: # Starting with A6xx, the clocks are usually defined in the GMU node
|
||||
properties:
|
||||
clocks: false
|
||||
clock-names: false
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,adreno-615.0
|
||||
- qcom,adreno-618.0
|
||||
- qcom,adreno-619.0
|
||||
- qcom,adreno-621.0
|
||||
- qcom,adreno-623.0
|
||||
- qcom,adreno-630.2
|
||||
- qcom,adreno-635.0
|
||||
- qcom,adreno-640.1
|
||||
- qcom,adreno-650.2
|
||||
- qcom,adreno-660.1
|
||||
- qcom,adreno-663.0
|
||||
- qcom,adreno-680.1
|
||||
- qcom,adreno-690.0
|
||||
- qcom,adreno-730.1
|
||||
- qcom,adreno-43030c00
|
||||
- qcom,adreno-43050a01
|
||||
- qcom,adreno-43050c01
|
||||
- qcom,adreno-43051401
|
||||
|
||||
reg-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: kgsl_3d0_reg_memory
|
||||
- const: cx_mem
|
||||
- const: cx_dbgc
|
||||
then: # Starting with A6xx, the clocks are usually defined in the GMU node
|
||||
properties:
|
||||
clocks: false
|
||||
clock-names: false
|
||||
|
||||
reg-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: kgsl_3d0_reg_memory
|
||||
- const: cx_mem
|
||||
- const: cx_dbgc
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
126
dts/upstream/Bindings/display/msm/qcom,adreno-rgmu.yaml
Normal file
126
dts/upstream/Bindings/display/msm/qcom,adreno-rgmu.yaml
Normal file
@ -0,0 +1,126 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
||||
%YAML 1.2
|
||||
---
|
||||
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,adreno-rgmu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: RGMU attached to certain Adreno GPUs
|
||||
|
||||
maintainers:
|
||||
- Rob Clark <robin.clark@oss.qualcomm.com>
|
||||
|
||||
description:
|
||||
RGMU (Reduced Graphics Management Unit) IP is present in some GPUs that
|
||||
belong to Adreno A6xx family. It is a small state machine that helps to
|
||||
toggle the GX GDSC (connected to CX rail) to implement IFPC feature and save
|
||||
power.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,adreno-rgmu-612.0
|
||||
- const: qcom,adreno-rgmu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Core RGMU registers
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: GMU clock
|
||||
- description: GPU CX clock
|
||||
- description: GPU AXI clock
|
||||
- description: GPU MEMNOC clock
|
||||
- description: GPU SMMU vote clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: gmu
|
||||
- const: cxo
|
||||
- const: axi
|
||||
- const: memnoc
|
||||
- const: smmu_vote
|
||||
|
||||
power-domains:
|
||||
items:
|
||||
- description: CX GDSC power domain
|
||||
- description: GX GDSC power domain
|
||||
|
||||
power-domain-names:
|
||||
items:
|
||||
- const: cx
|
||||
- const: gx
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: GMU OOB interrupt
|
||||
- description: GMU interrupt
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: oob
|
||||
- const: gmu
|
||||
|
||||
operating-points-v2: true
|
||||
opp-table:
|
||||
type: object
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- power-domains
|
||||
- power-domain-names
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- operating-points-v2
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,qcs615-gpucc.h>
|
||||
#include <dt-bindings/clock/qcom,qcs615-gcc.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/qcom,rpmhpd.h>
|
||||
|
||||
gmu@506a000 {
|
||||
compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu";
|
||||
|
||||
reg = <0x05000000 0x90000>;
|
||||
|
||||
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
|
||||
clock-names = "gmu",
|
||||
"cxo",
|
||||
"axi",
|
||||
"memnoc",
|
||||
"smmu_vote";
|
||||
|
||||
power-domains = <&gpucc CX_GDSC>,
|
||||
<&gpucc GX_GDSC>;
|
||||
power-domain-names = "cx",
|
||||
"gx";
|
||||
|
||||
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "oob",
|
||||
"gmu";
|
||||
|
||||
operating-points-v2 = <&gmu_opp_table>;
|
||||
|
||||
gmu_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -176,13 +176,17 @@ examples:
|
||||
};
|
||||
};
|
||||
|
||||
displayport-controller@ae90000 {
|
||||
displayport-controller@af54000 {
|
||||
compatible = "qcom,glymur-dp";
|
||||
reg = <0xae90000 0x200>,
|
||||
<0xae90200 0x200>,
|
||||
<0xae90400 0x600>,
|
||||
<0xae91000 0x400>,
|
||||
<0xae91400 0x400>;
|
||||
reg = <0xaf54000 0x200>,
|
||||
<0xaf54200 0x200>,
|
||||
<0xaf55000 0xc00>,
|
||||
<0xaf56000 0x400>,
|
||||
<0xaf57000 0x400>,
|
||||
<0xaf58000 0x400>,
|
||||
<0xaf59000 0x400>,
|
||||
<0xaf5a000 0x600>,
|
||||
<0xaf5b000 0x600>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <12>;
|
||||
|
||||
297
dts/upstream/Bindings/display/msm/qcom,kaanapali-mdss.yaml
Normal file
297
dts/upstream/Bindings/display/msm/qcom,kaanapali-mdss.yaml
Normal file
@ -0,0 +1,297 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,kaanapali-mdss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Kaanapali Display MDSS
|
||||
|
||||
maintainers:
|
||||
- Yongxing Mou <yongxing.mou@oss.qualcomm.com>
|
||||
- Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
|
||||
|
||||
description:
|
||||
Kaanapali MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks
|
||||
like DPU display controller, DSI and DP interfaces etc.
|
||||
|
||||
$ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,kaanapali-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB
|
||||
- description: Display hf AXI
|
||||
- description: Display core
|
||||
- description: Display AHB SWI
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: Interconnect path from mdp0 port to the data bus
|
||||
- description: Interconnect path from CPU to the reg bus
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: mdp0-mem
|
||||
- const: cpu-cfg
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,kaanapali-dpu
|
||||
|
||||
"^dsi@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,kaanapali-dsi-ctrl
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,kaanapali-dsi-phy-3nm
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,icc.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/phy/phy-qcom-qmp.h>
|
||||
#include <dt-bindings/power/qcom,rpmhpd.h>
|
||||
|
||||
display-subsystem@9800000 {
|
||||
compatible = "qcom,kaanapali-mdss";
|
||||
reg = <0x09800000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&disp_cc_mdss_ahb_clk>,
|
||||
<&gcc_disp_hf_axi_clk>,
|
||||
<&disp_cc_mdss_mdp_clk>,
|
||||
<&disp_cc_mdss_ahb_swi_clk>;
|
||||
resets = <&disp_cc_mdss_core_bcr>;
|
||||
|
||||
power-domains = <&mdss_gdsc>;
|
||||
|
||||
iommus = <&apps_smmu 0x800 0x2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
display-controller@9801000 {
|
||||
compatible = "qcom,kaanapali-dpu";
|
||||
reg = <0x09801000 0x1c8000>,
|
||||
<0x09b16000 0x3000>;
|
||||
reg-names = "mdp",
|
||||
"vbif";
|
||||
|
||||
interrupts-extended = <&mdss 0>;
|
||||
|
||||
clocks = <&gcc_disp_hf_axi_clk>,
|
||||
<&disp_cc_mdss_ahb_clk>,
|
||||
<&disp_cc_mdss_mdp_lut_clk>,
|
||||
<&disp_cc_mdss_mdp_clk>,
|
||||
<&disp_cc_mdss_vsync_clk>;
|
||||
clock-names = "nrt_bus",
|
||||
"iface",
|
||||
"lut",
|
||||
"core",
|
||||
"vsync";
|
||||
|
||||
assigned-clocks = <&disp_cc_mdss_vsync_clk>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
|
||||
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&mdss_dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
dpu_intf2_out: endpoint {
|
||||
remote-endpoint = <&mdss_dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdp_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-156000000 {
|
||||
opp-hz = /bits/ 64 <156000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs_d1>;
|
||||
};
|
||||
|
||||
opp-207000000 {
|
||||
opp-hz = /bits/ 64 <207000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-337000000 {
|
||||
opp-hz = /bits/ 64 <337000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-417000000 {
|
||||
opp-hz = /bits/ 64 <417000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
|
||||
opp-532000000 {
|
||||
opp-hz = /bits/ 64 <532000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
|
||||
opp-600000000 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
required-opps = <&rpmhpd_opp_nom_l1>;
|
||||
};
|
||||
|
||||
opp-650000000 {
|
||||
opp-hz = /bits/ 64 <650000000>;
|
||||
required-opps = <&rpmhpd_opp_turbo>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi@9ac0000 {
|
||||
compatible = "qcom,kaanapali-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x09ac0000 0x1000>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
interrupts-extended = <&mdss 4>;
|
||||
|
||||
clocks = <&disp_cc_mdss_byte0_clk>,
|
||||
<&disp_cc_mdss_byte0_intf_clk>,
|
||||
<&disp_cc_mdss_pclk0_clk>,
|
||||
<&disp_cc_mdss_esc0_clk>,
|
||||
<&disp_cc_mdss_ahb_clk>,
|
||||
<&gcc_disp_hf_axi_clk>,
|
||||
<&mdss_dsi0_phy 1>,
|
||||
<&mdss_dsi0_phy 0>,
|
||||
<&disp_cc_esync0_clk>,
|
||||
<&disp_cc_osc_clk>,
|
||||
<&disp_cc_mdss_byte0_clk_src>,
|
||||
<&disp_cc_mdss_pclk0_clk_src>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus",
|
||||
"dsi_pll_pixel",
|
||||
"dsi_pll_byte",
|
||||
"esync",
|
||||
"osc",
|
||||
"byte_src",
|
||||
"pixel_src";
|
||||
|
||||
operating-points-v2 = <&mdss_dsi_opp_table>;
|
||||
|
||||
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
||||
|
||||
phys = <&mdss_dsi0_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
mdss_dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
mdss_dsi0_out: endpoint {
|
||||
remote-endpoint = <&panel0_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-187500000 {
|
||||
opp-hz = /bits/ 64 <187500000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs_d1>;
|
||||
};
|
||||
|
||||
opp-250000000 {
|
||||
opp-hz = /bits/ 64 <250000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-312500000 {
|
||||
opp-hz = /bits/ 64 <312500000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-358000000 {
|
||||
opp-hz = /bits/ 64 <358000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi0_phy: phy@9ac1000 {
|
||||
compatible = "qcom,kaanapali-dsi-phy-3nm";
|
||||
reg = <0x09ac1000 0x1cc>,
|
||||
<0x09ac1200 0x80>,
|
||||
<0x09ac1500 0x400>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
clocks = <&disp_cc_mdss_ahb_clk>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface",
|
||||
"ref";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
@ -33,7 +33,7 @@ properties:
|
||||
- const: core
|
||||
|
||||
iommus:
|
||||
maxItems: 2
|
||||
maxItems: 1
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
@ -107,8 +107,7 @@ examples:
|
||||
interconnect-names = "mdp0-mem",
|
||||
"cpu-cfg";
|
||||
|
||||
iommus = <&apps_smmu 0x420 0x2>,
|
||||
<&apps_smmu 0x421 0x0>;
|
||||
iommus = <&apps_smmu 0x420 0x2>;
|
||||
ranges;
|
||||
|
||||
display-controller@5e01000 {
|
||||
|
||||
@ -53,13 +53,23 @@ patternProperties:
|
||||
contains:
|
||||
const: qcom,qcs8300-dp
|
||||
|
||||
"^dsi@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,qcs8300-dsi-ctrl
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,qcs8300-edp-phy
|
||||
enum:
|
||||
- qcom,qcs8300-dsi-phy-5nm
|
||||
- qcom,qcs8300-edp-phy
|
||||
|
||||
required:
|
||||
- compatible
|
||||
@ -71,6 +81,7 @@ examples:
|
||||
#include <dt-bindings/interconnect/qcom,icc.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,qcs8300-gcc.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
|
||||
#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
|
||||
#include <dt-bindings/power/qcom,rpmhpd.h>
|
||||
@ -142,6 +153,13 @@ examples:
|
||||
remote-endpoint = <&mdss_dp0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&mdss_dsi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdp_opp_table: opp-table {
|
||||
@ -169,6 +187,88 @@ examples:
|
||||
};
|
||||
};
|
||||
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,qcs8300-dsi-ctrl",
|
||||
"qcom,sa8775p-dsi-ctrl",
|
||||
"qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <4>;
|
||||
|
||||
clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>,
|
||||
<&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
||||
<&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
|
||||
phys = <&mdss_dsi0_phy>;
|
||||
|
||||
operating-points-v2 = <&dsi0_opp_table>;
|
||||
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
||||
|
||||
vdda-supply = <&vreg_l5a>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
mdss0_dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
mdss0_dsi0_out: endpoint { };
|
||||
};
|
||||
};
|
||||
|
||||
dsi0_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-358000000 {
|
||||
opp-hz = /bits/ 64 <358000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi0_phy: phy@ae94400 {
|
||||
compatible = "qcom,qcs8300-dsi-phy-5nm",
|
||||
"qcom,sa8775p-dsi-phy-5nm";
|
||||
reg = <0x0ae94400 0x200>,
|
||||
<0x0ae94600 0x280>,
|
||||
<0x0ae94900 0x27c>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
|
||||
vdds-supply = <&vreg_l4a>;
|
||||
};
|
||||
|
||||
mdss_dp0_phy: phy@aec2a00 {
|
||||
compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy";
|
||||
|
||||
|
||||
@ -16,6 +16,7 @@ properties:
|
||||
oneOf:
|
||||
- enum:
|
||||
- qcom,glymur-dpu
|
||||
- qcom,kaanapali-dpu
|
||||
- qcom,sa8775p-dpu
|
||||
- qcom,sm8650-dpu
|
||||
- qcom,sm8750-dpu
|
||||
|
||||
@ -10,7 +10,7 @@ maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
description:
|
||||
SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
|
||||
SM8750 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
|
||||
DPU display controller, DSI and DP interfaces etc.
|
||||
|
||||
$ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
@ -16,6 +16,8 @@ properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- anbernic,rg-ds-display-bottom
|
||||
- anbernic,rg-ds-display-top
|
||||
- chongzhou,cz101b4001
|
||||
- kingdisplay,kd101ne3-40ti
|
||||
- melfas,lmfbx101117480
|
||||
|
||||
@ -4,14 +4,16 @@
|
||||
$id: http://devicetree.org/schemas/display/panel/lg,sw43408.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: LG SW43408 1080x2160 DSI panel
|
||||
title: LG SW43408 AMOLED DDIC
|
||||
|
||||
maintainers:
|
||||
- Casey Connolly <casey.connolly@linaro.org>
|
||||
|
||||
description:
|
||||
This panel is used on the Pixel 3, it is a 60hz OLED panel which
|
||||
required DSC (Display Stream Compression) and has rounded corners.
|
||||
The SW43408 is display driver IC with connected panel.
|
||||
|
||||
LG LH546WF1-ED01 panel is used on the Pixel 3, it is a 60hz OLED panel
|
||||
which required DSC (Display Stream Compression) and has rounded corners.
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
@ -19,6 +21,9 @@ allOf:
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
# LG 5.46 inch, 1080x2160 pixels, 18:9 ratio
|
||||
- lg,sw43408-lh546wf1-ed01
|
||||
- const: lg,sw43408
|
||||
|
||||
reg:
|
||||
@ -46,7 +51,7 @@ examples:
|
||||
#size-cells = <0>;
|
||||
|
||||
panel@0 {
|
||||
compatible = "lg,sw43408";
|
||||
compatible = "lg,sw43408-lh546wf1-ed01", "lg,sw43408";
|
||||
reg = <0>;
|
||||
|
||||
vddi-supply = <&vreg_l14a_1p88>;
|
||||
|
||||
@ -55,6 +55,8 @@ properties:
|
||||
- panasonic,vvx10f004b00
|
||||
# Panasonic 10" WUXGA TFT LCD panel
|
||||
- panasonic,vvx10f034n00
|
||||
# Samsung ltl106hl02 10.6" Full HD TFT LCD panel
|
||||
- samsung,ltl106hl02-001
|
||||
# Samsung s6e3fa7 1080x2220 based AMS559NK06 AMOLED panel
|
||||
- samsung,s6e3fa7-ams559nk06
|
||||
# Shangai Top Display Optoelectronics 7" TL070WSH30 1024x600 TFT LCD panel
|
||||
|
||||
@ -154,6 +154,8 @@ properties:
|
||||
- hannstar,hsd070pww1
|
||||
# HannStar Display Corp. HSD100PXN1 10.1" XGA LVDS panel
|
||||
- hannstar,hsd100pxn1
|
||||
# HannStar Display Corp. HSD156JUW2 15.6" FHD (1920x1080) TFT LCD panel
|
||||
- hannstar,hsd156juw2
|
||||
# Hitachi Ltd. Corporation 9" WVGA (800x480) TFT LCD panel
|
||||
- hit,tx23d38vm0caa
|
||||
# Innolux AT043TN24 4.3" WQVGA TFT LCD panel
|
||||
@ -176,6 +178,8 @@ properties:
|
||||
- innolux,g121x1-l03
|
||||
# Innolux Corporation 12.1" G121XCE-L01 XGA (1024x768) TFT LCD panel
|
||||
- innolux,g121xce-l01
|
||||
# InnoLux 15.0" G150XGE-L05 XGA (1024x768) TFT LCD panel
|
||||
- innolux,g150xge-l05
|
||||
# InnoLux 15.6" FHD (1920x1080) TFT LCD panel
|
||||
- innolux,g156hce-l01
|
||||
# InnoLux 13.3" FHD (1920x1080) TFT LCD panel
|
||||
@ -347,7 +351,9 @@ if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: innolux,g101ice-l01
|
||||
enum:
|
||||
- innolux,g101ice-l01
|
||||
- yes-optoelectronics,ytc700tlag-05-201c
|
||||
then:
|
||||
properties:
|
||||
data-mapping: false
|
||||
|
||||
@ -6,11 +6,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung S6E3FC2X01 AMOLED DDIC
|
||||
|
||||
description: The S6E3FC2X01 is display driver IC with connected panel.
|
||||
|
||||
maintainers:
|
||||
- David Heidelberg <david@ixit.cz>
|
||||
|
||||
description: The S6E3FC2X01 is display driver IC with connected panel.
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
|
||||
@ -25,25 +25,21 @@ properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reset-gpios: true
|
||||
|
||||
port: true
|
||||
|
||||
vddio-supply:
|
||||
description: VDD regulator
|
||||
poc-supply:
|
||||
description: POC regulator
|
||||
|
||||
vci-supply:
|
||||
description: VCI regulator
|
||||
|
||||
poc-supply:
|
||||
description: POC regulator
|
||||
vddio-supply:
|
||||
description: VDD regulator
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reset-gpios
|
||||
- vddio-supply
|
||||
- vci-supply
|
||||
- poc-supply
|
||||
- vci-supply
|
||||
- vddio-supply
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
|
||||
@ -34,8 +34,9 @@ properties:
|
||||
spi-cpol: true
|
||||
|
||||
spi-rx-bus-width:
|
||||
minimum: 0
|
||||
maximum: 1
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 1
|
||||
|
||||
dc-gpios:
|
||||
maxItems: 1
|
||||
|
||||
@ -23,6 +23,7 @@ properties:
|
||||
- rockchip,rk3228-dw-hdmi
|
||||
- rockchip,rk3288-dw-hdmi
|
||||
- rockchip,rk3328-dw-hdmi
|
||||
- rockchip,rk3368-dw-hdmi
|
||||
- rockchip,rk3399-dw-hdmi
|
||||
- rockchip,rk3568-dw-hdmi
|
||||
|
||||
|
||||
@ -19,6 +19,7 @@ properties:
|
||||
- rockchip,rk3288-mipi-dsi
|
||||
- rockchip,rk3368-mipi-dsi
|
||||
- rockchip,rk3399-mipi-dsi
|
||||
- rockchip,rk3506-mipi-dsi
|
||||
- rockchip,rk3568-mipi-dsi
|
||||
- rockchip,rv1126-mipi-dsi
|
||||
- const: snps,dw-mipi-dsi
|
||||
@ -75,6 +76,7 @@ allOf:
|
||||
- rockchip,px30-mipi-dsi
|
||||
- rockchip,rk3128-mipi-dsi
|
||||
- rockchip,rk3368-mipi-dsi
|
||||
- rockchip,rk3506-mipi-dsi
|
||||
- rockchip,rk3568-mipi-dsi
|
||||
- rockchip,rv1126-mipi-dsi
|
||||
|
||||
|
||||
@ -69,6 +69,12 @@ properties:
|
||||
- const: main
|
||||
- const: hpd
|
||||
|
||||
no-hpd:
|
||||
type: boolean
|
||||
description:
|
||||
The HPD pin is not present or used for another purpose, and the EDID
|
||||
must be polled instead to determine if a device is attached.
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
description: The HDMI/eDP PHY
|
||||
|
||||
@ -31,6 +31,7 @@ properties:
|
||||
- rockchip,rk3368-vop
|
||||
- rockchip,rk3399-vop-big
|
||||
- rockchip,rk3399-vop-lit
|
||||
- rockchip,rk3506-vop
|
||||
- rockchip,rv1126-vop
|
||||
|
||||
reg:
|
||||
|
||||
@ -76,3 +76,28 @@ examples:
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
display@0 {
|
||||
compatible = "sitronix,st7571";
|
||||
reg = <0>;
|
||||
reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
|
||||
width-mm = <37>;
|
||||
height-mm = <27>;
|
||||
|
||||
panel-timing {
|
||||
hactive = <128>;
|
||||
vactive = <96>;
|
||||
hback-porch = <0>;
|
||||
vback-porch = <0>;
|
||||
clock-frequency = <0>;
|
||||
hfront-porch = <0>;
|
||||
hsync-len = <0>;
|
||||
vfront-porch = <0>;
|
||||
vsync-len = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
58
dts/upstream/Bindings/display/sitronix,st7920.yaml
Normal file
58
dts/upstream/Bindings/display/sitronix,st7920.yaml
Normal file
@ -0,0 +1,58 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/sitronix,st7920.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Sitronix ST7920 LCD Display Controllers
|
||||
|
||||
maintainers:
|
||||
- Iker Pedrosa <ikerpedrosam@gmail.com>
|
||||
|
||||
description:
|
||||
The Sitronix ST7920 is a controller for monochrome dot-matrix graphical LCDs,
|
||||
most commonly used for 128x64 pixel displays.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: sitronix,st7920
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
vdd-supply:
|
||||
description: Regulator that provides 5V Vdd power supply
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
|
||||
spi-max-frequency:
|
||||
maximum: 600000
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- spi-max-frequency
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
display@0 {
|
||||
compatible = "sitronix,st7920";
|
||||
reg = <0>;
|
||||
vdd-supply = <®_5v>;
|
||||
reset-gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
|
||||
spi-max-frequency = <600000>;
|
||||
spi-cs-high;
|
||||
};
|
||||
};
|
||||
@ -18,6 +18,7 @@ properties:
|
||||
enum:
|
||||
- nvidia,tegra114-mipi
|
||||
- nvidia,tegra124-mipi
|
||||
- nvidia,tegra132-mipi
|
||||
- nvidia,tegra210-mipi
|
||||
- nvidia,tegra186-mipi
|
||||
|
||||
|
||||
@ -16,16 +16,21 @@ properties:
|
||||
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: nvidia,tegra20-vi
|
||||
- const: nvidia,tegra30-vi
|
||||
- const: nvidia,tegra114-vi
|
||||
- const: nvidia,tegra124-vi
|
||||
- enum:
|
||||
- nvidia,tegra20-vi
|
||||
- nvidia,tegra114-vi
|
||||
- nvidia,tegra124-vi
|
||||
- nvidia,tegra210-vi
|
||||
- nvidia,tegra186-vi
|
||||
- nvidia,tegra194-vi
|
||||
|
||||
- items:
|
||||
- const: nvidia,tegra30-vi
|
||||
- const: nvidia,tegra20-vi
|
||||
|
||||
- items:
|
||||
- const: nvidia,tegra132-vi
|
||||
- const: nvidia,tegra124-vi
|
||||
- const: nvidia,tegra210-vi
|
||||
- const: nvidia,tegra186-vi
|
||||
- const: nvidia,tegra194-vi
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -11,8 +11,13 @@ maintainers:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra20-vip
|
||||
oneOf:
|
||||
- enum:
|
||||
- nvidia,tegra20-vip
|
||||
|
||||
- items:
|
||||
- const: nvidia,tegra30-vip
|
||||
- const: nvidia,tegra20-vip
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
$id: http://devicetree.org/schemas/dma/arm-pl08x.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM PrimeCells PL080 and PL081 and derivatives DMA controller
|
||||
title: ARM PrimeCell PL080 and PL081 and derivatives DMA controller
|
||||
|
||||
maintainers:
|
||||
- Vinod Koul <vkoul@kernel.org>
|
||||
|
||||
@ -33,7 +33,9 @@ properties:
|
||||
- microchip,sam9x7-dma
|
||||
- const: atmel,sama5d4-dma
|
||||
- items:
|
||||
- const: microchip,sama7d65-dma
|
||||
- enum:
|
||||
- microchip,lan9691-dma
|
||||
- microchip,sama7d65-dma
|
||||
- const: microchip,sama7g5-dma
|
||||
|
||||
"#dma-cells":
|
||||
|
||||
@ -7,6 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: MediaTek UART APDMA controller
|
||||
|
||||
maintainers:
|
||||
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
- Long Cheng <long.cheng@mediatek.com>
|
||||
|
||||
description: |
|
||||
@ -23,11 +24,29 @@ properties:
|
||||
- enum:
|
||||
- mediatek,mt2712-uart-dma
|
||||
- mediatek,mt6795-uart-dma
|
||||
- mediatek,mt8173-uart-dma
|
||||
- mediatek,mt8183-uart-dma
|
||||
- mediatek,mt8365-uart-dma
|
||||
- mediatek,mt8516-uart-dma
|
||||
- const: mediatek,mt6577-uart-dma
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt7988-uart-dma
|
||||
- mediatek,mt8186-uart-dma
|
||||
- mediatek,mt8188-uart-dma
|
||||
- mediatek,mt8192-uart-dma
|
||||
- mediatek,mt8195-uart-dma
|
||||
- const: mediatek,mt6835-uart-dma
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt6991-uart-dma
|
||||
- mediatek,mt8196-uart-dma
|
||||
- const: mediatek,mt6985-uart-dma
|
||||
- enum:
|
||||
- mediatek,mt6577-uart-dma
|
||||
- mediatek,mt6795-uart-dma
|
||||
- mediatek,mt6835-uart-dma
|
||||
- mediatek,mt6985-uart-dma
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
@ -58,6 +77,7 @@ properties:
|
||||
|
||||
mediatek,dma-33bits:
|
||||
type: boolean
|
||||
deprecated: true
|
||||
description: Enable 33-bits UART APDMA support
|
||||
|
||||
required:
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
x
Reference in New Issue
Block a user