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Xilinx changes for v2024.01-rc1

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clk:
 - Dont return error when assigned-clocks is empty or missing
 
 dm:
 - Support reading a single indexed u64 value
 - Add support for reading bootscript address/flash address from DT
 
 cmd:
 - Fix flash_is_unlocked API
 
 fpga:
 - Define fpga_load() for debug build
 
 global:
 - U-Boot project name cleanup (next2)
 
 net:
 - zynq_gem: Use generic_phy_valid() helper
 - axienet: Convert to ofnode functions
 - gmii2rgmii: Read bridge address from DT
 
 pytest:
 - skip tpm2_startup when env__tpm_device_test_skip=True
 
 spi-nor:
 - Add mx25u25635f support
 - zynqmp_qspi: Tune cache behavior
 
 trace:
 - Fix flyrecord alignment issue
 
 xilinx:
 - Move scriptaddr to DT as bootscr-address
 - Pick script_offset_f/script_size_f from DT as bootscr-flash-offset/size
 - Do not generate distro boot variables if disabled
 
 versal:
 - Extend memory ranges to cover HBM
 - Enable TPM, sha1sum and KASLRSEED
 - Fix distroboot prioritization in connection to available devices
 - Clean mini targets bootcommand
 - Fix clock driver
 
 versal-net:
 - Enable TPM, sha1sum and KASLRSEED
 - Fix distroboot prioritization in connection to available devices
 
 zynqmp;
 - Allow AES to run from SPL
 - Enable CMD_KASLRSEED
 - Add proper dependencies for USB and remove ZYNQMP_USB
 - Fix user si570 default frequency for zcu* boards
 - Cover SOM rev2 revision
 - Various DT changes
 - Add firmware and pinctrl support for tristate configuration
   (high impedance/output enable)
 - Add output-enable pins to SOMs
 - Fix distroboot prioritization in connection to available devices
 - Read bootscript address/flash address from DT
 - Fix pcap_prog address
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 IQYIAJ9WQrnZoCfi7MuxzYA2t34Dbx4gkwCgk1o6bX+R89jvjBOhgZOlXTQCbb0=
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Merge tag 'xilinx-for-v2024.01-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2024.01-rc1

clk:
- Dont return error when assigned-clocks is empty or missing

dm:
- Support reading a single indexed u64 value
- Add support for reading bootscript address/flash address from DT

cmd:
- Fix flash_is_unlocked API

fpga:
- Define fpga_load() for debug build

global:
- U-Boot project name cleanup (next2)

net:
- zynq_gem: Use generic_phy_valid() helper
- axienet: Convert to ofnode functions
- gmii2rgmii: Read bridge address from DT

pytest:
- skip tpm2_startup when env__tpm_device_test_skip=True

spi-nor:
- Add mx25u25635f support
- zynqmp_qspi: Tune cache behavior

trace:
- Fix flyrecord alignment issue

xilinx:
- Move scriptaddr to DT as bootscr-address
- Pick script_offset_f/script_size_f from DT as bootscr-flash-offset/size
- Do not generate distro boot variables if disabled

versal:
- Extend memory ranges to cover HBM
- Enable TPM, sha1sum and KASLRSEED
- Fix distroboot prioritization in connection to available devices
- Clean mini targets bootcommand
- Fix clock driver

versal-net:
- Enable TPM, sha1sum and KASLRSEED
- Fix distroboot prioritization in connection to available devices

zynqmp;
- Allow AES to run from SPL
- Enable CMD_KASLRSEED
- Add proper dependencies for USB and remove ZYNQMP_USB
- Fix user si570 default frequency for zcu* boards
- Cover SOM rev2 revision
- Various DT changes
- Add firmware and pinctrl support for tristate configuration
  (high impedance/output enable)
- Add output-enable pins to SOMs
- Fix distroboot prioritization in connection to available devices
- Read bootscript address/flash address from DT
- Fix pcap_prog address
This commit is contained in:
Tom Rini 2023-09-21 10:51:58 -04:00
commit 5d2fae79c7
66 changed files with 850 additions and 303 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/dts/versal-mini-ospi.dtsi
View File

@ -57,6 +57,7 @@
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <20000000>;
no-wp;
};
};
};

1
arch/arm/dts/versal-net-mini-ospi.dtsi
View File

@ -72,6 +72,7 @@
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <20000000>;
no-wp;
};
};
};

6
arch/arm/dts/xilinx-versal-net-virt.dts
View File

@ -8,4 +8,10 @@
/dts-v1/;
/ {
options {
u-boot {
compatible = "u-boot,config";
bootscr-address = /bits/ 64 <0x20000000>;
};
};
};

6
arch/arm/dts/xilinx-versal-virt.dts
View File

@ -8,4 +8,10 @@
/dts-v1/;
/ {
options {
u-boot {
compatible = "u-boot,config";
bootscr-address = /bits/ 64 <0x20000000>;
};
};
};

7
arch/arm/dts/zynq-7000.dtsi
View File

@ -11,6 +11,13 @@
#size-cells = <1>;
compatible = "xlnx,zynq-7000";
options {
u-boot {
compatible = "u-boot,config";
bootscr-address = /bits/ 64 <0x3000000>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;

4
arch/arm/dts/zynqmp-dlc21-revA.dts
View File

@ -61,14 +61,14 @@
non-removable;
disable-wp;
bus-width = <8>;
xlnx,mio_bank = <0>;
xlnx,mio-bank = <0>;
};
&sdhci1 { /* sd1 MIO45-51 cd in place */
status = "okay";
no-1-8-v;
disable-wp;
xlnx,mio_bank = <1>;
xlnx,mio-bank = <1>;
};
&psgtr {

7
arch/arm/dts/zynqmp-e-a2197-00-revA.dts
View File

@ -2,7 +2,8 @@
/*
* dts file for Xilinx Versal a2197 RevA System Controller
*
* (C) Copyright 2019 - 2021, Xilinx, Inc.
* (C) Copyright 2019 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@ -460,10 +461,10 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
si570_user1: clock-generator@5d { /* u205 */
si570_user1: clock-generator@5f { /* u205 */
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x5d>;
reg = <0x5f>;
temperature-stability = <50>;
factory-fout = <100000000>;
clock-frequency = <100000000>;

6
arch/arm/dts/zynqmp-sck-kr-g-revA.dts
View File

@ -250,6 +250,7 @@
conf-tx {
pins = "MIO36";
bias-disable;
output-enable;
};
mux {
@ -301,6 +302,7 @@
conf-bootstrap {
pins = "MIO45", "MIO47", "MIO49";
bias-disable;
output-enable;
low-power-disable;
};
@ -308,6 +310,7 @@
pins = "MIO38", "MIO39", "MIO40",
"MIO41", "MIO42", "MIO43";
bias-disable;
output-enable;
low-power-enable;
};
@ -316,6 +319,7 @@
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
output-enable;
};
mux-mdio {
@ -346,6 +350,7 @@
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
@ -373,6 +378,7 @@
pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
"MIO72", "MIO73", "MIO74", "MIO75";
bias-disable;
output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};

6
arch/arm/dts/zynqmp-sck-kr-g-revB.dts
View File

@ -250,6 +250,7 @@
conf-tx {
pins = "MIO36";
bias-disable;
output-enable;
};
mux {
@ -301,6 +302,7 @@
conf-bootstrap {
pins = "MIO45", "MIO47", "MIO49";
bias-disable;
output-enable;
low-power-disable;
};
@ -308,6 +310,7 @@
pins = "MIO38", "MIO39", "MIO40",
"MIO41", "MIO42", "MIO43";
bias-disable;
output-enable;
low-power-enable;
};
@ -316,6 +319,7 @@
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
output-enable;
};
mux-mdio {
@ -346,6 +350,7 @@
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
@ -373,6 +378,7 @@
pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
"MIO72", "MIO73", "MIO74", "MIO75";
bias-disable;
output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};

5
arch/arm/dts/zynqmp-sck-kv-g-revA.dts
View File

@ -205,6 +205,7 @@
conf-tx {
pins = "MIO36";
bias-disable;
output-enable;
};
mux {
@ -256,6 +257,7 @@
conf-bootstrap {
pins = "MIO71", "MIO73", "MIO75";
bias-disable;
output-enable;
low-power-disable;
};
@ -263,6 +265,7 @@
pins = "MIO64", "MIO65", "MIO66",
"MIO67", "MIO68", "MIO69";
bias-disable;
output-enable;
low-power-enable;
};
@ -271,6 +274,7 @@
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
output-enable;
};
mux-mdio {
@ -301,6 +305,7 @@
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};

5
arch/arm/dts/zynqmp-sck-kv-g-revB.dts
View File

@ -193,6 +193,7 @@
conf-tx {
pins = "MIO36";
bias-disable;
output-enable;
};
mux {
@ -244,6 +245,7 @@
conf-bootstrap {
pins = "MIO71", "MIO73", "MIO75";
bias-disable;
output-enable;
low-power-disable;
};
@ -251,6 +253,7 @@
pins = "MIO64", "MIO65", "MIO66",
"MIO67", "MIO68", "MIO69";
bias-disable;
output-enable;
low-power-enable;
};
@ -259,6 +262,7 @@
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
output-enable;
};
mux-mdio {
@ -289,6 +293,7 @@
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};

8
arch/arm/dts/zynqmp-sm-k26-revA.dts
View File

@ -1,8 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx ZynqMP SM-K26 rev1/B/A
* dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
* (C) Copyright 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@ -17,8 +18,9 @@
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
/ {
model = "ZynqMP SM-K26 Rev1/B/A";
compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
model = "ZynqMP SM-K26 Rev2/1/B/A";
compatible = "xlnx,zynqmp-sm-k26-rev2",
"xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
"xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
"xlnx,zynqmp";

8
arch/arm/dts/zynqmp-smk-k26-revA.dts
View File

@ -1,8 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx ZynqMP SMK-K26 rev1/B/A
* dts file for Xilinx ZynqMP SMK-K26 rev2/1/B/A
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
* (C) Copyright 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@ -10,8 +11,9 @@
#include "zynqmp-sm-k26-revA.dts"
/ {
model = "ZynqMP SMK-K26 Rev1/B/A";
compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB",
model = "ZynqMP SMK-K26 Rev2/1/B/A";
compatible = "xlnx,zynqmp-smk-k26-rev2",
"xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB",
"xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26",
"xlnx,zynqmp";
};

2
arch/arm/dts/zynqmp-zcu102-revA.dts
View File

@ -602,7 +602,7 @@
reg = <0x5d>;
temperature-stability = <50>; /* copy from zc702 */
factory-fout = <156250000>;
clock-frequency = <148500000>;
clock-frequency = <156250000>;
clock-output-names = "si570_mgt";
};
};

2
arch/arm/dts/zynqmp-zcu106-revA.dts
View File

@ -592,7 +592,7 @@
reg = <0x5d>;
temperature-stability = <50>; /* copy from zc702 */
factory-fout = <156250000>;
clock-frequency = <148500000>;
clock-frequency = <156250000>;
clock-output-names = "si570_mgt";
};
};

2
arch/arm/dts/zynqmp-zcu208-revA.dts
View File

@ -489,7 +489,7 @@
reg = <0x5d>;
temperature-stability = <50>;
factory-fout = <156250000>;
clock-frequency = <148500000>;
clock-frequency = <156250000>;
clock-output-names = "si570_mgt";
};
};

2
arch/arm/dts/zynqmp-zcu216-revA.dts
View File

@ -499,7 +499,7 @@
reg = <0x5d>;
temperature-stability = <50>;
factory-fout = <156250000>;
clock-frequency = <148500000>;
clock-frequency = <156250000>;
clock-output-names = "si570_mgt";
};
};

11
arch/arm/dts/zynqmp.dtsi
View File

@ -22,6 +22,13 @@
#address-cells = <2>;
#size-cells = <2>;
options {
u-boot {
compatible = "u-boot,config";
bootscr-address = /bits/ 64 <0x20000000>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -255,6 +262,7 @@
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
resets = <&zynqmp_reset ZYNQMP_RESET_CAN0>;
power-domains = <&zynqmp_firmware PD_CAN_0>;
};
@ -267,6 +275,7 @@
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
resets = <&zynqmp_reset ZYNQMP_RESET_CAN1>;
power-domains = <&zynqmp_firmware PD_CAN_1>;
};
@ -669,7 +678,7 @@
msi-parent = <&pcie>;
reg = <0x0 0xfd0e0000 0x0 0x1000>,
<0x0 0xfd480000 0x0 0x1000>,
<0x80 0x00000000 0x0 0x1000000>;
<0x80 0x00000000 0x0 0x10000000>;
reg-names = "breg", "pcireg", "cfg";
ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */
<0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */

3
arch/arm/mach-zynqmp/Kconfig
View File

@ -84,9 +84,6 @@ config ZYNQMP_SPL_PM_CFG_OBJ_FILE
Leave this option empty if your PMU firmware has a hard-coded
configuration object or you are loading it by any other means.
config ZYNQMP_USB
bool "Configure ZynqMP USB"
config ZYNQMP_NO_DDR
bool "Disable DDR MMU mapping"
help

3
arch/arm/mach-zynqmp/Makefile
View File

@ -3,8 +3,7 @@
# (C) Copyright 2014 - 2015 Xilinx, Inc.
# Michal Simek <michal.simek@amd.com>
obj-y += clk.o
obj-y += cpu.o
obj-y += aes.o clk.o cpu.o
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o psu_spl_init.o
obj-$(CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT) += ecc_spl_init.o

59
arch/arm/mach-zynqmp/aes.c Normal file
View File

@ -0,0 +1,59 @@
// SPDX-License-Identifier: GPL-2.0
/*
* (C) Copyright 2018 Xilinx, Inc.
* Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
*
* Copyright (C) 2023 Weidmueller Interface GmbH & Co. KG <oss@weidmueller.com>
* Christian Taedcke <christian.taedcke@weidmueller.com>
*/
#include <common.h>
#include <mach/zynqmp_aes.h>
#include <asm/arch/sys_proto.h>
#include <cpu_func.h>
#include <memalign.h>
#include <zynqmp_firmware.h>
int zynqmp_aes_operation(struct zynqmp_aes *aes)
{
u32 ret_payload[PAYLOAD_ARG_CNT];
int ret;
if (zynqmp_firmware_version() <= PMUFW_V1_0)
return -ENOENT;
if (aes->srcaddr && aes->ivaddr && aes->dstaddr) {
flush_dcache_range(aes->srcaddr,
aes->srcaddr +
roundup(aes->len, ARCH_DMA_MINALIGN));
flush_dcache_range(aes->ivaddr,
aes->ivaddr +
roundup(IV_SIZE, ARCH_DMA_MINALIGN));
flush_dcache_range(aes->dstaddr,
aes->dstaddr +
roundup(aes->len, ARCH_DMA_MINALIGN));
}
if (aes->keysrc == 0) {
if (aes->keyaddr == 0)
return -EINVAL;
flush_dcache_range(aes->keyaddr,
aes->keyaddr +
roundup(KEY_PTR_LEN, ARCH_DMA_MINALIGN));
}
flush_dcache_range((ulong)aes, (ulong)(aes) +
roundup(sizeof(struct zynqmp_aes), ARCH_DMA_MINALIGN));
ret = xilinx_pm_request(PM_SECURE_AES, upper_32_bits((ulong)aes),
lower_32_bits((ulong)aes), 0, 0, ret_payload);
if (ret || ret_payload[1]) {
printf("Failed: AES op status:0x%x, errcode:0x%x\n",
ret, ret_payload[1]);
return -EIO;
}
return 0;
}

2
arch/arm/mach-zynqmp/include/mach/hardware.h
View File

@ -166,7 +166,7 @@ struct csu_regs {
u32 jtag_dap_cfg;
u32 idcode;
u32 version;
u32 reserved2[3055];
u32 reserved2[3054];
u32 pcap_prog;
};

32
arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h Normal file
View File

@ -0,0 +1,32 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2023 Weidmueller Interface GmbH & Co. KG <oss@weidmueller.com>
* Christian Taedcke <christian.taedcke@weidmueller.com>
*
* Declaration of AES operation functionality for ZynqMP.
*/
#ifndef ZYNQMP_AES_H
#define ZYNQMP_AES_H
struct zynqmp_aes {
u64 srcaddr;
u64 ivaddr;
u64 keyaddr;
u64 dstaddr;
u64 len;
u64 op;
u64 keysrc;
};
/**
* zynqmp_aes_operation() - Performs an aes operation using the pmu firmware
*
* @aes: The aes operation buffer that must have been allocated using
* ALLOC_CACHE_ALIGN_BUFFER(struct zynqmp_aes, aes, 1)
*
* Return: 0 in case of success, in case of an error any other value
*/
int zynqmp_aes_operation(struct zynqmp_aes *aes);
#endif /* ZYNQMP_AES_H */

26
arch/sandbox/dts/test.dts
View File

@ -81,6 +81,15 @@
};
};
options {
u-boot {
compatible = "u-boot,config";
bootscr-ram-offset = /bits/ 64 <0x12345678>;
bootscr-flash-offset = /bits/ 64 <0>;
bootscr-flash-size = /bits/ 64 <0x2000>;
};
};
bootstd {
bootph-verify;
compatible = "u-boot,boot-std";
@ -301,6 +310,7 @@
uint-value = <(-1234)>;
int64-value = /bits/ 64 <0x1111222233334444>;
int-array = <5678 9123 4567>;
int64-array = /bits/ 64 <0x1111222233334444 0x4444333322221111>;
str-value = "test string";
interrupts-extended = <&irq 3 0>;
acpi,name = "GHIJ";
@ -613,6 +623,22 @@
clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
};
clk-test2 {
compatible = "sandbox,clk-test";
assigned-clock-rates = <321>;
};
clk-test3 {
compatible = "sandbox,clk-test";
assigned-clocks = <&clk_sandbox 1>;
};
clk-test4 {
compatible = "sandbox,clk-test";
assigned-clock-rates = <654>, <321>;
assigned-clocks = <&clk_sandbox 1>;
};
ccf: clk-ccf {
compatible = "sandbox,clk-ccf";
};

18
board/cobra5272/README
View File

@ -1,6 +1,6 @@
File: README.COBRA5272
Author: Florian Schlote for Sentec elektronik (linux@sentec-elektronik.de)
Contents: This is the README of u-boot (Universal bootloader) for our
Contents: This is the README of U-Boot (Universal bootloader) for our
COBRA5272 board.
Version: v01.00
Date: Tue Mar 30 00:28:33 CEST 2004
@ -31,7 +31,7 @@ Please refer to u-boot README (general info, u-boot-x-x-x/README),
to u-boot-x-x-x/board/cobra5272/README and
to the comments in u-boot-x-x-x/include/configs/cobra5272.h
Configuring u-boot is done by commenting/uncommenting preprocessor defines.
Configuring U-Boot is done by commenting/uncommenting preprocessor defines.
Default configuration is
@ -48,10 +48,10 @@ Default configuration is
#-----------------------------------
# u-boot FLASH version & RAM version
# U-Boot FLASH version & RAM version
#-----------------------------------
The u-boot bootloader for Coldfire processors can be configured
The U-Boot bootloader for Coldfire processors can be configured
1. as a standalone bootloader residing in flash & relocating itself to RAM on
startup automatically => "FLASH version"
@ -60,7 +60,7 @@ The u-boot bootloader for Coldfire processors can be configured
prestage bootloader ("chainloading") & is running only from the RAM address it
is linked to => "RAM version"
This version may be very helpful when installing u-boot for the first time
This version may be very helpful when installing U-Boot for the first time
since it can be used to make available s. th. like a "bootstrap
mechanism".
@ -71,7 +71,7 @@ How to build the different images:
Flash version
------------------------------
Compile u-boot
Compile U-Boot
in dir ./u-boot-x-x-x/
@ -81,14 +81,14 @@ please first check:
CONFIG_MONITOR_IS_IN_RAM has to be not present in the file
=> u-boot as single bootloader starting from flash
=> U-Boot as single bootloader starting from flash
in configs/cobra5272_defconfig CONFIG_TEXT_BASE should be
CONFIG_TEXT_BASE=0xffe00000
=> linking address for u-boot as single bootloader stored in flash
=> linking address for U-Boot as single bootloader stored in flash
then:
@ -116,7 +116,7 @@ please modify the settings:
CONFIG_MONITOR_IS_IN_RAM=y
=> u-boot as RAM version, chainloaded by another bootloader or using bdm cable
=> U-Boot as RAM version, chainloaded by another bootloader or using bdm cable
in configs/cobra5272_defconfig CONFIG_TEXT_BASE should be

2
board/emulation/qemu-ppce500/qemu-ppce500.c
View File

@ -320,7 +320,7 @@ ulong get_bus_freq(ulong dummy)
int cpu_numcores(void)
{
/*
* The QEMU u-boot target only needs to drive the first core,
* The QEMU U-Boot target only needs to drive the first core,
* spinning and device tree nodes get driven by QEMU itself
*/
return 1;

31
board/xilinx/common/board.c
View File

@ -411,19 +411,44 @@ int board_late_init_xilinx(void)
int i, id, macid = 0;
struct xilinx_board_description *desc;
phys_size_t bootm_size = gd->ram_top - gd->ram_base;
u64 bootscr_flash_offset, bootscr_flash_size;
if (!IS_ENABLED(CONFIG_MICROBLAZE)) {
ulong scriptaddr;
u64 bootscr_address;
u64 bootscr_offset;
/* Fetch bootscr_address/bootscr_offset from DT and update */
if (!ofnode_read_bootscript_address(&bootscr_address,
&bootscr_offset)) {
if (bootscr_offset)
ret |= env_set_hex("scriptaddr",
gd->ram_base +
bootscr_offset);
else
ret |= env_set_hex("scriptaddr",
bootscr_address);
} else {
/* Update scriptaddr(bootscr offset) from env */
scriptaddr = env_get_hex("scriptaddr", 0);
ret |= env_set_hex("scriptaddr", gd->ram_base + scriptaddr);
ret |= env_set_hex("scriptaddr",
gd->ram_base + scriptaddr);
}
}
if (!ofnode_read_bootscript_flash(&bootscr_flash_offset,
&bootscr_flash_size)) {
ret |= env_set_hex("script_offset_f", bootscr_flash_offset);
ret |= env_set_hex("script_size_f", bootscr_flash_size);
} else {
debug("!!! Please define bootscr-flash-offset via DT !!!\n");
ret |= env_set_hex("script_offset_f",
CONFIG_BOOT_SCRIPT_OFFSET);
}
if (IS_ENABLED(CONFIG_ARCH_ZYNQ) || IS_ENABLED(CONFIG_MICROBLAZE))
bootm_size = min(bootm_size, (phys_size_t)(SZ_512M + SZ_256M));
ret |= env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
ret |= env_set_addr("bootm_low", (void *)gd->ram_base);
ret |= env_set_addr("bootm_size", (void *)bootm_size);

56
board/xilinx/versal-net/board.c
View File

@ -194,25 +194,17 @@ static u8 versal_net_get_bootmode(void)
return bootmode;
}
int board_late_init(void)
static int boot_targets_setup(void)
{
u8 bootmode;
struct udevice *dev;
int bootseq = -1;
int bootseq_len = 0;
int env_targets_len = 0;
const char *mode;
const char *mode = NULL;
char *new_targets;
char *env_targets;
if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
debug("Saved variables - Skipping\n");
return 0;
}
if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
return 0;
bootmode = versal_net_get_bootmode();
puts("Bootmode: ");
@ -229,8 +221,8 @@ int board_late_init(void)
puts("QSPI_MODE_24\n");
if (uclass_get_device_by_name(UCLASS_SPI,
"spi@f1030000", &dev)) {
puts("Boot from QSPI but without QSPI enabled!\n");
return -1;
debug("QSPI driver for QSPI device is not present\n");
break;
}
mode = "xspi";
bootseq = dev_seq(dev);
@ -239,8 +231,8 @@ int board_late_init(void)
puts("QSPI_MODE_32\n");
if (uclass_get_device_by_name(UCLASS_SPI,
"spi@f1030000", &dev)) {
puts("Boot from QSPI but without QSPI enabled!\n");
return -1;
debug("QSPI driver for QSPI device is not present\n");
break;
}
mode = "xspi";
bootseq = dev_seq(dev);
@ -249,8 +241,8 @@ int board_late_init(void)
puts("OSPI_MODE\n");
if (uclass_get_device_by_name(UCLASS_SPI,
"spi@f1010000", &dev)) {
puts("Boot from OSPI but without OSPI enabled!\n");
return -1;
debug("OSPI driver for OSPI device is not present\n");
break;
}
mode = "xspi";
bootseq = dev_seq(dev);
@ -264,8 +256,8 @@ int board_late_init(void)
puts("SD_MODE\n");
if (uclass_get_device_by_name(UCLASS_MMC,
"mmc@f1040000", &dev)) {
puts("Boot from SD0 but without SD0 enabled!\n");
return -1;
debug("SD0 driver for SD0 device is not present\n");
break;
}
debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
@ -279,8 +271,8 @@ int board_late_init(void)
puts("SD_MODE1\n");
if (uclass_get_device_by_name(UCLASS_MMC,
"mmc@f1050000", &dev)) {
puts("Boot from SD1 but without SD1 enabled!\n");
return -1;
debug("SD1 driver for SD1 device is not present\n");
break;
}
debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
@ -288,11 +280,11 @@ int board_late_init(void)
bootseq = dev_seq(dev);
break;
default:
mode = "";
printf("Invalid Boot Mode:0x%x\n", bootmode);
break;
}
if (mode) {
if (bootseq >= 0) {
bootseq_len = snprintf(NULL, 0, "%i", bootseq);
debug("Bootseq len: %x\n", bootseq_len);
@ -319,6 +311,28 @@ int board_late_init(void)
env_targets ? env_targets : "");
env_set("boot_targets", new_targets);
}
return 0;
}
int board_late_init(void)
{
int ret;
if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
debug("Saved variables - Skipping\n");
return 0;
}
if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
return 0;
if (IS_ENABLED(CONFIG_DISTRO_DEFAULTS)) {
ret = boot_targets_setup();
if (ret)
return ret;
}
return board_late_init_xilinx();
}

48
board/xilinx/versal/board.c
View File

@ -126,25 +126,17 @@ static u8 versal_get_bootmode(void)
return bootmode;
}
int board_late_init(void)
static int boot_targets_setup(void)
{
u8 bootmode;
struct udevice *dev;
int bootseq = -1;
int bootseq_len = 0;
int env_targets_len = 0;
const char *mode;
const char *mode = NULL;
char *new_targets;
char *env_targets;
if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
debug("Saved variables - Skipping\n");
return 0;
}
if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
return 0;
bootmode = versal_get_bootmode();
puts("Bootmode: ");
@ -175,8 +167,8 @@ int board_late_init(void)
"mmc@f1050000", &dev) &&
uclass_get_device_by_name(UCLASS_MMC,
"sdhci@f1050000", &dev)) {
puts("Boot from EMMC but without SD1 enabled!\n");
return -1;
debug("SD1 driver for SD1 device is not present\n");
break;
}
debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
mode = "mmc";
@ -188,8 +180,8 @@ int board_late_init(void)
"mmc@f1040000", &dev) &&
uclass_get_device_by_name(UCLASS_MMC,
"sdhci@f1040000", &dev)) {
puts("Boot from SD0 but without SD0 enabled!\n");
return -1;
debug("SD0 driver for SD0 device is not present\n");
break;
}
debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
@ -205,8 +197,8 @@ int board_late_init(void)
"mmc@f1050000", &dev) &&
uclass_get_device_by_name(UCLASS_MMC,
"sdhci@f1050000", &dev)) {
puts("Boot from SD1 but without SD1 enabled!\n");
return -1;
debug("SD1 driver for SD1 device is not present\n");
break;
}
debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
@ -214,11 +206,11 @@ int board_late_init(void)
bootseq = dev_seq(dev);
break;
default:
mode = "";
printf("Invalid Boot Mode:0x%x\n", bootmode);
break;
}
if (mode) {
if (bootseq >= 0) {
bootseq_len = snprintf(NULL, 0, "%i", bootseq);
debug("Bootseq len: %x\n", bootseq_len);
@ -245,6 +237,28 @@ int board_late_init(void)
env_targets ? env_targets : "");
env_set("boot_targets", new_targets);
}
return 0;
}
int board_late_init(void)
{
int ret;
if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
debug("Saved variables - Skipping\n");
return 0;
}
if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
return 0;
if (IS_ENABLED(CONFIG_DISTRO_DEFAULTS)) {
ret = boot_targets_setup();
if (ret)
return ret;
}
return board_late_init_xilinx();
}

43
board/xilinx/zynqmp/cmds.c
View File

@ -14,16 +14,7 @@
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
struct aes {
u64 srcaddr;
u64 ivaddr;
u64 keyaddr;
u64 dstaddr;
u64 len;
u64 op;
u64 keysrc;
};
#include <mach/zynqmp_aes.h>
static int do_zynqmp_verify_secure(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
@ -121,9 +112,7 @@ static int do_zynqmp_mmio_write(struct cmd_tbl *cmdtp, int flag, int argc,
static int do_zynqmp_aes(struct cmd_tbl *cmdtp, int flag, int argc,
char * const argv[])
{
ALLOC_CACHE_ALIGN_BUFFER(struct aes, aes, 1);
int ret;
u32 ret_payload[PAYLOAD_ARG_CNT];
ALLOC_CACHE_ALIGN_BUFFER(struct zynqmp_aes, aes, 1);
if (zynqmp_firmware_version() <= PMUFW_V1_0) {
puts("ERR: PMUFW v1.0 or less is detected\n");
@ -142,40 +131,14 @@ static int do_zynqmp_aes(struct cmd_tbl *cmdtp, int flag, int argc,
aes->keysrc = hextoul(argv[6], NULL);
aes->dstaddr = hextoul(argv[7], NULL);
if (aes->srcaddr && aes->ivaddr && aes->dstaddr) {
flush_dcache_range(aes->srcaddr,
(aes->srcaddr +
roundup(aes->len, ARCH_DMA_MINALIGN)));
flush_dcache_range(aes->ivaddr,
(aes->ivaddr +
roundup(IV_SIZE, ARCH_DMA_MINALIGN)));
flush_dcache_range(aes->dstaddr,
(aes->dstaddr +
roundup(aes->len, ARCH_DMA_MINALIGN)));
}
if (aes->keysrc == 0) {
if (argc < cmdtp->maxargs)
return CMD_RET_USAGE;
aes->keyaddr = hextoul(argv[8], NULL);
if (aes->keyaddr)
flush_dcache_range(aes->keyaddr,
(aes->keyaddr +
roundup(KEY_PTR_LEN,
ARCH_DMA_MINALIGN)));
}
flush_dcache_range((ulong)aes, (ulong)(aes) +
roundup(sizeof(struct aes), ARCH_DMA_MINALIGN));
ret = xilinx_pm_request(PM_SECURE_AES, upper_32_bits((ulong)aes),
lower_32_bits((ulong)aes), 0, 0, ret_payload);
if (ret || ret_payload[1])
printf("Failed: AES op status:0x%x, errcode:0x%x\n",
ret, ret_payload[1]);
return ret;
return zynqmp_aes_operation(aes);
}
#ifdef CONFIG_DEFINE_TCM_OCM_MMAP

73
board/xilinx/zynqmp/zynqmp.c
View File

@ -384,37 +384,16 @@ static int set_fdtfile(void)
return 0;
}
int board_late_init(void)
static int boot_targets_setup(void)
{
u8 bootmode;
struct udevice *dev;
int bootseq = -1;
int bootseq_len = 0;
int env_targets_len = 0;
const char *mode;
const char *mode = NULL;
char *new_targets;
char *env_targets;
int ret, multiboot;
#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
usb_ether_init();
#endif
if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
debug("Saved variables - Skipping\n");
return 0;
}
if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
return 0;
ret = set_fdtfile();
if (ret)
return ret;
multiboot = multi_boot();
if (multiboot >= 0)
env_set_hex("multiboot", multiboot);
bootmode = zynqmp_get_bootmode();
@ -442,8 +421,8 @@ int board_late_init(void)
"mmc@ff160000", &dev) &&
uclass_get_device_by_name(UCLASS_MMC,
"sdhci@ff160000", &dev)) {
puts("Boot from EMMC but without SD0 enabled!\n");
return -1;
debug("SD0 driver for SD0 device is not present\n");
break;
}
debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
@ -457,8 +436,8 @@ int board_late_init(void)
"mmc@ff160000", &dev) &&
uclass_get_device_by_name(UCLASS_MMC,
"sdhci@ff160000", &dev)) {
puts("Boot from SD0 but without SD0 enabled!\n");
return -1;
debug("SD0 driver for SD0 device is not present\n");
break;
}
debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
@ -475,8 +454,8 @@ int board_late_init(void)
"mmc@ff170000", &dev) &&
uclass_get_device_by_name(UCLASS_MMC,
"sdhci@ff170000", &dev)) {
puts("Boot from SD1 but without SD1 enabled!\n");
return -1;
debug("SD1 driver for SD1 device is not present\n");
break;
}
debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
@ -490,11 +469,11 @@ int board_late_init(void)
env_set("modeboot", "nandboot");
break;
default:
mode = "";
printf("Invalid Boot Mode:0x%x\n", bootmode);
break;
}
if (mode) {
if (bootseq >= 0) {
bootseq_len = snprintf(NULL, 0, "%i", bootseq);
debug("Bootseq len: %x\n", bootseq_len);
@ -523,6 +502,40 @@ int board_late_init(void)
env_set("boot_targets", new_targets);
free(new_targets);
}
return 0;
}
int board_late_init(void)
{
int ret, multiboot;
#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
usb_ether_init();
#endif
if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
debug("Saved variables - Skipping\n");
return 0;
}
if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
return 0;
ret = set_fdtfile();
if (ret)
return ret;
multiboot = multi_boot();
if (multiboot >= 0)
env_set_hex("multiboot", multiboot);
if (IS_ENABLED(CONFIG_DISTRO_DEFAULTS)) {
ret = boot_targets_setup();
if (ret)
return ret;
}
reset_reason();

2
cmd/Kconfig
View File

@ -544,6 +544,8 @@ config CMD_SPL_WRITE_SIZE
config CMD_THOR_DOWNLOAD
bool "thor - TIZEN 'thor' download"
select DFU
select USB_FUNCTION_THOR
depends on USB_GADGET_DOWNLOAD
help
Implements the 'thor' download protocol. This is a way of
downloading a software update over USB from an attached host.

2
cmd/sf.c
View File

@ -366,7 +366,7 @@ static int do_spi_flash_erase(int argc, char *const argv[])
}
if (flash->flash_is_unlocked &&
!flash->flash_is_unlocked(flash, offset, len)) {
!flash->flash_is_unlocked(flash, offset, size)) {
printf("ERROR: flash area is locked\n");
return CMD_RET_FAILURE;
}

2
configs/xilinx_versal_mini_defconfig
View File

@ -21,8 +21,6 @@ CONFIG_SYS_MEMTEST_END=0x00001000
CONFIG_REMAKE_ELF=y
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_AUTOBOOT is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y

2
configs/xilinx_versal_mini_emmc0_defconfig
View File

@ -17,8 +17,6 @@ CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
# CONFIG_AUTOBOOT is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y

2
configs/xilinx_versal_mini_emmc1_defconfig
View File

@ -17,8 +17,6 @@ CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
# CONFIG_AUTOBOOT is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y

6
configs/xilinx_versal_net_virt_defconfig
View File

@ -32,6 +32,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_SHA1SUM=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
CONFIG_CMD_DM=y
@ -49,8 +50,10 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_CMD_RNG=y
CONFIG_CMD_KASLRSEED=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_SMC=y
CONFIG_CMD_TPM=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SQUASHFS=y
CONFIG_CMD_MTDPARTS=y
@ -109,7 +112,6 @@ CONFIG_ZYNQ_GEM=y
CONFIG_POWER_DOMAIN=y
CONFIG_ZYNQMP_POWER_DOMAIN=y
CONFIG_RESET_ZYNQMP=y
CONFIG_DM_RNG=y
CONFIG_ARM_DCC=y
CONFIG_PL01X_SERIAL=y
CONFIG_XILINX_UARTLITE=y
@ -121,6 +123,7 @@ CONFIG_CADENCE_QSPI=y
CONFIG_CADENCE_OSPI_VERSAL=y
CONFIG_ZYNQ_SPI=y
CONFIG_ZYNQMP_GQSPI=y
CONFIG_TPM2_TIS_SPI=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
@ -138,3 +141,4 @@ CONFIG_USB_FUNCTION_THOR=y
CONFIG_VIRTIO_MMIO=y
CONFIG_VIRTIO_NET=y
CONFIG_VIRTIO_BLK=y
CONFIG_TPM=y

7
configs/xilinx_versal_virt_defconfig
View File

@ -5,6 +5,7 @@ CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864
CONFIG_ARCH_VERSAL=y
CONFIG_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x100000
CONFIG_NR_DRAM_BANKS=36
CONFIG_DEFAULT_DEVICE_TREE="xilinx-versal-virt"
CONFIG_SYS_PROMPT="Versal> "
CONFIG_OF_LIBFDT_OVERLAY=y
@ -32,6 +33,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_SHA1SUM=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
CONFIG_CMD_DM=y
@ -49,8 +51,10 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_CMD_RNG=y
CONFIG_CMD_KASLRSEED=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_SMC=y
CONFIG_CMD_TPM=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SQUASHFS=y
CONFIG_CMD_MTDPARTS=y
@ -114,7 +118,6 @@ CONFIG_ZYNQ_GEM=y
CONFIG_POWER_DOMAIN=y
CONFIG_ZYNQMP_POWER_DOMAIN=y
CONFIG_RESET_ZYNQMP=y
CONFIG_DM_RNG=y
CONFIG_ARM_DCC=y
CONFIG_PL01X_SERIAL=y
CONFIG_XILINX_UARTLITE=y
@ -127,6 +130,7 @@ CONFIG_CQSPI_REF_CLK=200000000
CONFIG_CADENCE_OSPI_VERSAL=y
CONFIG_ZYNQ_SPI=y
CONFIG_ZYNQMP_GQSPI=y
CONFIG_TPM2_TIS_SPI=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
@ -144,3 +148,4 @@ CONFIG_USB_FUNCTION_THOR=y
CONFIG_VIRTIO_MMIO=y
CONFIG_VIRTIO_NET=y
CONFIG_VIRTIO_BLK=y
CONFIG_TPM=y

2
configs/xilinx_zynqmp_virt_defconfig
View File

@ -16,7 +16,6 @@ CONFIG_ENV_OFFSET_REDUND=0x1E80000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_CMD_FRU=y
CONFIG_ZYNQMP_USB=y
CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x00000000
@ -90,6 +89,7 @@ CONFIG_CMD_RTC=y
CONFIG_CMD_TIME=y
CONFIG_CMD_GETTIME=y
CONFIG_CMD_RNG=y
CONFIG_CMD_KASLRSEED=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_SMC=y

2
doc/board/xilinx/zynq.rst
View File

@ -83,7 +83,7 @@ Mainline status
---------------
- Added basic board configurations support.
- Added zynq u-boot bsp code - arch/arm/mach-zynq
- Added zynq U-Boot bsp code - arch/arm/mach-zynq
- Added zynq boards named - zc70x, zed, microzed, zc770_xm010/xm011/xm012/xm013
- Added zynq drivers:

4
doc/board/xilinx/zynqmp-r5.rst
View File

@ -26,7 +26,7 @@ configure and build armv7 toolchain::
Notes
^^^^^
Output fragment is u-boot.
Output fragment is U-Boot.
Loading
-------
@ -38,7 +38,7 @@ Bootgen
^^^^^^^
The first way is to use Xilinx FSBL (First stage
bootloader) to load u-boot and start it. The following bif can be used for boot
bootloader) to load U-Boot and start it. The following bif can be used for boot
image generation via Xilinx bootgen utility::

2
doc/imx/mkimage/imximage.txt
View File

@ -213,7 +213,7 @@ Disk identifier: 0xb712a870
Device Boot Start End Blocks Id System
/dev/mmcblk0p1 3 16 112455 83 Linux
I have set 100MB, leaving the first 2 sectors free. I will copy u-boot
I have set 100MB, leaving the first 2 sectors free. I will copy U-Boot
there.
8. Write the partition table and exit.

2
doc/usage/environment.rst
View File

@ -216,7 +216,7 @@ fdt_high
0xffffffffffffffff (64-bit machines) then
the fdt will not be copied at all on boot. For this
to work it must reside in writable memory, have
sufficient padding on the end of it for u-boot to
sufficient padding on the end of it for U-Boot to
add the information it needs into it, and the memory
must be accessible by the kernel. This usage is strongly discouraged
however as it also stops U-Boot from ensuring the device tree starting

2
doc/usage/semihosting.rst
View File

@ -23,7 +23,7 @@ eMMC or other NV media are available.
There are two main ARM virtual Fixed Virtual Platform (FVP) models,
`Versatile Express (VE) FVP and BASE FVP
<http://www.arm.com/products/tools/models/fast-models/foundation-model.php>`_.
The initial vexpress64 u-boot board created here runs on the VE virtual
The initial vexpress64 U-Boot board created here runs on the VE virtual
platform using the license-free Foundation_v8 simulator. Fortunately,
the Foundation_v8 simulator also supports the BASE_FVP model which
companies can purchase licenses for and contain much more functionality.

6
drivers/clk/clk-uclass.c
View File

@ -329,9 +329,15 @@ static int clk_set_default_rates(struct udevice *dev,
dev_dbg(dev,
"could not get assigned clock %d (err = %d)\n",
index, ret);
/* Skip if it is empty */
if (ret == -ENOENT) {
ret = 0;
continue;
}
return ret;
}
/* This is clk provider device trying to program itself
* It cannot be done right now but need to wait after the
* device is probed

96
drivers/clk/clk_versal.c
View File

@ -68,6 +68,13 @@
#define CLOCK_NODE_TYPE_DIV 4
#define CLOCK_NODE_TYPE_GATE 6
#define PM_CLK_REF_CLK (0x830c06aU)
#define PM_CLK_PL_ALT_REF_CLK (0x830c06bU)
#define PM_CLK_MUXED_IRO (0x830c06cU)
#define PM_CLK_EMIO (0x830c071U)
#define TOPOLOGY_TYPE_FIXEDFACTOR 0x3
enum clk_type {
CLK_TYPE_OUTPUT,
CLK_TYPE_EXTERNAL,
@ -365,48 +372,37 @@ static u32 versal_clock_set_div(u32 clk_id, u32 div)
return div;
}
static u64 versal_clock_ref(u32 clk_id)
static u64 versal_clock_get_ref_rate(u32 clk_id)
{
u32 ret_payload[PAYLOAD_ARG_CNT];
int ref;
xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload);
ref = ret_payload[0];
if (!(ref & 1))
if (clk_id == PM_CLK_REF_CLK || clk_id == PM_CLK_MUXED_IRO || clk_id == PM_CLK_EMIO)
return ref_clk;
if (ref & 2)
else if (clk_id == PM_CLK_PL_ALT_REF_CLK)
return pl_alt_ref_clk;
else
return 0;
}
static u64 versal_clock_get_pll_rate(u32 clk_id)
static int versal_clock_get_fixed_factor_rate(u32 clock_id, u32 parent_id)
{
struct versal_pm_query_data qdata = {0};
u32 ret_payload[PAYLOAD_ARG_CNT];
u32 fbdiv;
u32 res;
u32 frac;
u64 freq;
u32 parent_rate, parent_id;
u32 id = clk_id & 0xFFF;
u32 mult, div;
u32 parent_rate;
int ret;
xilinx_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
res = ret_payload[1];
if (!res) {
printf("0%x PLL not enabled\n", clk_id);
return 0;
}
qdata.qid = PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS;
qdata.arg1 = clock_id;
parent_id = clock[clock[id].parent[0].id].clk_id;
parent_rate = versal_clock_ref(parent_id);
ret = versal_pm_query(qdata, ret_payload);
if (ret)
return ret;
xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
fbdiv = ret_payload[1];
xilinx_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
frac = ret_payload[1];
mult = ret_payload[1];
div = ret_payload[2];
freq = (fbdiv * parent_rate) >> (1 << frac);
parent_rate = versal_clock_get_ref_rate(parent_id);
return parent_rate * mult / div;
return freq;
}
static u32 versal_clock_mux(u32 clk_id)
@ -437,6 +433,37 @@ static u32 versal_clock_get_parentid(u32 clk_id)
return clock[clock[id].parent[parent_id].id].clk_id;
}
static u64 versal_clock_get_pll_rate(u32 clk_id)
{
u32 ret_payload[PAYLOAD_ARG_CNT];
u32 fbdiv;
u32 res;
u32 frac;
u64 freq;
u32 parent_rate, parent_id, parent_ref_clk_id;
u32 id = clk_id & 0xFFF;
xilinx_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
res = ret_payload[1];
if (!res) {
printf("0%x PLL not enabled\n", clk_id);
return 0;
}
parent_id = clock[clock[id].parent[0].id].clk_id;
parent_ref_clk_id = versal_clock_get_parentid(parent_id);
parent_rate = versal_clock_get_ref_rate(parent_ref_clk_id);
xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
fbdiv = ret_payload[1];
xilinx_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
frac = ret_payload[1];
freq = (fbdiv * parent_rate) >> (1 << frac);
return freq;
}
static u32 versal_clock_gate(u32 clk_id)
{
u32 id = clk_id & 0xFFF;
@ -479,14 +506,19 @@ static u64 versal_clock_calc(u32 clk_id)
u32 parent_id;
u64 clk_rate;
u32 div;
struct clock_topology topology;
if (versal_clock_pll(clk_id, &clk_rate))
return clk_rate;
parent_id = versal_clock_get_parentid(clk_id);
if (((parent_id >> NODE_SUBCLASS_SHIFT) &
NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF)
return versal_clock_ref(clk_id);
NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF) {
topology = clock[clk_id & 0x3FF].node[0];
if (topology.type == TOPOLOGY_TYPE_FIXEDFACTOR)
return versal_clock_get_fixed_factor_rate(clk_id, parent_id);
return versal_clock_get_ref_rate(parent_id);
}
if (!parent_id)
return 0;
@ -505,7 +537,7 @@ static int versal_clock_get_rate(u32 clk_id, u64 *clk_rate)
{
if (((clk_id >> NODE_SUBCLASS_SHIFT) &
NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF)
*clk_rate = versal_clock_ref(clk_id);
*clk_rate = versal_clock_get_ref_rate(clk_id);
if (versal_clock_pll(clk_id, clk_rate))
return 0;

14
drivers/core/of_access.c
View File

@ -570,26 +570,34 @@ int of_read_u32_index(const struct device_node *np, const char *propname,
return 0;
}
int of_read_u64(const struct device_node *np, const char *propname, u64 *outp)
int of_read_u64_index(const struct device_node *np, const char *propname,
int index, u64 *outp)
{
const __be64 *val;
debug("%s: %s: ", __func__, propname);
if (!np)
return -EINVAL;
val = of_find_property_value_of_size(np, propname, sizeof(*outp));
val = of_find_property_value_of_size(np, propname,
sizeof(*outp) * (index + 1));
if (IS_ERR(val)) {
debug("(not found)\n");
return PTR_ERR(val);
}
*outp = be64_to_cpup(val);
*outp = be64_to_cpup(val + index);
debug("%#llx (%lld)\n", (unsigned long long)*outp,
(unsigned long long)*outp);
return 0;
}
int of_read_u64(const struct device_node *np, const char *propname, u64 *outp)
{
return of_read_u64_index(np, propname, 0, outp);
}
int of_property_match_string(const struct device_node *np, const char *propname,
const char *string)
{

89
drivers/core/ofnode.c
View File

@ -344,6 +344,36 @@ int ofnode_read_u32_index(ofnode node, const char *propname, int index,
return 0;
}
int ofnode_read_u64_index(ofnode node, const char *propname, int index,
u64 *outp)
{
const fdt64_t *cell;
int len;
assert(ofnode_valid(node));
if (ofnode_is_np(node))
return of_read_u64_index(ofnode_to_np(node), propname, index,
outp);
cell = fdt_getprop(ofnode_to_fdt(node), ofnode_to_offset(node),
propname, &len);
if (!cell) {
debug("(not found)\n");
return -EINVAL;
}
if (len < (sizeof(u64) * (index + 1))) {
debug("(not large enough)\n");
return -EOVERFLOW;
}
*outp = fdt64_to_cpu(cell[index]);
debug("%#llx (%lld)\n", *outp, *outp);
return 0;
}
u32 ofnode_read_u32_index_default(ofnode node, const char *propname, int index,
u32 def)
{
@ -1563,6 +1593,65 @@ const char *ofnode_conf_read_str(const char *prop_name)
return ofnode_read_string(node, prop_name);
}
int ofnode_read_bootscript_address(u64 *bootscr_address, u64 *bootscr_offset)
{
int ret;
ofnode uboot;
*bootscr_address = 0;
*bootscr_offset = 0;
uboot = ofnode_path("/options/u-boot");
if (!ofnode_valid(uboot)) {
debug("%s: Missing /u-boot node\n", __func__);
return -EINVAL;
}
ret = ofnode_read_u64(uboot, "bootscr-address", bootscr_address);
if (ret) {
ret = ofnode_read_u64(uboot, "bootscr-ram-offset",
bootscr_offset);
if (ret)
return -EINVAL;
}
return 0;
}
int ofnode_read_bootscript_flash(u64 *bootscr_flash_offset,
u64 *bootscr_flash_size)
{
int ret;
ofnode uboot;
*bootscr_flash_offset = 0;
*bootscr_flash_size = 0;
uboot = ofnode_path("/options/u-boot");
if (!ofnode_valid(uboot)) {
debug("%s: Missing /u-boot node\n", __func__);
return -EINVAL;
}
ret = ofnode_read_u64(uboot, "bootscr-flash-offset",
bootscr_flash_offset);
if (ret)
return -EINVAL;
ret = ofnode_read_u64(uboot, "bootscr-flash-size",
bootscr_flash_size);
if (ret)
return -EINVAL;
if (!bootscr_flash_size) {
debug("bootscr-flash-size is zero. Ignoring properties!\n");
*bootscr_flash_offset = 0;
return -EINVAL;
}
return 0;
}
ofnode ofnode_get_phy_node(ofnode node)
{
/* DT node properties that reference a PHY node */

13
drivers/firmware/firmware-zynqmp.c
View File

@ -195,6 +195,19 @@ int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value)
return ret;
}
int zynqmp_pm_feature(const u32 api_id)
{
int ret;
u32 ret_payload[PAYLOAD_ARG_CNT];
/* Check feature check API version */
ret = xilinx_pm_request(PM_FEATURE_CHECK, api_id, 0, 0, 0,
ret_payload);
/* Return feature check version */
return ret_payload[1] & FIRMWARE_VERSION_MASK;
}
int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
{
int ret;

1
drivers/mtd/spi/spi-nor-ids.c
View File

@ -249,6 +249,7 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, SECT_4K) },
{ INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K) },
{ INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K) },
{ INFO("mx25u51245g", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },

5
drivers/net/phy/phy.c
View File

@ -807,7 +807,10 @@ static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus,
ofnode_for_each_subnode(node, dev_ofnode(dev)) {
node = ofnode_by_compatible(node, "xlnx,gmii-to-rgmii-1.0");
if (ofnode_valid(node)) {
phydev = phy_device_create(bus, 0,
int gmiirgmii_phyaddr;
gmiirgmii_phyaddr = ofnode_read_u32_default(node, "reg", 0);
phydev = phy_device_create(bus, gmiirgmii_phyaddr,
PHY_GMII2RGMII_ID, false);
if (phydev)
phydev->node = node;

48
drivers/net/xilinx_axi_emac.c
View File

@ -112,7 +112,7 @@ struct axidma_plat {
int pcsaddr;
int phyaddr;
u8 eth_hasnobuf;
int phy_of_handle;
ofnode phynode;
enum emac_variant mactype;
};
@ -127,7 +127,7 @@ struct axidma_priv {
struct phy_device *phydev;
struct mii_dev *bus;
u8 eth_hasnobuf;
int phy_of_handle;
ofnode phynode;
enum emac_variant mactype;
};
@ -335,8 +335,8 @@ static int axiemac_phy_init(struct udevice *dev)
phydev->supported &= supported;
phydev->advertising = phydev->supported;
priv->phydev = phydev;
if (priv->phy_of_handle)
priv->phydev->node = offset_to_ofnode(priv->phy_of_handle);
if (ofnode_valid(priv->phynode))
priv->phydev->node = priv->phynode;
phy_config(phydev);
return 0;
@ -839,7 +839,7 @@ static int axi_emac_probe(struct udevice *dev)
priv->eth_hasnobuf = plat->eth_hasnobuf;
priv->pcsaddr = plat->pcsaddr;
priv->phyaddr = plat->phyaddr;
priv->phy_of_handle = plat->phy_of_handle;
priv->phynode = plat->phynode;
priv->interface = pdata->phy_interface;
if (IS_ENABLED(CONFIG_DM_ETH_PHY))
@ -894,20 +894,21 @@ static int axi_emac_of_to_plat(struct udevice *dev)
{
struct axidma_plat *plat = dev_get_plat(dev);
struct eth_pdata *pdata = &plat->eth_pdata;
int node = dev_of_offset(dev);
int offset = 0;
struct ofnode_phandle_args pcs_node, axistream_node;
ofnode phynode;
int ret;
pdata->iobase = dev_read_addr(dev);
plat->mactype = dev_get_driver_data(dev);
offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
"axistream-connected");
if (offset <= 0) {
ret = dev_read_phandle_with_args(dev, "axistream-connected", NULL, 0, 0,
&axistream_node);
if (ret) {
printf("%s: axistream is not found\n", __func__);
return -EINVAL;
}
plat->dmatx = (struct axidma_reg *)fdtdec_get_addr_size_auto_parent
(gd->fdt_blob, 0, offset, "reg", 0, NULL, false);
plat->dmatx = (struct axidma_reg *)ofnode_get_addr(axistream_node.node);
if (!plat->dmatx) {
printf("%s: axi_dma register space not found\n", __func__);
return -EINVAL;
@ -918,30 +919,27 @@ static int axi_emac_of_to_plat(struct udevice *dev)
/* PHYAD 0 always redirects to the PCS/PMA PHY */
plat->pcsaddr = 0;
offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
"phy-handle");
if (offset > 0) {
phynode = dev_get_phy_node(dev);
if (ofnode_valid(phynode)) {
if (!(IS_ENABLED(CONFIG_DM_ETH_PHY)))
plat->phyaddr = fdtdec_get_int(gd->fdt_blob,
offset,
plat->phyaddr = ofnode_read_u32_default(phynode,
"reg", -1);
plat->phy_of_handle = offset;
plat->phynode = phynode;
}
pdata->phy_interface = dev_read_phy_mode(dev);
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
plat->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
"xlnx,eth-hasnobuf");
plat->eth_hasnobuf = dev_read_bool(dev, "xlnx,eth-hasnobuf");
if (pdata->phy_interface == PHY_INTERFACE_MODE_SGMII ||
pdata->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
"pcs-handle");
if (offset > 0) {
plat->pcsaddr = fdtdec_get_int(gd->fdt_blob,
offset, "reg", -1);
ret = dev_read_phandle_with_args(dev, "pcs-handle", NULL, 0, 0,
&pcs_node);
if (!ret) {
plat->pcsaddr = ofnode_read_u32_default(pcs_node.node,
"reg", -1);
}
}
}

15
drivers/pinctrl/pinctrl-zynqmp.c
View File

@ -158,6 +158,12 @@ static int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, u32 valu
{
int ret;
if (param == PM_PINCTRL_CONFIG_TRI_STATE) {
ret = zynqmp_pm_feature(PM_PINCTRL_CONFIG_PARAM_SET);
if (ret < PM_PINCTRL_PARAM_SET_VERSION)
return -EOPNOTSUPP;
}
/* Request the pin first */
ret = xilinx_pm_request(PM_PINCTRL_REQUEST, pin, 0, 0, 0, NULL);
if (ret) {
@ -467,6 +473,10 @@ static int zynqmp_pinconf_set(struct udevice *dev, unsigned int pin,
pin);
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
param = PM_PINCTRL_CONFIG_TRI_STATE;
arg = PM_PINCTRL_TRI_STATE_ENABLE;
ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
break;
case PIN_CONFIG_LOW_POWER_MODE:
/*
* This cases are mentioned in dts but configurable
@ -475,6 +485,11 @@ static int zynqmp_pinconf_set(struct udevice *dev, unsigned int pin,
*/
ret = 0;
break;
case PIN_CONFIG_OUTPUT_ENABLE:
param = PM_PINCTRL_CONFIG_TRI_STATE;
arg = PM_PINCTRL_TRI_STATE_DISABLE;
ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
break;
default:
dev_warn(dev, "unsupported configuration parameter '%u'\n",
param);

4
drivers/spi/zynqmp_gqspi.c
View File

@ -690,7 +690,7 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv,
writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
addr = (unsigned long)buf;
size = roundup(priv->len, GQSPI_DMA_ALIGN);
flush_dcache_range(addr, addr + size);
invalidate_dcache_range(addr, addr + size);
while (priv->len) {
zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
@ -707,6 +707,8 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv,
return -ETIMEDOUT;
}
invalidate_dcache_range(addr, addr + size);
writel(GQSPI_DMA_DST_I_STS_DONE, &dma_regs->dmaisr);
debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",

7
include/configs/xilinx_versal.h
View File

@ -40,10 +40,11 @@
"kernel_size_r=0x10000000\0" \
"kernel_comp_addr_r=0x30000000\0" \
"kernel_comp_size=0x3C00000\0" \
"scriptaddr=0x20000000\0" \
"ramdisk_addr_r=0x02100000\0" \
"script_size_f=0x80000\0"
#if defined(CONFIG_DISTRO_DEFAULTS)
#if defined(CONFIG_MMC_SDHCI_ZYNQ)
# define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
#else
@ -125,6 +126,10 @@
#include <config_distro_bootcmd.h>
#else /* CONFIG_DISTRO_DEFAULTS */
# define BOOTENV
#endif /* CONFIG_DISTRO_DEFAULTS */
/* Initial environment variables */
#ifndef CFG_EXTRA_ENV_SETTINGS
#define CFG_EXTRA_ENV_SETTINGS \

7
include/configs/xilinx_versal_net.h
View File

@ -54,10 +54,11 @@
"kernel_size_r=0x10000000\0" \
"kernel_comp_addr_r=0x30000000\0" \
"kernel_comp_size=0x3C00000\0" \
"scriptaddr=0x20000000\0" \
"ramdisk_addr_r=0x02100000\0" \
"script_size_f=0x80000\0"
#if defined(CONFIG_DISTRO_DEFAULTS)
#if defined(CONFIG_MMC_SDHCI_ZYNQ)
# define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
#else
@ -126,6 +127,10 @@
#include <config_distro_bootcmd.h>
#else /* CONFIG_DISTRO_DEFAULTS */
# define BOOTENV
#endif /* CONFIG_DISTRO_DEFAULTS */
/* Initial environment variables */
#ifndef CFG_EXTRA_ENV_SETTINGS
#define CFG_EXTRA_ENV_SETTINGS \

11
include/configs/xilinx_zynqmp.h
View File

@ -29,7 +29,7 @@
/* Miscellaneous configurable options */
#if defined(CONFIG_ZYNQMP_USB)
#if defined(CONFIG_USB_STORAGE)
#define DFU_DEFAULT_POLL_TIMEOUT 300
# define PARTS_DEFAULT \
@ -57,13 +57,14 @@
"kernel_size_r=0x10000000\0" \
"kernel_comp_addr_r=0x30000000\0" \
"kernel_comp_size=0x3C00000\0" \
"scriptaddr=0x20000000\0" \
"ramdisk_addr_r=0x02100000\0" \
"script_size_f=0x80000\0" \
"stdin=serial\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0" \
#if defined(CONFIG_DISTRO_DEFAULTS)
#if defined(CONFIG_MMC_SDHCI_ZYNQ)
# define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
#else
@ -76,7 +77,7 @@
# define BOOT_TARGET_DEVICES_SCSI(func)
#endif
#if defined(CONFIG_ZYNQMP_USB)
#if defined(CONFIG_USB_STORAGE)
# define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) func(USB, usb, 1)
#else
# define BOOT_TARGET_DEVICES_USB(func)
@ -175,6 +176,10 @@
#include <config_distro_bootcmd.h>
#else /* CONFIG_DISTRO_DEFAULTS */
# define BOOTENV
#endif /* CONFIG_DISTRO_DEFAULTS */
/* Initial environment variables */
#ifndef CFG_EXTRA_ENV_SETTINGS
#define CFG_EXTRA_ENV_SETTINGS \

2
include/configs/zynq-common.h
View File

@ -172,12 +172,10 @@
/* Default environment */
#ifndef CFG_EXTRA_ENV_SETTINGS
#define CFG_EXTRA_ENV_SETTINGS \
"scriptaddr=0x20000\0" \
"script_size_f=0x40000\0" \
"fdt_addr_r=0x1f00000\0" \
"pxefile_addr_r=0x2000000\0" \
"kernel_addr_r=0x2000000\0" \
"scriptaddr=0x3000000\0" \
"ramdisk_addr_r=0x3100000\0" \
BOOTENV
#endif

19
include/dm/of_access.h
View File

@ -333,6 +333,25 @@ int of_read_u32(const struct device_node *np, const char *propname, u32 *outp);
int of_read_u32_index(const struct device_node *np, const char *propname,
int index, u32 *outp);
/**
* of_read_u64_index() - Find and read a 64-bit value from a multi-value
* property
*
* @np: device node from which the property value is to be read.
* @propname: name of the property to be searched.
* @index: index of the u32 in the list of values
* @outp: pointer to return value, modified only if return value is 0.
*
* Search for a property in a device node and read a 64-bit value from
* it.
*
* Return:
* 0 on success, -EINVAL if the property does not exist, or -EOVERFLOW if the
* property data isn't large enough.
*/
int of_read_u64_index(const struct device_node *np, const char *propname,
int index, u64 *outp);
/**
* of_read_u64() - Find and read a 64-bit integer from a property
*

65
include/dm/ofnode.h
View File

@ -20,6 +20,7 @@
struct resource;
#include <dm/ofnode_decl.h>
#include <linux/errno.h>
struct ofnode_phandle_args {
ofnode node;
@ -434,6 +435,18 @@ int ofnode_read_u32(ofnode node, const char *propname, u32 *outp);
int ofnode_read_u32_index(ofnode node, const char *propname, int index,
u32 *outp);
/**
* ofnode_read_u64_index() - Read a 64-bit integer from a multi-value property
*
* @node: valid node reference to read property from
* @propname: name of the property to read from
* @index: index of the integer to return
* @outp: place to put value (if found)
* Return: 0 if OK, -ve on error
*/
int ofnode_read_u64_index(ofnode node, const char *propname, int index,
u64 *outp);
/**
* ofnode_read_s32() - Read a 32-bit integer from a property
*
@ -1500,6 +1513,47 @@ int ofnode_conf_read_int(const char *prop_name, int default_val);
*/
const char *ofnode_conf_read_str(const char *prop_name);
/**
* ofnode_read_bootscript_address() - Read bootscr-address or bootscr-ram-offset
*
* @bootscr_address: pointer to 64bit address where bootscr-address property value
* is stored
* @bootscr_offset: pointer to 64bit offset address where bootscr-ram-offset
* property value is stored
*
* This reads a bootscr-address or bootscr-ram-offset property from
* the /options/u-boot/ node of the devicetree. bootscr-address holds the full
* address of the boot script file. bootscr-ram-offset holds the boot script
* file offset from the start of the ram base address. When bootscr-address is
* defined, bootscr-ram-offset property is ignored.
*
* This only works with the control FDT.
*
* Return: 0 if OK, -EINVAL if property is not found.
*/
int ofnode_read_bootscript_address(u64 *bootscr_address, u64 *bootscr_offset);
/**
* ofnode_read_bootscript_flash() - Read bootscr-flash-offset/size
*
* @bootscr_flash_offset: pointer to 64bit offset where bootscr-flash-offset
* property value is stored
* @bootscr_flash_size: pointer to 64bit size where bootscr-flash-size property
* value is stored
*
* This reads a bootscr-flash-offset and bootscr-flash-size properties from
* the /options/u-boot/ node of the devicetree. bootscr-flash-offset holds
* the offset of the boot script file from start of flash. bootscr-flash-size
* holds the boot script size in flash. When bootscr-flash-size is not defined,
* bootscr-flash-offset property is cleaned.
*
* This only works with the control FDT.
*
* Return: 0 if OK, -EINVAL if property is not found or incorrect.
*/
int ofnode_read_bootscript_flash(u64 *bootscr_flash_offset,
u64 *bootscr_flash_size);
#else /* CONFIG_DM */
static inline bool ofnode_conf_read_bool(const char *prop_name)
{
@ -1516,6 +1570,17 @@ static inline const char *ofnode_conf_read_str(const char *prop_name)
return NULL;
}
static inline int ofnode_read_bootscript_address(u64 *bootscr_address, u64 *bootscr_offset)
{
return -EINVAL;
}
static inline int ofnode_read_bootscript_flash(u64 *bootscr_flash_offset,
u64 *bootscr_flash_size)
{
return -EINVAL;
}
#endif /* CONFIG_DM */
/**

8
include/fpga.h
View File

@ -60,8 +60,16 @@ int fpga_add(fpga_type devtype, void *desc);
int fpga_count(void);
const fpga_desc *const fpga_get_desc(int devnum);
int fpga_is_partial_data(int devnum, size_t img_len);
#if CONFIG_IS_ENABLED(FPGA)
int fpga_load(int devnum, const void *buf, size_t bsize,
bitstream_type bstype, int flags);
#else
static inline int fpga_load(int devnum, const void *buf, size_t bsize,
bitstream_type bstype, int flags)
{
return FPGA_FAIL;
}
#endif
int fpga_fsload(int devnum, const void *buf, size_t size,
fpga_fs_info *fpga_fsinfo);
int fpga_loads(int devnum, const void *buf, size_t size,

3
include/zynqmp_firmware.h
View File

@ -456,6 +456,7 @@ int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,
int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
int zynqmp_mmio_read(const u32 address, u32 *value);
int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
int zynqmp_pm_feature(const u32 api_id);
/* Type of Config Object */
#define PM_CONFIG_OBJECT_TYPE_BASE 0x1U
@ -492,6 +493,8 @@ enum zynqmp_pm_request_ack {
/* PM API versions */
#define PM_API_VERSION_2 2
#define PM_PINCTRL_PARAM_SET_VERSION 2
struct zynqmp_ipi_msg {
size_t len;
u32 *buf;

9
test/dm/clk.c
View File

@ -36,6 +36,15 @@ static int dm_test_clk_base(struct unit_test_state *uts)
ut_asserteq(clk_is_match(&clk_method1, &clk_method2), true);
ut_asserteq(clk_method1.id, clk_method2.id);
ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test2", &dev));
ut_assertok(clk_set_defaults(dev, CLK_DEFAULTS_PRE));
ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test3", &dev));
ut_assertok(clk_set_defaults(dev, CLK_DEFAULTS_PRE));
ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test4", &dev));
ut_assertok(clk_set_defaults(dev, CLK_DEFAULTS_PRE));
return 0;
}

27
test/dm/ofnode.c
View File

@ -583,6 +583,25 @@ static int dm_test_ofnode_conf(struct unit_test_state *uts)
}
DM_TEST(dm_test_ofnode_conf, 0);
static int dm_test_ofnode_options(struct unit_test_state *uts)
{
u64 bootscr_address, bootscr_offset;
u64 bootscr_flash_offset, bootscr_flash_size;
ut_assertok(ofnode_read_bootscript_address(&bootscr_address,
&bootscr_offset));
ut_asserteq_64(0, bootscr_address);
ut_asserteq_64(0x12345678, bootscr_offset);
ut_assertok(ofnode_read_bootscript_flash(&bootscr_flash_offset,
&bootscr_flash_size));
ut_asserteq_64(0, bootscr_flash_offset);
ut_asserteq_64(0x2000, bootscr_flash_size);
return 0;
}
DM_TEST(dm_test_ofnode_options, 0);
static int dm_test_ofnode_for_each_compatible_node(struct unit_test_state *uts)
{
const char compatible[] = "denx,u-boot-fdt-test";
@ -967,6 +986,14 @@ static int dm_test_ofnode_u64(struct unit_test_state *uts)
ut_asserteq_64(0x1111222233334444, val);
ut_asserteq(-EINVAL, ofnode_read_u64(node, "missing", &val));
ut_assertok(ofnode_read_u64_index(node, "int64-array", 0, &val));
ut_asserteq_64(0x1111222233334444, val);
ut_assertok(ofnode_read_u64_index(node, "int64-array", 1, &val));
ut_asserteq_64(0x4444333322221111, val);
ut_asserteq(-EOVERFLOW,
ofnode_read_u64_index(node, "int64-array", 2, &val));
ut_asserteq(-EINVAL, ofnode_read_u64_index(node, "missing", 0, &val));
return 0;
}
DM_TEST(dm_test_ofnode_u64, UT_TESTF_SCAN_FDT);

3
test/py/tests/test_tpm2.py
View File

@ -71,6 +71,9 @@ def test_tpm2_startup(u_boot_console):
Initiate the TPM internal state machine.
"""
skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False)
if skip_test:
pytest.skip('skip TPM device test')
u_boot_console.run_command('tpm2 startup TPM2_SU_CLEAR')
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')

39
tools/proftool.c
View File

@ -1493,14 +1493,43 @@ static int write_pages(struct twriter *tw, enum out_format_t out_format,
static int write_flyrecord(struct twriter *tw, enum out_format_t out_format,
int *missing_countp, int *skip_countp)
{
int start, ret, len;
unsigned long long start, start_ofs, len;
int ret;
FILE *fout = tw->fout;
char str[200];
/* Record start pointer */
start_ofs = tw->ptr;
debug("Start of flyrecord header at: 0x%llx\n", start_ofs);
tw->ptr += fprintf(fout, "flyrecord%c", 0);
/* flyrecord\0 - allocated 10 bytes */
start_ofs += 10;
/*
* 8 bytes that are a 64-bit word containing the offset into the file
* that holds the data for the CPU.
*
* 8 bytes that are a 64-bit word containing the size of the CPU
* data at that offset.
*/
start_ofs += 16;
snprintf(str, sizeof(str),
"[local] global counter uptime perf mono mono_raw boot x86-tsc\n");
len = strlen(str);
/* trace clock length - 8 bytes */
start_ofs += 8;
/* trace clock data */
start_ofs += len;
debug("Calculated flyrecord header end at: 0x%llx, trace clock len: 0x%llx\n",
start_ofs, len);
/* trace data */
start = ALIGN(tw->ptr + 16, TRACE_PAGE_SIZE);
start = ALIGN(start_ofs, TRACE_PAGE_SIZE);
tw->ptr += tputq(fout, start);
/* use a placeholder for the size */
@ -1509,12 +1538,12 @@ static int write_flyrecord(struct twriter *tw, enum out_format_t out_format,
return -1;
tw->ptr += ret;
snprintf(str, sizeof(str),
"[local] global counter uptime perf mono mono_raw boot x86-tsc\n");
len = strlen(str);
tw->ptr += tputq(fout, len);
tw->ptr += tputs(fout, str);
debug("End of flyrecord header at: 0x%x, offset: 0x%llx\n",
tw->ptr, start);
debug("trace text base %lx, map file %lx\n", text_base, text_offset);
ret = write_pages(tw, out_format, missing_countp, skip_countp);