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Prepare v2025.07-rc4

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Merge tag 'v2025.07-rc4' into next

Prepare v2025.07-rc4
This commit is contained in:
Tom Rini 2025-06-09 16:28:28 -06:00
commit 59d00e20fc
111 changed files with 578 additions and 274 deletions
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2
Makefile
View File

@ -3,7 +3,7 @@
VERSION = 2025
PATCHLEVEL = 07
SUBLEVEL =
EXTRAVERSION = -rc3
EXTRAVERSION = -rc4
NAME =
# *DOCUMENTATION*

1
arch/arm/Kconfig
View File

@ -1091,6 +1091,7 @@ config ARCH_QEMU
imply USB_XHCI_PCI
imply USB_KEYBOARD
imply CMD_USB
imply POSITION_INDEPENDENT
config ARCH_RENESAS
bool "Renesas ARM SoCs"

2
arch/arm/cpu/armv7/start.S
View File

@ -182,6 +182,8 @@ saved_args:
.word 0
.endr
END(saved_args)
.section .text
#endif
#ifdef CONFIG_ARMV7_LPAE

5
arch/arm/dts/qemu-sbsa.dts
View File

@ -91,7 +91,10 @@
#interrupt-cells = <3>;
status = "okay";
interrupt-controller;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
/* vcpumntirq: virtual CPU interface maintenance interrupt */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = /bits/ 64 <SBSA_GIC_DIST_BASE_ADDR SBSA_GIC_DIST_LENGTH>,
/bits/ 64 <SBSA_GIC_REDIST_BASE_ADDR SBSA_GIC_REDIST_LENGTH>,
/bits/ 64 <0 0>,

12
arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
View File

@ -9,6 +9,14 @@
bootph-pre-ram;
};
&i2c0_xfer {
bootph-pre-ram;
};
&io_domains {
bootph-pre-ram;
};
&sdmmc {
pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
};
@ -19,8 +27,12 @@
&vcc3v0_sd {
bootph-pre-ram;
/delete-property/ regulator-always-on;
};
&vcc_sdio {
bootph-pre-ram;
/delete-property/ regulator-always-on;
/delete-property/ regulator-boot-on;
regulator-init-microvolt = <3000000>;
};

1
arch/arm/mach-k3/am62ax/am62a7_init.c
View File

@ -191,6 +191,7 @@ void board_init_f(ulong dummy)
if (ret)
panic("DRAM init failed: %d\n", ret);
#endif
spl_enable_cache();
setup_qos();

5
arch/arm/mach-rockchip/Kconfig
View File

@ -11,9 +11,8 @@ config ROCKCHIP_PX30
select TPL_TINY_FRAMEWORK if TPL
select TPL_HAVE_INIT_STACK if TPL
imply SPL_SEPARATE_BSS
select SPL_SERIAL
select TPL_SERIAL
select DEBUG_UART_BOARD_INIT
imply SPL_SERIAL
imply TPL_SERIAL
imply ROCKCHIP_COMMON_BOARD
imply ROCKCHIP_COMMON_STACK_ADDR
imply SPL_ROCKCHIP_COMMON_BOARD

63
arch/arm/mach-snapdragon/board.c
View File

@ -409,52 +409,39 @@ static void configure_env(void)
return;
}
/* The last compatible is always the SoC compatible */
ret = ofnode_read_string_index(root, "compatible", compat_count - 1, &last_compat);
if (ret < 0) {
log_warning("Can't read second compatible\n");
return;
}
/* Copy the second compat (e.g. "qcom,sdm845") into buf */
strlcpy(buf, last_compat, sizeof(buf) - 1);
tmp = buf;
/* strsep() is destructive, it replaces the comma with a \0 */
if (!strsep(&tmp, ",")) {
log_warning("second compatible '%s' has no ','\n", buf);
return;
}
/* tmp now points to just the "sdm845" part of the string */
env_set("soc", tmp);
/* Now figure out the "board" part from the first compatible */
memset(buf, 0, sizeof(buf));
strlcpy(buf, first_compat, sizeof(buf) - 1);
tmp = buf;
/* The Qualcomm reference boards (RBx, HDK, etc) */
if (!strncmp("qcom", buf, strlen("qcom"))) {
char *soc;
/*
* They all have the first compatible as "qcom,<soc>-<board>"
* (e.g. "qcom,qrb5165-rb5"). We extract just the part after
* the dash.
*/
if (!strsep(&tmp, "-")) {
if (!strsep(&tmp, ",")) {
log_warning("compatible '%s' has no ','\n", buf);
return;
}
soc = strsep(&tmp, "-");
if (!soc) {
log_warning("compatible '%s' has no '-'\n", buf);
return;
}
/* tmp is now "rb5" */
env_set("soc", soc);
env_set("board", tmp);
} else {
if (!strsep(&tmp, ",")) {
log_warning("compatible '%s' has no ','\n", buf);
return;
}
/* for thundercomm we just want the bit after the comma (e.g. "db845c"),
* for all other boards we replace the comma with a '-' and take both
* (e.g. "oneplus-enchilada")
/*
* For thundercomm we just want the bit after the comma
* (e.g. "db845c"), for all other boards we replace the comma
* with a '-' and take both (e.g. "oneplus-enchilada")
*/
if (!strncmp("thundercomm", buf, strlen("thundercomm"))) {
env_set("board", tmp);
@ -462,6 +449,28 @@ static void configure_env(void)
*(tmp - 1) = '-';
env_set("board", buf);
}
/* The last compatible is always the SoC compatible */
ret = ofnode_read_string_index(root, "compatible",
compat_count - 1, &last_compat);
if (ret < 0) {
log_warning("Can't read second compatible\n");
return;
}
/* Copy the last compat (e.g. "qcom,sdm845") into buf */
memset(buf, 0, sizeof(buf));
strlcpy(buf, last_compat, sizeof(buf) - 1);
tmp = buf;
/* strsep() is destructive, it replaces the comma with a \0 */
if (!strsep(&tmp, ",")) {
log_warning("second compatible '%s' has no ','\n", buf);
return;
}
/* tmp now points to just the "sdm845" part of the string */
env_set("soc", tmp);
}
/* Now build the full path name */

2
arch/arm/mach-uniphier/debug-uart/debug-uart.c
View File

@ -16,7 +16,7 @@
#define UNIPHIER_UART_LSR 0x14
#define UNIPHIER_UART_LDR 0x24
static void _debug_uart_putc(int c)
static inline void _debug_uart_putc(int c)
{
void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);

14
arch/riscv/dts/binman.dtsi
View File

@ -5,12 +5,6 @@
#include <config.h>
#ifdef CONFIG_64BIT
#define ARCH "riscv64"
#else
#define ARCH "riscv"
#endif
/ {
binman: binman {
multiple-images;
@ -37,7 +31,7 @@
description = "U-Boot";
type = "standalone";
os = "U-Boot";
arch = ARCH;
arch = "riscv";
compression = "none";
load = /bits/ 64 <CONFIG_TEXT_BASE>;
@ -49,7 +43,7 @@
description = "Linux";
type = "standalone";
os = "Linux";
arch = ARCH;
arch = "riscv";
compression = "none";
load = /bits/ 64 <CONFIG_TEXT_BASE>;
@ -62,7 +56,7 @@
tee {
description = "OP-TEE";
type = "tee";
arch = ARCH;
arch = "riscv";
compression = "none";
os = "tee";
load = /bits/ 64 <CONFIG_SPL_OPTEE_LOAD_ADDR>;
@ -76,7 +70,7 @@
description = "OpenSBI fw_dynamic Firmware";
type = "firmware";
os = "opensbi";
arch = ARCH;
arch = "riscv";
compression = "none";
load = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
entry = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>;

4
arch/riscv/include/asm/u-boot.h
View File

@ -23,10 +23,6 @@
#include <asm/u-boot-riscv.h>
/* For image.h:image_check_target_arch() */
#ifdef CONFIG_64BIT
#define IH_ARCH_DEFAULT IH_ARCH_RISCV64
#else
#define IH_ARCH_DEFAULT IH_ARCH_RISCV
#endif
#endif /* _U_BOOT_H_ */

4
arch/riscv/lib/bootm.c
View File

@ -90,10 +90,6 @@ static void boot_jump_linux(struct bootm_headers *images, int flag)
announce_and_cleanup(fake);
if (!fake) {
if (images->os.arch != IH_ARCH_DEFAULT) {
printf("Image arch not compatible with host arch.\n");
hang();
}
if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
#ifdef CONFIG_SMP
ret = smp_call_function(images->ep,

2
board/qualcomm/dragonboard410c/dragonboard410c.env
View File

@ -2,5 +2,5 @@
initrd_high=0xffffffffffffffff
fastboot=fastboot -l $fastboot_addr_r usb 0
boot_targets=usb mmc1 mmc0 pxe
button_cmd_0_name=vol_down
button_cmd_0_name=Volume Down
button_cmd_0=run fastboot

5
board/renesas/rzg2l/MAINTAINERS
View File

@ -1,6 +1,7 @@
RENESAS RZG2L BOARD FAMILY
M: Paul Barker <paul.barker.ct@bp.renesas.com>
S: Supported
M: Marek Vasut <marek.vasut+renesas@mailbox.org>
R: Paul Barker <paul@pbarker.dev>
S: Maintained
N: rz-smarc
N: rzg2l
N: r9a07g044

15
board/ti/am62ax/am62ax.env
View File

@ -17,18 +17,5 @@ mmcdev=1
bootpart=1:2
bootdir=/boot
rd_spec=-
init_mmc=run args_all args_mmc
get_overlay_mmc=
fdt address ${fdtaddr};
fdt resize 0x100000;
for overlay in $name_overlays;
do;
load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} &&
fdt apply ${dtboaddr};
done;
get_kern_mmc=load mmc ${bootpart} ${loadaddr}
${bootdir}/${name_kern}
get_fit_mmc=load mmc ${bootpart} ${addr_fit}
${bootdir}/${name_fit}
partitions=name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}
rproc_fw_binaries= 0 /lib/firmware/am62a-mcu-r5f0_0-fw 1 /lib/firmware/am62a-c71_0-fw

3
boot/bootm.c
View File

@ -1169,8 +1169,7 @@ void bootm_init(struct bootm_info *bmi)
{
memset(bmi, '\0', sizeof(struct bootm_info));
bmi->boot_progress = true;
if (IS_ENABLED(CONFIG_CMD_BOOTM))
bmi->images = &images;
bmi->images = &images;
}
/**

3
boot/image-android.c
View File

@ -488,7 +488,8 @@ int android_image_get_ramdisk(const void *hdr, const void *vendor_boot_img,
} else {
/* Ramdisk can be used in-place, use current ptr */
if (img_data.ramdisk_addr == 0 ||
img_data.ramdisk_addr == ANDROID_IMAGE_DEFAULT_RAMDISK_ADDR) {
img_data.ramdisk_addr == ANDROID_IMAGE_DEFAULT_RAMDISK_ADDR ||
img_data.ramdisk_addr == img_data.kernel_addr) {
*rd_data = img_data.ramdisk_ptr;
} else {
ramdisk_ptr = img_data.ramdisk_addr;

3
boot/image.c
View File

@ -92,8 +92,7 @@ static const table_entry_t uimage_arch[] = {
{ IH_ARCH_ARC, "arc", "ARC", },
{ IH_ARCH_X86_64, "x86_64", "AMD x86_64", },
{ IH_ARCH_XTENSA, "xtensa", "Xtensa", },
{ IH_ARCH_RISCV, "riscv", "RISC-V 32 Bit",},
{ IH_ARCH_RISCV64, "riscv64", "RISC-V 64 Bit",},
{ IH_ARCH_RISCV, "riscv", "RISC-V", },
{ -1, "", "", },
};

7
cmd/booti.c
View File

@ -131,11 +131,8 @@ int do_booti(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
bootm_disable_interrupts();
images.os.os = IH_OS_LINUX;
if (IS_ENABLED(CONFIG_RISCV))
if (IS_ENABLED(CONFIG_64BIT))
images.os.arch = IH_ARCH_RISCV64;
else
images.os.arch = IH_ARCH_RISCV;
if (IS_ENABLED(CONFIG_RISCV_SMODE))
images.os.arch = IH_ARCH_RISCV;
else if (IS_ENABLED(CONFIG_ARM64))
images.os.arch = IH_ARCH_ARM64;

2
common/board_f.c
View File

@ -1079,7 +1079,7 @@ void board_init_f(ulong boot_flags)
*/
static void initcall_run_f_r(void)
{
#if CONFIG_IS_ENABLED(X86_64)
#if !CONFIG_IS_ENABLED(X86_64)
INITCALL(init_cache_f_r);
#endif
}

12
common/usb_onboard_hub.c
View File

@ -146,7 +146,7 @@ static int usb_onboard_hub_probe(struct udevice *dev)
int ret;
ret = device_get_supply_regulator(dev, "vdd-supply", &hub->vdd);
if (ret && ret != -ENOENT) {
if (ret && ret != -ENOENT && ret != -ENOSYS) {
dev_err(dev, "can't get vdd-supply: %d\n", ret);
return ret;
}
@ -204,14 +204,16 @@ static int usb_onboard_hub_bind(struct udevice *dev)
static int usb_onboard_hub_remove(struct udevice *dev)
{
struct onboard_hub *hub = dev_get_priv(dev);
int ret;
int ret = 0;
if (hub->reset_gpio)
dm_gpio_free(hub->reset_gpio->dev, hub->reset_gpio);
ret = regulator_set_enable_if_allowed(hub->vdd, false);
if (ret)
dev_err(dev, "can't disable vdd-supply: %d\n", ret);
if (hub->vdd) {
ret = regulator_set_enable_if_allowed(hub->vdd, false);
if (ret)
dev_err(dev, "can't disable vdd-supply: %d\n", ret);
}
return ret;
}

2
configs/SBx81LIFKW_defconfig
View File

@ -15,7 +15,6 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-atl-sbx81lifkw"
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_IDENT_STRING="\nSBx81LIFKW"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
@ -63,7 +62,6 @@ CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_DM_RTC=y
CONFIG_RTC_MV=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y

2
configs/SBx81LIFXCAT_defconfig
View File

@ -15,7 +15,6 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-atl-sbx81lifxcat"
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_IDENT_STRING="\nSBx81LIFXCAT"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
@ -61,7 +60,6 @@ CONFIG_MV88E61XX_FIXED_PORTS=0x300
CONFIG_PHY_FIXED=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y

1
configs/amd_versal2_virt_defconfig
View File

@ -139,7 +139,6 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"

1
configs/brcp150_defconfig
View File

@ -111,7 +111,6 @@ CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y

1
configs/brcp170_defconfig
View File

@ -110,7 +110,6 @@ CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y

1
configs/brcp1_1r_defconfig
View File

@ -110,7 +110,6 @@ CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y

1
configs/brcp1_1r_switch_defconfig
View File

@ -111,7 +111,6 @@ CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y

1
configs/brcp1_2r_defconfig
View File

@ -110,7 +110,6 @@ CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y

1
configs/brsmarc2_defconfig
View File

@ -110,7 +110,6 @@ CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y

1
configs/colibri_t20_defconfig
View File

@ -69,7 +69,6 @@ CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y

2
configs/d2net_v2_defconfig
View File

@ -15,7 +15,6 @@ CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-d2net"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_IDENT_STRING=" D2 v2"
CONFIG_ENV_ADDR=0x70000
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
@ -66,7 +65,6 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y

2
configs/dns325_defconfig
View File

@ -13,7 +13,6 @@ CONFIG_ENV_OFFSET=0xE0000
CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-dns325"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_IDENT_STRING="\nD-Link DNS-325"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="if test -n ${bootenv} && usb start; then if run loadbootenv; then echo Loaded environment ${bootenv} from usb;run importbootenv;fi;if test -n ${bootenvcmd}; then echo Running bootenvcmd ...;run bootenvcmd;fi;fi;run setnandbootenv subbootcmd;"
@ -56,7 +55,6 @@ CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_DM_RTC=y
CONFIG_RTC_MV=y
CONFIG_DM_SERIAL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

5
configs/dragonboard410c_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_COUNTER_FREQUENCY=19200000
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
CONFIG_ARCH_SNAPDRAGON=y
CONFIG_TEXT_BASE=0x8f600000
CONFIG_SYS_MALLOC_LEN=0x802000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0
CONFIG_ENV_SIZE=0x2000
@ -56,14 +55,14 @@ CONFIG_PINCONF=y
CONFIG_PINCTRL_QCOM_APQ8016=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_QCOM=y
CONFIG_DM_RNG=y
CONFIG_RNG_MSM=y
CONFIG_MSM_SERIAL=y
CONFIG_SPMI_MSM=y
CONFIG_USB=y
# CONFIG_DM_USB_GADGET is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MSM=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y

1
configs/ds109_defconfig
View File

@ -17,7 +17,6 @@ CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-ds109"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_ENV_ADDR=0x3D0000
# CONFIG_SYS_MALLOC_F is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv ethact egiga0; ${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; bootm 0x6400000;"
CONFIG_USE_PREBOOT=y

2
configs/guruplug_defconfig
View File

@ -13,7 +13,6 @@ CONFIG_ENV_OFFSET=0xE0000
CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-guruplug-server-plus"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_IDENT_STRING="\nMarvell-GuruPlug"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=917504
CONFIG_BOOTDELAY=3
@ -58,7 +57,6 @@ CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_DM_RTC=y
CONFIG_RTC_MV=y
CONFIG_DM_SERIAL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

1
configs/harmony_defconfig
View File

@ -56,7 +56,6 @@ CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y

2
configs/hmibsc_defconfig
View File

@ -73,8 +73,6 @@ CONFIG_USB=y
# CONFIG_DM_USB_GADGET is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MSM=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y

2
configs/ib62x0_defconfig
View File

@ -13,7 +13,6 @@ CONFIG_ENV_OFFSET=0xE0000
CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-ib62x0"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_IDENT_STRING=" RaidSonic ICY BOX IB-NAS62x0"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi part root; ubifsmount ubi:rootfs; ubifsload 0x800000 ${kernel}; ubifsload 0x700000 ${fdt}; ubifsumount; fdt addr 0x700000; fdt resize; fdt chosen; bootz 0x800000 - 0x700000"
@ -57,7 +56,6 @@ CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_DM_SERIAL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

2
configs/inetspace_v2_defconfig
View File

@ -15,7 +15,6 @@ CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-is2"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_IDENT_STRING=" IS v2"
CONFIG_ENV_ADDR=0x70000
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
@ -66,7 +65,6 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y

1
configs/jaguar-rk3588_defconfig
View File

@ -108,4 +108,5 @@ CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_FS_EXFAT=y
CONFIG_ERRNO_STR=y

1
configs/mot_defconfig
View File

@ -77,7 +77,6 @@ CONFIG_POWEROFF_GPIO=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y

4
configs/mvebu_espressobin_ultra-88f3720_defconfig
View File

@ -86,6 +86,8 @@ CONFIG_MVEBU_COMPHY_SUPPORT=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_37XX=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RNG=y
CONFIG_RNG_TURRIS_RWTM=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF8563=y
CONFIG_DEFAULT_ENV_IS_RW=y
@ -97,5 +99,3 @@ CONFIG_USB_EHCI_HCD=y
# CONFIG_WATCHDOG_AUTOSTART is not set
CONFIG_WDT=y
CONFIG_WDT_ARMADA_37XX=y
CONFIG_DM_RNG=y
CONFIG_RNG_TURRIS_RWTM=y

7
configs/nanopc-t4-rk3399_defconfig
View File

@ -8,6 +8,7 @@ CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-nanopc-t4"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART_BASE=0xFF1A0000
@ -18,6 +19,8 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@ -33,6 +36,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_SPL_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
@ -46,8 +50,11 @@ CONFIG_NVME_PCI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_SPL_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2

7
configs/nanopi-m4-2gb-rk3399_defconfig
View File

@ -8,6 +8,7 @@ CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4-2gb"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART_BASE=0xFF1A0000
@ -19,6 +20,8 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4-2gb.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@ -37,6 +40,7 @@ CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_SPL_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
@ -50,8 +54,11 @@ CONFIG_NVME_PCI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_SPL_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SCSI=y
CONFIG_BAUDRATE=1500000

7
configs/nanopi-m4-rk3399_defconfig
View File

@ -8,6 +8,7 @@ CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-nanopi-m4"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART_BASE=0xFF1A0000
@ -19,6 +20,8 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@ -36,6 +39,7 @@ CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_SPL_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
@ -49,8 +53,11 @@ CONFIG_NVME_PCI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_SPL_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SCSI=y
CONFIG_BAUDRATE=1500000

7
configs/nanopi-m4b-rk3399_defconfig
View File

@ -8,6 +8,7 @@ CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-nanopi-m4b"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART_BASE=0xFF1A0000
@ -19,6 +20,8 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4b.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@ -36,6 +39,7 @@ CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_SPL_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
@ -49,8 +53,11 @@ CONFIG_NVME_PCI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_SPL_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SCSI=y
CONFIG_BAUDRATE=1500000

7
configs/nanopi-neo4-rk3399_defconfig
View File

@ -8,6 +8,7 @@ CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-nanopi-neo4"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART_BASE=0xFF1A0000
@ -17,6 +18,8 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@ -31,6 +34,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_SPL_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
@ -43,8 +47,11 @@ CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_SPL_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2

7
configs/nanopi-r4s-rk3399_defconfig
View File

@ -8,6 +8,7 @@ CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-nanopi-r4s"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART_BASE=0xFF1A0000
@ -17,6 +18,8 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@ -31,6 +34,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_SPL_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
@ -43,8 +47,11 @@ CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_SPL_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
CONFIG_BAUDRATE=1500000

2
configs/nas220_defconfig
View File

@ -13,7 +13,6 @@ CONFIG_ENV_OFFSET=0xA0000
CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-blackarmor-nas220"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_IDENT_STRING="\nNAS 220"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_USE_PREBOOT=y
@ -60,7 +59,6 @@ CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_DM_RTC=y
CONFIG_RTC_MV=y
CONFIG_DM_SERIAL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

2
configs/net2big_v2_defconfig
View File

@ -16,7 +16,6 @@ CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-net2big"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_IDENT_STRING=" 2Big v2"
CONFIG_ENV_ADDR=0x70000
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
@ -67,7 +66,6 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y

2
configs/netspace_lite_v2_defconfig
View File

@ -16,7 +16,6 @@ CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-ns2lite"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_IDENT_STRING=" NS v2 Lite"
CONFIG_ENV_ADDR=0x70000
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
@ -67,7 +66,6 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y

2
configs/netspace_max_v2_defconfig
View File

@ -16,7 +16,6 @@ CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-ns2max"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_IDENT_STRING=" NS Max v2"
CONFIG_ENV_ADDR=0x70000
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
@ -67,7 +66,6 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y

2
configs/netspace_mini_v2_defconfig
View File

@ -16,7 +16,6 @@ CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-ns2mini"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_IDENT_STRING=" NS v2 Mini"
CONFIG_ENV_ADDR=0x70000
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
@ -65,7 +64,6 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y

2
configs/netspace_v2_defconfig
View File

@ -16,7 +16,6 @@ CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-ns2"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_IDENT_STRING=" NS v2"
CONFIG_ENV_ADDR=0x70000
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
@ -67,7 +66,6 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y

1
configs/paz00_defconfig
View File

@ -45,7 +45,6 @@ CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y

1
configs/picasso_defconfig
View File

@ -70,7 +70,6 @@ CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y

1
configs/puma-rk3399_defconfig
View File

@ -104,4 +104,5 @@ CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_FS_EXFAT=y
CONFIG_ERRNO_STR=y

1
configs/qemu_arm64_defconfig
View File

@ -1,5 +1,4 @@
CONFIG_ARM=y
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_QEMU=y
CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_BLOBLIST_SIZE_RELOC=0x2000

1
configs/renesas_rcar.config
View File

@ -24,5 +24,6 @@ CONFIG_MTD=y
CONFIG_OF_CONTROL=y
CONFIG_RCAR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SERIAL_RX_BUFFER=y
CONFIG_SPI=y
CONFIG_VERSION_VARIABLE=y

1
configs/ringneck-px30_defconfig
View File

@ -110,6 +110,7 @@ CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_FS_EXFAT=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
# CONFIG_RSA is not set

1
configs/seaboard_defconfig
View File

@ -53,7 +53,6 @@ CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y

1
configs/star_defconfig
View File

@ -75,7 +75,6 @@ CONFIG_SYSRESET_MAX8907=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y

1
configs/syzygy_hub_defconfig
View File

@ -70,7 +70,6 @@ CONFIG_ARM_DCC=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"

37
configs/th1520_lpi4a_defconfig
View File

@ -1,24 +1,28 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="th1520-lichee-pi-4a"
CONFIG_SPL_STACK=0xffe0170000
CONFIG_SPL_BSS_START_ADDR=0xffe0160000
CONFIG_SPL_BSS_MAX_SIZE=0x10000
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x80200000
# CONFIG_SMP is not set
CONFIG_SPL=y
CONFIG_TARGET_TH1520_LPI4A=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_SYS_BOOT_GET_CMDLINE=y
CONFIG_SYS_BOOT_GET_KBD=y
# CONFIG_EFI_LOADER is not set
CONFIG_FIT=y
# CONFIG_FIT_FULL_CHECK is not set
# CONFIG_FIT_PRINT is not set
CONFIG_SPL_LOAD_FIT_ADDRESS=0xffe0040000
# CONFIG_BOOTSTD is not set
# CONFIG_LEGACY_IMAGE_FORMAT is not set
CONFIG_DISTRO_DEFAULTS=y
@ -31,6 +35,14 @@ CONFIG_LOG=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_HAVE_INIT_STACK=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x10000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x400000
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="LPI4A=> "
CONFIG_CMD_CONFIG=y
CONFIG_CMD_LICENSE=y
@ -79,8 +91,10 @@ CONFIG_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_SNPS=y
# CONFIG_MTD is not set
# CONFIG_POWER is not set
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_SPL_THEAD_TH1520_DDR=y
CONFIG_SYS_NS16550=y
CONFIG_RISCV_TIMER=y
CONFIG_AES=y
CONFIG_BLAKE2=y
CONFIG_SHA512=y
@ -91,20 +105,3 @@ CONFIG_ZLIB_UNCOMPRESS=y
CONFIG_BZIP2=y
CONFIG_ZSTD=y
CONFIG_LIB_RATIONAL=y
CONFIG_SPL=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_LOAD_FIT_ADDRESS=0xffe0040000
CONFIG_SPL_HAVE_INIT_STACK=y
CONFIG_SPL_STACK=0xffe0170000
CONFIG_SPL_BSS_START_ADDR=0xffe0160000
CONFIG_SPL_BSS_MAX_SIZE=0x10000
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_RAM_DEVICE=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_SPL_THEAD_TH1520_DDR=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_MMC_y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x10000000

1
configs/tiger-rk3588_defconfig
View File

@ -113,4 +113,5 @@ CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_FS_EXFAT=y
CONFIG_ERRNO_STR=y

1
configs/topic_miami_defconfig
View File

@ -85,7 +85,6 @@ CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"

1
configs/topic_miamilite_defconfig
View File

@ -71,7 +71,6 @@ CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"

1
configs/topic_miamiplus_defconfig
View File

@ -71,7 +71,6 @@ CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"

6
configs/total_compute_defconfig
View File

@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_TARGET_TOTAL_COMPUTE=y
CONFIG_TEXT_BASE=0xe0000000
CONFIG_SYS_MALLOC_LEN=0x3200000
CONFIG_BLOBLIST_SIZE_RELOC=0x10000
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0
@ -22,6 +23,8 @@ CONFIG_SYS_CBSIZE=512
CONFIG_SYS_PBSIZE=544
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BLOBLIST=y
CONFIG_BLOBLIST_PASSAGE_MANDATORY=y
CONFIG_SYS_PROMPT="TOTAL_COMPUTE# "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_XIMG is not set
@ -55,6 +58,3 @@ CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_SECT=256
# CONFIG_RANDOM_UUID is not set
CONFIG_LIBAVB=y
CONFIG_BLOBLIST=y
CONFIG_BLOBLIST_PASSAGE_MANDATORY=y
CONFIG_BLOBLIST_SIZE_RELOC=0x10000

1
configs/transformer_t20_defconfig
View File

@ -70,7 +70,6 @@ CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y

1
configs/ventana_defconfig
View File

@ -46,7 +46,6 @@ CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y

1
configs/xilinx_versal_net_virt_defconfig
View File

@ -139,7 +139,6 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"

1
configs/xilinx_versal_virt_defconfig
View File

@ -152,7 +152,6 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"

1
configs/xilinx_zynq_virt_defconfig
View File

@ -151,7 +151,6 @@ CONFIG_ZYNQ_QSPI=y
CONFIG_SPI_STACKED_PARALLEL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"

1
configs/xilinx_zynqmp_kria_defconfig
View File

@ -202,7 +202,6 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_ONBOARD_HUB=y
CONFIG_USB_HOST_ETHER=y

1
configs/xilinx_zynqmp_virt_defconfig
View File

@ -214,7 +214,6 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y

1
doc/board/beagle/j721e_beagleboneai64.rst
View File

@ -83,6 +83,7 @@ Target Images
Copy the below images to an SD card and boot:
* tiboot3-j721e-gp-evm.bin from R5 build as tiboot3.bin
* sysfw-j721e-gp-evm.itb from R5 build as sysfw.itb
* tispl.bin_unsigned from Cortex-A build as tispl.bin
* u-boot.img_unsigned from Cortex-A build as u-boot.img

2
doc/build/gcc.rst vendored
View File

@ -122,7 +122,7 @@ Out-of-tree building
~~~~~~~~~~~~~~~~~~~~
By default building is performed locally and the objects are saved in the source
directory. To build out-out-tree use one of the two methods below:
directory. To build out-of-tree use one of the two methods below:
Add O= parameter to the make command line:

2
doc/develop/release_cycle.rst
View File

@ -77,7 +77,7 @@ For the next scheduled release, release candidates were made on::
* U-Boot |next_ver|-rc3 was released on Mon 26 May 2025.
.. * U-Boot |next_ver|-rc4 was released on Mon 09 June 2025.
* U-Boot |next_ver|-rc4 was released on Mon 09 June 2025.
.. * U-Boot |next_ver|-rc5 was released on Mon 23 June 2025.

20
doc/usage/cmd/bootefi.rst
View File

@ -20,19 +20,19 @@ Synopsis
Description
-----------
The *bootefi* command is used to launch a UEFI binary which can be either of
The *bootefi* command is used to launch a UEFI binary which can be any of
* UEFI application
* UEFI boot services driver
* UEFI run-time services driver
An operating system requires a hardware description which can either be
presented as ACPI table (CONFIG\_GENERATE\_ACPI\_TABLE=y) or as device-tree.
The load address of the device-tree may be provided as parameter *fdt\_addr*. If
presented as ACPI table (CONFIG_GENERATE_ACPI_TABLE=y) or as device-tree.
The load address of the device-tree may be provided as parameter *fdt_addr*. If
this address is not specified, the bootefi command will try to fall back in
sequence to:
* the device-tree specified by environment variable *fdt\_addr*
* the device-tree specified by environment variable *fdt_addr*
* the device-tree specified by environment variable *fdtcontroladdr*
The load address of the binary is specified by parameter *image_address*. A
@ -110,7 +110,7 @@ U-Boot can be compiled with UEFI unit tests. These unit tests are invoked using
the *bootefi selftest* sub-command.
Which unit test is executed is controlled by the environment variable
*efi\_selftest*. If this variable is not set, all unit tests that are not marked
*efi_selftest*. If this variable is not set, all unit tests that are not marked
as 'on request' are executed.
To show a list of the available unit tests the value *list* can be used
@ -126,7 +126,7 @@ To show a list of the available unit tests the value *list* can be used
'configuration tables'
...
A single test is selected for execution by setting the *efi\_selftest*
A single test is selected for execution by setting the *efi_selftest*
environment variable to match one of the listed identifiers
::
@ -140,10 +140,10 @@ return to the command line but require a board reset.
Configuration
-------------
To use the *bootefi* command you must specify CONFIG\_CMD\_BOOTEFI=y.
The *bootefi bootmgr* sub-command requries CMD\_BOOTEFI\_BOOTMGR=y.
The *bootefi hello* sub-command requries CMD\_BOOTEFI\_HELLO=y.
The *bootefi selftest* sub-command depends on CMD\_BOOTEFI\_SELFTEST=y.
To use the *bootefi* command you must specify CONFIG_CMD_BOOTEFI=y.
The *bootefi bootmgr* sub-command requries CMD_BOOTEFI_BOOTMGR=y.
The *bootefi hello* sub-command requries CMD_BOOTEFI_HELLO=y.
The *bootefi selftest* sub-command depends on CMD_BOOTEFI_SELFTEST=y.
See also
--------

15
drivers/button/button-qcom-pmic.c
View File

@ -143,6 +143,21 @@ static int qcom_pwrkey_probe(struct udevice *dev)
priv->base = base;
ret = dev_read_u32(dev, "linux,code", &priv->code);
if (ret == 0) {
/* convert key, if read OK */
switch (priv->code) {
case KEY_VOLUMEDOWN:
priv->code = KEY_DOWN;
uc_plat->label = "Volume Down";
break;
case KEY_VOLUMEUP:
priv->code = KEY_UP;
uc_plat->label = "Volume Up";
break;
}
}
/* Do a sanity check */
ret = pmic_reg_read(priv->pmic, priv->base + REG_TYPE);
if (ret != 0x1 && ret != 0xb) {

17
drivers/clk/qcom/clock-apq8016.c
View File

@ -23,10 +23,7 @@
#define APCS_GPLL_ENA_VOTE (0x45000)
#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004)
#define SDCC_BCR(n) ((n * 0x1000) + 0x41000)
#define SDCC_CMD_RCGR(n) (((n + 1) * 0x1000) + 0x41004)
#define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018)
#define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C)
#define SDCC_CMD_RCGR(n) (((n) * 0x1000) + 0x42004)
/* BLSP1 AHB clock (root clock for BLSP) */
#define BLSP1_AHB_CBCR 0x1008
@ -54,9 +51,13 @@ static struct vote_clk gcc_blsp1_ahb_clk = {
};
static const struct gate_clk apq8016_clks[] = {
GATE_CLK(GCC_PRNG_AHB_CLK, 0x45004, BIT(8)),
GATE_CLK(GCC_USB_HS_AHB_CLK, 0x41008, BIT(0)),
GATE_CLK(GCC_USB_HS_SYSTEM_CLK, 0x41004, BIT(0)),
GATE_CLK_POLLED(GCC_PRNG_AHB_CLK, 0x45004, BIT(8), 0x13004),
GATE_CLK_POLLED(GCC_SDCC1_AHB_CLK, 0x4201c, BIT(0), 0x4201c),
GATE_CLK_POLLED(GCC_SDCC1_APPS_CLK, 0x42018, BIT(0), 0x42018),
GATE_CLK_POLLED(GCC_SDCC2_AHB_CLK, 0x4301c, BIT(0), 0x4301c),
GATE_CLK_POLLED(GCC_SDCC2_APPS_CLK, 0x43018, BIT(0), 0x43018),
GATE_CLK_POLLED(GCC_USB_HS_AHB_CLK, 0x41008, BIT(0), 0x41008),
GATE_CLK_POLLED(GCC_USB_HS_SYSTEM_CLK, 0x41004, BIT(0), 0x41004),
};
/* SDHCI */
@ -67,12 +68,10 @@ static int apq8016_clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
if (rate == 200000000)
div = 4;
clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot));
/* 800Mhz/div, gpll0 */
clk_rcg_set_rate_mnd(priv->base, SDCC_CMD_RCGR(slot), div, 0, 0,
CFG_CLK_SRC_GPLL0, 8);
clk_enable_gpll0(priv->base, &gpll0_vote_clk);
clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));
return rate;
}

27
drivers/clk/qcom/clock-qcom.c
View File

@ -74,6 +74,33 @@ void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk)
} while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL));
}
int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
{
if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0) {
log_err("gcc@%#08llx: unknown clock ID %lu!\n",
priv->base, id);
return -ENOENT;
}
setbits_le32(priv->base + priv->data->clks[id].reg, priv->data->clks[id].en_val);
if (priv->data->clks[id].cbcr_reg) {
unsigned int count;
u32 val;
for (count = 0; count < 200; count++) {
val = readl(priv->base + priv->data->clks[id].cbcr_reg);
val &= BRANCH_CHECK_MASK;
if (val == BRANCH_ON_VAL || val == BRANCH_NOC_FSM_ON_VAL)
break;
udelay(1);
}
if (WARN(count == 200, "WARNING: Clock @ %#lx [%#010x] stuck at off\n",
priv->data->clks[id].cbcr_reg, val))
return -EBUSY;
}
return 0;
}
#define APPS_CMD_RCGR_UPDATE BIT(0)
/* Update clock command via CMD_RCGR */

26
drivers/clk/qcom/clock-qcom.h
View File

@ -52,13 +52,20 @@ struct freq_tbl {
struct gate_clk {
uintptr_t reg;
u32 en_val;
uintptr_t cbcr_reg;
const char *name;
};
/*
* GATE_CLK() is deprecated: Use GATE_CLK_POLLED() instead to ensure the clock
* is running before we start making use of devices or registers.
*/
#ifdef DEBUG
#define GATE_CLK(clk, reg, val) [clk] = { reg, val, #clk }
#define GATE_CLK(clk, reg, val) [clk] = { reg, val, 0, #clk }
#define GATE_CLK_POLLED(clk, en_reg, val, cbcr_reg) [clk] = { en_reg, val, cbcr_reg, #clk }
#else
#define GATE_CLK(clk, reg, val) [clk] = { reg, val, NULL }
#define GATE_CLK(clk, reg, val) [clk] = { reg, val, 0, NULL }
#define GATE_CLK_POLLED(clk, en_reg, val, cbcr_reg) [clk] = { en_reg, val, cbcr_reg, NULL }
#endif
struct qcom_reset_map {
@ -107,19 +114,6 @@ void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div,
int source);
void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled);
static inline int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
{
u32 val;
if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0) {
log_err("gcc@%#08llx: unknown clock ID %lu!\n",
priv->base, id);
return -ENOENT;
}
val = readl(priv->base + priv->data->clks[id].reg);
writel(val | priv->data->clks[id].en_val, priv->base + priv->data->clks[id].reg);
return 0;
}
int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id);
#endif

25
drivers/crypto/fsl/jr.c
View File

@ -217,6 +217,13 @@ static int jr_enqueue(uint32_t *desc_addr,
jr->head = (head + 1) & (jr->size - 1);
/* Invalidate output ring */
start = (unsigned long)jr->output_ring &
~(ARCH_DMA_MINALIGN - 1);
end = ALIGN((unsigned long)jr->output_ring + jr->op_size,
ARCH_DMA_MINALIGN);
invalidate_dcache_range(start, end);
sec_out32(&regs->irja, 1);
return 0;
@ -236,7 +243,6 @@ static int jr_dequeue(int sec_idx, struct caam_regs *caam)
#else
uint32_t *addr;
#endif
unsigned long start, end;
while (sec_in32(&regs->orsf) && CIRC_CNT(jr->head, jr->tail,
jr->size)) {
@ -244,11 +250,6 @@ static int jr_dequeue(int sec_idx, struct caam_regs *caam)
found = 0;
caam_dma_addr_t op_desc;
/* Invalidate output ring */
start = (unsigned long)jr->output_ring & ~(ARCH_DMA_MINALIGN - 1);
end = ALIGN((unsigned long)jr->output_ring + jr->op_size, ARCH_DMA_MINALIGN);
invalidate_dcache_range(start, end);
#ifdef CONFIG_CAAM_64BIT
/* Read the 64 bit Descriptor address from Output Ring.
* The 32 bit hign and low part of the address will
@ -282,13 +283,8 @@ static int jr_dequeue(int sec_idx, struct caam_regs *caam)
}
/* Error condition if match not found */
if (!found) {
int slots_full = sec_in32(&regs->orsf);
jr->tail = (jr->tail + slots_full) & (jr->size - 1);
sec_out32(&regs->orjr, slots_full);
if (!found)
return -1;
}
jr->info[idx].op_done = 1;
callback = (void *)jr->info[idx].callback;
@ -300,14 +296,14 @@ static int jr_dequeue(int sec_idx, struct caam_regs *caam)
*/
if (idx == tail)
do {
jr->info[tail].op_done = 0;
tail = (tail + 1) & (jr->size - 1);
} while (jr->info[tail].op_done);
jr->tail = tail;
jr->read_idx = (jr->read_idx + 1) & (jr->size - 1);
sec_out32(&regs->orjr, 1);
jr->info[idx].op_done = 0;
callback(status, arg);
}
@ -382,6 +378,7 @@ static int jr_sw_cleanup(uint8_t sec_idx, struct caam_regs *caam)
jr->head = 0;
jr->tail = 0;
jr->read_idx = 0;
jr->write_idx = 0;
memset(jr->info, 0, sizeof(jr->info));
memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));

4
drivers/crypto/fsl/jr.h
View File

@ -83,6 +83,10 @@ struct jobring {
* in-order job completion
*/
int tail;
/* Read index of the output ring. It may not match with tail in case
* of out of order completetion
*/
int read_idx;
/* Write index to input ring. Would be always equal to head */
int write_idx;
/* Size of the rings. */

7
drivers/fpga/intel_sdm_mb.c
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Intel Corporation <www.intel.com>
* Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
#include <altera.h>
@ -9,6 +10,8 @@
#include <watchdog.h>
#include <asm/arch/mailbox_s10.h>
#include <asm/arch/smc_api.h>
#include <asm/cache.h>
#include <cpu_func.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/intel-smc.h>
@ -738,6 +741,8 @@ int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
debug("Invoking FPGA_CONFIG_START...\n");
flush_dcache_range((unsigned long)rbf_data, (unsigned long)(rbf_data + rbf_size));
ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, &arg, 1, NULL, 0);
if (ret) {
@ -1023,6 +1028,8 @@ int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
u32 resp_len = 2;
u32 resp_buf[2];
flush_dcache_range((unsigned long)rbf_data, (unsigned long)(rbf_data + rbf_size));
debug("Sending MBOX_RECONFIG...\n");
ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RECONFIG, MBOX_CMD_DIRECT, 0,
NULL, 0, &resp_len, resp_buf);

30
drivers/i2c/designware_i2c.c
View File

@ -404,7 +404,7 @@ static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
/* Evaluate timeout */
if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
return 1;
return -ETIMEDOUT;
}
return 0;
@ -413,8 +413,10 @@ static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
int alen)
{
if (i2c_wait_for_bb(i2c_base))
return 1;
int ret = i2c_wait_for_bb(i2c_base);
if (ret)
return ret;
i2c_setaddress(i2c_base, chip);
while (alen) {
@ -429,6 +431,7 @@ static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
static int i2c_xfer_finish(struct i2c_regs *i2c_base)
{
ulong start_stop_det = get_timer(0);
int ret;
while (1) {
if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
@ -439,9 +442,10 @@ static int i2c_xfer_finish(struct i2c_regs *i2c_base)
}
}
if (i2c_wait_for_bb(i2c_base)) {
ret = i2c_wait_for_bb(i2c_base);
if (ret) {
printf("Timed out waiting for bus\n");
return 1;
return ret;
}
i2c_flush_rxfifo(i2c_base);
@ -464,6 +468,7 @@ static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
{
unsigned long start_time_rx;
unsigned int active = 0;
int ret;
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
/*
@ -484,8 +489,9 @@ static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
addr);
#endif
if (i2c_xfer_init(i2c_base, dev, addr, alen))
return 1;
ret = i2c_xfer_init(i2c_base, dev, addr, alen);
if (ret)
return ret;
start_time_rx = get_timer(0);
while (len) {
@ -510,7 +516,7 @@ static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
start_time_rx = get_timer(0);
active = 0;
} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
return 1;
return -ETIMEDOUT;
}
}
@ -532,6 +538,7 @@ static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
{
int nb = len;
unsigned long start_time_tx;
int ret;
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
/*
@ -552,8 +559,9 @@ static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
addr);
#endif
if (i2c_xfer_init(i2c_base, dev, addr, alen))
return 1;
ret = i2c_xfer_init(i2c_base, dev, addr, alen);
if (ret)
return ret;
start_time_tx = get_timer(0);
while (len) {
@ -569,7 +577,7 @@ static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
} else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
printf("Timed out. i2c write Failed\n");
return 1;
return -ETIMEDOUT;
}
}

8
drivers/misc/Kconfig
View File

@ -114,6 +114,14 @@ config ROCKCHIP_IODOMAIN
for the IO-domain setting of the SoC to match the voltage supplied
by the regulators.
config SPL_ROCKCHIP_IODOMAIN
bool "Rockchip IO-domain driver support in SPL"
depends on SPL_MISC && SPL_DM_REGULATOR && ARCH_ROCKCHIP
help
Enable support for IO-domains in Rockchip SoCs in SPL. It is necessary
for the IO-domain setting of the SoC to match the voltage supplied
by the regulators.
config SIFIVE_OTP
bool "SiFive eMemory OTP driver"
depends on MISC

5
drivers/misc/rockchip-io-domain.c
View File

@ -344,8 +344,10 @@ static int rockchip_iodomain_probe(struct udevice *dev)
continue;
ret = device_get_supply_regulator(dev, supply_name, &reg);
if (ret)
if (ret) {
dev_dbg(dev, "%s: Regulator not found\n", supply_name);
continue;
}
ret = regulator_autoset(reg);
if (ret && ret != -EALREADY && ret != -EMEDIUMTYPE &&
@ -353,6 +355,7 @@ static int rockchip_iodomain_probe(struct udevice *dev)
continue;
uV = regulator_get_value(reg);
dev_dbg(dev, "%s: Regulator %s at %d uV\n", supply_name, reg->name, uV);
if (uV <= 0)
continue;

5
drivers/mmc/am654_sdhci.c
View File

@ -527,11 +527,16 @@ static int am654_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
void am654_sdhci_set_control_reg(struct sdhci_host *host)
{
struct mmc *mmc = host->mmc;
u32 reg;
reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
reg &= ~SDHCI_CTRL_UHS_MASK;
sdhci_set_voltage(host);
if (mmc->selected_mode > MMC_HS_52)
sdhci_set_uhs_timing(host);
else
sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
}
const struct sdhci_ops am654_sdhci_ops = {

14
drivers/net/zynq_gem.c
View File

@ -567,12 +567,14 @@ static int zynq_gem_init(struct udevice *dev)
}
#endif
ret = clk_get_rate(&priv->tx_clk);
if (ret != clk_rate) {
ret = clk_set_rate(&priv->tx_clk, clk_rate);
if (IS_ERR_VALUE(ret)) {
dev_err(dev, "failed to set tx clock rate %ld\n", clk_rate);
return ret;
if (priv->interface != PHY_INTERFACE_MODE_MII) {
ret = clk_get_rate(&priv->tx_clk);
if (ret != clk_rate) {
ret = clk_set_rate(&priv->tx_clk, clk_rate);
if (IS_ERR_VALUE(ret)) {
dev_err(dev, "failed to set tx clock rate %ld\n", clk_rate);
return ret;
}
}
}

7
drivers/pci/pcie-xilinx-nwl.c
View File

@ -303,6 +303,13 @@ static int nwl_pcie_parse_dt(struct nwl_pcie *pcie)
return PTR_ERR(pcie->breg_base);
pcie->phys_breg_base = res.start;
ret = dev_read_resource_byname(dev, "pcireg", &res);
if (ret)
return ret;
pcie->pcireg_base = devm_ioremap(dev, res.start, resource_size(&res));
if (IS_ERR(pcie->pcireg_base))
return PTR_ERR(pcie->pcireg_base);
ret = dev_read_resource_byname(dev, "cfg", &res);
if (ret)
return ret;

6
drivers/phy/phy-zynqmp.c
View File

@ -138,6 +138,7 @@
#define PROT_BUS_WIDTH_40 0x2
#define PROT_BUS_WIDTH_MASK 0x3
#define PROT_BUS_WIDTH_SHIFT 2
#define GEM_CLK_CTRL_WIDTH_SHIFT 5
/* Number of GT lanes */
#define NUM_LANES 4
@ -400,6 +401,7 @@ static void xpsgtr_phy_init_sgmii(struct xpsgtr_phy *gtr_phy)
{
struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
u32 shift = gtr_phy->lane * PROT_BUS_WIDTH_SHIFT;
u32 clk_ctrl_shift = gtr_phy->lane * GEM_CLK_CTRL_WIDTH_SHIFT;
/* Set SGMII protocol TX and RX bus width to 10 bits. */
xpsgtr_clr_set(gtr_dev, TX_PROT_BUS_WIDTH, PROT_BUS_WIDTH_MASK << shift,
@ -417,9 +419,9 @@ static void xpsgtr_phy_init_sgmii(struct xpsgtr_phy *gtr_phy)
*/
/* GEM I/O Clock Control */
clrsetbits_le32(ZYNQMP_IOU_SLCR_BASEADDR + IOU_SLCR_GEM_CLK_CTRL,
0xf << shift,
0xf << clk_ctrl_shift,
(GEM_CTRL_GEM_SGMII_MODE | GEM_CTRL_GEM_REF_SRC_SEL) <<
shift);
clk_ctrl_shift);
/* Setup signal detect */
clrsetbits_le32(ZYNQMP_IOU_SLCR_BASEADDR + IOU_SLCR_GEM_CTRL,

2
drivers/power/pmic/rk8xx.c
View File

@ -91,7 +91,7 @@ void rk8xx_off_for_plugin(struct udevice *dev)
static struct reg_data rk806_init_reg[] = {
/* RST_FUN */
{ RK806_REG_SYS_CFG3, GENMASK(7, 6), BIT(7)},
{ RK806_REG_SYS_CFG3, BIT(7), GENMASK(7, 6)},
};
static struct reg_data rk817_init_reg[] = {

9
drivers/power/regulator/Kconfig
View File

@ -264,6 +264,15 @@ config REGULATOR_RK8XX
by the PMIC device. This driver is controlled by a device tree node
which includes voltage limits.
config SPL_REGULATOR_RK8XX
bool "Enable driver for RK8XX regulators in SPL"
depends on SPL_DM_REGULATOR && SPL_PMIC_RK8XX
help
Enable support for the regulator functions of the RK8XX PMIC in SPL. The
driver implements get/set api for the various BUCKS and LDOs supported
by the PMIC device. This driver is controlled by a device tree node
which includes voltage limits.
config DM_REGULATOR_S2MPS11
bool "Enable driver for S2MPS11 regulator"
depends on DM_REGULATOR && PMIC_S2MPS11

37
drivers/power/regulator/qcom_usb_vbus_regulator.c
View File

@ -15,14 +15,33 @@
#include <power/pmic.h>
#include <power/regulator.h>
#define CMD_OTG 0x50
enum pm8x50b_vbus {
PM8150B,
PM8550B,
};
#define OTG_EN BIT(0)
// The 0 bit in this register's bit field is undocumented
#define OTG_CFG 0x56
#define OTG_EN_SRC_CFG BIT(1)
struct qcom_otg_regs {
u32 otg_cmd;
u32 otg_cfg;
};
struct qcom_usb_vbus_priv {
phys_addr_t base;
struct qcom_otg_regs *regs;
};
static const struct qcom_otg_regs qcom_otg[] = {
[PM8150B] = {
.otg_cmd = 0x40,
.otg_cfg = 0x53,
},
[PM8550B] = {
.otg_cmd = 0x50,
.otg_cfg = 0x56,
},
};
static int qcom_usb_vbus_regulator_of_to_plat(struct udevice *dev)
@ -38,8 +57,9 @@ static int qcom_usb_vbus_regulator_of_to_plat(struct udevice *dev)
static int qcom_usb_vbus_regulator_get_enable(struct udevice *dev)
{
const struct qcom_otg_regs *regs = &qcom_otg[dev_get_driver_data(dev)];
struct qcom_usb_vbus_priv *priv = dev_get_priv(dev);
int otg_en_reg = priv->base + CMD_OTG;
int otg_en_reg = priv->base + regs->otg_cmd;
int ret;
ret = pmic_reg_read(dev->parent, otg_en_reg);
@ -53,8 +73,9 @@ static int qcom_usb_vbus_regulator_get_enable(struct udevice *dev)
static int qcom_usb_vbus_regulator_set_enable(struct udevice *dev, bool enable)
{
const struct qcom_otg_regs *regs = &qcom_otg[dev_get_driver_data(dev)];
struct qcom_usb_vbus_priv *priv = dev_get_priv(dev);
int otg_en_reg = priv->base + CMD_OTG;
int otg_en_reg = priv->base + regs->otg_cmd;
int ret;
if (enable) {
@ -76,8 +97,9 @@ static int qcom_usb_vbus_regulator_set_enable(struct udevice *dev, bool enable)
static int qcom_usb_vbus_regulator_probe(struct udevice *dev)
{
const struct qcom_otg_regs *regs = &qcom_otg[dev_get_driver_data(dev)];
struct qcom_usb_vbus_priv *priv = dev_get_priv(dev);
int otg_cfg_reg = priv->base + OTG_CFG;
int otg_cfg_reg = priv->base + regs->otg_cfg;
int ret;
/* Disable HW logic for VBUS enable */
@ -96,7 +118,8 @@ static const struct dm_regulator_ops qcom_usb_vbus_regulator_ops = {
};
static const struct udevice_id qcom_usb_vbus_regulator_ids[] = {
{ .compatible = "qcom,pm8150b-vbus-reg"},
{ .compatible = "qcom,pm8150b-vbus-reg", .data = PM8150B },
{ .compatible = "qcom,pm8550b-vbus-reg", .data = PM8550B },
{ },
};

8
drivers/power/regulator/rk8xx.c
View File

@ -16,10 +16,6 @@
#include <power/pmic.h>
#include <power/regulator.h>
#ifndef CONFIG_XPL_BUILD
#define ENABLE_DRIVER
#endif
/* Not used or exisit register and configure */
#define NA 0xff
@ -202,7 +198,7 @@ static const struct rk8xx_reg_info rk818_buck[] = {
{ 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, 0x00, 0x1f },
};
#ifdef ENABLE_DRIVER
#if CONFIG_IS_ENABLED(REGULATOR_RK8XX)
static const struct rk8xx_reg_info rk806_nldo[] = {
/* nldo 1 */
{ 500000, 12500, RK806_NLDO_ON_VSEL(1), RK806_NLDO_SLP_VSEL(1), NA, RK806_NLDO_VSEL_MASK, 0x00, 0xe7},
@ -454,7 +450,7 @@ static int _buck_set_enable(struct udevice *pmic, int buck, bool enable)
return ret;
}
#ifdef ENABLE_DRIVER
#if CONFIG_IS_ENABLED(REGULATOR_RK8XX)
static int _buck_set_suspend_value(struct udevice *pmic, int buck, int uvolt)
{
const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt);

1
drivers/ram/rockchip/Kconfig
View File

@ -15,6 +15,7 @@ if RAM_ROCKCHIP
config RAM_ROCKCHIP_DEBUG
bool "Rockchip ram drivers debugging"
depends on DEBUG_UART
default y
help
This enables debugging ram driver API's for the platforms

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