From b236a66ab576c3e55f5768074b3d5a9e1399dcb8 Mon Sep 17 00:00:00 2001 From: Jessica Clarke Date: Fri, 12 Aug 2022 18:50:03 +0100 Subject: [PATCH 1/5] riscv: dts: Sync important Unmatched pmic and qspi0 changes from Linux This adds the onkey, RTC and watchdog children to the DA9063 PMIC node, fixes the compatible for qspi0's flash node to match the official DT schema (it being an is25wp256 is discoverable, hence jedec,spi-nor is the only compatible that should be present) and exposes the card detect GPIO. Note that the device trees still diverge in some places (including important things like the PCIe controller's clock name) and should be cleaned up so that a common device tree is used in both projects rather than having different bindings. This patch does not attempt to do that, merely expose important functionality present in Linux's that is not in U-Boot's so that it can be used without the OS providing its own bundled copy. Signed-off-by: Jessica Clarke Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/hifive-unmatched-a00.dts | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/riscv/dts/hifive-unmatched-a00.dts b/arch/riscv/dts/hifive-unmatched-a00.dts index b44e8c160db..ea32ae72e8c 100644 --- a/arch/riscv/dts/hifive-unmatched-a00.dts +++ b/arch/riscv/dts/hifive-unmatched-a00.dts @@ -76,6 +76,18 @@ interrupts = <1 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; + onkey { + compatible = "dlg,da9063-onkey"; + }; + + rtc { + compatible = "dlg,da9063-rtc"; + }; + + wdt { + compatible = "dlg,da9063-watchdog"; + }; + regulators { vdd_bcore1: bcore1 { regulator-min-microvolt = <1050000>; @@ -217,7 +229,7 @@ &qspi0 { status = "okay"; flash@0 { - compatible = "issi,is25wp256", "jedec,spi-nor"; + compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <50000000>; m25p,fast-read; @@ -234,6 +246,7 @@ spi-max-frequency = <20000000>; voltage-ranges = <3300 3300>; disable-wp; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; }; }; From d13cd77068eb3c52271412db821ecc0ab1e8f4f4 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 25 Aug 2022 16:11:18 +0800 Subject: [PATCH 2/5] dt-bindings: clock: sifive: sync FU740 PRCI clock binding header This commit sychronizes the header file for FU740 PRCI clocks with the one from Linux 5.19. The constant values are the same, but all constant names are changed (most are just prefixed with FU740_). Signed-off-by: Icenowy Zheng Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/fu740-c000-u-boot.dtsi | 16 +++++------ arch/riscv/dts/fu740-c000.dtsi | 28 +++++++++---------- drivers/clk/sifive/fu740-prci.c | 18 ++++++------ drivers/clk/sifive/sifive-prci.c | 4 +-- include/dt-bindings/clock/sifive-fu740-prci.h | 25 ++++++++--------- 5 files changed, 45 insertions(+), 46 deletions(-) diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi b/arch/riscv/dts/fu740-c000-u-boot.dtsi index a6f7a0873ee..917e9bf1634 100644 --- a/arch/riscv/dts/fu740-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi @@ -7,11 +7,11 @@ / { cpus { - assigned-clocks = <&prci PRCI_CLK_COREPLL>; + assigned-clocks = <&prci FU740_PRCI_CLK_COREPLL>; assigned-clock-rates = <1200000000>; u-boot,dm-spl; cpu0: cpu@0 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU740_PRCI_CLK_COREPLL>; u-boot,dm-spl; status = "okay"; cpu0_intc: interrupt-controller { @@ -19,28 +19,28 @@ }; }; cpu1: cpu@1 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU740_PRCI_CLK_COREPLL>; u-boot,dm-spl; cpu1_intc: interrupt-controller { u-boot,dm-spl; }; }; cpu2: cpu@2 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU740_PRCI_CLK_COREPLL>; u-boot,dm-spl; cpu2_intc: interrupt-controller { u-boot,dm-spl; }; }; cpu3: cpu@3 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU740_PRCI_CLK_COREPLL>; u-boot,dm-spl; cpu3_intc: interrupt-controller { u-boot,dm-spl; }; }; cpu4: cpu@4 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU740_PRCI_CLK_COREPLL>; u-boot,dm-spl; cpu4_intc: interrupt-controller { u-boot,dm-spl; @@ -76,7 +76,7 @@ reg = <0x0 0x100b0000 0x0 0x0800 0x0 0x100b2000 0x0 0x2000 0x0 0x100b8000 0x0 0x1000>; - clocks = <&prci PRCI_CLK_DDRPLL>; + clocks = <&prci FU740_PRCI_CLK_DDRPLL>; clock-frequency = <933333324>; u-boot,dm-spl; }; @@ -100,7 +100,7 @@ }; ð0 { - assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>; + assigned-clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>; assigned-clock-rates = <125125000>; }; diff --git a/arch/riscv/dts/fu740-c000.dtsi b/arch/riscv/dts/fu740-c000.dtsi index 649efe400ac..0e14aa71e76 100644 --- a/arch/riscv/dts/fu740-c000.dtsi +++ b/arch/riscv/dts/fu740-c000.dtsi @@ -166,7 +166,7 @@ reg = <0x0 0x10010000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <39>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; status = "disabled"; }; uart1: serial@10011000 { @@ -174,7 +174,7 @@ reg = <0x0 0x10011000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <40>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; status = "disabled"; }; i2c0: i2c@10030000 { @@ -182,7 +182,7 @@ reg = <0x0 0x10030000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <52>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; reg-shift = <2>; reg-io-width = <1>; #address-cells = <1>; @@ -194,7 +194,7 @@ reg = <0x0 0x10031000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <53>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; reg-shift = <2>; reg-io-width = <1>; #address-cells = <1>; @@ -207,7 +207,7 @@ 0x0 0x20000000 0x0 0x10000000>; interrupt-parent = <&plic0>; interrupts = <41>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -218,7 +218,7 @@ 0x0 0x30000000 0x0 0x10000000>; interrupt-parent = <&plic0>; interrupts = <42>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -228,7 +228,7 @@ reg = <0x0 0x10050000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <43>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -241,8 +241,8 @@ 0x0 0x100a0000 0x0 0x1000>; local-mac-address = [00 00 00 00 00 00]; clock-names = "pclk", "hclk"; - clocks = <&prci PRCI_CLK_GEMGXLPLL>, - <&prci PRCI_CLK_GEMGXLPLL>; + clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>, + <&prci FU740_PRCI_CLK_GEMGXLPLL>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -252,7 +252,7 @@ reg = <0x0 0x10020000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <44 45 46 47>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; #pwm-cells = <3>; status = "disabled"; }; @@ -261,7 +261,7 @@ reg = <0x0 0x10021000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <48 49 50 51>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; #pwm-cells = <3>; status = "disabled"; }; @@ -287,7 +287,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; status = "disabled"; }; pcie@e00000000 { @@ -318,8 +318,8 @@ <0x0 0x0 0x0 0x4 &plic0 60>; pwren-gpios = <&gpio 5 0>; reset-gpios = <&gpio 8 0>; - clocks = <&prci PRCI_CLK_PCIEAUX>; - clock-names = "pcieaux"; + clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>; + clock-names = "pcie_aux"; resets = <&prci PRCI_RST_PCIE_POWER_UP_N>; reset-names = "rst_n"; diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c index b025050e224..5edc864e4bd 100644 --- a/drivers/clk/sifive/fu740-prci.c +++ b/drivers/clk/sifive/fu740-prci.c @@ -103,53 +103,53 @@ static const struct __prci_clock_ops sifive_fu740_prci_pcieaux_clk_ops = { /* List of clock controls provided by the PRCI */ struct __prci_clock __prci_init_clocks_fu740[] = { - [PRCI_CLK_COREPLL] = { + [FU740_PRCI_CLK_COREPLL] = { .name = "corepll", .parent_name = "hfclk", .ops = &sifive_fu740_prci_wrpll_clk_ops, .pwd = &__prci_corepll_data, }, - [PRCI_CLK_DDRPLL] = { + [FU740_PRCI_CLK_DDRPLL] = { .name = "ddrpll", .parent_name = "hfclk", .ops = &sifive_fu740_prci_wrpll_clk_ops, .pwd = &__prci_ddrpll_data, }, - [PRCI_CLK_GEMGXLPLL] = { + [FU740_PRCI_CLK_GEMGXLPLL] = { .name = "gemgxlpll", .parent_name = "hfclk", .ops = &sifive_fu740_prci_wrpll_clk_ops, .pwd = &__prci_gemgxlpll_data, }, - [PRCI_CLK_DVFSCOREPLL] = { + [FU740_PRCI_CLK_DVFSCOREPLL] = { .name = "dvfscorepll", .parent_name = "hfclk", .ops = &sifive_fu740_prci_wrpll_clk_ops, .pwd = &__prci_dvfscorepll_data, }, - [PRCI_CLK_HFPCLKPLL] = { + [FU740_PRCI_CLK_HFPCLKPLL] = { .name = "hfpclkpll", .parent_name = "hfclk", .ops = &sifive_fu740_prci_wrpll_clk_ops, .pwd = &__prci_hfpclkpll_data, }, - [PRCI_CLK_CLTXPLL] = { + [FU740_PRCI_CLK_CLTXPLL] = { .name = "cltxpll", .parent_name = "hfclk", .ops = &sifive_fu740_prci_wrpll_clk_ops, .pwd = &__prci_cltxpll_data, }, - [PRCI_CLK_TLCLK] = { + [FU740_PRCI_CLK_TLCLK] = { .name = "tlclk", .parent_name = "corepll", .ops = &sifive_fu740_prci_tlclksel_clk_ops, }, - [PRCI_CLK_PCLK] = { + [FU740_PRCI_CLK_PCLK] = { .name = "pclk", .parent_name = "hfpclkpll", .ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops, }, - [PRCI_CLK_PCIEAUX] { + [FU740_PRCI_CLK_PCIE_AUX] { .name = "pcieaux", .parent_name = "", .ops = &sifive_fu740_prci_pcieaux_clk_ops, diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index 52ae268e0c8..c8fb6002907 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -685,14 +685,14 @@ static int sifive_prci_probe(struct udevice *dev) * case the design uses hfpclk to drive * Chiplink */ - pc = &data->clks[PRCI_CLK_HFPCLKPLL]; + pc = &data->clks[FU740_PRCI_CLK_HFPCLKPLL]; parent_rate = sifive_prci_parent_rate(pc, data); sifive_prci_wrpll_set_rate(pc, 260000000, parent_rate); pc->ops->enable_clk(pc, 1); } else if (prci_pll_reg & PRCI_PRCIPLL_CLTXPLL) { /* CLTX pll init */ - pc = &data->clks[PRCI_CLK_CLTXPLL]; + pc = &data->clks[FU740_PRCI_CLK_CLTXPLL]; parent_rate = sifive_prci_parent_rate(pc, data); sifive_prci_wrpll_set_rate(pc, 260000000, parent_rate); diff --git a/include/dt-bindings/clock/sifive-fu740-prci.h b/include/dt-bindings/clock/sifive-fu740-prci.h index c1224783c08..672bdadbf6c 100644 --- a/include/dt-bindings/clock/sifive-fu740-prci.h +++ b/include/dt-bindings/clock/sifive-fu740-prci.h @@ -1,10 +1,9 @@ -/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* - * Copyright (C) 2020-2021 SiFive, Inc. + * Copyright (C) 2019 SiFive, Inc. * Wesley Terpstra * Paul Walmsley * Zong Li - * Pragnesh Patel */ #ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H @@ -12,14 +11,14 @@ /* Clock indexes for use by Device Tree data and the PRCI driver */ -#define PRCI_CLK_COREPLL 0 -#define PRCI_CLK_DDRPLL 1 -#define PRCI_CLK_GEMGXLPLL 2 -#define PRCI_CLK_DVFSCOREPLL 3 -#define PRCI_CLK_HFPCLKPLL 4 -#define PRCI_CLK_CLTXPLL 5 -#define PRCI_CLK_TLCLK 6 -#define PRCI_CLK_PCLK 7 -#define PRCI_CLK_PCIEAUX 8 +#define FU740_PRCI_CLK_COREPLL 0 +#define FU740_PRCI_CLK_DDRPLL 1 +#define FU740_PRCI_CLK_GEMGXLPLL 2 +#define FU740_PRCI_CLK_DVFSCOREPLL 3 +#define FU740_PRCI_CLK_HFPCLKPLL 4 +#define FU740_PRCI_CLK_CLTXPLL 5 +#define FU740_PRCI_CLK_TLCLK 6 +#define FU740_PRCI_CLK_PCLK 7 +#define FU740_PRCI_CLK_PCIE_AUX 8 -#endif +#endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */ From ac48fc3deb3708fec4bfd49dc878b67b57a8ebfb Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 25 Aug 2022 16:11:19 +0800 Subject: [PATCH 3/5] riscv: dts: sifive: Synchronize FU740 and Unmatched DT These DT files are synchronized from Linux 5.19. Signed-off-by: Icenowy Zheng Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/fu740-c000.dtsi | 69 ++++++++++----------- arch/riscv/dts/hifive-unmatched-a00.dts | 80 +++++++++---------------- 2 files changed, 60 insertions(+), 89 deletions(-) diff --git a/arch/riscv/dts/fu740-c000.dtsi b/arch/riscv/dts/fu740-c000.dtsi index 0e14aa71e76..7b77c13496d 100644 --- a/arch/riscv/dts/fu740-c000.dtsi +++ b/arch/riscv/dts/fu740-c000.dtsi @@ -1,10 +1,9 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2020-2021 SiFive, Inc */ +/* Copyright (c) 2020 SiFive, Inc */ /dts-v1/; #include -#include / { #address-cells = <2>; @@ -139,20 +138,21 @@ soc { #address-cells = <2>; #size-cells = <2>; - compatible = "sifive,fu740-c000", "sifive,fu740", "simple-bus"; + compatible = "simple-bus"; ranges; plic0: interrupt-controller@c000000 { #interrupt-cells = <1>; - compatible = "sifive,plic-1.0.0"; + #address-cells = <0>; + compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; reg = <0x0 0xc000000 0x0 0x4000000>; riscv,ndev = <69>; interrupt-controller; - interrupts-extended = < - &cpu0_intc 0xffffffff - &cpu1_intc 0xffffffff &cpu1_intc 9 - &cpu2_intc 0xffffffff &cpu2_intc 9 - &cpu3_intc 0xffffffff &cpu3_intc 9 - &cpu4_intc 0xffffffff &cpu4_intc 9>; + interrupts-extended = + <&cpu0_intc 0xffffffff>, + <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, + <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, + <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, + <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>; }; prci: clock-controller@10000000 { compatible = "sifive,fu740-c000-prci"; @@ -203,8 +203,8 @@ }; qspi0: spi@10040000 { compatible = "sifive,fu740-c000-spi", "sifive,spi0"; - reg = <0x0 0x10040000 0x0 0x1000 - 0x0 0x20000000 0x0 0x10000000>; + reg = <0x0 0x10040000 0x0 0x1000>, + <0x0 0x20000000 0x0 0x10000000>; interrupt-parent = <&plic0>; interrupts = <41>; clocks = <&prci FU740_PRCI_CLK_PCLK>; @@ -214,8 +214,8 @@ }; qspi1: spi@10041000 { compatible = "sifive,fu740-c000-spi", "sifive,spi0"; - reg = <0x0 0x10041000 0x0 0x1000 - 0x0 0x30000000 0x0 0x10000000>; + reg = <0x0 0x10041000 0x0 0x1000>, + <0x0 0x30000000 0x0 0x10000000>; interrupt-parent = <&plic0>; interrupts = <42>; clocks = <&prci FU740_PRCI_CLK_PCLK>; @@ -237,8 +237,8 @@ compatible = "sifive,fu540-c000-gem"; interrupt-parent = <&plic0>; interrupts = <55>; - reg = <0x0 0x10090000 0x0 0x2000 - 0x0 0x100a0000 0x0 0x1000>; + reg = <0x0 0x10090000 0x0 0x2000>, + <0x0 0x100a0000 0x0 0x1000>; local-mac-address = [00 00 00 00 00 00]; clock-names = "pclk", "hclk"; clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>, @@ -251,7 +251,7 @@ compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; reg = <0x0 0x10020000 0x0 0x1000>; interrupt-parent = <&plic0>; - interrupts = <44 45 46 47>; + interrupts = <44>, <45>, <46>, <47>; clocks = <&prci FU740_PRCI_CLK_PCLK>; #pwm-cells = <3>; status = "disabled"; @@ -260,7 +260,7 @@ compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; reg = <0x0 0x10021000 0x0 0x1000>; interrupt-parent = <&plic0>; - interrupts = <48 49 50 51>; + interrupts = <48>, <49>, <50>, <51>; clocks = <&prci FU740_PRCI_CLK_PCLK>; #pwm-cells = <3>; status = "disabled"; @@ -273,7 +273,7 @@ cache-size = <2097152>; cache-unified; interrupt-parent = <&plic0>; - interrupts = <19 21 22 20>; + interrupts = <19>, <21>, <22>, <20>; reg = <0x0 0x2010000 0x0 0x1000>; }; gpio: gpio@10060000 { @@ -291,24 +291,23 @@ status = "disabled"; }; pcie@e00000000 { - #address-cells = <3>; - #interrupt-cells = <1>; - #num-lanes = <8>; - #size-cells = <2>; compatible = "sifive,fu740-pcie"; - reg = <0xe 0x00000000 0x1 0x0 - 0xd 0xf0000000 0x0 0x10000000 - 0x0 0x100d0000 0x0 0x1000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + reg = <0xe 0x00000000 0x0 0x80000000>, + <0xd 0xf0000000 0x0 0x10000000>, + <0x0 0x100d0000 0x0 0x1000>; reg-names = "dbi", "config", "mgmt"; device_type = "pci"; dma-coherent; bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000 - 0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000 - 0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000 - 0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; + ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */ + <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */ + <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */ + <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */ num-lanes = <0x8>; - interrupts = <56 57 58 59 60 61 62 63 64>; + interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>; interrupt-names = "msi", "inta", "intb", "intc", "intd"; interrupt-parent = <&plic0>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; @@ -316,13 +315,11 @@ <0x0 0x0 0x0 0x2 &plic0 58>, <0x0 0x0 0x0 0x3 &plic0 59>, <0x0 0x0 0x0 0x4 &plic0 60>; + clock-names = "pcie_aux"; + clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>; pwren-gpios = <&gpio 5 0>; reset-gpios = <&gpio 8 0>; - clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>; - clock-names = "pcie_aux"; - resets = <&prci PRCI_RST_PCIE_POWER_UP_N>; - reset-names = "rst_n"; - + resets = <&prci 4>; status = "okay"; }; }; diff --git a/arch/riscv/dts/hifive-unmatched-a00.dts b/arch/riscv/dts/hifive-unmatched-a00.dts index ea32ae72e8c..c4ed9efdff0 100644 --- a/arch/riscv/dts/hifive-unmatched-a00.dts +++ b/arch/riscv/dts/hifive-unmatched-a00.dts @@ -1,5 +1,5 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* Copyright (c) 2019-2021 SiFive, Inc */ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020 SiFive, Inc */ #include "fu740-c000.dtsi" #include @@ -9,8 +9,6 @@ #define RTCCLK_FREQ 1000000 / { - #address-cells = <2>; - #size-cells = <2>; model = "SiFive HiFive Unmatched A00"; compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000", "sifive,fu740"; @@ -28,9 +26,6 @@ reg = <0x0 0x80000000 0x4 0x00000000>; }; - soc { - }; - hfclk: hfclk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -65,10 +60,21 @@ temperature-sensor@4c { compatible = "ti,tmp451"; reg = <0x4c>; + vcc-supply = <&vdd_bpro>; interrupt-parent = <&gpio>; interrupts = <6 IRQ_TYPE_LEVEL_LOW>; }; + eeprom@54 { + compatible = "microchip,24c02", "atmel,24c02"; + reg = <0x54>; + vcc-supply = <&vdd_bpro>; + label = "board-id"; + pagesize = <16>; + read-only; + size = <256>; + }; + pmic@58 { compatible = "dlg,da9063"; reg = <0x58>; @@ -89,47 +95,31 @@ }; regulators { - vdd_bcore1: bcore1 { + vdd_bcore: bcores-merged { regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; - regulator-min-microamp = <5000000>; - regulator-max-microamp = <5000000>; - regulator-always-on; - }; - - vdd_bcore2: bcore2 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-min-microamp = <5000000>; - regulator-max-microamp = <5000000>; + regulator-min-microamp = <4800000>; + regulator-max-microamp = <4800000>; regulator-always-on; }; vdd_bpro: bpro { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-min-microamp = <2500000>; - regulator-max-microamp = <2500000>; + regulator-min-microamp = <2400000>; + regulator-max-microamp = <2400000>; regulator-always-on; }; vdd_bperi: bperi { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <1060000>; + regulator-max-microvolt = <1060000>; regulator-min-microamp = <1500000>; regulator-max-microamp = <1500000>; regulator-always-on; }; - vdd_bmem: bmem { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <3000000>; - regulator-always-on; - }; - - vdd_bio: bio { + vdd_bmem_bio: bmem-bio-merged { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-min-microamp = <3000000>; @@ -140,86 +130,66 @@ vdd_ldo1: ldo1 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-min-microamp = <100000>; - regulator-max-microamp = <100000>; regulator-always-on; }; vdd_ldo2: ldo2 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; regulator-always-on; }; vdd_ldo3: ldo3 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; regulator-always-on; }; vdd_ldo4: ldo4 { regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; regulator-always-on; }; vdd_ldo5: ldo5 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-min-microamp = <100000>; - regulator-max-microamp = <100000>; regulator-always-on; }; vdd_ldo6: ldo6 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; regulator-always-on; }; vdd_ldo7: ldo7 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; regulator-always-on; }; vdd_ldo8: ldo8 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; regulator-always-on; }; vdd_ld09: ldo9 { regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; + regulator-always-on; }; vdd_ldo10: ldo10 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; - regulator-min-microamp = <300000>; - regulator-max-microamp = <300000>; + regulator-always-on; }; vdd_ldo11: ldo11 { regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; - regulator-min-microamp = <300000>; - regulator-max-microamp = <300000>; regulator-always-on; }; }; @@ -269,4 +239,8 @@ &gpio { status = "okay"; + gpio-line-names = "J29.1", "PMICNTB", "PMICSHDN", "J8.1", "J8.3", + "PCIe_PWREN", "THERM", "UBRDG_RSTN", "PCIe_PERSTN", + "ULPI_RSTN", "J8.2", "UHUB_RSTN", "GEMGXL_RST", "J8.4", + "EN_VDD_SD", "SD_CD"; }; From aa8aa48b4c32fafaf2c393b4a937b0b35668943e Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 14 Aug 2022 21:57:14 +0200 Subject: [PATCH 4/5] cmd/sbi: format KVM version Format the KVM implementation number in a human readable form. With the patch output of the sbi command for Linux 5.19.1 looks like: => sbi SBI 0.3 KVM 5.19.1 Machine: Vendor ID 0 Architecture ID 7005c Implementation ID 7005c Extensions: SBI Base Functionality Timer Extension IPI Extension RFENCE Extension Hart State Management Extension System Reset Extension Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang --- cmd/riscv/sbi.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c index ee11e0f88e4..522f502435b 100644 --- a/cmd/riscv/sbi.c +++ b/cmd/riscv/sbi.c @@ -68,11 +68,21 @@ static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc, ret = sbi_get_impl_version(&vers); if (ret < 0) break; - if (impl_id == 1) + switch (impl_id) { + case 1: /* OpenSBI */ printf("%ld.%ld", vers >> 16, vers & 0xffff); - else + break; + case 3: /* KVM */ + printf("%ld.%ld.%ld", + vers >> 16, + (vers >> 8) & 0xff, + vers & 0xff); + break; + default: printf("0x%lx", vers); + break; + } break; } } From 4a98207b2335b7108e964b831dc92f0333346c87 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 5 Sep 2022 16:40:49 +0200 Subject: [PATCH 5/5] RISC-V: enable CONFIG_SYSRESET_SBI by default System reset via the SRST extension in the SBI should be the default. The driver checks if the extension is available when probing. So there is no risk in enabling it. Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang --- drivers/sysreset/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index a0acffa4b07..03f7fdd5978 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -113,6 +113,7 @@ config SYSRESET_PSCI config SYSRESET_SBI bool "Enable support for SBI System Reset" depends on RISCV_SMODE && SBI_V02 + default y select SYSRESET_CMD_POWEROFF if CMD_POWEROFF help Enable system reset and poweroff via the SBI system reset extension.