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adc: stm32mp13: add support of adc to stm32mp13
Add support of STM32 ADCs to STM32MP13x. This patch introduces stm32_adc_regspec structure, as this is already done in kernel driver, to manage smartly the differences in register set between STMP32MP15 and STM32MP13 ADCs. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
This commit is contained in:
Olivier Moysan
Tom Rini
parent
87b0ab0365
commit
58d718b111
@ -200,6 +200,7 @@ err_aclk_disable:
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static const struct udevice_id stm32_adc_core_ids[] = {
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{ .compatible = "st,stm32h7-adc-core" },
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{ .compatible = "st,stm32mp1-adc-core" },
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{ .compatible = "st,stm32mp13-adc-core" },
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{}
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};
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@ -49,29 +49,68 @@
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/* STM32H7_ADC_SQR1 - bit fields */
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#define STM32H7_SQ1_SHIFT 6
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/* STM32H7_ADC_DIFSEL - bit fields */
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#define STM32H7_DIFSEL_SHIFT 0
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#define STM32H7_DIFSEL_MASK GENMASK(19, 0)
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/* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
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#define STM32H7_BOOST_CLKRATE 20000000UL
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/* STM32MP13 - Registers for each ADC instance */
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#define STM32MP13_ADC_DIFSEL 0xB0
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/* STM32MP13_ADC_CFGR specific bit fields */
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#define STM32MP13_DMAEN BIT(0)
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#define STM32MP13_DMACFG BIT(1)
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/* STM32MP13_ADC_DIFSEL - bit fields */
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#define STM32MP13_DIFSEL_SHIFT 0
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#define STM32MP13_DIFSEL_MASK GENMASK(18, 0)
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#define STM32_ADC_CH_MAX 20 /* max number of channels */
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#define STM32_ADC_TIMEOUT_US 100000
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struct stm32_adc_cfg {
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unsigned int max_channels;
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unsigned int num_bits;
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bool has_vregready;
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};
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struct stm32_adc {
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void __iomem *regs;
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int active_channel;
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const struct stm32_adc_cfg *cfg;
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};
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struct stm32_adc_regs {
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int reg;
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int mask;
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int shift;
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};
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struct stm32_adc_regspec {
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const struct stm32_adc_regs difsel;
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};
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struct stm32_adc_cfg {
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const struct stm32_adc_regspec *regs;
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unsigned int max_channels;
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unsigned int num_bits;
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bool has_vregready;
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bool has_boostmode;
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bool has_linearcal;
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bool has_presel;
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};
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static const struct stm32_adc_regspec stm32h7_adc_regspec = {
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.difsel = { STM32H7_ADC_DIFSEL, STM32H7_DIFSEL_MASK },
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};
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static const struct stm32_adc_regspec stm32mp13_adc_regspec = {
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.difsel = { STM32MP13_ADC_DIFSEL, STM32MP13_DIFSEL_MASK },
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};
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static void stm32_adc_enter_pwr_down(struct udevice *dev)
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{
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struct stm32_adc *adc = dev_get_priv(dev);
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clrbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_BOOST);
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if (adc->cfg->has_boostmode)
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clrbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_BOOST);
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/* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */
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setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_DEEPPWD);
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}
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@ -90,8 +129,7 @@ static int stm32_adc_exit_pwr_down(struct udevice *dev)
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/* Exit deep power down, then enable ADC voltage regulator */
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clrbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_DEEPPWD);
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setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADVREGEN);
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if (common->rate > STM32H7_BOOST_CLKRATE)
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if (adc->cfg->has_boostmode && common->rate > STM32H7_BOOST_CLKRATE)
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setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_BOOST);
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/* Wait for startup time */
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@ -134,7 +172,7 @@ static int stm32_adc_start_channel(struct udevice *dev, int channel)
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return ret;
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/* Only use single ended channels */
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writel(0, adc->regs + STM32H7_ADC_DIFSEL);
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clrbits_le32(adc->regs + adc->cfg->regs->difsel.reg, adc->cfg->regs->difsel.mask);
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/* Enable ADC, Poll for ADRDY to be set (after adc startup time) */
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setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADEN);
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@ -147,7 +185,8 @@ static int stm32_adc_start_channel(struct udevice *dev, int channel)
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}
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/* Preselect channels */
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writel(uc_pdata->channel_mask, adc->regs + STM32H7_ADC_PCSEL);
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if (adc->cfg->has_presel)
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writel(uc_pdata->channel_mask, adc->regs + STM32H7_ADC_PCSEL);
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/* Set sampling time to max value by default */
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writel(0xffffffff, adc->regs + STM32H7_ADC_SMPR1);
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@ -156,9 +195,11 @@ static int stm32_adc_start_channel(struct udevice *dev, int channel)
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/* Program regular sequence: chan in SQ1 & len = 0 for one channel */
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writel(channel << STM32H7_SQ1_SHIFT, adc->regs + STM32H7_ADC_SQR1);
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/* Trigger detection disabled (conversion can be launched in SW) */
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clrbits_le32(adc->regs + STM32H7_ADC_CFGR, STM32H7_EXTEN |
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STM32H7_DMNGT);
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/*
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* Trigger detection disabled (conversion can be launched in SW)
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* STM32H7_DMNGT is equivalent to STM32MP13_DMAEN & STM32MP13_DMACFG
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*/
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clrbits_le32(adc->regs + STM32H7_ADC_CFGR, STM32H7_EXTEN | STM32H7_DMNGT);
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adc->active_channel = channel;
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return 0;
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@ -206,7 +247,7 @@ static int stm32_adc_selfcalib(struct udevice *dev)
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{
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struct stm32_adc *adc = dev_get_priv(dev);
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int ret;
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u32 val;
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u32 val, mask;
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/*
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* Select calibration mode:
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@ -231,7 +272,10 @@ static int stm32_adc_selfcalib(struct udevice *dev)
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* - Linearity calibration (needs to be done only once for single/diff)
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* will run simultaneously with offset calibration.
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*/
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setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADCALDIF | STM32H7_ADCALLIN);
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mask = STM32H7_ADCALDIF;
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if (adc->cfg->has_linearcal)
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mask |= STM32H7_ADCALLIN;
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setbits_le32(adc->regs + STM32H7_ADC_CR, mask);
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/* Start calibration, then wait for completion */
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setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADCAL);
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@ -394,14 +438,28 @@ static const struct adc_ops stm32_adc_ops = {
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};
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static const struct stm32_adc_cfg stm32h7_adc_cfg = {
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.regs = &stm32h7_adc_regspec,
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.num_bits = 16,
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.max_channels = STM32_ADC_CH_MAX,
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.has_boostmode = true,
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.has_linearcal = true,
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.has_presel = true,
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};
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static const struct stm32_adc_cfg stm32mp1_adc_cfg = {
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.regs = &stm32h7_adc_regspec,
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.num_bits = 16,
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.max_channels = STM32_ADC_CH_MAX,
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.has_vregready = true,
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.has_boostmode = true,
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.has_linearcal = true,
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.has_presel = true,
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};
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static const struct stm32_adc_cfg stm32mp13_adc_cfg = {
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.regs = &stm32mp13_adc_regspec,
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.num_bits = 12,
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.max_channels = STM32_ADC_CH_MAX - 1,
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};
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static const struct udevice_id stm32_adc_ids[] = {
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@ -409,6 +467,8 @@ static const struct udevice_id stm32_adc_ids[] = {
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.data = (ulong)&stm32h7_adc_cfg },
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{ .compatible = "st,stm32mp1-adc",
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.data = (ulong)&stm32mp1_adc_cfg },
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{ .compatible = "st,stm32mp13-adc",
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.data = (ulong)&stm32mp13_adc_cfg },
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{}
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};
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