diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
index 2bbc4a49418..a94a571df5e 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -3,52 +3,7 @@
  * Copyright 2021 Collabora Ltd.
  */
 
-#include "imx8mn-u-boot.dtsi"
-
-&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
-	bootph-pre-ram;
-};
-
-&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
-	bootph-pre-ram;
-};
-
-&eeprom_som {
-	#address-cells = <1>;
-	#size-cells = <1>;
-	eth_mac_address: eth-mac-address@19 {
-		reg = <0x19 0x06>;
-	};
-};
-
-&fec1 {
-	nvmem-cells = <&eth_mac_address>;
-	nvmem-cell-names = "mac-address";
-};
-
-&gpio1 {
-	bootph-pre-ram;
-};
-
-&gpio2 {
-	bootph-pre-ram;
-};
-
-&gpio4 {
-	bootph-pre-ram;
-};
-
-&i2c1 {
-	bootph-all;
-};
-
-&pinctrl_i2c1 {
-	bootph-all;
-};
-
-&pinctrl_pmic {
-	bootph-pre-ram;
-};
+#include "imx8mn-var-som-u-boot.dtsi"
 
 &pinctrl_reg_usdhc2_vmmc {
 	bootph-pre-ram;
@@ -62,14 +17,6 @@
 	bootph-pre-ram;
 };
 
-&pinctrl_usdhc3 {
-	bootph-pre-ram;
-};
-
-&pinctrl_wdog {
-	bootph-pre-ram;
-};
-
 &uart4 {
 	bootph-pre-ram;
 };
@@ -77,11 +24,3 @@
 &usdhc2 {
 	bootph-pre-ram;
 };
-
-&usdhc3 {
-	bootph-pre-ram;
-};
-
-&eeprom_som {
-	bootph-all;
-};
diff --git a/arch/arm/dts/imx8mn-var-som-u-boot.dtsi b/arch/arm/dts/imx8mn-var-som-u-boot.dtsi
new file mode 100644
index 00000000000..c27ad08377e
--- /dev/null
+++ b/arch/arm/dts/imx8mn-var-som-u-boot.dtsi
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 Dimonoff
+ */
+
+#include "imx8mn-u-boot.dtsi"
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
+	bootph-pre-ram;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
+	bootph-pre-ram;
+};
+
+&eeprom_som {
+	bootph-all;
+	#address-cells = <1>;
+	#size-cells = <1>;
+	eth_mac_address: eth-mac-address@19 {
+		reg = <0x19 0x06>;
+	};
+};
+
+&fec1 {
+	nvmem-cells = <&eth_mac_address>;
+	nvmem-cell-names = "mac-address";
+};
+
+&gpio1 {
+	bootph-pre-ram;
+};
+
+&gpio2 {
+	bootph-pre-ram;
+};
+
+&gpio4 {
+	bootph-pre-ram;
+};
+
+&i2c1 {
+	bootph-all;
+};
+
+&usdhc3 {
+	bootph-pre-ram;
+};
+
+&pinctrl_i2c1 {
+	bootph-all;
+};
+
+&pinctrl_wdog {
+	bootph-pre-ram;
+};
+
+&pinctrl_pmic {
+	bootph-pre-ram;
+};
+
+&pinctrl_usdhc3 {
+	bootph-pre-ram;
+};