mirrors/u-boot
1
0
Fork 0
mirror of https://source.denx.de/u-boot/u-boot.git synced 2025-10-31 16:31:25 +01:00
Code Issues Actions Packages Projects Releases Wiki Activity

Merge branch 'next-sync' of git://git.denx.de/u-boot-arm into next

Browse Source
This commit is contained in:
Wolfgang Denk 2009-12-01 12:10:51 +01:00
commit 57bf140ac6
101 changed files with 5258 additions and 870 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
MAINTAINERS
View File

@ -545,6 +545,10 @@ Rick Bronson <rick@efn.org>
AT91RM9200DK at91rm9200
Po-Yu Chuang <ratbert@faraday-tech.com>
a320evb FA526 (ARM920T-like) (a320 SoC)
George G. Davis <gdavis@mvista.com>
assabet SA1100
@ -714,6 +718,10 @@ Andrea Scian <andrea.scian@dave-tech.it>
B2 ARM7TDMI (S3C44B0X)
Nick Thompson <nick.thompson@gefanuc.com>
da830evm ARM926EJS (DA830/OMAP-L137)
Albin Tonnerre <albin.tonnerre@free-electrons.com>
sbc35_a9g20 ARM926EJS (AT91SAM9G20 SoC)

2
MAKEALL
View File

@ -539,6 +539,7 @@ LIST_ARM7=" \
#########################################################################
LIST_ARM9=" \
a320evb \
ap920t \
ap922_XA10 \
ap926ejs \
@ -549,6 +550,7 @@ LIST_ARM9=" \
cp926ejs \
cp946es \
cp966 \
da830evm \
imx27lite \
lpd7a400 \
mv88f6281gtw_ge \

6
Makefile
View File

@ -2696,6 +2696,9 @@ shannon_config : unconfig
## ARM92xT Systems
#########################################################################
a320evb_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t a320evb faraday a320
#########################################################################
## Atmel AT91RM9200 Systems
#########################################################################
@ -2930,6 +2933,9 @@ cp922_XA10_config \
cp1026_config: unconfig
@board/armltd/integrator/split_by_variant.sh cp $@
da830evm_config: unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs da830evm davinci davinci
davinci_dvevm_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs dvevm davinci davinci

10
board/Marvell/sheevaplug/kwbimage.cfg
View File

@ -74,11 +74,11 @@ DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
# bit12-11: TW2W
# bit31-13: zero required
DATA 0xFFD01410 0x00000099 # DDR Address Control
# bit1-0: 01, Cs0width=x16
# bit3-2: 10, Cs0size=512Mb
# bit5-4: 01, Cs1width=x16
# bit7-6: 10, Cs1size=512Mb
DATA 0xFFD01410 0x000000cc # DDR Address Control
# bit1-0: 00, Cs0width=x8
# bit3-2: 11, Cs0size=1Gb
# bit5-4: 00, Cs1width=x8
# bit7-6: 11, Cs1size=1Gb
# bit9-8: 00, Cs2width=nonexistent
# bit11-10: 00, Cs2size =nonexistent
# bit13-12: 00, Cs3width=nonexistent

48
board/davinci/common/misc.c
View File

@ -1,6 +1,7 @@
/*
* Miscelaneous DaVinci functions.
*
* Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com>
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
* Copyright (C) 2008 Lyrtech <www.lyrtech.com>
* Copyright (C) 2004 Texas Instruments.
@ -27,7 +28,8 @@
#include <i2c.h>
#include <net.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
#include "misc.h"
DECLARE_GLOBAL_DATA_PTR;
@ -109,3 +111,47 @@ void dv_configure_mac_address(uint8_t *rom_enetaddr)
}
#endif /* DAVINCI_EMAC */
/*
* Change the setting of a pin multiplexer field.
*
* Takes an array of pinmux settings similar to:
*
* struct pinmux_config uart_pins[] = {
* { &davinci_syscfg_regs->pinmux[8], 2, 7 },
* { &davinci_syscfg_regs->pinmux[9], 2, 0 }
* };
*
* Stepping through the array, each pinmux[n] register has the given value
* set in the pin mux field specified.
*
* The number of pins in the array must be passed (ARRAY_SIZE can provide
* this value conveniently).
*
* Returns 0 if all field numbers and values are in the correct range,
* else returns -1.
*/
int davinci_configure_pin_mux(const struct pinmux_config *pins,
const int n_pins)
{
int i;
/* check for invalid pinmux values */
for (i = 0; i < n_pins; i++) {
if (pins[i].field >= PIN_MUX_NUM_FIELDS ||
(pins[i].value & ~PIN_MUX_FIELD_MASK) != 0)
return -1;
}
/* configure the pinmuxes */
for (i = 0; i < n_pins; i++) {
const int offset = pins[i].field * PIN_MUX_FIELD_SIZE;
const unsigned int value = pins[i].value << offset;
const unsigned int mask = PIN_MUX_FIELD_MASK << offset;
const dv_reg *mux = pins[i].mux;
writel(value | (readl(mux) & (~mask)), mux);
}
return 0;
}

12
board/davinci/common/misc.h
View File

@ -22,8 +22,20 @@
#ifndef __MISC_H
#define __MISC_H
/* pin muxer definitions */
#define PIN_MUX_NUM_FIELDS 8 /* Per register */
#define PIN_MUX_FIELD_SIZE 4 /* n in bits */
#define PIN_MUX_FIELD_MASK ((1 << PIN_MUX_FIELD_SIZE) - 1)
/* pin definition */
struct pinmux_config {
dv_reg *mux; /* Address of mux register */
unsigned char value; /* Value to set in field */
unsigned char field; /* field number */
};
int dvevm_read_mac_address(uint8_t *buf);
void dv_configure_mac_address(uint8_t *rom_enetaddr);
int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins);
#endif /* __MISC_H */

51
board/davinci/da830evm/Makefile Normal file
View File

@ -0,0 +1,51 @@
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := da830evm.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak *~ .depend
#########################################################################
# This is for $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

43
board/davinci/da830evm/config.mk Normal file
View File

@ -0,0 +1,43 @@
#
# (C) Copyright 2008, Texas Instruments, Inc. http://www.ti.com/
#
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
#
# (C) Copyright 2002
# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# Texas Instruments DA8xx EVM board (ARM925EJS) cpu
# see http://www.ti.com/ for more information on Texas Instruments
#
# DA8xx EVM has 1 bank of 64 MB SDRAM (2 16Meg x16 chips).
# Physical Address:
# C000'0000 to C400'0000
#
# Linux-Kernel is expected to be at C000'8000, entry C000'8000
# (mem base + reserved)
#
# we load ourself to C108 '0000
#Provide at least 16MB spacing between us and the Linux Kernel image
TEXT_BASE = 0xC1080000

127
board/davinci/da830evm/da830evm.c Normal file
View File

@ -0,0 +1,127 @@
/*
* Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
*
* Base on code from TI. Original Notices follow:
*
* (C) Copyright 2008, Texas Instruments, Inc. http://www.ti.com/
*
* Modified for DA8xx EVM.
*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Parts are shamelessly stolen from various TI sources, original copyright
* follows:
* -----------------------------------------------------------------
*
* Copyright (C) 2004 Texas Instruments.
*
* ----------------------------------------------------------------------------
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
* ----------------------------------------------------------------------------
*/
#include <common.h>
#include <i2c.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
#include "../common/misc.h"
DECLARE_GLOBAL_DATA_PTR;
#define pinmux &davinci_syscfg_regs->pinmux
#ifdef CONFIG_SPI_FLASH
/* SPI0 pin muxer settings */
const struct pinmux_config spi0_pins[] = {
{ pinmux[7], 1, 3 },
{ pinmux[7], 1, 4 },
{ pinmux[7], 1, 5 },
{ pinmux[7], 1, 6 },
{ pinmux[7], 1, 7 }
};
#endif
/* UART pin muxer settings */
const struct pinmux_config uart_pins[] = {
{ pinmux[8], 2, 7 },
{ pinmux[9], 2, 0 }
};
/* I2C pin muxer settings */
const struct pinmux_config i2c_pins[] = {
{ pinmux[9], 2, 3 },
{ pinmux[9], 2, 4 }
};
int board_init(void)
{
#ifndef CONFIG_USE_IRQ
/*
* Mask all IRQs by clearing the global enable and setting
* the enable clear for all the 90 interrupts.
*/
writel(0, &davinci_aintc_regs->ger);
writel(0, &davinci_aintc_regs->hier);
writel(0xffffffff, &davinci_aintc_regs->ecr1);
writel(0xffffffff, &davinci_aintc_regs->ecr2);
writel(0xffffffff, &davinci_aintc_regs->ecr3);
#endif
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA830_EVM;
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
/*
* Power on required peripherals
* ARM does not have access by default to PSC0 and PSC1
* assuming here that the DSP bootloader has set the IOPU
* such that PSC access is available to ARM
*/
lpsc_on(DAVINCI_LPSC_AEMIF); /* NAND, NOR */
lpsc_on(DAVINCI_LPSC_SPI0); /* Serial Flash */
lpsc_on(DAVINCI_LPSC_EMAC); /* image download */
lpsc_on(DAVINCI_LPSC_UART2); /* console */
lpsc_on(DAVINCI_LPSC_GPIO);
/* setup the SUSPSRC for ARM to control emulation suspend */
writel(readl(&davinci_syscfg_regs->suspsrc) &
~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
DAVINCI_SYSCFG_SUSPSRC_SPI0 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
DAVINCI_SYSCFG_SUSPSRC_UART2),
&davinci_syscfg_regs->suspsrc);
#ifdef CONFIG_SPI_FLASH
if (davinci_configure_pin_mux(spi0_pins, ARRAY_SIZE(spi0_pins)) != 0)
return 1;
#endif
if (davinci_configure_pin_mux(uart_pins, ARRAY_SIZE(uart_pins)) != 0)
return 1;
if (davinci_configure_pin_mux(i2c_pins, ARRAY_SIZE(i2c_pins)) != 0)
return 1;
/* enable the console UART */
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
DAVINCI_UART_PWREMU_MGMT_UTRST),
&davinci_uart2_ctrl_regs->pwremu_mgmt);
return(0);
}

11
board/davinci/dm6467evm/dm6467evm.c
View File

@ -18,6 +18,8 @@
#include <common.h>
#include <asm/io.h>
#include <nand.h>
#include <asm/arch/nand_defs.h>
DECLARE_GLOBAL_DATA_PTR;
@ -28,3 +30,12 @@ int board_init(void)
return 0;
}
#ifdef CONFIG_NAND_DAVINCI
int board_nand_init(struct nand_chip *nand)
{
davinci_nand_init(nand);
return 0;
}
#endif

51
board/faraday/a320evb/Makefile Normal file
View File

@ -0,0 +1,51 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := a320evb.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

73
board/faraday/a320evb/a320evb.c Normal file
View File

@ -0,0 +1,73 @@
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/ftsmc020.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Miscellaneous platform dependent initialisations
*/
int board_init(void)
{
gd->bd->bi_arch_number = MACH_TYPE_FARADAY;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
ftsmc020_init(); /* initialize Flash */
return 0;
}
int dram_init(void)
{
unsigned long sdram_base = PHYS_SDRAM_1;
unsigned long expected_size = PHYS_SDRAM_1_SIZE;
unsigned long actual_size;
actual_size = get_ram_size((void *)sdram_base, expected_size);
gd->bd->bi_dram[0].start = sdram_base;
gd->bd->bi_dram[0].size = actual_size;
if (expected_size != actual_size)
printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
actual_size >> 20, expected_size >> 20);
return 0;
}
int board_eth_init(bd_t *bd)
{
return ftmac100_initialize(bd);
}
ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
{
if (banknum == 0) { /* non-CFI boot flash */
info->portwidth = FLASH_CFI_8BIT;
info->chipwidth = FLASH_CFI_BY8;
info->interface = FLASH_CFI_X8;
return 1;
} else
return 0;
}

35
board/faraday/a320evb/config.mk Normal file
View File

@ -0,0 +1,35 @@
#
# (C) Copyright 2009 Faraday Technology
# Po-Yu Chuang <ratbert@faraday-tech.com>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# Faraday A320 board with FA526/FA626TE/ARM926EJ-S cpus
#
# see http://www.faraday-tech.com/ for more information
# A320 has 1 bank of 64 MB DRAM
#
# 1000'0000 to 1400'0000
#
# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
#
# we load ourself to 13f8'0000
#
# download area is 1200'0000
TEXT_BASE = 0x13f80000

118
board/faraday/a320evb/lowlevel_init.S Normal file
View File

@ -0,0 +1,118 @@
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <config.h>
#include <version.h>
#include <asm/macro.h>
#include <asm/arch/ftsdmc020.h>
/*
* parameters for the SDRAM controller
*/
#define TP0_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP0)
#define TP1_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP1)
#define CR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_CR)
#define B0_BSR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_BANK0_BSR)
#define ACR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_ACR)
#define TP0_D CONFIG_SYS_FTSDMC020_TP0
#define TP1_D CONFIG_SYS_FTSDMC020_TP1
#define CR_D1 FTSDMC020_CR_IPREC
#define CR_D2 FTSDMC020_CR_ISMR
#define CR_D3 FTSDMC020_CR_IREF
#define B0_BSR_D (CONFIG_SYS_FTSDMC020_BANK0_BSR | \
FTSDMC020_BANK_BASE(PHYS_SDRAM_1))
#define ACR_D FTSDMC020_ACR_TOC(0x18)
/*
* numeric 7 segment display
*/
.macro led, num
write32 CONFIG_DEBUG_LED, \num
.endm
/*
* Waiting for SDRAM to set up
*/
.macro wait_sdram
ldr r0, =CONFIG_FTSDMC020_BASE
1:
ldr r1, [r0, #FTSDMC020_OFFSET_CR]
cmp r1, #0
bne 1b
.endm
.globl lowlevel_init
lowlevel_init:
mov r11, lr
led 0x0
bl init_sdmc
led 0x1
/* everything is fine now */
mov lr, r11
mov pc, lr
/*
* memory initialization
*/
init_sdmc:
led 0x10
/* set SDRAM register */
write32 TP0_A, TP0_D
led 0x11
write32 TP1_A, TP1_D
led 0x12
/* set to precharge */
write32 CR_A, CR_D1
led 0x13
wait_sdram
led 0x14
/* set mode register */
write32 CR_A, CR_D2
led 0x15
wait_sdram
led 0x16
/* set to refresh */
write32 CR_A, CR_D3
led 0x17
wait_sdram
led 0x18
write32 B0_BSR_A, B0_BSR_D
led 0x19
write32 ACR_A, ACR_D
led 0x1a
mov pc, lr

2
board/mpl/vcma9/vcma9.c
View File

@ -27,7 +27,7 @@
#include <common.h>
#include <netdev.h>
#include <s3c2410.h>
#include <asm/arch/s3c24x0_cpu.h>
#include <stdio_dev.h>
#include <i2c.h>

16
board/mpl/vcma9/vcma9.h
View File

@ -25,7 +25,7 @@
* Global routines used for VCMA9
*****************************************************************************/
#include <s3c2410.h>
#include <asm/arch/s3c24x0_cpu.h>
extern int mem_test(unsigned long start, unsigned long ramsize,int mode);
@ -118,13 +118,13 @@ static inline u32 NF_Read_ECC(void)
/* VCMA9 PLD regsiters */
typedef struct {
S3C24X0_REG8 ID;
S3C24X0_REG8 NIC;
S3C24X0_REG8 CAN;
S3C24X0_REG8 MISC;
S3C24X0_REG8 GPCD;
S3C24X0_REG8 BOARD;
S3C24X0_REG8 SDRAM;
u8 ID;
u8 NIC;
u8 CAN;
u8 MISC;
u8 GPCD;
u8 BOARD;
u8 SDRAM;
} /*__attribute__((__packed__))*/ VCMA9_PLD;
#define VCMA9_PLD_BASE 0x2C000100

3
board/pandora/pandora.h
View File

@ -219,7 +219,8 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)) /*GPIO_147,*/\
/*UART2_RX*/\
/*Serial Interface (Peripheral boot, Linux console, on AV connector)*/\
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX*/\
/*RX pulled up to avoid noise when nothing is connected to serial port*/\
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | EN | M0)) /*UART3_RX*/\
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX*/\
/*LEDs (Controlled by OMAP)*/\
MUX_VAL(CP(MMC1_DAT6), (IDIS | PTD | DIS | M4)) /*GPIO_128*/\

2
board/samsung/smdk2400/smdk2400.c
View File

@ -27,7 +27,7 @@
#include <common.h>
#include <netdev.h>
#include <s3c2400.h>
#include <asm/arch/s3c24x0_cpu.h>
DECLARE_GLOBAL_DATA_PTR;

2
board/samsung/smdk2410/smdk2410.c
View File

@ -27,7 +27,7 @@
#include <common.h>
#include <netdev.h>
#include <s3c2410.h>
#include <asm/arch/s3c24x0_cpu.h>
DECLARE_GLOBAL_DATA_PTR;

2
board/samsung/smdk6400/lowlevel_init.S
View File

@ -34,7 +34,7 @@
#include <config.h>
#include <version.h>
#include <s3c6400.h>
#include <asm/arch/s3c6400.h>
#ifdef CONFIG_SERIAL1
#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET)

2
board/samsung/smdk6400/smdk6400.c
View File

@ -30,7 +30,7 @@
#include <common.h>
#include <netdev.h>
#include <s3c6400.h>
#include <asm/arch/s3c6400.h>
/* ------------------------------------------------------------------------- */
#define CS8900_Tacs 0x0 /* 0clk address set-up */

2
board/sbc2410x/sbc2410x.c
View File

@ -30,7 +30,7 @@
#include <common.h>
#include <netdev.h>
#include <s3c2410.h>
#include <asm/arch/s3c24x0_cpu.h>
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand.h>

2
board/trab/cmd_trab.c
View File

@ -25,7 +25,7 @@
#include <common.h>
#include <command.h>
#include <s3c2400.h>
#include <asm/arch/s3c24x0_cpu.h>
#include <rtc.h>
/*

2
board/trab/rs485.c
View File

@ -22,7 +22,7 @@
*/
#include <common.h>
#include <s3c2400.h>
#include <asm/arch/s3c24x0_cpu.h>
#include "rs485.h"
static void rs485_setbrg (void);

2
board/trab/rs485.h
View File

@ -24,7 +24,7 @@
#ifndef _RS485_H_
#define _RS485_H_
#include <s3c2400.h>
#include <asm/arch/s3c24x0_cpu.h>
int rs485_init (void);
int rs485_getc (void);

2
board/trab/trab.c
View File

@ -26,7 +26,7 @@
#include <common.h>
#include <netdev.h>
#include <malloc.h>
#include <s3c2400.h>
#include <asm/arch/s3c24x0_cpu.h>
#include <command.h>
DECLARE_GLOBAL_DATA_PTR;

2
board/trab/trab_fkt.c
View File

@ -26,7 +26,7 @@
#include <common.h>
#include <exports.h>
#include <timestamp.h>
#include <s3c2400.h>
#include <asm/arch/s3c24x0_cpu.h>
#include "tsc2000.h"
#include "rs485.h"

2
board/trab/tsc2000.c
View File

@ -26,7 +26,7 @@
*/
#include <common.h>
#include <s3c2400.h>
#include <asm/arch/s3c24x0_cpu.h>
#include <asm/io.h>
#include <div64.h>
#include "tsc2000.h"

2
board/trab/vfd.c
View File

@ -37,7 +37,7 @@
#include <stdarg.h>
#include <linux/types.h>
#include <stdio_dev.h>
#include <s3c2400.h>
#include <asm/arch/s3c24x0_cpu.h>
DECLARE_GLOBAL_DATA_PTR;

2
cpu/arm1176/cpu.c
View File

@ -33,7 +33,7 @@
#include <common.h>
#include <command.h>
#include <s3c6400.h>
#include <asm/arch/s3c6400.h>
#include <asm/system.h>
static void cache_flush (void);

2
cpu/arm1176/s3c64xx/cpu_init.S
View File

@ -24,7 +24,7 @@
*/
#include <config.h>
#include <s3c6400.h>
#include <asm/arch/s3c6400.h>
.globl mem_ctrl_asm_init
mem_ctrl_asm_init:

2
cpu/arm1176/s3c64xx/reset.S
View File

@ -21,7 +21,7 @@
* MA 02111-1307 USA
*/
#include <s3c6400.h>
#include <asm/arch/s3c6400.h>
.globl reset_cpu
reset_cpu:

2
cpu/arm1176/s3c64xx/speed.c
View File

@ -31,7 +31,7 @@
*/
#include <common.h>
#include <s3c6400.h>
#include <asm/arch/s3c6400.h>
#define APLL 0
#define MPLL 1

2
cpu/arm1176/s3c64xx/timer.c
View File

@ -40,7 +40,7 @@
#include <common.h>
#include <asm/proc-armv/ptrace.h>
#include <s3c6400.h>
#include <asm/arch/s3c6400.h>
#include <div64.h>
static ulong timer_load_val;

9
cpu/arm1176/start.S
View File

@ -35,7 +35,7 @@
#ifdef CONFIG_ENABLE_MMU
#include <asm/proc/domain.h>
#endif
#include <s3c6400.h>
#include <asm/arch/s3c6400.h>
#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
@ -241,16 +241,11 @@ mmu_enable:
skip_hw_init:
/* Set up the stack */
stack_setup:
#ifdef CONFIG_MEMORY_UPPER_CODE
ldr sp, =(CONFIG_SYS_UBOOT_BASE + CONFIG_SYS_UBOOT_SIZE - 0xc)
#else
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
ldr r0, =CONFIG_SYS_UBOOT_BASE /* base of copy in DRAM */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
sub sp, r0, #12 /* leave 3 words for abort-stack */
#endif
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */

47
cpu/arm920t/a320/Makefile Normal file
View File

@ -0,0 +1,47 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
SOBJS += reset.o
COBJS += timer.o
COBJS += ftsmc020.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

51
cpu/arm920t/a320/ftsmc020.c Normal file
View File

@ -0,0 +1,51 @@
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/arch/ftsmc020.h>
struct ftsmc020_config {
unsigned int config;
unsigned int timing;
};
static struct ftsmc020_config config[] = CONFIG_SYS_FTSMC020_CONFIGS;
static struct ftsmc020 *smc = (struct ftsmc020 *)CONFIG_FTSMC020_BASE;
static void ftsmc020_setup_bank(unsigned int bank, struct ftsmc020_config *cfg)
{
if (bank > 3) {
printf("bank # %u invalid\n", bank);
return;
}
writel(cfg->config, &smc->bank[bank].cr);
writel(cfg->timing, &smc->bank[bank].tpr);
}
void ftsmc020_init(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(config); i++)
ftsmc020_setup_bank(i, &config[i]);
}

22
cpu/arm920t/a320/reset.S Normal file
View File

@ -0,0 +1,22 @@
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
.global reset_cpu
reset_cpu:
b reset_cpu

193
cpu/arm920t/a320/timer.c Normal file
View File

@ -0,0 +1,193 @@
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/ftpmu010.h>
#include <asm/arch/fttmr010.h>
static ulong timestamp;
static ulong lastdec;
static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
#define TIMER_CLOCK 32768
#define TIMER_LOAD_VAL 0xffffffff
int timer_init(void)
{
unsigned int oscc;
unsigned int cr;
debug("%s()\n", __func__);
/* disable timers */
writel(0, &tmr->cr);
/*
* use 32768Hz oscillator for RTC, WDT, TIMER
*/
/* enable the 32768Hz oscillator */
oscc = readl(&pmu->OSCC);
oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI);
writel(oscc, &pmu->OSCC);
/* wait until ready */
while (!(readl(&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE))
;
/* select 32768Hz oscillator */
oscc = readl(&pmu->OSCC);
oscc |= FTPMU010_OSCC_OSCL_RTCLSEL;
writel(oscc, &pmu->OSCC);
/* setup timer */
writel(TIMER_LOAD_VAL, &tmr->timer3_load);
writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
writel(0, &tmr->timer3_match1);
writel(0, &tmr->timer3_match2);
/* we don't want timer to issue interrupts */
writel(FTTMR010_TM3_MATCH1 |
FTTMR010_TM3_MATCH2 |
FTTMR010_TM3_OVERFLOW,
&tmr->interrupt_mask);
cr = readl(&tmr->cr);
cr |= FTTMR010_TM3_CLOCK; /* use external clock */
cr |= FTTMR010_TM3_ENABLE;
writel(cr, &tmr->cr);
/* init the timestamp and lastdec value */
reset_timer_masked();
return 0;
}
/*
* timer without interrupts
*/
/*
* reset time
*/
void reset_timer_masked(void)
{
/* capure current decrementer value time */
lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
timestamp = 0; /* start "advancing" time stamp from 0 */
debug("%s(): lastdec = %lx\n", __func__, lastdec);
}
void reset_timer(void)
{
debug("%s()\n", __func__);
reset_timer_masked();
}
/*
* return timer ticks
*/
ulong get_timer_masked(void)
{
/* current tick value */
ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
if (lastdec >= now) {
/*
* normal mode (non roll)
* move stamp fordward with absoulte diff ticks
*/
timestamp += lastdec - now;
} else {
/*
* we have overflow of the count down timer
*
* nts = ts + ld + (TLV - now)
* ts=old stamp, ld=time that passed before passing through -1
* (TLV-now) amount of time after passing though -1
* nts = new "advancing time stamp"...it could also roll and
* cause problems.
*/
timestamp += lastdec + TIMER_LOAD_VAL - now;
}
lastdec = now;
debug("%s() returns %lx\n", __func__, timestamp);
return timestamp;
}
/*
* return difference between timer ticks and base
*/
ulong get_timer(ulong base)
{
debug("%s(%lx)\n", __func__, base);
return get_timer_masked() - base;
}
void set_timer(ulong t)
{
debug("%s(%lx)\n", __func__, t);
timestamp = t;
}
/* delay x useconds AND perserve advance timstamp value */
void udelay(unsigned long usec)
{
long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
unsigned long now, last = readl(&tmr->timer3_counter);
debug("%s(%lu)\n", __func__, usec);
while (tmo > 0) {
now = readl(&tmr->timer3_counter);
if (now > last) /* count down timer overflow */
tmo -= TIMER_LOAD_VAL + last - now;
else
tmo -= last - now;
last = now;
}
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
debug("%s()\n", __func__);
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
debug("%s()\n", __func__);
return CONFIG_SYS_HZ;
}

6
cpu/arm920t/s3c24x0/interrupts.c
View File

@ -31,11 +31,7 @@
#include <common.h>
#if defined(CONFIG_S3C2400)
#include <s3c2400.h>
#elif defined(CONFIG_S3C2410)
#include <s3c2410.h>
#endif
#include <asm/arch/s3c24x0_cpu.h>
#include <asm/proc-armv/ptrace.h>
void do_irq (struct pt_regs *pt_regs)

13
cpu/arm920t/s3c24x0/speed.c
View File

@ -30,15 +30,10 @@
*/
#include <common.h>
#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
#ifdef CONFIG_S3C24X0
#include <asm/io.h>
#if defined(CONFIG_S3C2400)
#include <s3c2400.h>
#elif defined(CONFIG_S3C2410)
#include <s3c2410.h>
#endif
#include <asm/arch/s3c24x0_cpu.h>
#define MPLL 0
#define UPLL 1
@ -100,6 +95,4 @@ ulong get_UCLK(void)
return get_PLLCLK(UPLL);
}
#endif /* defined(CONFIG_S3C2400) ||
defined (CONFIG_S3C2410) ||
defined (CONFIG_TRAB) */
#endif /* CONFIG_S3C24X0 */

15
cpu/arm920t/s3c24x0/timer.c
View File

@ -30,17 +30,10 @@
*/
#include <common.h>
#if defined(CONFIG_S3C2400) || \
defined(CONFIG_S3C2410) || \
defined(CONFIG_TRAB)
#ifdef CONFIG_S3C24X0
#include <asm/io.h>
#if defined(CONFIG_S3C2400)
#include <s3c2400.h>
#elif defined(CONFIG_S3C2410)
#include <s3c2410.h>
#endif
#include <asm/arch/s3c24x0_cpu.h>
int timer_load_val = 0;
static ulong timer_clk;
@ -225,6 +218,4 @@ void reset_cpu(ulong ignored)
/*NOTREACHED*/
}
#endif /* defined(CONFIG_S3C2400) ||
defined (CONFIG_S3C2410) ||
defined (CONFIG_TRAB) */
#endif /* CONFIG_S3C24X0 */

17
cpu/arm920t/s3c24x0/usb.c
View File

@ -23,15 +23,11 @@
#include <common.h>
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
# if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
#if defined(CONFIG_S3C2400)
# include <s3c2400.h>
#elif defined(CONFIG_S3C2410)
# include <s3c2410.h>
#endif
#if defined(CONFIG_USB_OHCI_NEW) && \
defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
defined(CONFIG_S3C24X0)
#include <asm/arch/s3c24x0_cpu.h>
#include <asm/io.h>
int usb_cpu_init(void)
@ -70,5 +66,6 @@ int usb_cpu_init_fail(void)
return 0;
}
# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */
#endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
#endif /* defined(CONFIG_USB_OHCI_NEW) && \
defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
defined(CONFIG_S3C24X0) */

11
cpu/arm920t/s3c24x0/usb_ohci.c
View File

@ -36,14 +36,9 @@
#include <common.h>
/* #include <pci.h> no PCI on the S3C24X0 */
#ifdef CONFIG_USB_OHCI
#if defined(CONFIG_S3C2400)
#include <s3c2400.h>
#elif defined(CONFIG_S3C2410)
#include <s3c2410.h>
#endif
#if defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0)
#include <asm/arch/s3c24x0_cpu.h>
#include <asm/io.h>
#include <malloc.h>
#include <usb.h>
@ -1757,4 +1752,4 @@ int usb_lowlevel_stop(void)
return 0;
}
#endif /* CONFIG_USB_OHCI */
#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0) */

4
cpu/arm920t/start.S
View File

@ -131,7 +131,7 @@ copyex:
bne copyex
#endif
#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
#ifdef CONFIG_S3C24X0
/* turn off the watchdog */
# if defined(CONFIG_S3C2400)
@ -166,7 +166,7 @@ copyex:
ldr r0, =CLKDIVN
mov r1, #3
str r1, [r0]
#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */
#endif /* CONFIG_S3C24X0 */
/*
* we do sys-critical inits only at reboot,

50
cpu/arm926ejs/davinci/cpu.c
View File

@ -23,7 +23,7 @@
#include <common.h>
#include <netdev.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
/* offsets from PLL controller base */
#define PLLC_PLLCTL 0x100
@ -60,6 +60,54 @@
#define DDR_PLLDIV PLLC_PLLDIV1
#endif
#ifdef CONFIG_SOC_DA8XX
const dv_reg * const sysdiv[7] = {
&davinci_pllc_regs->plldiv1, &davinci_pllc_regs->plldiv2,
&davinci_pllc_regs->plldiv3, &davinci_pllc_regs->plldiv4,
&davinci_pllc_regs->plldiv5, &davinci_pllc_regs->plldiv6,
&davinci_pllc_regs->plldiv7
};
int clk_get(enum davinci_clk_ids id)
{
int pre_div;
int pllm;
int post_div;
int pll_out;
pll_out = CONFIG_SYS_OSCIN_FREQ;
if (id == DAVINCI_AUXCLK_CLKID)
goto out;
/*
* Lets keep this simple. Combining operations can result in
* unexpected approximations
*/
pre_div = (readl(&davinci_pllc_regs->prediv) &
DAVINCI_PLLC_DIV_MASK) + 1;
pllm = readl(&davinci_pllc_regs->pllm) + 1;
pll_out /= pre_div;
pll_out *= pllm;
if (id == DAVINCI_PLLM_CLKID)
goto out;
post_div = (readl(&davinci_pllc_regs->postdiv) &
DAVINCI_PLLC_DIV_MASK) + 1;
pll_out /= post_div;
if (id == DAVINCI_PLLC_CLKID)
goto out;
pll_out /= (readl(sysdiv[id - 1]) & DAVINCI_PLLC_DIV_MASK) + 1;
out:
return pll_out;
}
#endif /* CONFIG_SOC_DA8XX */
#ifdef CONFIG_DISPLAY_CPUINFO

43
cpu/arm926ejs/davinci/psc.c
View File

@ -25,6 +25,7 @@
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
/*
* The PSC manages three inputs to a "module" which may be a peripheral or
@ -47,21 +48,45 @@
/* Works on Always On power domain only (no PD argument) */
void lpsc_on(unsigned int id)
{
dv_reg_p mdstat, mdctl;
dv_reg_p mdstat, mdctl, ptstat, ptcmd;
#ifdef CONFIG_SOC_DA8XX
struct davinci_psc_regs *psc_regs;
#endif
#ifndef CONFIG_SOC_DA8XX
if (id >= DAVINCI_LPSC_GEM)
return; /* Don't work on DSP Power Domain */
mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
ptstat = REG_P(PSC_PTSTAT);
ptcmd = REG_P(PSC_PTCMD);
#else
if (id < DAVINCI_LPSC_PSC1_BASE) {
if (id >= PSC_PSC0_MODULE_ID_CNT)
return;
psc_regs = davinci_psc0_regs;
mdstat = &psc_regs->psc0.mdstat[id];
mdctl = &psc_regs->psc0.mdctl[id];
} else {
id -= DAVINCI_LPSC_PSC1_BASE;
if (id >= PSC_PSC1_MODULE_ID_CNT)
return;
psc_regs = davinci_psc1_regs;
mdstat = &psc_regs->psc1.mdstat[id];
mdctl = &psc_regs->psc1.mdctl[id];
}
ptstat = &psc_regs->ptstat;
ptcmd = &psc_regs->ptcmd;
#endif
while (REG(PSC_PTSTAT) & 0x01)
while (readl(ptstat) & 0x01)
continue;
if ((*mdstat & 0x1f) == 0x03)
return; /* Already on and enabled */
if ((readl(mdstat) & 0x1f) == 0x03)
return; /* Already on and enabled */
*mdctl |= 0x03;
writel(readl(mdctl) | 0x03, mdctl);
switch (id) {
#ifdef CONFIG_SOC_DM644X
@ -80,16 +105,16 @@ void lpsc_on(unsigned int id)
case DAVINCI_LPSC_MEMSTICK:
case DAVINCI_LPSC_McBSP:
case DAVINCI_LPSC_GPIO:
*mdctl |= 0x200;
writel(readl(mdctl) | 0x200, mdctl);
break;
#endif
}
REG(PSC_PTCMD) = 0x01;
writel(0x01, ptcmd);
while (REG(PSC_PTSTAT) & 0x03)
while (readl(ptstat) & 0x01)
continue;
while ((*mdstat & 0x1f) != 0x03) /* Probably an overkill... */
while ((readl(mdstat) & 0x1f) != 0x03)
continue;
}

28
cpu/arm926ejs/davinci/timer.c
View File

@ -38,8 +38,9 @@
*/
#include <common.h>
#include <asm/io.h>
typedef volatile struct {
struct davinci_timer {
u_int32_t pid12;
u_int32_t emumgt;
u_int32_t na1;
@ -51,9 +52,10 @@ typedef volatile struct {
u_int32_t tcr;
u_int32_t tgcr;
u_int32_t wdtcr;
} davinci_timer;
};
davinci_timer *timer = (davinci_timer *)CONFIG_SYS_TIMERBASE;
static struct davinci_timer * const timer =
(struct davinci_timer *)CONFIG_SYS_TIMERBASE;
#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
#define TIM_CLK_DIV 16
@ -64,30 +66,30 @@ static ulong lastinc;
int timer_init(void)
{
/* We are using timer34 in unchained 32-bit mode, full speed */
timer->tcr = 0x0;
timer->tgcr = 0x0;
timer->tgcr = 0x06 | ((TIM_CLK_DIV - 1) << 8);
timer->tim34 = 0x0;
timer->prd34 = TIMER_LOAD_VAL;
writel(0x0, &timer->tcr);
writel(0x0, &timer->tgcr);
writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
writel(0x0, &timer->tim34);
writel(TIMER_LOAD_VAL, &timer->prd34);
lastinc = 0;
timestamp = 0;
timer->tcr = 2 << 22;
writel(2 << 22, &timer->tcr);
return(0);
}
void reset_timer(void)
{
timer->tcr = 0x0;
timer->tim34 = 0;
writel(0x0, &timer->tcr);
writel(0x0, &timer->tim34);
lastinc = 0;
timestamp = 0;
timer->tcr = 2 << 22;
writel(2 << 22, &timer->tcr);
}
static ulong get_timer_raw(void)
{
ulong now = timer->tim34;
ulong now = readl(&timer->tim34);
if (now >= lastinc) {
/* normal mode */

5
cpu/arm_cortexa8/omap3/mem.c
View File

@ -161,10 +161,11 @@ void do_sdrc_init(u32 cs, u32 early)
writel(0, &sdrc_base->sysconfig);
/* setup sdrc to ball mux */
writel(SDP_SDRC_SHARING, &sdrc_base->sharing);
writel(SDRC_SHARING, &sdrc_base->sharing);
/* Disable Power Down of CKE cuz of 1 CKE on combo part */
writel(SRFRONRESET | PAGEPOLICY_HIGH, &sdrc_base->power);
writel(WAKEUPPROC | PWDNEN | SRFRONRESET | PAGEPOLICY_HIGH,
&sdrc_base->power);
writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
sdelay(0x20000);

2
cpu/arm_cortexa8/omap3/sys_info.c
View File

@ -109,7 +109,7 @@ u32 get_cpu_rev(void)
****************************************************/
u32 is_mem_sdr(void)
{
if (readl(&sdrc_base->cs[CS0].mr) == SDP_SDRC_MR_0_SDR)
if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
return 1;
return 0;
}

2
cpu/at32ap/Makefile
View File

@ -30,7 +30,7 @@ LIB := $(obj)lib$(CPU).a
START-y += start.o
COBJS-y += cpu.o
COBJS-y += hsdramc.o
COBJS-$(CONFIG_SYS_HSDRAMC) += hsdramc.o
COBJS-y += exception.o
COBJS-y += cache.o
COBJS-y += interrupts.o

3
cpu/at32ap/hsdramc.c
View File

@ -21,7 +21,6 @@
*/
#include <common.h>
#ifdef CONFIG_SYS_HSDRAMC
#include <asm/io.h>
#include <asm/sdram.h>
@ -116,5 +115,3 @@ unsigned long sdram_init(void *sdram_base, const struct sdram_config *config)
return sdram_size;
}
#endif /* CONFIG_SYS_HSDRAMC */

116
doc/README.davinci Normal file
View File

@ -0,0 +1,116 @@
Summary
=======
This README is about U-Boot support for TI's ARM 926EJS based family of SoCs.
These SOCs are used for cameras, video security and surveillance, DVR's, etc.
DaVinci SOC's comprise of DM644x, DM646x, DM35x and DM36x series of SOC's
Additionally there are some SOCs meant for the audio market which though have
an OMAP part number are very similar to the DaVinci series of SOC's
Additionally, some family members contain a TI DSP and/or graphics
co processors along with a host of other peripherals.
Currently the following boards are supported:
* TI DaVinci DM644x EVM
* TI DaVinci DM646x EVM
* TI DaVinci DM355 EVM
* TI DaVinci DM365 EVM
* TI DA830 EVM
* DM355 based Leopard board
* DM644x based schmoogie board
* DM644x based sffsdr board
* DM644x based sonata board
Build
=====
* TI DaVinci DM644x EVM:
make davinci_dvevm_config
make
* TI DaVinci DM646x EVM:
make davinci_dm6467evm_config
make
* TI DaVinci DM355 EVM:
make davinci_dm355evm_config
make
* TI DaVinci DM365 EVM:
make davinci_dm365evm_config
make
* TI DA830 EVM:
make da830evm_config
make
* DM355 based Leopard board:
make davinci_dm355leopard_config
make
* DM644x based schmoogie board:
make davinci_schmoogie_config
make
* DM644x based sffsdr board:
make davinci_sffsdr_config
make
* DM644x based sonata board:
make davinci_sonata_config
make
Bootloaders
===============
The DaVinci SOC's use 2 bootloaders. The low level initialization
is done by a UBL(user boot loader). The UBL is written to a NAND/NOR/SPI flash
by a programmer. During initial bootup, the ROM Bootloader reads the UBL
from a storage device and loads it into the IRAM. The UBL then loads the U-Boot
into the RAM.
The programmers and UBL are always released as part of any standard TI
software release associated with an SOC.
Links
=====
1) TI DaVinci DM355 EVM:
http://focus.ti.com/docs/prod/folders/print/tms320dm355.html
http://www.spectrumdigital.com/product_info.php?cPath=103&products_id=203&osCsid=c499af6087317f11b3da19b4e8f1af32
2) TI DaVinci DM365 EVM:
http://focus.ti.com/docs/prod/folders/print/tms320dm365.html?247SEM=
http://support.spectrumdigital.com/boards/evmdm365/revc/
3) DaVinci DM355 based leopard board
http://designsomething.org/leopardboard/default.aspx
http://www.spectrumdigital.com/product_info.php?cPath=103&products_id=192&osCsid=67c20335668ffc57cb35727106eb24b1
4) TI DaVinci DM6467 EVM:
http://focus.ti.com/docs/prod/folders/print/tms320dm6467.html
http://support.spectrumdigital.com/boards/evmdm6467/revf/
5) TI DaVinci DM6446 EVM:
http://focus.ti.com/docs/prod/folders/print/tms320dm6446.html
http://www.spectrumdigital.com/product_info.php?cPath=103&products_id=222
6) TI DA830 EVM
http://focus.ti.com/apps/docs/gencontent.tsp?appId=1&contentId=52385
http://www.spectrumdigital.com/product_info.php?cPath=37&products_id=214

6
drivers/i2c/s3c24x0_i2c.c
View File

@ -27,11 +27,7 @@
*/
#include <common.h>
#if defined(CONFIG_S3C2400)
#include <s3c2400.h>
#elif defined(CONFIG_S3C2410)
#include <s3c2410.h>
#endif
#include <asm/arch/s3c24x0_cpu.h>
#include <asm/io.h>
#include <i2c.h>

2
drivers/mmc/omap3_mmc.c
View File

@ -63,7 +63,9 @@ unsigned char mmc_board_init(void)
{
t2_t *t2_base = (t2_t *)T2_BASE;
#if defined(CONFIG_TWL4030_POWER)
twl4030_power_mmc_init();
#endif
writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,

2
drivers/mtd/nand/s3c2410_nand.c
View File

@ -21,7 +21,7 @@
#include <common.h>
#include <nand.h>
#include <s3c2410.h>
#include <asm/arch/s3c24x0_cpu.h>
#include <asm/io.h>
#define S3C2410_NFCONF_EN (1<<15)

2
drivers/mtd/nand/s3c64xx.c
View File

@ -28,7 +28,7 @@
#include <common.h>
#include <nand.h>
#include <s3c6400.h>
#include <asm/arch/s3c6400.h>
#include <asm/io.h>
#include <asm/errno.h>

1
drivers/rtc/Makefile
View File

@ -40,6 +40,7 @@ COBJS-$(CONFIG_RTC_DS1556) += ds1556.o
COBJS-$(CONFIG_RTC_DS164x) += ds164x.o
COBJS-$(CONFIG_RTC_DS174x) += ds174x.o
COBJS-$(CONFIG_RTC_DS3231) += ds3231.o
COBJS-$(CONFIG_RTC_FTRTC010) += ftrtc010.o
COBJS-$(CONFIG_RTC_ISL1208) += isl1208.o
COBJS-$(CONFIG_RTC_M41T11) += m41t11.o
COBJS-$(CONFIG_RTC_M41T60) += m41t60.o

124
drivers/rtc/ftrtc010.c Normal file
View File

@ -0,0 +1,124 @@
/*
* Faraday FTRTC010 Real Time Clock
*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <config.h>
#include <common.h>
#include <rtc.h>
#include <asm/io.h>
struct ftrtc010 {
unsigned int sec; /* 0x00 */
unsigned int min; /* 0x04 */
unsigned int hour; /* 0x08 */
unsigned int day; /* 0x0c */
unsigned int alarm_sec; /* 0x10 */
unsigned int alarm_min; /* 0x14 */
unsigned int alarm_hour; /* 0x18 */
unsigned int record; /* 0x1c */
unsigned int cr; /* 0x20 */
};
/*
* RTC Control Register
*/
#define FTRTC010_CR_ENABLE (1 << 0)
#define FTRTC010_CR_INTERRUPT_SEC (1 << 1) /* per second irq */
#define FTRTC010_CR_INTERRUPT_MIN (1 << 2) /* per minute irq */
#define FTRTC010_CR_INTERRUPT_HR (1 << 3) /* per hour irq */
#define FTRTC010_CR_INTERRUPT_DAY (1 << 4) /* per day irq */
static struct ftrtc010 *rtc = (struct ftrtc010 *)CONFIG_FTRTC010_BASE;
static void ftrtc010_enable(void)
{
writel(FTRTC010_CR_ENABLE, &rtc->cr);
}
/*
* return current time in seconds
*/
static unsigned long ftrtc010_time(void)
{
unsigned long day;
unsigned long hour;
unsigned long minute;
unsigned long second;
unsigned long second2;
do {
second = readl(&rtc->sec);
day = readl(&rtc->day);
hour = readl(&rtc->hour);
minute = readl(&rtc->min);
second2 = readl(&rtc->sec);
} while (second != second2);
return day * 24 * 60 * 60 + hour * 60 * 60 + minute * 60 + second;
}
/*
* Get the current time from the RTC
*/
int rtc_get(struct rtc_time *tmp)
{
unsigned long now;
debug("%s(): record register: %x\n",
__func__, readl(&rtc->record));
now = ftrtc010_time() + readl(&rtc->record);
to_tm(now, tmp);
return 0;
}
/*
* Set the RTC
*/
int rtc_set(struct rtc_time *tmp)
{
unsigned long new;
unsigned long now;
debug("%s(): DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
__func__,
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
new = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_hour,
tmp->tm_min, tmp->tm_sec);
now = ftrtc010_time();
debug("%s(): write %lx to record register\n", __func__, new - now);
writel(new - now, &rtc->record);
return 0;
}
void rtc_reset(void)
{
debug("%s()\n", __func__);
ftrtc010_enable();
}

1
drivers/rtc/m41t94.c
View File

@ -120,5 +120,4 @@ void rtc_reset(void)
* Could not be tested as the reset pin is not wired on
* the sbc35-ag20 board
*/
return 0;
}

6
drivers/rtc/s3c24x0_rtc.c
View File

@ -30,11 +30,7 @@
#if (defined(CONFIG_CMD_DATE))
#if defined(CONFIG_S3C2400)
#include <s3c2400.h>
#elif defined(CONFIG_S3C2410)
#include <s3c2410.h>
#endif
#include <asm/arch/s3c24x0_cpu.h>
#include <rtc.h>
#include <asm/io.h>

2
drivers/serial/s3c64xx.c
View File

@ -23,7 +23,7 @@
#include <common.h>
#include <s3c6400.h>
#include <asm/arch/s3c6400.h>
#ifdef CONFIG_SERIAL1
#define UART_NR S3C64XX_UART0

6
drivers/serial/serial_s3c24x0.c
View File

@ -19,11 +19,7 @@
*/
#include <common.h>
#if defined(CONFIG_S3C2400) || defined(CONFIG_TRAB)
#include <s3c2400.h>
#elif defined(CONFIG_S3C2410)
#include <s3c2410.h>
#endif
#include <asm/arch/s3c24x0_cpu.h>
DECLARE_GLOBAL_DATA_PTR;

22
drivers/serial/serial_s5pc1xx.c
View File

@ -98,14 +98,24 @@ int serial_init_dev(const int dev_index)
return 0;
}
static int serial_err_check(const int dev_index)
static int serial_err_check(const int dev_index, int op)
{
struct s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(dev_index);
unsigned int mask;
if (readl(&uart->uerstat) & 0xf)
return 1;
/*
* UERSTAT
* Break Detect [3]
* Frame Err [2] : receive operation
* Parity Err [1] : receive operation
* Overrun Err [0] : receive operation
*/
if (op)
mask = 0x8;
else
mask = 0xf;
return 0;
return readl(&uart->uerstat) & mask;
}
/*
@ -119,7 +129,7 @@ int serial_getc_dev(const int dev_index)
/* wait for character to arrive */
while (!(readl(&uart->utrstat) & 0x1)) {
if (serial_err_check(dev_index))
if (serial_err_check(dev_index, 0))
return 0;
}
@ -135,7 +145,7 @@ void serial_putc_dev(const char c, const int dev_index)
/* wait for room in the tx FIFO */
while (!(readl(&uart->utrstat) & 0x2)) {
if (serial_err_check(dev_index))
if (serial_err_check(dev_index, 1))
return;
}

3
drivers/usb/host/ohci-hcd.c
View File

@ -65,8 +65,7 @@
#endif
#if defined(CONFIG_ARM920T) || \
defined(CONFIG_S3C2400) || \
defined(CONFIG_S3C2410) || \
defined(CONFIG_S3C24X0) || \
defined(CONFIG_S3C6400) || \
defined(CONFIG_440EP) || \
defined(CONFIG_PCI_OHCI) || \

2
drivers/usb/host/s3c64xx-hcd.c
View File

@ -25,7 +25,7 @@
*/
#include <common.h>
#include <s3c6400.h>
#include <asm/arch/s3c6400.h>
int usb_cpu_init(void)
{

35
include/asm-arm/arch-a320/a320.h Normal file
View File

@ -0,0 +1,35 @@
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __A320_H
#define __A320_H
/*
* Hardware register bases
*/
#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller */
#define CONFIG_DEBUG_LED 0x902ffffc /* Debug LED */
#define CONFIG_FTSDMC020_BASE 0x90300000 /* SDRAM Controller */
#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */
#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */
#define CONFIG_FTTMR010_BASE 0x98400000 /* Timer */
#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock*/
#endif /* __A320_H */

146
include/asm-arm/arch-a320/ftpmu010.h Normal file
View File

@ -0,0 +1,146 @@
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*
* Power Management Unit
*/
#ifndef __FTPMU010_H
#define __FTPMU010_H
struct ftpmu010 {
unsigned int IDNMBR0; /* 0x00 */
unsigned int reserved0; /* 0x04 */
unsigned int OSCC; /* 0x08 */
unsigned int PMODE; /* 0x0C */
unsigned int PMCR; /* 0x10 */
unsigned int PED; /* 0x14 */
unsigned int PEDSR; /* 0x18 */
unsigned int reserved1; /* 0x1C */
unsigned int PMSR; /* 0x20 */
unsigned int PGSR; /* 0x24 */
unsigned int MFPSR; /* 0x28 */
unsigned int MISC; /* 0x2C */
unsigned int PDLLCR0; /* 0x30 */
unsigned int PDLLCR1; /* 0x34 */
unsigned int AHBMCLKOFF; /* 0x38 */
unsigned int APBMCLKOFF; /* 0x3C */
unsigned int DCSRCR0; /* 0x40 */
unsigned int DCSRCR1; /* 0x44 */
unsigned int DCSRCR2; /* 0x48 */
unsigned int SDRAMHTC; /* 0x4C */
unsigned int PSPR0; /* 0x50 */
unsigned int PSPR1; /* 0x54 */
unsigned int PSPR2; /* 0x58 */
unsigned int PSPR3; /* 0x5C */
unsigned int PSPR4; /* 0x60 */
unsigned int PSPR5; /* 0x64 */
unsigned int PSPR6; /* 0x68 */
unsigned int PSPR7; /* 0x6C */
unsigned int PSPR8; /* 0x70 */
unsigned int PSPR9; /* 0x74 */
unsigned int PSPR10; /* 0x78 */
unsigned int PSPR11; /* 0x7C */
unsigned int PSPR12; /* 0x80 */
unsigned int PSPR13; /* 0x84 */
unsigned int PSPR14; /* 0x88 */
unsigned int PSPR15; /* 0x8C */
unsigned int AHBDMA_RACCS; /* 0x90 */
unsigned int reserved2; /* 0x94 */
unsigned int reserved3; /* 0x98 */
unsigned int JSS; /* 0x9C */
unsigned int CFC_RACC; /* 0xA0 */
unsigned int SSP1_RACC; /* 0xA4 */
unsigned int UART1TX_RACC; /* 0xA8 */
unsigned int UART1RX_RACC; /* 0xAC */
unsigned int UART2TX_RACC; /* 0xB0 */
unsigned int UART2RX_RACC; /* 0xB4 */
unsigned int SDC_RACC; /* 0xB8 */
unsigned int I2SAC97_RACC; /* 0xBC */
unsigned int IRDATX_RACC; /* 0xC0 */
unsigned int reserved4; /* 0xC4 */
unsigned int USBD_RACC; /* 0xC8 */
unsigned int IRDARX_RACC; /* 0xCC */
unsigned int IRDA_RACC; /* 0xD0 */
unsigned int ED0_RACC; /* 0xD4 */
unsigned int ED1_RACC; /* 0xD8 */
};
/*
* ID Number 0 Register
*/
#define FTPMU010_ID_A320A 0x03200000
#define FTPMU010_ID_A320C 0x03200010
#define FTPMU010_ID_A320D 0x03200030
/*
* OSC Control Register
*/
#define FTPMU010_OSCC_OSCH_TRI (1 << 11)
#define FTPMU010_OSCC_OSCH_STABLE (1 << 9)
#define FTPMU010_OSCC_OSCH_OFF (1 << 8)
#define FTPMU010_OSCC_OSCL_TRI (1 << 3)
#define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2)
#define FTPMU010_OSCC_OSCL_STABLE (1 << 1)
#define FTPMU010_OSCC_OSCL_OFF (1 << 0)
/*
* Power Mode Register
*/
#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4)
#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4)
#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4)
#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4)
#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4)
#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4)
#define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7)
#define FTPMU010_PMODE_FCS (1 << 2)
#define FTPMU010_PMODE_TURBO (1 << 1)
#define FTPMU010_PMODE_SLEEP (1 << 0)
/*
* Power Manager Status Register
*/
#define FTPMU010_PMSR_SMR (1 << 10)
#define FTPMU010_PMSR_RDH (1 << 2)
#define FTPMU010_PMSR_PH (1 << 1)
#define FTPMU010_PMSR_CKEHLOW (1 << 0)
/*
* Multi-Function Port Setting Register
*/
#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14)
#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13)
#define FTPMU010_MFPSR_AC97PINSEL (1 << 3)
/*
* PLL/DLL Control Register 0
*/
#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) >> 20) & 0xf)
#define FTPMU010_PDLLCR0_DLLFRAG (1 << 19)
#define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18)
#define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17)
#define FTPMU010_PDLLCR0_DLLDIS (1 << 16)
#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) >> 3) & 0x1ff)
#define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2)
#define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1)
#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0)
#endif /* __FTPMU010_H */

103
include/asm-arm/arch-a320/ftsdmc020.h Normal file
View File

@ -0,0 +1,103 @@
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*
* SDRAM Controller
*/
#ifndef __FTSDMC020_H
#define __FTSDMC020_H
#define FTSDMC020_OFFSET_TP0 0x00
#define FTSDMC020_OFFSET_TP1 0x04
#define FTSDMC020_OFFSET_CR 0x08
#define FTSDMC020_OFFSET_BANK0_BSR 0x0C
#define FTSDMC020_OFFSET_BANK1_BSR 0x10
#define FTSDMC020_OFFSET_BANK2_BSR 0x14
#define FTSDMC020_OFFSET_BANK3_BSR 0x18
#define FTSDMC020_OFFSET_BANK4_BSR 0x1C
#define FTSDMC020_OFFSET_BANK5_BSR 0x20
#define FTSDMC020_OFFSET_BANK6_BSR 0x24
#define FTSDMC020_OFFSET_BANK7_BSR 0x28
#define FTSDMC020_OFFSET_ACR 0x34
/*
* Timing Parametet 0 Register
*/
#define FTSDMC020_TP0_TCL(x) ((x) & 0x3)
#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4)
#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8)
#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12)
#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16)
#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20)
/*
* Timing Parametet 1 Register
*/
#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff)
#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16)
#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20)
/*
* Configuration Register
*/
#define FTSDMC020_CR_SREF (1 << 0)
#define FTSDMC020_CR_PWDN (1 << 1)
#define FTSDMC020_CR_ISMR (1 << 2)
#define FTSDMC020_CR_IREF (1 << 3)
#define FTSDMC020_CR_IPREC (1 << 4)
#define FTSDMC020_CR_REFTYPE (1 << 5)
/*
* SDRAM External Bank Base/Size Register
*/
#define FTSDMC020_BANK_ENABLE (1 << 28)
#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16)
#define FTSDMC020_BANK_DDW_X4 (0 << 12)
#define FTSDMC020_BANK_DDW_X8 (1 << 12)
#define FTSDMC020_BANK_DDW_X16 (2 << 12)
#define FTSDMC020_BANK_DDW_X32 (3 << 12)
#define FTSDMC020_BANK_DSZ_16M (0 << 8)
#define FTSDMC020_BANK_DSZ_64M (1 << 8)
#define FTSDMC020_BANK_DSZ_128M (2 << 8)
#define FTSDMC020_BANK_DSZ_256M (3 << 8)
#define FTSDMC020_BANK_MBW_8 (0 << 4)
#define FTSDMC020_BANK_MBW_16 (1 << 4)
#define FTSDMC020_BANK_MBW_32 (2 << 4)
#define FTSDMC020_BANK_SIZE_1M 0x0
#define FTSDMC020_BANK_SIZE_2M 0x1
#define FTSDMC020_BANK_SIZE_4M 0x2
#define FTSDMC020_BANK_SIZE_8M 0x3
#define FTSDMC020_BANK_SIZE_16M 0x4
#define FTSDMC020_BANK_SIZE_32M 0x5
#define FTSDMC020_BANK_SIZE_64M 0x6
#define FTSDMC020_BANK_SIZE_128M 0x7
#define FTSDMC020_BANK_SIZE_256M 0x8
/*
* Arbiter Control Register
*/
#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f)
#define FTSDMC020_ACR_TOE (1 << 8)
#endif /* __FTSDMC020_H */

79
include/asm-arm/arch-a320/ftsmc020.h Normal file
View File

@ -0,0 +1,79 @@
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*
* Static Memory Controller
*/
#ifndef __FTSMC020_H
#define __FTSMC020_H
#ifndef __ASSEMBLY__
struct ftsmc020 {
struct {
unsigned int cr; /* 0x00, 0x08, 0x10, 0x18 */
unsigned int tpr; /* 0x04, 0x0c, 0x14, 0x1c */
} bank[4];
unsigned int pad[8]; /* 0x20 - 0x3c */
unsigned int ssr; /* 0x40 */
};
void ftsmc020_init(void);
#endif /* __ASSEMBLY__ */
/*
* Memory Bank Configuration Register
*/
#define FTSMC020_BANK_ENABLE (1 << 28)
#define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000)
#define FTSMC020_BANK_WPROT (1 << 11)
#define FTSMC020_BANK_SIZE_32K (0xb << 4)
#define FTSMC020_BANK_SIZE_64K (0xc << 4)
#define FTSMC020_BANK_SIZE_128K (0xd << 4)
#define FTSMC020_BANK_SIZE_256K (0xe << 4)
#define FTSMC020_BANK_SIZE_512K (0xf << 4)
#define FTSMC020_BANK_SIZE_1M (0x0 << 4)
#define FTSMC020_BANK_SIZE_2M (0x1 << 4)
#define FTSMC020_BANK_SIZE_4M (0x2 << 4)
#define FTSMC020_BANK_SIZE_8M (0x3 << 4)
#define FTSMC020_BANK_SIZE_16M (0x4 << 4)
#define FTSMC020_BANK_SIZE_32M (0x5 << 4)
#define FTSMC020_BANK_MBW_8 (0x0 << 0)
#define FTSMC020_BANK_MBW_16 (0x1 << 0)
#define FTSMC020_BANK_MBW_32 (0x2 << 0)
/*
* Memory Bank Timing Parameter Register
*/
#define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28)
#define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24)
#define FTSMC020_TPR_RBE (1 << 20)
#define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18)
#define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16)
#define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12)
#define FTSMC020_TPR_AT2(x) (((x) & 0x3) << 8)
#define FTSMC020_TPR_WTC(x) (((x) & 0x3) << 6)
#define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4)
#define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0)
#endif /* __FTSMC020_H */

73
include/asm-arm/arch-a320/fttmr010.h Normal file
View File

@ -0,0 +1,73 @@
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*
* Timer
*/
#ifndef __FTTMR010_H
#define __FTTMR010_H
struct fttmr010 {
unsigned int timer1_counter; /* 0x00 */
unsigned int timer1_load; /* 0x04 */
unsigned int timer1_match1; /* 0x08 */
unsigned int timer1_match2; /* 0x0c */
unsigned int timer2_counter; /* 0x10 */
unsigned int timer2_load; /* 0x14 */
unsigned int timer2_match1; /* 0x18 */
unsigned int timer2_match2; /* 0x1c */
unsigned int timer3_counter; /* 0x20 */
unsigned int timer3_load; /* 0x24 */
unsigned int timer3_match1; /* 0x28 */
unsigned int timer3_match2; /* 0x2c */
unsigned int cr; /* 0x30 */
unsigned int interrupt_state; /* 0x34 */
unsigned int interrupt_mask; /* 0x38 */
};
/*
* Timer Control Register
*/
#define FTTMR010_TM3_UPDOWN (1 << 11)
#define FTTMR010_TM2_UPDOWN (1 << 10)
#define FTTMR010_TM1_UPDOWN (1 << 9)
#define FTTMR010_TM3_OFENABLE (1 << 8)
#define FTTMR010_TM3_CLOCK (1 << 7)
#define FTTMR010_TM3_ENABLE (1 << 6)
#define FTTMR010_TM2_OFENABLE (1 << 5)
#define FTTMR010_TM2_CLOCK (1 << 4)
#define FTTMR010_TM2_ENABLE (1 << 3)
#define FTTMR010_TM1_OFENABLE (1 << 2)
#define FTTMR010_TM1_CLOCK (1 << 1)
#define FTTMR010_TM1_ENABLE (1 << 0)
/*
* Timer Interrupt State & Mask Registers
*/
#define FTTMR010_TM3_OVERFLOW (1 << 8)
#define FTTMR010_TM3_MATCH2 (1 << 7)
#define FTTMR010_TM3_MATCH1 (1 << 6)
#define FTTMR010_TM2_OVERFLOW (1 << 5)
#define FTTMR010_TM2_MATCH2 (1 << 4)
#define FTTMR010_TM2_MATCH1 (1 << 3)
#define FTTMR010_TM1_OVERFLOW (1 << 2)
#define FTTMR010_TM1_MATCH2 (1 << 1)
#define FTTMR010_TM1_MATCH1 (1 << 0)
#endif /* __FTTMR010_H */

237
include/asm-arm/arch-davinci/hardware.h
View File

@ -49,6 +49,8 @@ typedef volatile unsigned int * dv_reg_p;
* on other DaVinci chips. Double check them before you try
* using the addresses ... or PSC module identifiers, etc.
*/
#ifndef CONFIG_SOC_DA8XX
#define DAVINCI_DMA_3PCC_BASE (0x01c00000)
#define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
#define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
@ -116,10 +118,46 @@ typedef volatile unsigned int * dv_reg_p;
#endif
#else /* CONFIG_SOC_DA8XX */
#define DAVINCI_UART0_BASE 0x01c42000
#define DAVINCI_UART1_BASE 0x01d0c000
#define DAVINCI_UART2_BASE 0x01d0d000
#define DAVINCI_I2C0_BASE 0x01c22000
#define DAVINCI_I2C1_BASE 0x01e28000
#define DAVINCI_TIMER0_BASE 0x01c20000
#define DAVINCI_TIMER1_BASE 0x01c21000
#define DAVINCI_WDOG_BASE 0x01c21000
#define DAVINCI_PLL_CNTRL0_BASE 0x01c11000
#define DAVINCI_PSC0_BASE 0x01c10000
#define DAVINCI_PSC1_BASE 0x01e27000
#define DAVINCI_SPI0_BASE 0x01c41000
#define DAVINCI_USB_OTG_BASE 0x01e00000
#define DAVINCI_SPI1_BASE 0x01e12000
#define DAVINCI_GPIO_BASE 0x01e26000
#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000
#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000
#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000
#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x68000000
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x40000000
#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x60000000
#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x62000000
#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE 0x64000000
#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE 0x66000000
#define DAVINCI_DDR_EMIF_CTRL_BASE 0xb0000000
#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000
#define DAVINCI_INTC_BASE 0xfffee000
#define DAVINCI_BOOTCFG_BASE 0x01c14000
#endif /* CONFIG_SOC_DA8XX */
/* Power and Sleep Controller (PSC) Domains */
#define DAVINCI_GPSC_ARMDOMAIN 0
#define DAVINCI_GPSC_DSPDOMAIN 1
#ifndef CONFIG_SOC_DA8XX
#define DAVINCI_LPSC_VPSSMSTR 0
#define DAVINCI_LPSC_VPSSSLV 1
#define DAVINCI_LPSC_TPCC 2
@ -166,6 +204,52 @@ typedef volatile unsigned int * dv_reg_p;
#define DAVINCI_DM646X_LPSC_UART0 26
#define DAVINCI_DM646X_LPSC_I2C 31
#else /* CONFIG_SOC_DA8XX */
enum davinci_lpsc_ids {
DAVINCI_LPSC_TPCC = 0,
DAVINCI_LPSC_TPTC0,
DAVINCI_LPSC_TPTC1,
DAVINCI_LPSC_AEMIF,
DAVINCI_LPSC_SPI0,
DAVINCI_LPSC_MMC_SD,
DAVINCI_LPSC_AINTC,
DAVINCI_LPSC_ARM_RAM_ROM,
DAVINCI_LPSC_SECCTL_KEYMGR,
DAVINCI_LPSC_UART0,
DAVINCI_LPSC_SCR0,
DAVINCI_LPSC_SCR1,
DAVINCI_LPSC_SCR2,
DAVINCI_LPSC_DMAX,
DAVINCI_LPSC_ARM,
DAVINCI_LPSC_GEM,
/* for LPSCs in PSC1, offset from 32 for differentiation */
DAVINCI_LPSC_PSC1_BASE = 32,
DAVINCI_LPSC_USB11,
DAVINCI_LPSC_USB20,
DAVINCI_LPSC_GPIO,
DAVINCI_LPSC_UHPI,
DAVINCI_LPSC_EMAC,
DAVINCI_LPSC_DDR_EMIF,
DAVINCI_LPSC_McASP0,
DAVINCI_LPSC_McASP1,
DAVINCI_LPSC_McASP2,
DAVINCI_LPSC_SPI1,
DAVINCI_LPSC_I2C1,
DAVINCI_LPSC_UART1,
DAVINCI_LPSC_UART2,
DAVINCI_LPSC_LCDC,
DAVINCI_LPSC_ePWM,
DAVINCI_LPSC_eCAP,
DAVINCI_LPSC_eQEP,
DAVINCI_LPSC_SCR_P0,
DAVINCI_LPSC_SCR_P1,
DAVINCI_LPSC_CR_P3,
DAVINCI_LPSC_L3_CBA_RAM
};
#endif /* CONFIG_SOC_DA8XX */
void lpsc_on(unsigned int id);
void dsp_on(void);
@ -174,6 +258,8 @@ void davinci_enable_emac(void);
void davinci_enable_i2c(void);
void davinci_errata_workarounds(void);
#ifndef CONFIG_SOC_DA8XX
/* Some PSC defines */
#define PSC_CHP_SHRTSW (0x01c40038)
#define PSC_GBLCTL (0x01c41010)
@ -194,6 +280,39 @@ void davinci_errata_workarounds(void);
#define PSC_SILVER_BULLET (0x01c41a20)
#else /* CONFIG_SOC_DA8XX */
#define PSC_PSC0_MODULE_ID_CNT 16
#define PSC_PSC1_MODULE_ID_CNT 32
struct davinci_psc_regs {
dv_reg revid;
dv_reg rsvd0[71];
dv_reg ptcmd;
dv_reg rsvd1;
dv_reg ptstat;
dv_reg rsvd2[437];
union {
struct {
dv_reg mdstat[PSC_PSC0_MODULE_ID_CNT];
dv_reg rsvd3[112];
dv_reg mdctl[PSC_PSC0_MODULE_ID_CNT];
} psc0;
struct {
dv_reg mdstat[PSC_PSC1_MODULE_ID_CNT];
dv_reg rsvd3[96];
dv_reg mdctl[PSC_PSC1_MODULE_ID_CNT];
} psc1;
};
};
#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)
#endif /* CONFIG_SOC_DA8XX */
#ifndef CONFIG_SOC_DA8XX
/* Miscellania... */
#define VBPR (0x20000020)
@ -206,4 +325,122 @@ void davinci_errata_workarounds(void);
#define PINMUX3 0x01c4000c
#define PINMUX4 0x01c40010
#else /* CONFIG_SOC_DA8XX */
struct davinci_pllc_regs {
dv_reg revid;
dv_reg rsvd1[56];
dv_reg rstype;
dv_reg rsvd2[6];
dv_reg pllctl;
dv_reg ocsel;
dv_reg rsvd3[2];
dv_reg pllm;
dv_reg prediv;
dv_reg plldiv1;
dv_reg plldiv2;
dv_reg plldiv3;
dv_reg oscdiv;
dv_reg postdiv;
dv_reg rsvd4[3];
dv_reg pllcmd;
dv_reg pllstat;
dv_reg alnctl;
dv_reg dchange;
dv_reg cken;
dv_reg ckstat;
dv_reg systat;
dv_reg rsvd5[3];
dv_reg plldiv4;
dv_reg plldiv5;
dv_reg plldiv6;
dv_reg plldiv7;
dv_reg rsvd6[32];
dv_reg emucnt0;
dv_reg emucnt1;
};
#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
#define DAVINCI_PLLC_DIV_MASK 0x1f
/* Clock IDs */
enum davinci_clk_ids {
DAVINCI_SPI0_CLKID = 2,
DAVINCI_UART2_CLKID = 2,
DAVINCI_MDIO_CLKID = 4,
DAVINCI_ARM_CLKID = 6,
DAVINCI_PLLM_CLKID = 0xff,
DAVINCI_PLLC_CLKID = 0x100,
DAVINCI_AUXCLK_CLKID = 0x101
};
int clk_get(enum davinci_clk_ids id);
/* Boot config */
struct davinci_syscfg_regs {
dv_reg revid;
dv_reg rsvd[71];
dv_reg pinmux[20];
dv_reg suspsrc;
dv_reg chipsig;
dv_reg chipsig_clr;
dv_reg cfgchip0;
dv_reg cfgchip1;
dv_reg cfgchip2;
dv_reg cfgchip3;
dv_reg cfgchip4;
};
#define davinci_syscfg_regs \
((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)
/* Emulation suspend bits */
#define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5)
#define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16)
#define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21)
#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20)
#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27)
/* Interrupt controller */
struct davinci_aintc_regs {
dv_reg revid;
dv_reg cr;
dv_reg dummy0[2];
dv_reg ger;
dv_reg dummy1[219];
dv_reg ecr1;
dv_reg ecr2;
dv_reg ecr3;
dv_reg dummy2[1117];
dv_reg hier;
};
#define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE)
struct davinci_uart_ctrl_regs {
dv_reg revid1;
dv_reg revid2;
dv_reg pwremu_mgmt;
dv_reg mdr;
};
#define DAVINCI_UART_CTRL_BASE 0x28
#define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE)
#define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE)
#define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE)
#define davinci_uart0_ctrl_regs \
((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR)
#define davinci_uart1_ctrl_regs \
((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR)
#define davinci_uart2_ctrl_regs \
((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR)
/* UART PWREMU_MGMT definitions */
#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
#endif /* CONFIG_SOC_DA8XX */
#endif /* __ASM_ARCH_HARDWARE_H */

5
include/asm-arm/arch-davinci/i2c_defs.h
View File

@ -28,7 +28,11 @@
#define I2C_WRITE 0
#define I2C_READ 1
#ifndef CONFIG_SOC_DA8XX
#define I2C_BASE 0x01c21000
#else
#define I2C_BASE 0x01c22000
#endif
#define I2C_OA (I2C_BASE + 0x00)
#define I2C_IE (I2C_BASE + 0x04)
@ -88,6 +92,7 @@
#define I2C_CON_XA (1 << 8) /* Expand address */
#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */
#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */
#define I2C_CON_FREE (1 << 14) /* Free run on emulation */
#define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */

1
include/asm-arm/arch-omap3/cpu.h
View File

@ -222,6 +222,7 @@ struct sdrc {
#define PAGEPOLICY_HIGH (0x1 << 0)
#define SRFRONRESET (0x1 << 7)
#define PWDNEN (0x1 << 2)
#define WAKEUPPROC (0x1 << 26)
#define DDR_SDRAM (0x1 << 0)

98
include/asm-arm/arch-omap3/mem.h
View File

@ -40,11 +40,8 @@ enum {
#define EARLY_INIT 1
/* Slower full frequency range default timings for x32 operation*/
#define SDP_SDRC_SHARING 0x00000100
#define SDP_SDRC_MR_0_SDR 0x00000031
/* optimized timings good for current shipping parts */
#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
#define SDRC_SHARING 0x00000100
#define SDRC_MR_0_SDR 0x00000031
#define DLL_OFFSET 0
#define DLL_WRITEDDRCLKX2DIS 1
@ -71,29 +68,78 @@ enum {
* TCKE = 2
* XSR = 120/6 = 20
*/
#define TDAL_165 6
#define TDPL_165 3
#define TRRD_165 2
#define TRCD_165 3
#define TRP_165 3
#define TRAS_165 7
#define TRC_165 10
#define TRFC_165 21
#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | \
(TRAS_165 << 18) | (TRP_165 << 15) | \
(TRCD_165 << 12) | (TRRD_165 << 9) | \
(TDPL_165 << 6) | (TDAL_165))
#define INFINEON_TDAL_165 6
#define INFINEON_TDPL_165 3
#define INFINEON_TRRD_165 2
#define INFINEON_TRCD_165 3
#define INFINEON_TRP_165 3
#define INFINEON_TRAS_165 7
#define INFINEON_TRC_165 10
#define INFINEON_TRFC_165 12
#define INFINEON_V_ACTIMA_165 ((INFINEON_TRFC_165 << 27) | \
(INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) | \
(INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) | \
(INFINEON_TRRD_165 << 9) | (INFINEON_TDPL_165 << 6) | \
(INFINEON_TDAL_165))
#define TWTR_165 1
#define TCKE_165 1
#define TXP_165 5
#define XSR_165 23
#define V_ACTIMB_165 (((TCKE_165 << 12) | (XSR_165 << 0)) | \
(TXP_165 << 8) | (TWTR_165 << 16))
#define INFINEON_TWTR_165 1
#define INFINEON_TCKE_165 2
#define INFINEON_TXP_165 2
#define INFINEON_XSR_165 20
#define INFINEON_V_ACTIMB_165 ((INFINEON_TCKE_165 << 12) | \
(INFINEON_XSR_165 << 0) | (INFINEON_TXP_165 << 8) | \
(INFINEON_TWTR_165 << 16))
#define SDP_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165
#define SDP_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165
#define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz
/* Micron part of 3430 EVM (165MHz optimized) 6.06ns
* ACTIMA
* TDAL = Twr/Tck + Trp/tck= 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6
* TDPL (Twr) = 15/6 = 2.5 -> 3
* TRRD = 12/6 = 2
* TRCD = 18/6 = 3
* TRP = 18/6 = 3
* TRAS = 42/6 = 7
* TRC = 60/6 = 10
* TRFC = 125/6 = 21
* ACTIMB
* TWTR = 1
* TCKE = 1
* TXSR = 138/6 = 23
* TXP = 25/6 = 4.1 ~5
*/
#define MICRON_TDAL_165 6
#define MICRON_TDPL_165 3
#define MICRON_TRRD_165 2
#define MICRON_TRCD_165 3
#define MICRON_TRP_165 3
#define MICRON_TRAS_165 7
#define MICRON_TRC_165 10
#define MICRON_TRFC_165 21
#define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) | \
(MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) | \
(MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) | \
(MICRON_TRRD_165 << 9) | (MICRON_TDPL_165 << 6) | \
(MICRON_TDAL_165))
#define MICRON_TWTR_165 1
#define MICRON_TCKE_165 1
#define MICRON_XSR_165 23
#define MICRON_TXP_165 5
#define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) | \
(MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) | \
(MICRON_TWTR_165 << 16))
#ifdef CONFIG_OMAP3_INFINEON_DDR
#define V_ACTIMA_165 INFINEON_V_ACTIMA_165
#define V_ACTIMB_165 INFINEON_V_ACTIMB_165
#endif
#ifdef CONFIG_OMAP3_MICRON_DDR
#define V_ACTIMA_165 MICRON_V_ACTIMA_165
#define V_ACTIMB_165 MICRON_V_ACTIMB_165
#endif
#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165)
#error "Please choose the right DDR type in config header"
#endif
/*
* GPMC settings -

18
include/s3c2400.h → include/asm-arm/arch-s3c24x0/s3c2400.h
View File

@ -60,74 +60,90 @@ enum s3c24x0_uarts_nr {
#define S3C2400_MMC_BASE 0x15A00000
/* include common stuff */
#include <s3c24x0.h>
#include <asm/arch/s3c24x0.h>
static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
{
return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
}
static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
{
return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
}
static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
{
return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
}
static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
{
return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
}
static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
{
return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
}
static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
{
return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
}
static inline struct s3c24x0_uart
*s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
{
return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
}
static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
{
return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
}
static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
{
return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
}
static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
{
return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
}
static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
{
return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
}
static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
{
return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
}
static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
{
return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
}
static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
{
return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
}
static inline struct s3c2400_adc *s3c2400_get_base_adc(void)
{
return (struct s3c2400_adc *)S3C24X0_ADC_BASE;
}
static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
{
return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
}
static inline struct s3c2400_mmc *s3c2400_get_base_mmc(void)
{
return (struct s3c2400_mmc *)S3C2400_MMC_BASE;

19
include/s3c2410.h → include/asm-arm/arch-s3c24x0/s3c2410.h
View File

@ -66,78 +66,95 @@ enum s3c24x0_uarts_nr {
/* include common stuff */
#include <s3c24x0.h>
#include <asm/arch/s3c24x0.h>
static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
{
return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
}
static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
{
return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
}
static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
{
return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
}
static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
{
return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
}
static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
{
return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
}
static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
{
return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
}
static inline struct s3c2410_nand *s3c2410_get_base_nand(void)
{
return (struct s3c2410_nand *)S3C2410_NAND_BASE;
}
static inline struct s3c24x0_uart
*s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
{
return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
}
static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
{
return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
}
static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
{
return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
}
static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
{
return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
}
static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
{
return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
}
static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
{
return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
}
static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
{
return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
}
static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
{
return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
}
static inline struct s3c2410_adc *s3c2410_get_base_adc(void)
{
return (struct s3c2410_adc *)S3C2410_ADC_BASE;
}
static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
{
return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
}
static inline struct s3c2410_sdi *s3c2410_get_base_sdi(void)
{
return (struct s3c2410_sdi *)S3C2410_SDI_BASE;

652
include/asm-arm/arch-s3c24x0/s3c24x0.h Normal file
View File

@ -0,0 +1,652 @@
/*
* (C) Copyright 2003
* David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/************************************************
* NAME : s3c24x0.h
* Version : 31.3.2003
*
* common stuff for SAMSUNG S3C24X0 SoC
************************************************/
#ifndef __S3C24X0_H__
#define __S3C24X0_H__
/* Memory controller (see manual chapter 5) */
struct s3c24x0_memctl {
u32 BWSCON;
u32 BANKCON[8];
u32 REFRESH;
u32 BANKSIZE;
u32 MRSRB6;
u32 MRSRB7;
};
/* USB HOST (see manual chapter 12) */
struct s3c24x0_usb_host {
u32 HcRevision;
u32 HcControl;
u32 HcCommonStatus;
u32 HcInterruptStatus;
u32 HcInterruptEnable;
u32 HcInterruptDisable;
u32 HcHCCA;
u32 HcPeriodCuttendED;
u32 HcControlHeadED;
u32 HcControlCurrentED;
u32 HcBulkHeadED;
u32 HcBuldCurrentED;
u32 HcDoneHead;
u32 HcRmInterval;
u32 HcFmRemaining;
u32 HcFmNumber;
u32 HcPeriodicStart;
u32 HcLSThreshold;
u32 HcRhDescriptorA;
u32 HcRhDescriptorB;
u32 HcRhStatus;
u32 HcRhPortStatus1;
u32 HcRhPortStatus2;
};
/* INTERRUPT (see manual chapter 14) */
struct s3c24x0_interrupt {
u32 SRCPND;
u32 INTMOD;
u32 INTMSK;
u32 PRIORITY;
u32 INTPND;
u32 INTOFFSET;
#ifdef CONFIG_S3C2410
u32 SUBSRCPND;
u32 INTSUBMSK;
#endif
};
/* DMAS (see manual chapter 8) */
struct s3c24x0_dma {
u32 DISRC;
#ifdef CONFIG_S3C2410
u32 DISRCC;
#endif
u32 DIDST;
#ifdef CONFIG_S3C2410
u32 DIDSTC;
#endif
u32 DCON;
u32 DSTAT;
u32 DCSRC;
u32 DCDST;
u32 DMASKTRIG;
#ifdef CONFIG_S3C2400
u32 res[1];
#endif
#ifdef CONFIG_S3C2410
u32 res[7];
#endif
};
struct s3c24x0_dmas {
struct s3c24x0_dma dma[4];
};
/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
/* (see S3C2410 manual chapter 7) */
struct s3c24x0_clock_power {
u32 LOCKTIME;
u32 MPLLCON;
u32 UPLLCON;
u32 CLKCON;
u32 CLKSLOW;
u32 CLKDIVN;
};
/* LCD CONTROLLER (see manual chapter 15) */
struct s3c24x0_lcd {
u32 LCDCON1;
u32 LCDCON2;
u32 LCDCON3;
u32 LCDCON4;
u32 LCDCON5;
u32 LCDSADDR1;
u32 LCDSADDR2;
u32 LCDSADDR3;
u32 REDLUT;
u32 GREENLUT;
u32 BLUELUT;
u32 res[8];
u32 DITHMODE;
u32 TPAL;
#ifdef CONFIG_S3C2410
u32 LCDINTPND;
u32 LCDSRCPND;
u32 LCDINTMSK;
u32 LPCSEL;
#endif
};
/* NAND FLASH (see S3C2410 manual chapter 6) */
struct s3c2410_nand {
u32 NFCONF;
u32 NFCMD;
u32 NFADDR;
u32 NFDATA;
u32 NFSTAT;
u32 NFECC;
};
/* UART (see manual chapter 11) */
struct s3c24x0_uart {
u32 ULCON;
u32 UCON;
u32 UFCON;
u32 UMCON;
u32 UTRSTAT;
u32 UERSTAT;
u32 UFSTAT;
u32 UMSTAT;
#ifdef __BIG_ENDIAN
u8 res1[3];
u8 UTXH;
u8 res2[3];
u8 URXH;
#else /* Little Endian */
u8 UTXH;
u8 res1[3];
u8 URXH;
u8 res2[3];
#endif
u32 UBRDIV;
};
/* PWM TIMER (see manual chapter 10) */
struct s3c24x0_timer {
u32 TCNTB;
u32 TCMPB;
u32 TCNTO;
};
struct s3c24x0_timers {
u32 TCFG0;
u32 TCFG1;
u32 TCON;
struct s3c24x0_timer ch[4];
u32 TCNTB4;
u32 TCNTO4;
};
/* USB DEVICE (see manual chapter 13) */
struct s3c24x0_usb_dev_fifos {
#ifdef __BIG_ENDIAN
u8 res[3];
u8 EP_FIFO_REG;
#else /* little endian */
u8 EP_FIFO_REG;
u8 res[3];
#endif
};
struct s3c24x0_usb_dev_dmas {
#ifdef __BIG_ENDIAN
u8 res1[3];
u8 EP_DMA_CON;
u8 res2[3];
u8 EP_DMA_UNIT;
u8 res3[3];
u8 EP_DMA_FIFO;
u8 res4[3];
u8 EP_DMA_TTC_L;
u8 res5[3];
u8 EP_DMA_TTC_M;
u8 res6[3];
u8 EP_DMA_TTC_H;
#else /* little endian */
u8 EP_DMA_CON;
u8 res1[3];
u8 EP_DMA_UNIT;
u8 res2[3];
u8 EP_DMA_FIFO;
u8 res3[3];
u8 EP_DMA_TTC_L;
u8 res4[3];
u8 EP_DMA_TTC_M;
u8 res5[3];
u8 EP_DMA_TTC_H;
u8 res6[3];
#endif
};
struct s3c24x0_usb_device {
#ifdef __BIG_ENDIAN
u8 res1[3];
u8 FUNC_ADDR_REG;
u8 res2[3];
u8 PWR_REG;
u8 res3[3];
u8 EP_INT_REG;
u8 res4[15];
u8 USB_INT_REG;
u8 res5[3];
u8 EP_INT_EN_REG;
u8 res6[15];
u8 USB_INT_EN_REG;
u8 res7[3];
u8 FRAME_NUM1_REG;
u8 res8[3];
u8 FRAME_NUM2_REG;
u8 res9[3];
u8 INDEX_REG;
u8 res10[7];
u8 MAXP_REG;
u8 res11[3];
u8 EP0_CSR_IN_CSR1_REG;
u8 res12[3];
u8 IN_CSR2_REG;
u8 res13[7];
u8 OUT_CSR1_REG;
u8 res14[3];
u8 OUT_CSR2_REG;
u8 res15[3];
u8 OUT_FIFO_CNT1_REG;
u8 res16[3];
u8 OUT_FIFO_CNT2_REG;
#else /* little endian */
u8 FUNC_ADDR_REG;
u8 res1[3];
u8 PWR_REG;
u8 res2[3];
u8 EP_INT_REG;
u8 res3[15];
u8 USB_INT_REG;
u8 res4[3];
u8 EP_INT_EN_REG;
u8 res5[15];
u8 USB_INT_EN_REG;
u8 res6[3];
u8 FRAME_NUM1_REG;
u8 res7[3];
u8 FRAME_NUM2_REG;
u8 res8[3];
u8 INDEX_REG;
u8 res9[7];
u8 MAXP_REG;
u8 res10[7];
u8 EP0_CSR_IN_CSR1_REG;
u8 res11[3];
u8 IN_CSR2_REG;
u8 res12[3];
u8 OUT_CSR1_REG;
u8 res13[7];
u8 OUT_CSR2_REG;
u8 res14[3];
u8 OUT_FIFO_CNT1_REG;
u8 res15[3];
u8 OUT_FIFO_CNT2_REG;
u8 res16[3];
#endif /* __BIG_ENDIAN */
struct s3c24x0_usb_dev_fifos fifo[5];
struct s3c24x0_usb_dev_dmas dma[5];
};
/* WATCH DOG TIMER (see manual chapter 18) */
struct s3c24x0_watchdog {
u32 WTCON;
u32 WTDAT;
u32 WTCNT;
};
/* IIC (see manual chapter 20) */
struct s3c24x0_i2c {
u32 IICCON;
u32 IICSTAT;
u32 IICADD;
u32 IICDS;
};
/* IIS (see manual chapter 21) */
struct s3c24x0_i2s {
#ifdef __BIG_ENDIAN
u16 res1;
u16 IISCON;
u16 res2;
u16 IISMOD;
u16 res3;
u16 IISPSR;
u16 res4;
u16 IISFCON;
u16 res5;
u16 IISFIFO;
#else /* little endian */
u16 IISCON;
u16 res1;
u16 IISMOD;
u16 res2;
u16 IISPSR;
u16 res3;
u16 IISFCON;
u16 res4;
u16 IISFIFO;
u16 res5;
#endif
};
/* I/O PORT (see manual chapter 9) */
struct s3c24x0_gpio {
#ifdef CONFIG_S3C2400
u32 PACON;
u32 PADAT;
u32 PBCON;
u32 PBDAT;
u32 PBUP;
u32 PCCON;
u32 PCDAT;
u32 PCUP;
u32 PDCON;
u32 PDDAT;
u32 PDUP;
u32 PECON;
u32 PEDAT;
u32 PEUP;
u32 PFCON;
u32 PFDAT;
u32 PFUP;
u32 PGCON;
u32 PGDAT;
u32 PGUP;
u32 OPENCR;
u32 MISCCR;
u32 EXTINT;
#endif
#ifdef CONFIG_S3C2410
u32 GPACON;
u32 GPADAT;
u32 res1[2];
u32 GPBCON;
u32 GPBDAT;
u32 GPBUP;
u32 res2;
u32 GPCCON;
u32 GPCDAT;
u32 GPCUP;
u32 res3;
u32 GPDCON;
u32 GPDDAT;
u32 GPDUP;
u32 res4;
u32 GPECON;
u32 GPEDAT;
u32 GPEUP;
u32 res5;
u32 GPFCON;
u32 GPFDAT;
u32 GPFUP;
u32 res6;
u32 GPGCON;
u32 GPGDAT;
u32 GPGUP;
u32 res7;
u32 GPHCON;
u32 GPHDAT;
u32 GPHUP;
u32 res8;
u32 MISCCR;
u32 DCLKCON;
u32 EXTINT0;
u32 EXTINT1;
u32 EXTINT2;
u32 EINTFLT0;
u32 EINTFLT1;
u32 EINTFLT2;
u32 EINTFLT3;
u32 EINTMASK;
u32 EINTPEND;
u32 GSTATUS0;
u32 GSTATUS1;
u32 GSTATUS2;
u32 GSTATUS3;
u32 GSTATUS4;
#endif
};
/* RTC (see manual chapter 17) */
struct s3c24x0_rtc {
#ifdef __BIG_ENDIAN
u8 res1[67];
u8 RTCCON;
u8 res2[3];
u8 TICNT;
u8 res3[11];
u8 RTCALM;
u8 res4[3];
u8 ALMSEC;
u8 res5[3];
u8 ALMMIN;
u8 res6[3];
u8 ALMHOUR;
u8 res7[3];
u8 ALMDATE;
u8 res8[3];
u8 ALMMON;
u8 res9[3];
u8 ALMYEAR;
u8 res10[3];
u8 RTCRST;
u8 res11[3];
u8 BCDSEC;
u8 res12[3];
u8 BCDMIN;
u8 res13[3];
u8 BCDHOUR;
u8 res14[3];
u8 BCDDATE;
u8 res15[3];
u8 BCDDAY;
u8 res16[3];
u8 BCDMON;
u8 res17[3];
u8 BCDYEAR;
#else /* little endian */
u8 res0[64];
u8 RTCCON;
u8 res1[3];
u8 TICNT;
u8 res2[11];
u8 RTCALM;
u8 res3[3];
u8 ALMSEC;
u8 res4[3];
u8 ALMMIN;
u8 res5[3];
u8 ALMHOUR;
u8 res6[3];
u8 ALMDATE;
u8 res7[3];
u8 ALMMON;
u8 res8[3];
u8 ALMYEAR;
u8 res9[3];
u8 RTCRST;
u8 res10[3];
u8 BCDSEC;
u8 res11[3];
u8 BCDMIN;
u8 res12[3];
u8 BCDHOUR;
u8 res13[3];
u8 BCDDATE;
u8 res14[3];
u8 BCDDAY;
u8 res15[3];
u8 BCDMON;
u8 res16[3];
u8 BCDYEAR;
u8 res17[3];
#endif
};
/* ADC (see manual chapter 16) */
struct s3c2400_adc {
u32 ADCCON;
u32 ADCDAT;
};
/* ADC (see manual chapter 16) */
struct s3c2410_adc {
u32 ADCCON;
u32 ADCTSC;
u32 ADCDLY;
u32 ADCDAT0;
u32 ADCDAT1;
};
/* SPI (see manual chapter 22) */
struct s3c24x0_spi_channel {
u8 SPCON;
u8 res1[3];
u8 SPSTA;
u8 res2[3];
u8 SPPIN;
u8 res3[3];
u8 SPPRE;
u8 res4[3];
u8 SPTDAT;
u8 res5[3];
u8 SPRDAT;
u8 res6[3];
u8 res7[16];
};
struct s3c24x0_spi {
struct s3c24x0_spi_channel ch[S3C24X0_SPI_CHANNELS];
};
/* MMC INTERFACE (see S3C2400 manual chapter 19) */
struct s3c2400_mmc {
#ifdef __BIG_ENDIAN
u8 res1[3];
u8 MMCON;
u8 res2[3];
u8 MMCRR;
u8 res3[3];
u8 MMFCON;
u8 res4[3];
u8 MMSTA;
u16 res5;
u16 MMFSTA;
u8 res6[3];
u8 MMPRE;
u16 res7;
u16 MMLEN;
u8 res8[3];
u8 MMCR7;
u32 MMRSP[4];
u8 res9[3];
u8 MMCMD0;
u32 MMCMD1;
u16 res10;
u16 MMCR16;
u8 res11[3];
u8 MMDAT;
#else
u8 MMCON;
u8 res1[3];
u8 MMCRR;
u8 res2[3];
u8 MMFCON;
u8 res3[3];
u8 MMSTA;
u8 res4[3];
u16 MMFSTA;
u16 res5;
u8 MMPRE;
u8 res6[3];
u16 MMLEN;
u16 res7;
u8 MMCR7;
u8 res8[3];
u32 MMRSP[4];
u8 MMCMD0;
u8 res9[3];
u32 MMCMD1;
u16 MMCR16;
u16 res10;
u8 MMDAT;
u8 res11[3];
#endif
};
/* SD INTERFACE (see S3C2410 manual chapter 19) */
struct s3c2410_sdi {
u32 SDICON;
u32 SDIPRE;
u32 SDICARG;
u32 SDICCON;
u32 SDICSTA;
u32 SDIRSP0;
u32 SDIRSP1;
u32 SDIRSP2;
u32 SDIRSP3;
u32 SDIDTIMER;
u32 SDIBSIZE;
u32 SDIDCON;
u32 SDIDCNT;
u32 SDIDSTA;
u32 SDIFSTA;
#ifdef __BIG_ENDIAN
u8 res[3];
u8 SDIDAT;
#else
u8 SDIDAT;
u8 res[3];
#endif
u32 SDIIMSK;
};
#endif /*__S3C24X0_H__*/

27
include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h Normal file
View File

@ -0,0 +1,27 @@
/*
* (C) Copyright 2009
* Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt@fearnside-systems.co.uk>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifdef CONFIG_S3C2400
#include <asm/arch/s3c2400.h>
#elif defined CONFIG_S3C2410
#include <asm/arch/s3c2410.h>
#else
#error Please define the s3c24x0 cpu type
#endif

0
include/s3c6400.h → include/asm-arm/arch-s3c64xx/s3c6400.h
View File

0
include/s3c64x0.h → include/asm-arm/arch-s3c64xx/s3c64x0.h
View File

1976
include/asm-arm/mach-types.h
View File

File diff suppressed because it is too large Load Diff

8
include/common.h
View File

@ -107,6 +107,9 @@ typedef volatile unsigned char vu_char;
#ifdef CONFIG_BLACKFIN
#include <asm/blackfin.h>
#endif
#ifdef CONFIG_SOC_DA8XX
#include <asm/arch/hardware.h>
#endif
#include <part.h>
#include <flash.h>
@ -495,8 +498,9 @@ int prt_mpc8220_clks (void);
ulong get_OPB_freq (void);
ulong get_PCI_freq (void);
#endif
#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || \
defined(CONFIG_LH7A40X) || defined(CONFIG_S3C6400)
#if defined(CONFIG_S3C24X0) || \
defined(CONFIG_LH7A40X) || \
defined(CONFIG_S3C6400)
ulong get_FCLK (void);
ulong get_HCLK (void);
ulong get_PCLK (void);

7
include/configs/VCMA9.h
View File

@ -33,9 +33,10 @@
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */
#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */

222
include/configs/a320evb.h Normal file
View File

@ -0,0 +1,222 @@
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* Configuation settings for the Faraday A320 board.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/a320.h>
/*-----------------------------------------------------------------------
* CPU and Board Configuration Options
*/
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#undef CONFIG_SKIP_LOWLEVEL_INIT
/*-----------------------------------------------------------------------
* Timer
*/
#define CONFIG_SYS_HZ 1000 /* timer ticks per second */
/*-----------------------------------------------------------------------
* Real Time Clock
*/
#define CONFIG_RTC_FTRTC010
/*-----------------------------------------------------------------------
* Serial console configuration
*/
/* FTUART is a high speed NS 16C550A compatible UART */
#define CONFIG_BAUDRATE 38400
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_COM1 0x98200000
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_CLK 18432000
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*-----------------------------------------------------------------------
* Ethernet
*/
#define CONFIG_NET_MULTI
#define CONFIG_FTMAC100
#define CONFIG_BOOTDELAY 3
/*-----------------------------------------------------------------------
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_PING
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* max number of command args */
#define CONFIG_SYS_MAXARGS 16
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
#endif
/*-----------------------------------------------------------------------
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
/*-----------------------------------------------------------------------
* size in bytes reserved for initial data
*/
#define CONFIG_SYS_GBL_DATA_SIZE 128
/*-----------------------------------------------------------------------
* SDRAM controller configuration
*/
#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \
FTSDMC020_TP0_TRP(1) | \
FTSDMC020_TP0_TRCD(1) | \
FTSDMC020_TP0_TRF(3) | \
FTSDMC020_TP0_TWR(1) | \
FTSDMC020_TP0_TCL(2))
#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \
FTSDMC020_TP1_INI_REFT(8) | \
FTSDMC020_TP1_REF_INTV(0x180))
#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \
FTSDMC020_BANK_DDW_X16 | \
FTSDMC020_BANK_DSZ_256M | \
FTSDMC020_BANK_MBW_32 | \
FTSDMC020_BANK_SIZE_64M)
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
/*
* Load address and memory test area should agree with
* board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
*/
#define CONFIG_SYS_LOAD_ADDR 0x12000000
/* memtest works on 63 MB in DRAM */
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x13F00000
/*-----------------------------------------------------------------------
* Static memory controller configuration
*/
#include <asm/arch/ftsmc020.h>
#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
FTSMC020_BANK_SIZE_1M | \
FTSMC020_BANK_MBW_8)
#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \
FTSMC020_TPR_AST(3) | \
FTSMC020_TPR_CTW(3) | \
FTSMC020_TPR_ATI(0xf) | \
FTSMC020_TPR_AT2(3) | \
FTSMC020_TPR_WTC(3) | \
FTSMC020_TPR_AHT(3) | \
FTSMC020_TPR_TRNA(0xf))
#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \
FTSMC020_BANK_BASE(PHYS_FLASH_2) | \
FTSMC020_BANK_SIZE_32M | \
FTSMC020_BANK_MBW_32)
#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \
FTSMC020_TPR_CTW(3) | \
FTSMC020_TPR_ATI(0xf) | \
FTSMC020_TPR_AT2(3) | \
FTSMC020_TPR_WTC(3) | \
FTSMC020_TPR_AHT(3) | \
FTSMC020_TPR_TRNA(0xf))
#define CONFIG_SYS_FTSMC020_CONFIGS { \
{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
}
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
/* use CFI framework */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
/* support JEDEC */
#define CONFIG_FLASH_CFI_LEGACY
#define CONFIG_SYS_FLASH_LEGACY_512Kx8
#define PHYS_FLASH_1 0x00000000
#define PHYS_FLASH_2 0x00400000
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, }
#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_BANKS 2
/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT 512
#undef CONFIG_SYS_FLASH_EMPTY_INFO
/* environments */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR 0x00060000
#define CONFIG_ENV_SIZE 0x20000
#endif /* __CONFIG_H */

243
include/configs/da830evm.h Normal file
View File

@ -0,0 +1,243 @@
/*
* Copyright (C) 2008 Texas Instruments, Inc <www.ti.com>
*
* Based on davinci_dvevm.h. Original Copyrights follow:
*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* Board
*/
/*
* SoC Configuration
*/
#define CONFIG_MACH_DAVINCI_DA830_EVM
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SYS_HZ 1000
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
/*
* Memory Info
*/
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */
#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* memtest start addr */
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024) /* 16MB test */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define CONFIG_STACKSIZE (256*1024) /* regular stack */
/*
* Serial Driver info
*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* I2C Configuration
*/
#define CONFIG_HARD_I2C
#define CONFIG_DRIVER_DAVINCI_I2C
#define CONFIG_SYS_I2C_SPEED 25000 /* 100Kbps won't work, H/W bug */
#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/*
* I2C EEPROM definitions for catalyst 24W256 EEPROM chip
*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
/*
* Network & Ethernet Configuration
*/
#ifdef CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_NET_MULTI
#endif
/*
* Flash & Environment
*/
#ifdef CONFIG_USE_NAND
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
#define CONFIG_ENV_SIZE (128 << 10)
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_CS 3
#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
#define CONFIG_SYS_CLE_MASK 0x10
#define CONFIG_SYS_ALE_MASK 0x8
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_MAX_CHIPS 1
#define DEF_BOOTM ""
#endif
#ifdef CONFIG_USE_NOR
#define CONFIG_ENV_IS_IN_FLASH
#undef CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
#define CONFIG_SYS_FLASH_SECT_SZ (64 << 10) /* 64KB */
#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*3)
#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
#define PHYS_FLASH_SIZE (32 << 20) /* Flash size 32MB */
#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
#define CONFIG_SYS_FLASH_SPL_ACCESS
#endif
#ifdef CONFIG_USE_SPIFLASH
#undef CONFIG_ENV_IS_IN_FLASH
#undef CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE (16 << 10)
#define CONFIG_ENV_OFFSET (256 << 10)
#define CONFIG_ENV_SECT_SIZE 4096
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SPI
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
#define CONFIG_SF_DEFAULT_SPEED 50000000
#define CONFIG_SYS_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#endif
/*
* U-Boot general configuration
*/
#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#undef CONFIG_MISC_INIT_R
#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_PROMPT "DA830-evm > " /* Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_MEMTEST_START + 0x700000)
#define CONFIG_VERSION_VARIABLE
#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
/*
* Linux Information
*/
#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100)
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTARGS "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock/2 rw noinitrd ip=dhcp"
#define CONFIG_BOOTCOMMAND ""
#define CONFIG_BOOTDELAY 3
/*
* U-Boot commands
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ENV
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_MEMORY
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#define CONFIG_CMD_EEPROM
#ifndef CONFIG_DRIVER_TI_EMAC
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_DHCP
#undef CONFIG_CMD_MII
#undef CONFIG_CMD_PING
#endif
#ifdef CONFIG_USE_NAND
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_UBI
#define CONFIG_RBTREE
#endif
#ifdef CONFIG_USE_SPIFLASH
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_FLASH
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SAVEENV
#endif
#if !defined(CONFIG_USE_NAND) && \
!defined(CONFIG_USE_NOR) && \
!defined(CONFIG_USE_SPIFLASH)
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_SIZE (16 << 10)
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_ENV
#endif
#ifdef CONFIG_USB_DA8XX
#define CONFIG_CMD_USB /* include support for usb */
#define CONFIG_CMD_STORAGE /* include support for usb */
#define CONFIG_CMD_FAT /* include support for FAT/storage*/
#define CONFIG_DOS_PARTITION /* include support for FAT/storage*/
#endif
#endif /* __CONFIG_H */

3
include/configs/devkit8000.h
View File

@ -66,6 +66,9 @@
/* Hardware drivers */
/* DDR - I use Micron DDR */
#define CONFIG_OMAP3_MICRON_DDR 1
/* DM9000 */
#define CONFIG_NET_MULTI 1
#define CONFIG_NET_RETRY_COUNT 20

1
include/configs/imx27lite.h
View File

@ -156,6 +156,7 @@
#define CONFIG_SYS_NAND_BASE 0xd8000000
#define CONFIG_JFFS2_NAND
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
/*
* SD/MMC

3
include/configs/omap3_beagle.h
View File

@ -97,6 +97,9 @@
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
/* DDR - I use Micron DDR */
#define CONFIG_OMAP3_MICRON_DDR 1
/* commands to include */
#include <config_cmd_default.h>

3
include/configs/omap3_evm.h
View File

@ -101,6 +101,9 @@
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
/* DDR - I use Micron DDR */
#define CONFIG_OMAP3_MICRON_DDR 1
/* commands to include */
#include <config_cmd_default.h>

3
include/configs/omap3_overo.h
View File

@ -89,6 +89,9 @@
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
/* DDR - I use Micron DDR */
#define CONFIG_OMAP3_MICRON_DDR 1
/* commands to include */
#include <config_cmd_default.h>

3
include/configs/omap3_pandora.h
View File

@ -92,6 +92,9 @@
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
/* DDR - I use Micron DDR */
#define CONFIG_OMAP3_MICRON_DDR 1
/* commands to include */
#include <config_cmd_default.h>

3
include/configs/omap3_sdp3430.h
View File

@ -137,6 +137,9 @@
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/* DDR - I use Infineon DDR */
#define CONFIG_OMAP3_INFINEON_DDR 1
/* OMITTED: single 1 Gbit MT29F1G NAND flash */
/*

3
include/configs/omap3_zoom1.h
View File

@ -98,6 +98,9 @@
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
/* DDR - I use Micron DDR */
#define CONFIG_OMAP3_MICRON_DDR 1
/* commands to include */
#include <config_cmd_default.h>

3
include/configs/omap3_zoom2.h
View File

@ -98,6 +98,9 @@
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
/* DDR - I use Micron DDR */
#define CONFIG_OMAP3_MICRON_DDR 1
/* Status LED */
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED 1

7
include/configs/sbc2410x.h
View File

@ -43,9 +43,10 @@
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */
#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000/* the SBC2410X has 12MHz input clock */

7
include/configs/smdk2400.h
View File

@ -34,9 +34,10 @@
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_ARM920T 1 /* This is an ARM920T core */
#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */
#define CONFIG_SMDK2400 1 /* on an SAMSUNG SMDK2400 Board */
#define CONFIG_ARM920T 1 /* This is an ARM920T core */
#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
#define CONFIG_S3C2400 1 /* specifically a SAMSUNG S3C2400 SoC */
#define CONFIG_SMDK2400 1 /* on an SAMSUNG SMDK2400 Board */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000 /* SMDK2400 has 12 MHz input clock */

7
include/configs/smdk2410.h
View File

@ -33,9 +33,10 @@
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */
#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000/* the SMDK2410 has 12MHz input clock */

2
include/configs/smdk6400.h
View File

@ -49,8 +49,6 @@
#define CONFIG_ENABLE_MMU
#endif
#define CONFIG_MEMORY_UPPER_CODE
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG

9
include/configs/trab.h
View File

@ -40,10 +40,11 @@
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_ARM920T 1 /* This is an arm920t CPU */
#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */
#define CONFIG_TRAB 1 /* on a TRAB Board */
#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */
#define CONFIG_ARM920T 1 /* This is an arm920t CPU */
#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
#define CONFIG_S3C2400 1 /* specifically a SAMSUNG S3C2400 SoC */
#define CONFIG_TRAB 1 /* on a TRAB Board */
#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */
/* automatic software updates (see board/trab/auto_update.c) */
#define CONFIG_AUTO_UPDATE 1

Some files were not shown because too many files have changed in this diff Show More