Merge https://source.denx.de/u-boot/custodians/u-boot-riscv

MAINTAINERS

@@ -981,6 +981,7 @@ F:	arch/powerpc/cpu/mpc86xx/
 
 RISC-V
 M:	Rick Chen <rick@andestech.com>
+M:	Leo <ycliang@andestech.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-riscv.git
 F:	arch/riscv/

arch/riscv/cpu/fu540/spl.c

@@ -6,9 +6,6 @@
 
 #include <dm.h>
 #include <log.h>
-#include <asm/csr.h>
-
-#define CSR_U74_FEATURE_DISABLE	0x7c1
 
 int spl_soc_init(void)
 {
@@ -24,15 +21,3 @@ int spl_soc_init(void)
 
 	return 0;
 }
-
-void harts_early_init(void)
-{
-	/*
-	 * Feature Disable CSR
-	 *
-	 * Clear feature disable CSR to '0' to turn on all features for
-	 * each core. This operation must be in M-mode.
-	 */
-	if (CONFIG_IS_ENABLED(RISCV_MMODE))
-		csr_write(CSR_U74_FEATURE_DISABLE, 0);
-}

arch/riscv/dts/k210.dtsi

@@ -86,22 +86,12 @@
 		reg = <0x80000000 0x400000>,
 		      <0x80400000 0x200000>,
 		      <0x80600000 0x200000>;
-		reg-names = "sram0", "sram1", "airam";
+		reg-names = "sram0", "sram1", "aisram";
 		clocks = <&sysclk K210_CLK_SRAM0>,
 			 <&sysclk K210_CLK_SRAM1>,
-			 <&sysclk K210_CLK_PLL1>;
+			 <&sysclk K210_CLK_AI>;
-		clock-names = "sram0", "sram1", "airam";
+		clock-names = "sram0", "sram1", "aisram";
-	};
+		u-boot,dm-pre-reloc;
-
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		ai_reserved: ai@80600000 {
-			reg = <0x80600000 0x200000>;
-			reusable;
-		};
 	};
 
 	clocks {
@@ -109,6 +99,7 @@
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <26000000>;
+			u-boot,dm-pre-reloc;
 		};
 	};
 
@@ -177,7 +168,6 @@
 			reg = <0x40800000 0xc00000>;
 			interrupts = <25>;
 			clocks = <&sysclk K210_CLK_AI>;
-			memory-region = <&ai_reserved>;
 			status = "disabled";
 		};
 
@@ -505,11 +495,13 @@
 					     "syscon", "simple-mfd";
 				reg = <0x50440000 0x100>;
 				reg-io-width = <4>;
+				u-boot,dm-pre-reloc;
 
 				sysclk: clock-controller {
 					#clock-cells = <1>;
 					compatible = "kendryte,k210-clk";
 					clocks = <&in0>;
+					u-boot,dm-pre-reloc;
 				};
 
 				sysrst: reset-controller {

board/sipeed/maix/maix.c

@@ -14,10 +14,10 @@ phys_size_t get_effective_memsize(void)
 	return CONFIG_SYS_SDRAM_SIZE;
 }
 
-int board_init(void)
+static int sram_init(void)
 {
 	int ret, i;
-	const char * const banks[] = { "sram0", "sram1", "airam" };
+	const char * const banks[] = { "sram0", "sram1", "aisram" };
 	ofnode memory;
 	struct clk clk;
 
@@ -39,3 +39,13 @@ int board_init(void)
 
 	return 0;
 }
+
+int board_early_init_f(void)
+{
+	return sram_init();
+}
+
+int board_init(void)
+{
+	return 0;
+}

configs/sipeed_maix_bitm_defconfig

@@ -1,4 +1,5 @@
 CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_F_LEN=0x10000
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0xfff000
 CONFIG_ENV_SECT_SIZE=0x1000
@@ -7,6 +8,7 @@ CONFIG_ARCH_RV64I=y
 CONFIG_STACK_SIZE=0x100000
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="run k210_bootcmd"
+CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
 CONFIG_MTDIDS_DEFAULT="nor0=spi3:0"
 CONFIG_MTDPARTS_DEFAULT="nor0:1M(u-boot),0x1000@0xfff000(env)"

drivers/clk/clk-uclass.c

@@ -14,6 +14,7 @@
 #include <errno.h>
 #include <log.h>
 #include <malloc.h>
+#include <dm/device_compat.h>
 #include <dm/device-internal.h>
 #include <dm/devres.h>
 #include <dm/read.h>
@@ -309,8 +310,9 @@ static int clk_set_default_rates(struct udevice *dev, int stage)
 		ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
 					      index, &clk);
 		if (ret) {
-			debug("%s: could not get assigned clock %d for %s\n",
+			dev_dbg(dev,
-			      __func__, index, dev_read_name(dev));
+				"could not get assigned clock %d (err = %d)\n",
+				index, ret);
 			continue;
 		}
 
@@ -332,8 +334,9 @@ static int clk_set_default_rates(struct udevice *dev, int stage)
 		ret = clk_set_rate(c, rates[index]);
 
 		if (ret < 0) {
-			debug("%s: failed to set rate on clock index %d (%ld) for %s\n",
+			dev_warn(dev,
-			      __func__, index, clk.id, dev_read_name(dev));
+				 "failed to set rate on clock index %d (%ld) (error = %d)\n",
+				 index, clk.id, ret);
 			break;
 		}
 	}

drivers/clk/kendryte/clk.c

@@ -347,9 +347,7 @@ static const struct k210_comp_params k210_comps[] = {
 #undef COMP_NOMUX_ID
 #undef COMP_LIST
 
-static struct clk *k210_bypass_children = {
+static struct clk *k210_bypass_children __section(.data);
-	NULL,
-};
 
 /* Helper functions to create sub-clocks */
 static struct clk_mux *k210_create_mux(const struct k210_mux_params *params,
@@ -475,7 +473,14 @@ cleanup_mux:
 	return comp;
 }
 
-static bool probed;
+static bool __section(.data) probed;
+
+/* reset probed so we will probe again post-relocation */
+static int k210_clk_bind(struct udevice *dev)
+{
+	probed = false;
+	return 0;
+}
 
 static int k210_clk_probe(struct udevice *dev)
 {
@@ -528,14 +533,10 @@ static int k210_clk_probe(struct udevice *dev)
 		return -ENOMEM;
 	}
 
-	{
+	pll = k210_create_pll(&k210_plls[1], base);
-		const struct k210_pll_params *params = &k210_plls[1];
+	if (pll)
-
 		clk_dm(K210_CLK_PLL1,
-		       k210_register_pll("pll1", in0, base + params->off,
+		       k210_register_pll_struct("pll1", in0, pll));
-					 base + params->lock_off, params->shift,
-					 params->width));
-	}
 
 	/* PLL2 is muxed, so set up a composite clock */
 	mux = k210_create_mux(&k210_muxes[MUXIFY(K210_CLK_PLL2)], base);
@@ -647,7 +648,7 @@ static int k210_clk_probe(struct udevice *dev)
 
 	/* The MTIME register in CLINT runs at one 50th the CPU clock speed */
 	clk_dm(K210_CLK_CLINT,
-	       clk_register_fixed_factor(NULL, "clint", "cpu", 0, 1, 50));
+	       clk_register_fixed_factor(NULL, "clint", "aclk", 0, 1, 50));
 
 	return 0;
 }
@@ -662,5 +663,6 @@ U_BOOT_DRIVER(k210_clk) = {
 	.id = UCLASS_CLK,
 	.of_match = k210_clk_ids,
 	.ops = &k210_clk_ops,
+	.bind = k210_clk_bind,
 	.probe = k210_clk_probe,
 };

drivers/clk/kendryte/pll.c

@@ -512,7 +512,8 @@ static int k210_pll_enable(struct clk *clk)
 	struct k210_pll *pll = to_k210_pll(clk);
 	u32 reg = readl(pll->reg);
 
-	if ((reg | K210_PLL_PWRD) && !(reg | K210_PLL_RESET))
+	if ((reg & K210_PLL_PWRD) && (reg & K210_PLL_EN) &&
+	    !(reg & K210_PLL_RESET))
 		return 0;
 
 	reg |= K210_PLL_PWRD;
@@ -531,6 +532,7 @@ static int k210_pll_enable(struct clk *clk)
 	k210_pll_waitfor_lock(pll);
 
 	reg &= ~K210_PLL_BYPASS;
+	reg |= K210_PLL_EN;
 	writel(reg, pll->reg);
 
 	return 0;
@@ -550,6 +552,7 @@ static int k210_pll_disable(struct clk *clk)
 	writel(reg, pll->reg);
 
 	reg &= ~K210_PLL_PWRD;
+	reg &= ~K210_PLL_EN;
 	writel(reg, pll->reg);
 	return 0;
 }
@@ -575,27 +578,6 @@ struct clk *k210_register_pll_struct(const char *name, const char *parent_name,
 	return clk;
 }
 
-struct clk *k210_register_pll(const char *name, const char *parent_name,
-			      void __iomem *reg, void __iomem *lock, u8 shift,
-			      u8 width)
-{
-	struct clk *clk;
-	struct k210_pll *pll;
-
-	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
-	if (!pll)
-		return ERR_PTR(-ENOMEM);
-	pll->reg = reg;
-	pll->lock = lock;
-	pll->shift = shift;
-	pll->width = width;
-
-	clk = k210_register_pll_struct(name, parent_name, pll);
-	if (IS_ERR(clk))
-		kfree(pll);
-	return clk;
-}
-
 U_BOOT_DRIVER(k210_pll) = {
 	.name	= CLK_K210_PLL,
 	.id	= UCLASS_CLK,

drivers/pwm/pwm-sifive.c

@@ -38,6 +38,9 @@
 #define PWM_SIFIVE_SIZE_PWMCMP          4
 #define PWM_SIFIVE_CMPWIDTH             16
 
+#define PWM_SIFIVE_CHANNEL_ENABLE_VAL   0
+#define PWM_SIFIVE_CHANNEL_DISABLE_VAL  0xffff
+
 DECLARE_GLOBAL_DATA_PTR;
 
 struct pwm_sifive_regs {
@@ -77,7 +80,7 @@ static int pwm_sifive_set_config(struct udevice *dev, uint channel,
 	 */
 	scale_pow = lldiv((uint64_t)priv->freq * period_ns, 1000000000);
 	scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf);
-	val |= FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale);
+	val |= (FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale) | PWM_SIFIVE_PWMCFG_EN_ALWAYS);
 
 	/*
 	 * The problem of output producing mixed setting as mentioned at top,
@@ -88,6 +91,7 @@ static int pwm_sifive_set_config(struct udevice *dev, uint channel,
 	num = (u64)duty_ns * (1U << PWM_SIFIVE_CMPWIDTH);
 	frac = DIV_ROUND_CLOSEST_ULL(num, period_ns);
 	frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1);
+	frac = (1U << PWM_SIFIVE_CMPWIDTH) - 1 - frac;
 
 	writel(val, priv->base + regs->cfg);
 	writel(frac, priv->base + regs->cmp0 + channel *
@@ -100,18 +104,15 @@ static int pwm_sifive_set_enable(struct udevice *dev, uint channel, bool enable)
 {
 	struct pwm_sifive_priv *priv = dev_get_priv(dev);
 	const struct pwm_sifive_regs *regs = &priv->data->regs;
-	u32 val;
 
 	debug("%s: Enable '%s'\n", __func__, dev->name);
 
-	if (enable) {
+	if (enable)
-		val = readl(priv->base + regs->cfg);
+		writel(PWM_SIFIVE_CHANNEL_ENABLE_VAL, priv->base +
-		val |= PWM_SIFIVE_PWMCFG_EN_ALWAYS;
+		       regs->cmp0 + channel * PWM_SIFIVE_SIZE_PWMCMP);
-		writel(val, priv->base + regs->cfg);
+	else
-	} else {
+		writel(PWM_SIFIVE_CHANNEL_DISABLE_VAL, priv->base +
-		writel(0, priv->base + regs->cmp0 + channel *
+		       regs->cmp0 + channel * PWM_SIFIVE_SIZE_PWMCMP);
-		       PWM_SIFIVE_SIZE_PWMCMP);
-	}
 
 	return 0;
 }

include/configs/sipeed-maix.h

@@ -15,8 +15,7 @@
 #define CONFIG_SYS_CACHELINE_SIZE 64
 
 #define CONFIG_SYS_SDRAM_BASE 0x80000000
-/* Don't relocate into AI ram since it isn't set up yet */
+#define CONFIG_SYS_SDRAM_SIZE SZ_8M
-#define CONFIG_SYS_SDRAM_SIZE (SZ_4M + SZ_2M)
 
 #ifndef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS \

include/kendryte/pll.h

@@ -55,8 +55,4 @@ extern const struct clk_ops k210_pll_ops;
 
 struct clk *k210_register_pll_struct(const char *name, const char *parent_name,
 				     struct k210_pll *pll);
-struct clk *k210_register_pll(const char *name, const char *parent_name,
-			      void __iomem *reg, void __iomem *lock, u8 shift,
-			      u8 width);
-
 #endif /* K210_PLL_H */