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imx: bootaux: cleanup code
Use if (CONFIG_IS_ENABLED()) to make code cleaner Enable elf support for i.MX8M Signed-off-by: Peng Fan <peng.fan@nxp.com>
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290ffe5788
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@ -14,7 +14,13 @@
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#include <linux/compiler.h>
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#include <linux/compiler.h>
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#include <cpu_func.h>
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#include <cpu_func.h>
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#ifndef CONFIG_IMX8M
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/* Just to avoid build error */
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#if CONFIG_IS_ENABLED(IMX8M)
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#define SRC_M4C_NON_SCLR_RST_MASK BIT(0)
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#define SRC_M4_ENABLE_MASK BIT(0)
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#define SRC_M4_REG_OFFSET 0
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#endif
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const __weak struct rproc_att hostmap[] = { };
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const __weak struct rproc_att hostmap[] = { };
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static const struct rproc_att *get_host_mapping(unsigned long auxcore)
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static const struct rproc_att *get_host_mapping(unsigned long auxcore)
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@ -59,7 +65,7 @@ static unsigned long load_elf_image_m_core_phdr(unsigned long addr)
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return 0;
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return 0;
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}
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}
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dst = (void *)(phdr->p_paddr - mmap->da) + mmap->sa;
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dst = (void *)(ulong)(phdr->p_paddr - mmap->da) + mmap->sa;
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src = (void *)addr + phdr->p_offset;
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src = (void *)addr + phdr->p_offset;
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debug("Loading phdr %i to 0x%p (%i bytes)\n",
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debug("Loading phdr %i to 0x%p (%i bytes)\n",
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@ -77,7 +83,6 @@ static unsigned long load_elf_image_m_core_phdr(unsigned long addr)
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return ehdr->e_entry;
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return ehdr->e_entry;
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}
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}
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#endif
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int arch_auxiliary_core_up(u32 core_id, ulong addr)
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int arch_auxiliary_core_up(u32 core_id, ulong addr)
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{
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{
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@ -86,10 +91,6 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)
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if (!addr)
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if (!addr)
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return -EINVAL;
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return -EINVAL;
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#ifdef CONFIG_IMX8M
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stack = *(u32 *)addr;
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pc = *(u32 *)(addr + 4);
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#else
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/*
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/*
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* handling ELF64 binaries
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* handling ELF64 binaries
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* isn't supported yet.
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* isn't supported yet.
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@ -109,7 +110,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)
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stack = *(u32 *)addr;
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stack = *(u32 *)addr;
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pc = *(u32 *)(addr + 4);
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pc = *(u32 *)(addr + 4);
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}
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}
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#endif
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printf("## Starting auxiliary core stack = 0x%08lX, pc = 0x%08lX...\n",
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printf("## Starting auxiliary core stack = 0x%08lX, pc = 0x%08lX...\n",
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stack, pc);
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stack, pc);
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@ -120,36 +121,32 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)
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flush_dcache_all();
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flush_dcache_all();
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/* Enable M4 */
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/* Enable M4 */
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#ifdef CONFIG_IMX8M
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if (CONFIG_IS_ENABLED(IMX8M)) {
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arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0,
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arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0, 0, 0, 0, NULL);
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0, 0, 0, 0, NULL);
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} else {
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#else
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clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
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clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
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SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
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SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
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}
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#endif
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return 0;
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return 0;
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}
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}
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int arch_auxiliary_core_check_up(u32 core_id)
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int arch_auxiliary_core_check_up(u32 core_id)
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{
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{
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#ifdef CONFIG_IMX8M
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struct arm_smccc_res res;
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struct arm_smccc_res res;
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arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0,
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0, 0, 0, 0, &res);
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return res.a0;
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#else
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unsigned int val;
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unsigned int val;
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if (CONFIG_IS_ENABLED(IMX8M)) {
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arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, 0, 0, 0, 0, &res);
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return res.a0;
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}
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val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET);
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val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET);
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if (val & SRC_M4C_NON_SCLR_RST_MASK)
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if (val & SRC_M4C_NON_SCLR_RST_MASK)
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return 0; /* assert in reset */
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return 0; /* assert in reset */
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return 1;
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return 1;
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#endif
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}
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}
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/*
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/*
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