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pinctrl: gpio: sx150x: add Semtech SX150x I2C GPIO expander and pinctrl driver
implement a driver to use semtech pinctrl and gpio expander, this driver is adapted from a existent linux driver that is written by Gregory Bean <gbean@codeaurora.org>. Signed-off-by: Anis Chali <chalianis1@gmail.com>
This commit is contained in:
Anis Chali
Tom Rini
parent
a4fb99ce4e
commit
5451504256
@ -263,6 +263,24 @@ config PINCTRL_ROCKCHIP_RV1108
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both the GPIO definitions and pin control functions for each
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available multiplex function.
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config PINCTRL_SX150X
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bool "Semtech SX150x I2C GPIO expander pinctrl driver"
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depends on DM && PINCTRL_FULL
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help
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Say yes here to provide support for Semtech SX150x-series I2C
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GPIO expanders as pinctrl module.
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Compatible models include:
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- 8 bits: sx1508q, sx1502q
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- 16 bits: sx1509q, sx1506q
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config SPL_PINCTRL_SX150X
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bool "Semtech SX150x I2C GPIO expander pinctrl driver in SPL"
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depends on DM && SPL_PINCTRL_FULL
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help
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This option is an SPL-variant of the PINCTRL_SX150X option.
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See the help of PINCTRL_SX150X for details.
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config PINCTRL_SANDBOX
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bool "Sandbox pinctrl driver"
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depends on SANDBOX
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@ -32,6 +32,7 @@ obj-$(CONFIG_PINCTRL_QE) += pinctrl-qe-io.o
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obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
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obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o
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obj-$(CONFIG_PINCTRL_STM32) += pinctrl_stm32.o
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obj-$(CONFIG_$(PHASE_)PINCTRL_SX150X) += pinctrl-sx150x.o
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obj-$(CONFIG_$(PHASE_)PINCTRL_STMFX) += pinctrl-stmfx.o
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obj-y += broadcom/
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obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o
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902
drivers/pinctrl/pinctrl-sx150x.c
Normal file
902
drivers/pinctrl/pinctrl-sx150x.c
Normal file
@ -0,0 +1,902 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2024, Exfo Inc - All Rights Reserved
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*
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* Author: Anis CHALI <anis.chali@exfo.com>
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* inspired and adapted from linux driver of sx150x written by Gregory Bean
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* <gbean@codeaurora.org>
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*/
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#include <asm/gpio.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <dm/device.h>
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#include <dm/device_compat.h>
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#include <dm/lists.h>
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#include <dm/pinctrl.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <i2c.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <log.h>
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#include <power/regulator.h>
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#include <regmap.h>
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#define err(format, arg...) printf("ERR:" format "\n", ##arg)
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#define dbg(format, arg...) printf("DBG:" format "\n", ##arg)
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#define SX150X_PIN(_pin, _name) { .pin = _pin, .name = _name }
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/* The chip models of sx150x */
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enum {
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SX150X_123 = 0,
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SX150X_456,
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SX150X_789,
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};
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enum {
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SX150X_789_REG_MISC_AUTOCLEAR_OFF = 1 << 0,
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SX150X_MAX_REGISTER = 0xad,
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SX150X_IRQ_TYPE_EDGE_RISING = 0x1,
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SX150X_IRQ_TYPE_EDGE_FALLING = 0x2,
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SX150X_789_RESET_KEY1 = 0x12,
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SX150X_789_RESET_KEY2 = 0x34,
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};
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struct sx150x_123_pri {
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u8 reg_pld_mode;
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u8 reg_pld_table0;
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u8 reg_pld_table1;
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u8 reg_pld_table2;
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u8 reg_pld_table3;
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u8 reg_pld_table4;
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u8 reg_advanced;
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};
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struct sx150x_456_pri {
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u8 reg_pld_mode;
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u8 reg_pld_table0;
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u8 reg_pld_table1;
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u8 reg_pld_table2;
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u8 reg_pld_table3;
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u8 reg_pld_table4;
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u8 reg_advanced;
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};
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struct sx150x_789_pri {
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u8 reg_drain;
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u8 reg_polarity;
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u8 reg_clock;
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u8 reg_misc;
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u8 reg_reset;
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u8 ngpios;
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};
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struct sx150x_pin_desc {
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u32 pin;
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u8 *name;
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};
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struct sx150x_device_data {
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u8 model;
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u8 reg_pullup;
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u8 reg_pulldn;
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u8 reg_dir;
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u8 reg_data;
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u8 reg_irq_mask;
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u8 reg_irq_src;
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u8 reg_sense;
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u8 ngpios;
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union {
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struct sx150x_123_pri x123;
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struct sx150x_456_pri x456;
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struct sx150x_789_pri x789;
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} pri;
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const struct sx150x_pin_desc *pins;
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unsigned int npins;
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};
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struct sx150x_pinctrl_priv {
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char name[32];
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struct udevice *gpio;
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struct udevice *i2c;
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const struct sx150x_device_data *data;
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};
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static const struct sx150x_pin_desc sx150x_4_pins[] = {
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SX150X_PIN(0, "gpio0"), SX150X_PIN(1, "gpio1"), SX150X_PIN(2, "gpio2"),
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SX150X_PIN(3, "gpio3"), SX150X_PIN(4, "oscio"),
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};
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static const struct sx150x_pin_desc sx150x_8_pins[] = {
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SX150X_PIN(0, "gpio0"), SX150X_PIN(1, "gpio1"), SX150X_PIN(2, "gpio2"),
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SX150X_PIN(3, "gpio3"), SX150X_PIN(4, "gpio4"), SX150X_PIN(5, "gpio5"),
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SX150X_PIN(6, "gpio6"), SX150X_PIN(7, "gpio7"), SX150X_PIN(8, "oscio"),
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};
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static const struct sx150x_pin_desc sx150x_16_pins[] = {
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SX150X_PIN(0, "gpio0"), SX150X_PIN(1, "gpio1"),
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SX150X_PIN(2, "gpio2"), SX150X_PIN(3, "gpio3"),
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SX150X_PIN(4, "gpio4"), SX150X_PIN(5, "gpio5"),
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SX150X_PIN(6, "gpio6"), SX150X_PIN(7, "gpio7"),
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SX150X_PIN(8, "gpio8"), SX150X_PIN(9, "gpio9"),
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SX150X_PIN(10, "gpio10"), SX150X_PIN(11, "gpio11"),
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SX150X_PIN(12, "gpio12"), SX150X_PIN(13, "gpio13"),
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SX150X_PIN(14, "gpio14"), SX150X_PIN(15, "gpio15"),
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SX150X_PIN(16, "oscio"),
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};
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static const struct sx150x_device_data sx1501q_device_data = {
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.model = SX150X_123,
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.reg_pullup = 0x02,
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.reg_pulldn = 0x03,
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.reg_dir = 0x01,
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.reg_data = 0x00,
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.reg_irq_mask = 0x05,
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.reg_irq_src = 0x08,
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.reg_sense = 0x07,
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.pri.x123 = {
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.reg_pld_mode = 0x10,
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.reg_pld_table0 = 0x11,
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.reg_pld_table2 = 0x13,
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.reg_advanced = 0xad,
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},
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.ngpios = 4,
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.pins = sx150x_4_pins,
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.npins = 4, /* oscio not available */
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};
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static const struct sx150x_device_data sx1502q_device_data = {
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.model = SX150X_123,
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.reg_pullup = 0x02,
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.reg_pulldn = 0x03,
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.reg_dir = 0x01,
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.reg_data = 0x00,
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.reg_irq_mask = 0x05,
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.reg_irq_src = 0x08,
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.reg_sense = 0x06,
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.pri.x123 = {
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.reg_pld_mode = 0x10,
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.reg_pld_table0 = 0x11,
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.reg_pld_table1 = 0x12,
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.reg_pld_table2 = 0x13,
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.reg_pld_table3 = 0x14,
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.reg_pld_table4 = 0x15,
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.reg_advanced = 0xad,
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},
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.ngpios = 8,
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.pins = sx150x_8_pins,
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.npins = 8, /* oscio not available */
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};
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static const struct sx150x_device_data sx1503q_device_data = {
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.model = SX150X_123,
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.reg_pullup = 0x04,
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.reg_pulldn = 0x06,
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.reg_dir = 0x02,
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.reg_data = 0x00,
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.reg_irq_mask = 0x08,
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.reg_irq_src = 0x0e,
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.reg_sense = 0x0a,
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.pri.x123 = {
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.reg_pld_mode = 0x20,
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.reg_pld_table0 = 0x22,
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.reg_pld_table1 = 0x24,
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.reg_pld_table2 = 0x26,
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.reg_pld_table3 = 0x28,
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.reg_pld_table4 = 0x2a,
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.reg_advanced = 0xad,
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},
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.ngpios = 16,
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.pins = sx150x_16_pins,
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.npins = 16, /* oscio not available */
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};
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static const struct sx150x_device_data sx1504q_device_data = {
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.model = SX150X_456,
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.reg_pullup = 0x02,
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.reg_pulldn = 0x03,
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.reg_dir = 0x01,
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.reg_data = 0x00,
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.reg_irq_mask = 0x05,
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.reg_irq_src = 0x08,
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.reg_sense = 0x07,
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.pri.x456 = {
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.reg_pld_mode = 0x10,
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.reg_pld_table0 = 0x11,
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.reg_pld_table2 = 0x13,
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},
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.ngpios = 4,
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.pins = sx150x_4_pins,
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.npins = 4, /* oscio not available */
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};
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static const struct sx150x_device_data sx1505q_device_data = {
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.model = SX150X_456,
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.reg_pullup = 0x02,
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.reg_pulldn = 0x03,
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.reg_dir = 0x01,
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.reg_data = 0x00,
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.reg_irq_mask = 0x05,
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.reg_irq_src = 0x08,
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.reg_sense = 0x06,
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.pri.x456 = {
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.reg_pld_mode = 0x10,
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.reg_pld_table0 = 0x11,
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.reg_pld_table1 = 0x12,
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.reg_pld_table2 = 0x13,
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.reg_pld_table3 = 0x14,
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.reg_pld_table4 = 0x15,
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},
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.ngpios = 8,
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.pins = sx150x_8_pins,
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.npins = 8, /* oscio not available */
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};
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static const struct sx150x_device_data sx1506q_device_data = {
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.model = SX150X_456,
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.reg_pullup = 0x04,
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.reg_pulldn = 0x06,
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.reg_dir = 0x02,
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.reg_data = 0x00,
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.reg_irq_mask = 0x08,
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.reg_irq_src = 0x0e,
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.reg_sense = 0x0a,
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.pri.x456 = {
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.reg_pld_mode = 0x20,
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.reg_pld_table0 = 0x22,
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.reg_pld_table1 = 0x24,
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.reg_pld_table2 = 0x26,
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.reg_pld_table3 = 0x28,
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.reg_pld_table4 = 0x2a,
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.reg_advanced = 0xad,
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},
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.ngpios = 16,
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.pins = sx150x_16_pins,
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.npins = 16, /* oscio not available */
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};
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static const struct sx150x_device_data sx1507q_device_data = {
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.model = SX150X_789,
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.reg_pullup = 0x03,
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.reg_pulldn = 0x04,
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.reg_dir = 0x07,
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.reg_data = 0x08,
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.reg_irq_mask = 0x09,
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.reg_irq_src = 0x0b,
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.reg_sense = 0x0a,
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.pri.x789 = {
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.reg_drain = 0x05,
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.reg_polarity = 0x06,
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.reg_clock = 0x0d,
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.reg_misc = 0x0e,
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.reg_reset = 0x7d,
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},
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.ngpios = 4,
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.pins = sx150x_4_pins,
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.npins = ARRAY_SIZE(sx150x_4_pins),
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};
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static const struct sx150x_device_data sx1508q_device_data = {
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.model = SX150X_789,
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.reg_pullup = 0x03,
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.reg_pulldn = 0x04,
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.reg_dir = 0x07,
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.reg_data = 0x08,
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.reg_irq_mask = 0x09,
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.reg_irq_src = 0x0c,
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.reg_sense = 0x0a,
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.pri.x789 = {
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.reg_drain = 0x05,
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.reg_polarity = 0x06,
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.reg_clock = 0x0f,
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.reg_misc = 0x10,
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.reg_reset = 0x7d,
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},
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.ngpios = 8,
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.pins = sx150x_8_pins,
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.npins = ARRAY_SIZE(sx150x_8_pins),
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};
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static const struct sx150x_device_data sx1509q_device_data = {
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.model = SX150X_789,
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.reg_pullup = 0x06,
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.reg_pulldn = 0x08,
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.reg_dir = 0x0e,
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.reg_data = 0x10,
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.reg_irq_mask = 0x12,
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.reg_irq_src = 0x18,
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.reg_sense = 0x14,
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.pri.x789 = {
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.reg_drain = 0x0a,
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.reg_polarity = 0x0c,
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.reg_clock = 0x1e,
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.reg_misc = 0x1f,
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.reg_reset = 0x7d,
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},
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.ngpios = 16,
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.pins = sx150x_16_pins,
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.npins = ARRAY_SIZE(sx150x_16_pins),
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};
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static bool sx150x_pin_is_oscio(struct sx150x_pinctrl_priv *pctl,
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unsigned int pin)
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{
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if (pin >= pctl->data->npins)
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return false;
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/* OSCIO pin is only present in 789 devices */
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if (pctl->data->model != SX150X_789)
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return false;
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return !strcmp(pctl->data->pins[pin].name, "oscio");
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}
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static int sx150x_reg_width(struct sx150x_pinctrl_priv *pctl, unsigned int reg)
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{
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const struct sx150x_device_data *data = pctl->data;
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if (reg == data->reg_sense) {
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/*
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* RegSense packs two bits of configuration per GPIO,
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* so we'd need to read twice as many bits as there
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* are GPIO in our chip
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*/
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return 2 * data->ngpios;
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} else if ((data->model == SX150X_789 &&
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(reg == data->pri.x789.reg_misc ||
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reg == data->pri.x789.reg_clock ||
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reg == data->pri.x789.reg_reset)) ||
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(data->model == SX150X_123 &&
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reg == data->pri.x123.reg_advanced) ||
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(data->model == SX150X_456 && data->pri.x456.reg_advanced &&
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reg == data->pri.x456.reg_advanced)) {
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return 8;
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} else {
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return data->ngpios;
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}
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}
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static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl_priv *pctl,
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unsigned int reg, unsigned int val)
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{
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unsigned int a, b;
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const struct sx150x_device_data *data = pctl->data;
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/*
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* Whereas SX1509 presents RegSense in a simple layout as such:
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* reg [ f f e e d d c c ]
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* reg 1 [ b b a a 9 9 8 8 ]
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* reg 2 [ 7 7 6 6 5 5 4 4 ]
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* reg 3 [ 3 3 2 2 1 1 0 0 ]
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*
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* SX1503 and SX1506 deviate from that data layout, instead storing
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* their contents as follows:
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*
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* reg [ f f e e d d c c ]
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* reg 1 [ 7 7 6 6 5 5 4 4 ]
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* reg 2 [ b b a a 9 9 8 8 ]
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* reg 3 [ 3 3 2 2 1 1 0 0 ]
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*
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* so, taking that into account, we swap two
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* inner bytes of a 4-byte result
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*/
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if (reg == data->reg_sense && data->ngpios == 16 &&
|
||||
(data->model == SX150X_123 || data->model == SX150X_456)) {
|
||||
a = val & 0x00ff0000;
|
||||
b = val & 0x0000ff00;
|
||||
|
||||
val &= 0xff0000ff;
|
||||
val |= b << 8;
|
||||
val |= a >> 8;
|
||||
}
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
/*
|
||||
* In order to mask the differences between 16 and 8 bit expander
|
||||
* devices we set up a sligthly ficticious regmap that pretends to be
|
||||
* a set of 32-bit (to accommodate RegSenseLow/RegSenseHigh
|
||||
* pair/quartet) registers and transparently reconstructs those
|
||||
* registers via multiple I2C/SMBus reads
|
||||
*
|
||||
* This way the rest of the driver code, interfacing with the chip via
|
||||
* regmap API, can work assuming that each GPIO pin is represented by
|
||||
* a group of bits at an offset proportional to GPIO number within a
|
||||
* given register.
|
||||
*/
|
||||
static int sx150x_reg_read(struct sx150x_pinctrl_priv *pctl, unsigned int reg,
|
||||
unsigned int *result)
|
||||
{
|
||||
int ret, n;
|
||||
const int width = sx150x_reg_width(pctl, reg);
|
||||
unsigned int idx, val;
|
||||
|
||||
/*
|
||||
* There are four potential cases covered by this function:
|
||||
*
|
||||
* 1) 8-pin chip, single configuration bit register
|
||||
*
|
||||
* This is trivial the code below just needs to read:
|
||||
* reg [ 7 6 5 4 3 2 1 0 ]
|
||||
*
|
||||
* 2) 8-pin chip, double configuration bit register (RegSense)
|
||||
*
|
||||
* The read will be done as follows:
|
||||
* reg [ 7 7 6 6 5 5 4 4 ]
|
||||
* reg 1 [ 3 3 2 2 1 1 0 0 ]
|
||||
*
|
||||
* 3) 16-pin chip, single configuration bit register
|
||||
*
|
||||
* The read will be done as follows:
|
||||
* reg [ f e d c b a 9 8 ]
|
||||
* reg 1 [ 7 6 5 4 3 2 1 0 ]
|
||||
*
|
||||
* 4) 16-pin chip, double configuration bit register (RegSense)
|
||||
*
|
||||
* The read will be done as follows:
|
||||
* reg [ f f e e d d c c ]
|
||||
* reg 1 [ b b a a 9 9 8 8 ]
|
||||
* reg 2 [ 7 7 6 6 5 5 4 4 ]
|
||||
* reg 3 [ 3 3 2 2 1 1 0 0 ]
|
||||
*/
|
||||
|
||||
for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx) {
|
||||
val <<= 8;
|
||||
|
||||
ret = dm_i2c_reg_read(pctl->i2c, idx);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
val |= ret;
|
||||
}
|
||||
|
||||
*result = sx150x_maybe_swizzle(pctl, reg, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sx150x_reg_write(struct sx150x_pinctrl_priv *pctl, unsigned int reg,
|
||||
unsigned int val)
|
||||
{
|
||||
int ret, n;
|
||||
const int width = sx150x_reg_width(pctl, reg);
|
||||
|
||||
val = sx150x_maybe_swizzle(pctl, reg, val);
|
||||
|
||||
n = (width - 1) & ~7;
|
||||
do {
|
||||
const u8 byte = (val >> n) & 0xff;
|
||||
|
||||
ret = dm_i2c_reg_write(pctl->i2c, reg, byte);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
reg;
|
||||
n -= 8;
|
||||
} while (n >= 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned int sx150x_read(struct sx150x_pinctrl_priv *pctl, uint reg)
|
||||
{
|
||||
int ret;
|
||||
unsigned int res;
|
||||
|
||||
ret = sx150x_reg_read(pctl, reg, &res);
|
||||
if (ret) {
|
||||
err("%s: failed to read reg(%x) with %d", pctl->name, reg, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
static int sx150x_write(struct sx150x_pinctrl_priv *pctl, uint reg, uint val)
|
||||
{
|
||||
return sx150x_reg_write(pctl, reg, val);
|
||||
}
|
||||
|
||||
static int sx150x_write_bits(struct sx150x_pinctrl_priv *pctl, uint reg,
|
||||
uint mask, uint val)
|
||||
{
|
||||
int orig, tmp;
|
||||
|
||||
orig = sx150x_read(pctl, reg);
|
||||
if (orig < 0)
|
||||
return orig;
|
||||
|
||||
tmp = orig & ~mask;
|
||||
tmp |= val & mask;
|
||||
|
||||
return sx150x_write(pctl, reg, tmp);
|
||||
}
|
||||
|
||||
static int sx150x_reset(struct udevice *dev)
|
||||
{
|
||||
struct sx150x_pinctrl_priv *pctl = dev_get_priv(dev);
|
||||
int err;
|
||||
|
||||
err = sx150x_write(pctl, pctl->data->pri.x789.reg_reset,
|
||||
SX150X_789_RESET_KEY1);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
err = sx150x_write(pctl, pctl->data->pri.x789.reg_reset,
|
||||
SX150X_789_RESET_KEY2);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int sx150x_init_misc(struct udevice *dev)
|
||||
{
|
||||
struct sx150x_pinctrl_priv *pctl = dev_get_priv(dev);
|
||||
u8 reg, value;
|
||||
|
||||
switch (pctl->data->model) {
|
||||
case SX150X_789:
|
||||
reg = pctl->data->pri.x789.reg_misc;
|
||||
value = 0x0;
|
||||
break;
|
||||
case SX150X_456:
|
||||
reg = pctl->data->pri.x456.reg_advanced;
|
||||
value = 0x00;
|
||||
|
||||
/*
|
||||
* Only SX1506 has RegAdvanced, SX1504/5 are expected
|
||||
* to initialize this offset to zero
|
||||
*/
|
||||
if (!reg)
|
||||
return 0;
|
||||
break;
|
||||
case SX150X_123:
|
||||
reg = pctl->data->pri.x123.reg_advanced;
|
||||
value = 0x00;
|
||||
break;
|
||||
default:
|
||||
WARN(1, "Unknown chip model %d\n", pctl->data->model);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return sx150x_write(pctl, reg, value);
|
||||
}
|
||||
|
||||
static int sx150x_init_hw(struct udevice *dev)
|
||||
{
|
||||
struct sx150x_pinctrl_priv *pctl = dev_get_priv(dev);
|
||||
const u8 reg[] = {
|
||||
[SX150X_789] = pctl->data->pri.x789.reg_polarity,
|
||||
[SX150X_456] = pctl->data->pri.x456.reg_pld_mode,
|
||||
[SX150X_123] = pctl->data->pri.x123.reg_pld_mode,
|
||||
};
|
||||
int err;
|
||||
|
||||
if (pctl->data->model == SX150X_789 &&
|
||||
dev_read_bool(dev, "semtech,probe-reset")) {
|
||||
err = sx150x_reset(dev);
|
||||
if (err < 0)
|
||||
return err;
|
||||
}
|
||||
|
||||
err = sx150x_init_misc(dev);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
/* Set all pins to work in normal mode */
|
||||
return sx150x_write(pctl, reg[pctl->data->model], 0);
|
||||
}
|
||||
|
||||
static int sx150x_gpio_get_value(struct udevice *dev, unsigned int offset)
|
||||
{
|
||||
struct sx150x_pinctrl_priv *pctl = dev_get_priv(dev->parent);
|
||||
|
||||
if (sx150x_pin_is_oscio(pctl, offset))
|
||||
return -EINVAL;
|
||||
|
||||
int val = sx150x_read(pctl, pctl->data->reg_data);
|
||||
|
||||
return !!(val & BIT(offset));
|
||||
}
|
||||
|
||||
static int sx150x_gpio_set(struct udevice *dev, unsigned int offset, int value)
|
||||
{
|
||||
struct sx150x_pinctrl_priv *pctl = dev_get_priv(dev->parent);
|
||||
|
||||
return sx150x_write_bits(pctl, pctl->data->reg_data, BIT(offset),
|
||||
value ? BIT(offset) : 0);
|
||||
}
|
||||
|
||||
static int sx150x_gpio_oscio_set(struct udevice *dev, int value)
|
||||
{
|
||||
struct sx150x_pinctrl_priv *pctl = dev_get_priv(dev->parent);
|
||||
|
||||
return sx150x_write(pctl, pctl->data->pri.x789.reg_clock,
|
||||
(value ? 0x1f : 0x10));
|
||||
}
|
||||
|
||||
static int sx150x_gpio_set_value(struct udevice *dev, unsigned int offset,
|
||||
int value)
|
||||
{
|
||||
struct sx150x_pinctrl_priv *pctl = dev_get_priv(dev->parent);
|
||||
|
||||
if (sx150x_pin_is_oscio(pctl, offset))
|
||||
sx150x_gpio_oscio_set(dev->parent, value);
|
||||
else
|
||||
sx150x_gpio_set(dev->parent, offset, value);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sx150x_gpio_get_direction(struct udevice *dev, unsigned int offset)
|
||||
{
|
||||
struct sx150x_pinctrl_priv *pctl = dev_get_priv(dev->parent);
|
||||
int val;
|
||||
|
||||
if (sx150x_pin_is_oscio(pctl, offset))
|
||||
return GPIOF_OUTPUT;
|
||||
|
||||
val = sx150x_read(pctl, pctl->data->reg_data);
|
||||
if (val < 0)
|
||||
return val;
|
||||
|
||||
if (val & BIT(offset))
|
||||
return GPIOF_INPUT;
|
||||
|
||||
return GPIOF_OUTPUT;
|
||||
}
|
||||
|
||||
static int sx150x_gpio_direction_input(struct udevice *dev, unsigned int offset)
|
||||
{
|
||||
struct sx150x_pinctrl_priv *pctl = dev_get_priv(dev->parent);
|
||||
|
||||
if (sx150x_pin_is_oscio(pctl, offset))
|
||||
return -EINVAL;
|
||||
|
||||
return sx150x_write_bits(pctl, pctl->data->reg_dir, BIT(offset),
|
||||
BIT(offset));
|
||||
}
|
||||
|
||||
static int sx150x_gpio_direction_output(struct udevice *dev,
|
||||
unsigned int offset, int value)
|
||||
{
|
||||
struct sx150x_pinctrl_priv *pctl = dev_get_priv(dev->parent);
|
||||
int ret;
|
||||
|
||||
if (sx150x_pin_is_oscio(pctl, offset))
|
||||
return sx150x_gpio_oscio_set(dev, value);
|
||||
|
||||
ret = sx150x_write_bits(pctl, pctl->data->reg_dir, BIT(offset), 0);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return sx150x_gpio_set(dev, offset, value);
|
||||
}
|
||||
|
||||
static int sx150x_gpio_probe(struct udevice *dev)
|
||||
{
|
||||
struct sx150x_pinctrl_priv *pctl = dev_get_priv(dev->parent);
|
||||
struct gpio_dev_priv *uc_priv;
|
||||
|
||||
uc_priv = dev_get_uclass_priv(dev);
|
||||
uc_priv->bank_name = pctl->name;
|
||||
uc_priv->gpio_count = pctl->data->ngpios;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct dm_gpio_ops sx150x_gpio_ops = {
|
||||
.get_value = sx150x_gpio_get_value,
|
||||
.set_value = sx150x_gpio_set_value,
|
||||
.get_function = sx150x_gpio_get_direction,
|
||||
.direction_input = sx150x_gpio_direction_input,
|
||||
.direction_output = sx150x_gpio_direction_output,
|
||||
};
|
||||
|
||||
static struct driver sx150x_gpio_driver = {
|
||||
.name = "sx150x-gpio",
|
||||
.id = UCLASS_GPIO,
|
||||
.probe = sx150x_gpio_probe,
|
||||
.ops = &sx150x_gpio_ops,
|
||||
};
|
||||
|
||||
static const struct udevice_id sx150x_pinctrl_of_match[] = {
|
||||
{ .compatible = "semtech,sx1501q",
|
||||
.data = (ulong)&sx1501q_device_data },
|
||||
{ .compatible = "semtech,sx1502q",
|
||||
.data = (ulong)&sx1502q_device_data },
|
||||
{ .compatible = "semtech,sx1503q",
|
||||
.data = (ulong)&sx1503q_device_data },
|
||||
{ .compatible = "semtech,sx1504q",
|
||||
.data = (ulong)&sx1504q_device_data },
|
||||
{ .compatible = "semtech,sx1505q",
|
||||
.data = (ulong)&sx1505q_device_data },
|
||||
{ .compatible = "semtech,sx1506q",
|
||||
.data = (ulong)&sx1506q_device_data },
|
||||
{ .compatible = "semtech,sx1507q",
|
||||
.data = (ulong)&sx1507q_device_data },
|
||||
{ .compatible = "semtech,sx1508q",
|
||||
.data = (ulong)&sx1508q_device_data },
|
||||
{ .compatible = "semtech,sx1509q",
|
||||
.data = (ulong)&sx1509q_device_data },
|
||||
{},
|
||||
};
|
||||
|
||||
static const struct pinconf_param sx150x_conf_params[] = {
|
||||
{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
|
||||
{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
|
||||
{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
|
||||
{ "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 },
|
||||
{ "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 },
|
||||
{ "output", PIN_CONFIG_OUTPUT, 0 },
|
||||
};
|
||||
|
||||
static int sx150x_pinctrl_get_pins_count(struct udevice *dev)
|
||||
{
|
||||
struct sx150x_pinctrl_priv *pctl = dev_get_priv(dev);
|
||||
|
||||
return pctl->data->ngpios;
|
||||
}
|
||||
|
||||
static const char *sx150x_pinctrl_get_pin_name(struct udevice *dev,
|
||||
unsigned int selector)
|
||||
{
|
||||
struct sx150x_pinctrl_priv *pctl = dev_get_priv(dev);
|
||||
static char pin_name[PINNAME_SIZE];
|
||||
|
||||
snprintf(pin_name, PINNAME_SIZE, "%s", pctl->data->pins[selector].name);
|
||||
return pin_name;
|
||||
}
|
||||
|
||||
static int sx150x_pinctrl_conf_set(struct udevice *dev, unsigned int pin,
|
||||
unsigned int param, unsigned int arg)
|
||||
{
|
||||
int ret;
|
||||
struct sx150x_pinctrl_priv *pctl = dev_get_priv(dev);
|
||||
|
||||
if (sx150x_pin_is_oscio(pctl, pin)) {
|
||||
if (param == PIN_CONFIG_OUTPUT) {
|
||||
ret = sx150x_gpio_direction_output(pctl->gpio, pin,
|
||||
arg);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
} else {
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
}
|
||||
|
||||
switch (param) {
|
||||
case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
|
||||
case PIN_CONFIG_BIAS_DISABLE:
|
||||
ret = sx150x_write_bits(pctl, pctl->data->reg_pulldn, BIT(pin),
|
||||
0);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = sx150x_write_bits(pctl, pctl->data->reg_pullup, BIT(pin),
|
||||
0);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
ret = sx150x_write_bits(pctl, pctl->data->reg_pullup, BIT(pin),
|
||||
BIT(pin));
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
ret = sx150x_write_bits(pctl, pctl->data->reg_pulldn, BIT(pin),
|
||||
BIT(pin));
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
|
||||
if (pctl->data->model != SX150X_789 ||
|
||||
sx150x_pin_is_oscio(pctl, pin))
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
ret = sx150x_write_bits(pctl, pctl->data->pri.x789.reg_drain,
|
||||
BIT(pin), BIT(pin));
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_DRIVE_PUSH_PULL:
|
||||
if (pctl->data->model != SX150X_789 ||
|
||||
sx150x_pin_is_oscio(pctl, pin))
|
||||
return 0;
|
||||
|
||||
ret = sx150x_write_bits(pctl, pctl->data->pri.x789.reg_drain,
|
||||
BIT(pin), 0);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_OUTPUT:
|
||||
ret = sx150x_gpio_direction_output(pctl->gpio, pin, arg);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
break;
|
||||
default:
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sx150x_pinctrl_bind(struct udevice *dev)
|
||||
{
|
||||
struct sx150x_pinctrl_priv *pctl = dev_get_plat(dev);
|
||||
int ret, reg;
|
||||
|
||||
if (!dev_read_bool(dev, "gpio-controller"))
|
||||
return 0;
|
||||
|
||||
reg = (int)dev_read_addr_ptr(dev);
|
||||
|
||||
ret = device_bind(dev, &sx150x_gpio_driver, dev_read_name(dev), NULL,
|
||||
dev_ofnode(dev), &pctl->gpio);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sx150x_pinctrl_probe(struct udevice *dev)
|
||||
{
|
||||
struct sx150x_pinctrl_priv *pctl = dev_get_priv(dev);
|
||||
const struct sx150x_device_data *drv_data =
|
||||
(const struct sx150x_device_data *)dev_get_driver_data(dev);
|
||||
int ret, reg;
|
||||
|
||||
if (!drv_data)
|
||||
return -ENOENT;
|
||||
|
||||
pctl->data = drv_data;
|
||||
|
||||
reg = (int)dev_read_addr_ptr(dev);
|
||||
ret = dm_i2c_probe(dev->parent, reg, 0, &pctl->i2c);
|
||||
if (ret) {
|
||||
err("Cannot find I2C chip %02x (%d)", reg, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = sx150x_init_hw(dev);
|
||||
if (ret) {
|
||||
err("Cannot initialize GPIO expander at %02x with %d", reg,
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
snprintf(pctl->name, 32, "gpio-ext@%x_", reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct pinctrl_ops sx150x_pinctrl_ops = {
|
||||
.set_state = pinctrl_generic_set_state,
|
||||
.get_pins_count = sx150x_pinctrl_get_pins_count,
|
||||
.get_pin_name = sx150x_pinctrl_get_pin_name,
|
||||
#if CONFIG_IS_ENABLED(PINCONF)
|
||||
.pinconf_set = sx150x_pinctrl_conf_set,
|
||||
.pinconf_num_params = ARRAY_SIZE(sx150x_conf_params),
|
||||
.pinconf_params = sx150x_conf_params,
|
||||
#endif
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(sx150x_pinctrl) = {
|
||||
.name = "sx150x-pinctrl",
|
||||
.id = UCLASS_PINCTRL,
|
||||
.of_match = sx150x_pinctrl_of_match,
|
||||
.priv_auto = sizeof(struct sx150x_pinctrl_priv),
|
||||
.ops = &sx150x_pinctrl_ops,
|
||||
.probe = sx150x_pinctrl_probe,
|
||||
.bind = sx150x_pinctrl_bind,
|
||||
};
|
||||
Loading…
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Reference in New Issue
Block a user