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board: verdin-imx8mp: update ddrc config for different lpddr4 memories

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Add support to Verdin IMX8MP V1.1B SKU which uses
MT53E1G32D2FW-046 WT:B memory.
Compared to the 8 GB memory (MT53E2G32D4NQ-046 WT:A) used on
Verdin IMX8MP V1.0A it has 16 row addresses instead of 17.
In fact, the new memory, is a 2 GB/rank memory. The 8 GB memory is a
4 GB/rank memory.

Manually tweaking Host Interface addresses vs LPDDR4 signals mapping it
is possible to have a single configuration working with both memories:
 - Old configuration: HIF bit 30 -> rank, HIF bit 29 -> Row 16
 - New configuration: HIF bit 29 -> rank, HIF bit 30 -> Row 16

With this change the memory space from the host processor is contiguous
for both the configurations and the correct memory size is computed
using get_ram_size() at runtime.

Support for single rank memories still works thanks to the fact
dual ranks training fails (ddr_init->ddr_cfg_phy) toward single rank
memories.

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
This commit is contained in:
Emanuele Ghidoli 2023-04-03 14:01:53 +02:00 committed by Stefano Babic
parent bc1bcd272e
commit 54351fe542
2 changed files with 4 additions and 5 deletions
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4
board/toradex/verdin-imx8mp/lpddr4_timing.c
View File

@ -55,13 +55,13 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d4001c4, 0x1 }, { 0x3d4001c4, 0x1 },
{ 0x3d4000f4, 0xc99 }, { 0x3d4000f4, 0xc99 },
{ 0x3d400108, 0x9121c1c }, { 0x3d400108, 0x9121c1c },
{ 0x3d400200, 0x18 }, { 0x3d400200, 0x17 },
{ 0x3d40020c, 0x0 }, { 0x3d40020c, 0x0 },
{ 0x3d400210, 0x1f1f }, { 0x3d400210, 0x1f1f },
{ 0x3d400204, 0x80808 }, { 0x3d400204, 0x80808 },
{ 0x3d400214, 0x7070707 }, { 0x3d400214, 0x7070707 },
{ 0x3d400218, 0x7070707 }, { 0x3d400218, 0x7070707 },
{ 0x3d40021c, 0xf07 }, { 0x3d40021c, 0xf08 },
{ 0x3d400250, 0x1705 }, { 0x3d400250, 0x1705 },
{ 0x3d400254, 0x2c }, { 0x3d400254, 0x2c },
{ 0x3d40025c, 0x4000030 }, { 0x3d40025c, 0x4000030 },

5
board/toradex/verdin-imx8mp/spl.c
View File

@ -34,11 +34,10 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
void spl_dram_init(void) void spl_dram_init(void)
{ {
/* /*
* try configuring for quad die, dual rank aka 8 GB falling back to * Try configuring for dual rank memory falling back to single rank
* dual die, single rank aka 1 GB (untested), 2 GB or 4 GB if it fails
*/ */
if (ddr_init(&dram_timing)) { if (ddr_init(&dram_timing)) {
printf("Quad die, dual rank failed, attempting dual die, single rank configuration.\n"); printf("Dual rank failed, attempting single rank configuration.\n");
ddr_init(&dram_timing2); ddr_init(&dram_timing2);
} }
} }