From fcabdf1e7c9616b27b682010889e9139851dc785 Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Wed, 12 Oct 2022 11:03:45 +0200 Subject: [PATCH 01/19] microblaze: Make extended addressing support default Axi qspi controller supports 32-bit & 24-bit addressing modes for micron, macronix & spansion flash parts. But for winbond flashes it only supports 24-bit addressing mode. Enable CONFIG_SPI_FLASH_BAR to use extended addressing mode to make 32-bit addressing mode work on all flashes. Signed-off-by: T Karthik Reddy Acked-by: Ashok Reddy Soma Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/f3864966c8ddd766a1702ad61b0e008a1f57462f.1665565423.git.michal.simek@amd.com --- configs/microblaze-generic_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 1a23dc51d6e..f1b9cb461b9 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -71,6 +71,7 @@ CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=2048 +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y From 7b84fe768402f5b2e64945a75578312b6eb03d2e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 12 Oct 2022 11:35:30 +0200 Subject: [PATCH 02/19] arm64: zynqmp: Disable watchdog by default for virt platform Disable watchdog based on request in past that not all Linux rootfs have proper utilities ready to service it. Enable it if your rootfs have proper watchdog handling. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/62dfc08f32635abee42feab26aaa9efed52134c0.1665567328.git.michal.simek@amd.com --- configs/xilinx_zynqmp_virt_defconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index ea111272366..9696e418daf 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -81,7 +81,6 @@ CONFIG_CMD_SF_TEST=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_WDT=y CONFIG_BOOTP_MAY_FAIL=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_TFTPPUT=y @@ -229,7 +228,6 @@ CONFIG_SPLASH_SCREEN=y CONFIG_BMP_16BPP=y CONFIG_BMP_24BPP=y CONFIG_BMP_32BPP=y -CONFIG_WDT=y CONFIG_PANIC_HANG=y CONFIG_TPM=y CONFIG_SPL_GZIP=y From 716527299a496afcbf495d38bd9e5edfd71ce120 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 13 Oct 2022 13:05:39 +0200 Subject: [PATCH 03/19] Revert "pinctrl: zynqmp: Add support for output-enable and bias-high-impedance" This reverts commit 123462e5e534d6e17b1b7d2006734bbe54b03e0a. On systems with older PMUFW using these pinctrl properties can cause system hang because there is missing feature autodetection. When it is implemented support for these two properties should go back. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/c2900319ea80484f21692997f296269aee701c1f.1665659138.git.michal.simek@amd.com --- drivers/pinctrl/pinctrl-zynqmp.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index 52d428f566f..7c5a02db1b9 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -467,10 +467,6 @@ static int zynqmp_pinconf_set(struct udevice *dev, unsigned int pin, pin); break; case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: - param = PM_PINCTRL_CONFIG_TRI_STATE; - arg = PM_PINCTRL_TRI_STATE_ENABLE; - ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); - break; case PIN_CONFIG_LOW_POWER_MODE: /* * This cases are mentioned in dts but configurable @@ -479,11 +475,6 @@ static int zynqmp_pinconf_set(struct udevice *dev, unsigned int pin, */ ret = 0; break; - case PIN_CONFIG_OUTPUT_ENABLE: - param = PM_PINCTRL_CONFIG_TRI_STATE; - arg = PM_PINCTRL_TRI_STATE_DISABLE; - ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); - break; default: dev_warn(dev, "unsupported configuration parameter '%u'\n", param); From ba74bcf3e07b10ffebf42e72a656b420215b5a2e Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Mon, 17 Oct 2022 15:18:18 +0530 Subject: [PATCH 04/19] xilinx: common: Remove zynq_board_read_rom_ethaddr() Removing the zynq_board_read_rom_ethaddr() function as xlnx,eeprom is not used anymore. As all board dts to use nvmem alias instead of xlnx,eeprom. Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20221017094818.17996-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- arch/arm/mach-zynq/include/mach/sys_proto.h | 2 -- arch/arm/mach-zynqmp/include/mach/sys_proto.h | 1 - board/xilinx/common/board.c | 28 ------------------- drivers/net/zynq_gem.c | 16 ----------- 4 files changed, 47 deletions(-) diff --git a/arch/arm/mach-zynq/include/mach/sys_proto.h b/arch/arm/mach-zynq/include/mach/sys_proto.h index 1dc16d479ea..268ec50ad84 100644 --- a/arch/arm/mach-zynq/include/mach/sys_proto.h +++ b/arch/arm/mach-zynq/include/mach/sys_proto.h @@ -17,6 +17,4 @@ extern int zynq_slcr_get_mio_pin_status(const char *periph); extern void zynq_ddrc_init(void); extern unsigned int zynq_get_silicon_version(void); -int zynq_board_read_rom_ethaddr(unsigned char *ethaddr); - #endif /* _SYS_PROTO_H_ */ diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index 9fffb4e541c..c6733ed1bbe 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -46,7 +46,6 @@ enum { TCM_SPLIT, }; -int zynq_board_read_rom_ethaddr(unsigned char *ethaddr); unsigned int zynqmp_get_silicon_version(void); int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 99fdbac639b..59d87f23520 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -54,34 +54,6 @@ struct efi_capsule_update_info update_info = { u8 num_image_type_guids = ARRAY_SIZE(fw_images); #endif /* EFI_HAVE_CAPSULE_SUPPORT */ -#if defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) -int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) -{ - int ret = -EINVAL; - struct udevice *dev; - ofnode eeprom; - - eeprom = ofnode_get_chosen_node("xlnx,eeprom"); - if (!ofnode_valid(eeprom)) - return -ENODEV; - - debug("%s: Path to EEPROM %s\n", __func__, - ofnode_read_chosen_string("xlnx,eeprom")); - - ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev); - if (ret) - return ret; - - ret = dm_i2c_read(dev, CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, ethaddr, 6); - if (ret) - debug("%s: I2C EEPROM MAC address read failed\n", __func__); - else - debug("%s: I2C EEPROM MAC %pM\n", __func__, ethaddr); - - return ret; -} -#endif - #define EEPROM_HEADER_MAGIC 0xdaaddeed #define EEPROM_HDR_MANUFACTURER_LEN 16 #define EEPROM_HDR_NAME_LEN 16 diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 3f4357ec80b..507b19b7597 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -662,21 +662,6 @@ static void zynq_gem_halt(struct udevice *dev) ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); } -__weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) -{ - return -ENOSYS; -} - -static int zynq_gem_read_rom_mac(struct udevice *dev) -{ - struct eth_pdata *pdata = dev_get_plat(dev); - - if (!pdata) - return -ENOSYS; - - return zynq_board_read_rom_ethaddr(pdata->enetaddr); -} - static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg) { @@ -884,7 +869,6 @@ static const struct eth_ops zynq_gem_ops = { .free_pkt = zynq_gem_free_pkt, .stop = zynq_gem_halt, .write_hwaddr = zynq_gem_setup_mac, - .read_rom_hwaddr = zynq_gem_read_rom_mac, }; static int zynq_gem_of_to_plat(struct udevice *dev) From 1e766a04c723e003c001c0f1a4f301aef026a75e Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Wed, 12 Oct 2022 08:36:54 +0300 Subject: [PATCH 05/19] timer-uclass: add timer_get_ops() macro Align timer uclass with the other subsystems and provide a timer_get_ops() convenience macro. Using this instead of the generic device_get_ops() also prevents -Wdiscarded-qualifiers warnings when used with non-const variables. Signed-off-by: Ovidiu Panait Reviewed-by: Simon Glass Link: https://lore.kernel.org/r/20221012053656.1492457-1-ovpanait@gmail.com Signed-off-by: Michal Simek --- drivers/timer/timer-uclass.c | 2 +- include/timer.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c index cbc36476987..bdc77b38223 100644 --- a/drivers/timer/timer-uclass.c +++ b/drivers/timer/timer-uclass.c @@ -32,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR; int notrace timer_get_count(struct udevice *dev, u64 *count) { - const struct timer_ops *ops = device_get_ops(dev); + struct timer_ops *ops = timer_get_ops(dev); if (!ops->get_count) return -ENOSYS; diff --git a/include/timer.h b/include/timer.h index a044cb034ed..d33a26e28fe 100644 --- a/include/timer.h +++ b/include/timer.h @@ -6,6 +6,8 @@ #ifndef _TIMER_H_ #define _TIMER_H_ +#define timer_get_ops(dev) ((struct timer_ops *)(dev)->driver->ops) + /** * dm_timer_init() - initialize a timer for time keeping. On success * initializes gd->timer so that lib/timer can use it for future From 8272d4cb897ca15eef2f39afe488f6731312e5c2 Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Wed, 12 Oct 2022 08:36:55 +0300 Subject: [PATCH 06/19] timer-uclass: relocate ops pointers for CONFIG_NEEDS_MANUAL_RELOC Relocate timer_ops pointers when CONFIG_NEEDS_MANUAL_RELOC is enabled. The (gd->flags & GD_FLG_RELOC) check was added to make sure the reloc_done logic works for drivers that use DM_FLAG_PRE_RELOC. Signed-off-by: Ovidiu Panait Reviewed-by: Simon Glass Link: https://lore.kernel.org/r/20221012053656.1492457-2-ovpanait@gmail.com Signed-off-by: Michal Simek --- drivers/timer/timer-uclass.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c index bdc77b38223..bb719792135 100644 --- a/drivers/timer/timer-uclass.c +++ b/drivers/timer/timer-uclass.c @@ -18,6 +18,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -50,6 +51,19 @@ unsigned long notrace timer_get_rate(struct udevice *dev) static int timer_pre_probe(struct udevice *dev) { + if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC) && + (gd->flags & GD_FLG_RELOC)) { + struct timer_ops *ops = timer_get_ops(dev); + static int reloc_done; + + if (!reloc_done) { + if (ops->get_count) + MANUAL_RELOC(ops->get_count); + + reloc_done++; + } + } + if (CONFIG_IS_ENABLED(OF_REAL)) { struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); struct clk timer_clk; From b34bc22bd9921547246c117fb95eb58bedaceff5 Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Wed, 12 Oct 2022 08:36:56 +0300 Subject: [PATCH 07/19] timer: xilinx-timer: use timer_conv_64() to fix timer wrap around Current xilinx_timer_get_count() implementation does not take into account the periodic 32-bit wrap arounds, as it directly returns the 32-bit counter register value. The roll-overs cause problems in the upper timer layers, as generic timer code expects an incrementing 64-bit value from get_count() to work correctly. Add the missing 64-bit up-conversion to fix random hangs/delays in __udelay(). Fixes: a36d86720f ("microblaze: Convert axi timer to DM driver") Signed-off-by: Ovidiu Panait Reviewed-by: Michal Simek Link: https://lore.kernel.org/r/20221012053656.1492457-3-ovpanait@gmail.com Signed-off-by: Michal Simek --- drivers/timer/xilinx-timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/timer/xilinx-timer.c b/drivers/timer/xilinx-timer.c index 75b4473b639..172fd9f9296 100644 --- a/drivers/timer/xilinx-timer.c +++ b/drivers/timer/xilinx-timer.c @@ -40,7 +40,7 @@ static u64 xilinx_timer_get_count(struct udevice *dev) regmap_read(priv->regs, TIMER_COUNTER_OFFSET, &value); - return value; + return timer_conv_64(value); } static int xilinx_timer_probe(struct udevice *dev) From 96dcde487e7ece6de437a55175f9a5ec5c4ecd59 Mon Sep 17 00:00:00 2001 From: Christian Kohn Date: Wed, 12 Oct 2022 11:30:33 +0200 Subject: [PATCH 08/19] ARM: zynq: DT: Enable all FCLKs by default The fclk-enable property is set to 0 which disables all FCLKs. Enable all FCLKs so they can be used as clock sources in the programmable logic. Signed-off-by: Christian Kohn Acked-by: Soren Brinkmann Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/b1308dc1f14f8eb24662019f7376c959e5e763b8.1665567031.git.michal.simek@amd.com --- arch/arm/dts/zynq-7000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index edc147d63f1..f72ef526f05 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -340,7 +340,7 @@ u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; - fclk-enable = <0>; + fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", From 2e9946aba8e770a626ea5b9a23c95981569d6e61 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 31 Oct 2022 17:08:44 -0700 Subject: [PATCH 09/19] net: phy: Fix ethernet-phy-id in the code Use dot instead of comma. The fix doesn't affect anything but it is good to be aligned with used pattern. The first is used only for string size calculation and the second change is in the comment. Fixes: db681d4929ca ("net: phy: Add new read ethernet phy id function") Signed-off-by: Michal Simek --- drivers/core/ofnode.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 14bbfe72327..4d56b1a7675 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -1197,12 +1197,12 @@ int ofnode_read_eth_phy_id(ofnode node, u16 *vendor, u16 *device) while (list < end) { len = strlen(list); - if (len >= strlen("ethernet-phy-idVVVV,DDDD")) { + if (len >= strlen("ethernet-phy-idVVVV.DDDD")) { char *s = strstr(list, "ethernet-phy-id"); /* * check if the string is something like - * ethernet-phy-idVVVV,DDDD + * ethernet-phy-idVVVV.DDDD */ if (s && s[19] == '.') { s += strlen("ethernet-phy-id"); From 7ca9662d7f6b96e5fcbe7d52b90523261102f6d1 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 26 Oct 2022 09:38:00 +0200 Subject: [PATCH 10/19] arm64: zynqmp: Create vck190 spl link for revB vck190 system controller low level setup is the same for revB that's why also create symlink to revA. Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp-e-a2197-00-revB | 1 + 1 file changed, 1 insertion(+) create mode 120000 board/xilinx/zynqmp/zynqmp-e-a2197-00-revB diff --git a/board/xilinx/zynqmp/zynqmp-e-a2197-00-revB b/board/xilinx/zynqmp/zynqmp-e-a2197-00-revB new file mode 120000 index 00000000000..15ccce3fd24 --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-e-a2197-00-revB @@ -0,0 +1 @@ +zynqmp-e-a2197-00-revA \ No newline at end of file From 6b067f4bfacb9e57423d0b15a343abe51ca3fff8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Sat, 5 Nov 2022 18:21:27 -0700 Subject: [PATCH 11/19] xilinx: versal-net: Fix incorrect platform name in Kconfig Fix incorrect name used in entry description. Signed-off-by: Michal Simek --- arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7866e8f3c4d..f95ed71b246 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1230,7 +1230,7 @@ config ARCH_VERSAL imply ENV_VARS_UBOOT_RUNTIME_CONFIG config ARCH_VERSAL_NET - bool "Support Xilinx Keystone Platform" + bool "Support Xilinx Versal NET Platform" select ARM64 select CLK select DM From 9dc51069f4dfc64f8b86565239c46995aad09dec Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Sun, 6 Nov 2022 11:48:06 -0800 Subject: [PATCH 12/19] xilinx: versal-net: Fix SYS_LOAD_ADDR to point to OCM Versal NET mini U-Boot configuration is used for memory testing that's why load address can't be really placed in memory which doesn't need to work that's why move it to start of OCM which is the same memory which U-Boot is running from. Signed-off-by: Michal Simek --- configs/xilinx_versal_net_mini_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/xilinx_versal_net_mini_defconfig b/configs/xilinx_versal_net_mini_defconfig index e3aa45c83e6..03a63288acd 100644 --- a/configs/xilinx_versal_net_mini_defconfig +++ b/configs/xilinx_versal_net_mini_defconfig @@ -13,7 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini" CONFIG_SYS_PROMPT="Versal NET> " CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set -CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_SYS_LOAD_ADDR=0xBBF00000 CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y From 38920451c71844e2da82b4def8111a541997d649 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 16 Nov 2022 11:59:19 +0100 Subject: [PATCH 13/19] arm64: zynqmp: Describe TI phy as ethernet-phy-id with reset on zcu106 zcu106 also connects ethernet phy reset via tca6416 chip as is done on other evaluation boards. That's why describe this connection to make sure that ethernet phy is reset before it's use. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/21ccd672b799b5858021f6059098a1247c311fae.1668596358.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-zcu106-revA.dts | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 3e137676feb..4858b4d1f5e 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -200,12 +200,19 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + reg = <0xc>; + compatible = "ethernet-phy-id2000.a231"; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; }; }; From de4a22e70328893289747ec4e1f4bfb2143adf26 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 16 Nov 2022 16:33:17 +0100 Subject: [PATCH 14/19] xilinx: versal-net: Disable LMB for mini configuration There is no reason to have LMB enabled on mini configuration because it is only consuming space that's why disable it. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/47067c87b6b2e7600d3c2808e7d0aa6fe82aa1fe.1668612795.git.michal.simek@amd.com --- configs/xilinx_versal_net_mini_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_versal_net_mini_defconfig b/configs/xilinx_versal_net_mini_defconfig index 03a63288acd..c5fa431a8c9 100644 --- a/configs/xilinx_versal_net_mini_defconfig +++ b/configs/xilinx_versal_net_mini_defconfig @@ -70,3 +70,4 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y # CONFIG_GZIP is not set +# CONFIG_LMB is not set From 64fc7fc887a5341bff46ac030d0b5c68eb781b5a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 16 Nov 2022 16:36:35 +0100 Subject: [PATCH 15/19] soc: xilinx: versal-net: Add soc_xilinx_versal_net driver Add soc_xilinx_versal_net driver to identify the family & revision of versal-net SoC. Add Kconfig option CONFIG_SOC_XILINX_VERSAL_NET to enable/disable this driver. To enable this driver by default, add this config to xilinx_versal_net_virt_defconfig file. This driver will be probed using platdata U_BOOT_DEVICE structure which is specified in mach-versal-net/cpu.c. Signed-off-by: Michal Simek Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/613d6bcffd9070f62cf348079ed16c120f8fc56f.1668612993.git.michal.simek@amd.com --- MAINTAINERS | 1 + arch/arm/mach-versal-net/cpu.c | 5 ++ configs/xilinx_versal_net_virt_defconfig | 2 + drivers/soc/Kconfig | 8 +++ drivers/soc/Makefile | 1 + drivers/soc/soc_xilinx_versal_net.c | 78 ++++++++++++++++++++++++ 6 files changed, 95 insertions(+) create mode 100644 drivers/soc/soc_xilinx_versal_net.c diff --git a/MAINTAINERS b/MAINTAINERS index 97b2f69f659..bc9081b62a9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -664,6 +664,7 @@ M: Michal Simek S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/arm/mach-versal-net/ +F: drivers/soc/soc_xilinx_versal_net.c N: (? #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -87,3 +88,7 @@ u64 get_page_table_size(void) { return 0x14000; } + +U_BOOT_DRVINFO(soc_xilinx_versal_net) = { + .name = "soc_xilinx_versal_net", +}; diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index 8a53490ba87..431a8de9fcf 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -108,6 +108,8 @@ CONFIG_RESET_ZYNQMP=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y CONFIG_XILINX_UARTLITE=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_XILINX_VERSAL_NET=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 292dc41b6fa..acf555baaec 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -32,6 +32,14 @@ config SOC_XILINX_VERSAL This allows other drivers to verify the SoC familiy & revision using matching SoC attributes. +config SOC_XILINX_VERSAL_NET + bool "Enable SoC Device ID driver for Xilinx Versal NET" + depends on SOC_DEVICE && ARCH_VERSAL_NET + help + Enable this option to select SoC device id driver for Xilinx Versal NET. + This allows other drivers to verify the SoC familiy & revision using + matching SoC attributes. + source "drivers/soc/ti/Kconfig" endmenu diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 031fa7612f4..84385650d46 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_SOC_DEVICE_TI_K3) += soc_ti_k3.o obj-$(CONFIG_SANDBOX) += soc_sandbox.o obj-$(CONFIG_SOC_XILINX_ZYNQMP) += soc_xilinx_zynqmp.o obj-$(CONFIG_SOC_XILINX_VERSAL) += soc_xilinx_versal.o +obj-$(CONFIG_SOC_XILINX_VERSAL_NET) += soc_xilinx_versal_net.o diff --git a/drivers/soc/soc_xilinx_versal_net.c b/drivers/soc/soc_xilinx_versal_net.c new file mode 100644 index 00000000000..146d068bb4a --- /dev/null +++ b/drivers/soc/soc_xilinx_versal_net.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal NET SOC driver + * + * Copyright (C) 2022, Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include + +#include + +/* + * v1 -> 0x10 - ES1 + * v2 -> 0x20 - Production + */ +static const char versal_family[] = "Versal NET"; + +struct soc_xilinx_versal_net_priv { + const char *family; + char revision; +}; + +static int soc_xilinx_versal_net_get_family(struct udevice *dev, char *buf, int size) +{ + struct soc_xilinx_versal_net_priv *priv = dev_get_priv(dev); + + return snprintf(buf, size, "%s", priv->family); +} + +static int soc_xilinx_versal_net_get_revision(struct udevice *dev, char *buf, int size) +{ + struct soc_xilinx_versal_net_priv *priv = dev_get_priv(dev); + + return snprintf(buf, size, "v%d", priv->revision); +} + +static const struct soc_ops soc_xilinx_versal_net_ops = { + .get_family = soc_xilinx_versal_net_get_family, + .get_revision = soc_xilinx_versal_net_get_revision, +}; + +static int soc_xilinx_versal_net_probe(struct udevice *dev) +{ + struct soc_xilinx_versal_net_priv *priv = dev_get_priv(dev); + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + priv->family = versal_family; + + if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) { + ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, + ret_payload); + if (ret) + return ret; + } else { + ret_payload[2] = readl(PMC_TAP_VERSION); + if (!ret_payload[2]) + return -EINVAL; + } + + priv->revision = FIELD_GET(PS_VERSION_MASK, ret_payload[2]); + + return 0; +} + +U_BOOT_DRIVER(soc_xilinx_versal_net) = { + .name = "soc_xilinx_versal_net", + .id = UCLASS_SOC, + .ops = &soc_xilinx_versal_net_ops, + .probe = soc_xilinx_versal_net_probe, + .priv_auto = sizeof(struct soc_xilinx_versal_net_priv), + .flags = DM_FLAG_PRE_RELOC, +}; From 450d8eb54fe3016d7e265f9acca96575d2bf1f6e Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Wed, 16 Nov 2022 16:40:30 +0100 Subject: [PATCH 16/19] qspi: versal-net: Add condition for tapdelay register Add CONFIG_ARCH_VERSAL_NET to select tapdelay register for versal-net. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/2500dd688214e2ec2d54ed3fabbfee0b1ca861a6.1668613229.git.michal.simek@amd.com --- drivers/spi/zynqmp_gqspi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 49facc46d3c..48eff777dfb 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -104,7 +104,8 @@ #define TAP_DLY_BYPASS_LQSPI_RX_VALUE 0x1 #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 2 #define GQSPI_DATA_DLY_ADJ_OFST 0x000001F8 -#define IOU_TAPDLY_BYPASS_OFST !IS_ENABLED(CONFIG_ARCH_VERSAL) ? \ +#define IOU_TAPDLY_BYPASS_OFST !(IS_ENABLED(CONFIG_ARCH_VERSAL) || \ + IS_ENABLED(CONFIG_ARCH_VERSAL_NET)) ? \ 0xFF180390 : 0xF103003C #define GQSPI_LPBK_DLY_ADJ_LPBK_MASK 0x00000020 #define GQSPI_FREQ_37_5MHZ 37500000 From 3c53ebdd5c24c57927ff74f491dbec03c7dc0aa5 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Wed, 16 Nov 2022 07:11:53 -0700 Subject: [PATCH 17/19] arm64: versal: Add qspi flash mini u-boot configuration Add configuration file for mini u-boot configuration which runs on a smaller footprint from on chip memory(OCM). This configuration has required CONFIG's enabled to support qspi flash and uses DCC terminal for console output. Add required dts files for qspi mini configuration. Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20221116141155.14788-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 1 + arch/arm/dts/versal-mini-qspi-single.dts | 16 +++++ arch/arm/dts/versal-mini-qspi.dtsi | 72 ++++++++++++++++++++++ configs/xilinx_versal_mini_qspi_defconfig | 75 +++++++++++++++++++++++ 4 files changed, 164 insertions(+) create mode 100644 arch/arm/dts/versal-mini-qspi-single.dts create mode 100644 arch/arm/dts/versal-mini-qspi.dtsi create mode 100644 configs/xilinx_versal_mini_qspi_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e89598af305..7d3cac0eb75 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -383,6 +383,7 @@ dtb-$(CONFIG_ARCH_VERSAL) += \ versal-mini.dtb \ versal-mini-emmc0.dtb \ versal-mini-emmc1.dtb \ + versal-mini-qspi-single.dtb \ xilinx-versal-virt.dtb dtb-$(CONFIG_ARCH_VERSAL_NET) += \ versal-net-mini.dtb \ diff --git a/arch/arm/dts/versal-mini-qspi-single.dts b/arch/arm/dts/versal-mini-qspi-single.dts new file mode 100644 index 00000000000..ee518d5d6a5 --- /dev/null +++ b/arch/arm/dts/versal-mini-qspi-single.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal QSPI single DTS + * + * Copyright (C) 2018-2019 Xilinx, Inc. + */ + +#include "versal-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal MINI QSPI SINGLE"; +}; + +&flash0 { + spi-rx-bus-width = <4>; +}; diff --git a/arch/arm/dts/versal-mini-qspi.dtsi b/arch/arm/dts/versal-mini-qspi.dtsi new file mode 100644 index 00000000000..71d0ba5e00b --- /dev/null +++ b/arch/arm/dts/versal-mini-qspi.dtsi @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal Mini QSPI Configuration + * + * (C) Copyright 2018-2019, Xilinx, Inc. + * + * Siva Durga Prasad + * Michal Simek + */ + +/dts-v1/; + +/ { + compatible = "xlnx,versal"; + #address-cells = <2>; + #size-cells = <2>; + model = "Xilinx Versal MINI QSPI"; + + clk150: clk150 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <150000000>; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "okay"; + u-boot,dm-pre-reloc; + }; + + amba: amba { + u-boot,dm-pre-reloc; + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + + qspi: spi@f1030000 { + compatible = "xlnx,versal-qspi-1.0"; + status = "okay"; + clock-names = "ref_clk", "pclk"; + num-cs = <0x1>; + reg = <0x0 0xf1030000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk150 &clk150>; + + flash0: flash@0 { + compatible = "n25q512a", "micron,m25p80", + "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-max-frequency = <20000000>; + }; + }; + }; + + aliases { + serial0 = &dcc; + spi0 = &qspi; + }; + + chosen { + stdout-path = "serial0:115200"; + }; + + memory@fffc0000 { + device_type = "memory"; + reg = <0x0 0xfffc0000 0x0 0x40000>; + }; +}; diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig new file mode 100644 index 00000000000..0062f6a69f8 --- /dev/null +++ b/configs/xilinx_versal_mini_qspi_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini_qspi" +CONFIG_COUNTER_FREQUENCY=100000000 +CONFIG_ARCH_VERSAL=y +CONFIG_TEXT_BASE=0xFFFC0000 +CONFIG_SYS_MALLOC_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x80 +CONFIG_DEFAULT_DEVICE_TREE="versal-mini-qspi-single" +CONFIG_SYS_PROMPT="Versal> " +CONFIG_SYS_MEM_RSVD_FOR_MMU=y +CONFIG_VERSAL_NO_DDR=y +# CONFIG_PSCI_RESET is not set +CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFE0000 +# CONFIG_EXPERT is not set +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +# CONFIG_AUTOBOOT is not set +CONFIG_LOGLEVEL=0 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_BOARD_LATE_INIT is not set +# CONFIG_CMDLINE_EDITING is not set +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_SYS_LONGHELP is not set +# CONFIG_SYS_XTRACE is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG is not set +# CONFIG_NET is not set +# CONFIG_DM_WARN is not set +# CONFIG_DM_DEVICE_REMOVE is not set +# CONFIG_GPIO is not set +# CONFIG_I2C is not set +# CONFIG_INPUT is not set +# CONFIG_MMC is not set +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=30000000 +# CONFIG_SPI_FLASH_SMART_HWCAPS is not set +# CONFIG_SPI_FLASH_UNLOCK_ALL is not set +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +# CONFIG_POWER is not set +CONFIG_ARM_DCC=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ZYNQMP_GQSPI=y +# CONFIG_LMB is not set From ce8adf1a415b3027cc74c4e41e32cffad3e5ea40 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Wed, 16 Nov 2022 07:11:54 -0700 Subject: [PATCH 18/19] spi: cadence-qspi: Fix compilation error in mini u-boot flash reset When cadence_qspi_versal_flash_reset() function is called in mini u-boot where there is no firmware support, it is missing defines for macro's BOOT_MODE_POR_0 & BOOT_MODE_POR_1. Remove them and replace with already define macro's which have same values as these. Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20221116141155.14788-3-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- drivers/spi/cadence_ospi_versal.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index a9547a82003..e0d5e6b9e69 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -182,11 +182,11 @@ int cadence_qspi_versal_flash_reset(struct udevice *dev) /* set direction as output */ writel((readl(BOOT_MODE_DIR) | BIT(FLASH_RESET_GPIO)), - BOOT_MODE_POR_0); + BOOT_MODE_DIR); /* Data output enable */ writel((readl(BOOT_MODE_OUT) | BIT(FLASH_RESET_GPIO)), - BOOT_MODE_POR_1); + BOOT_MODE_OUT); /* IOU SLCR write enable */ writel(0, WPROT_PMC_MIO); From 3655dd22a4c219d0ee69dc4a29e5553c1a1bb5d7 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Wed, 16 Nov 2022 07:11:55 -0700 Subject: [PATCH 19/19] arm64: versal: Add octal spi flash mini u-boot configuration Add configuration file for mini u-boot configuration which runs on a smaller footprint from on chip memory(OCM). This configuration has required CONFIG's enabled to support octal spi flash and uses DCC terminal for console output. Add required dts for octal spi flash mini u-boot configuration. Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20221116141155.14788-4-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 1 + arch/arm/dts/versal-mini-ospi-single.dts | 16 +++++ arch/arm/dts/versal-mini-ospi.dtsi | 77 +++++++++++++++++++++++ configs/xilinx_versal_mini_ospi_defconfig | 72 +++++++++++++++++++++ 4 files changed, 166 insertions(+) create mode 100644 arch/arm/dts/versal-mini-ospi-single.dts create mode 100644 arch/arm/dts/versal-mini-ospi.dtsi create mode 100644 configs/xilinx_versal_mini_ospi_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7d3cac0eb75..43951a7731e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -383,6 +383,7 @@ dtb-$(CONFIG_ARCH_VERSAL) += \ versal-mini.dtb \ versal-mini-emmc0.dtb \ versal-mini-emmc1.dtb \ + versal-mini-ospi-single.dtb \ versal-mini-qspi-single.dtb \ xilinx-versal-virt.dtb dtb-$(CONFIG_ARCH_VERSAL_NET) += \ diff --git a/arch/arm/dts/versal-mini-ospi-single.dts b/arch/arm/dts/versal-mini-ospi-single.dts new file mode 100644 index 00000000000..23f6e47a18a --- /dev/null +++ b/arch/arm/dts/versal-mini-ospi-single.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal QSPI single DTS + * + * Copyright (C) 2018-2020 Xilinx, Inc. + */ + +#include "versal-mini-ospi.dtsi" + +/ { + model = "Xilinx Versal MINI OSPI SINGLE"; +}; + +&flash0 { + spi-rx-bus-width = <8>; +}; diff --git a/arch/arm/dts/versal-mini-ospi.dtsi b/arch/arm/dts/versal-mini-ospi.dtsi new file mode 100644 index 00000000000..a4b76e2b995 --- /dev/null +++ b/arch/arm/dts/versal-mini-ospi.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal Mini OSPI Configuration + * + * (C) Copyright 2018-2019, Xilinx, Inc. + * + * Siva Durga Prasad + * Michal Simek + */ + +/dts-v1/; + +/ { + compatible = "xlnx,versal"; + #address-cells = <2>; + #size-cells = <2>; + model = "Xilinx Versal MINI OSPI"; + + clk125: clk125 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <125000000>; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "okay"; + u-boot,dm-pre-reloc; + }; + + amba: amba { + u-boot,dm-pre-reloc; + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + + ospi: spi@f1010000 { + compatible = "cadence,qspi", "cdns,qspi-nor"; + status = "okay"; + reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>; + clock-names = "ref_clk", "pclk"; + clocks = <&clk125 &clk125>; + bus-num = <2>; + num-cs = <1>; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,is-dma = <1>; + cdns,trigger-address = <0xc0000000>; + #address-cells = <1>; + #size-cells = <0>; + + flash0: flash@0 { + compatible = "n25q512a", "micron,m25p80", + "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <20000000>; + }; + }; + }; + + aliases { + serial0 = &dcc; + spi0 = &ospi; + }; + + chosen { + stdout-path = "serial0:115200"; + }; + + memory@fffc0000 { + device_type = "memory"; + reg = <0x0 0xfffc0000 0x0 0x40000>; + }; +}; diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig new file mode 100644 index 00000000000..2c4e21028df --- /dev/null +++ b/configs/xilinx_versal_mini_ospi_defconfig @@ -0,0 +1,72 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini_qspi" +CONFIG_COUNTER_FREQUENCY=100000000 +CONFIG_ARCH_VERSAL=y +CONFIG_TEXT_BASE=0xFFFC0000 +CONFIG_SYS_MALLOC_LEN=0x2000 +CONFIG_SYS_MALLOC_F_LEN=0x500 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x80 +# CONFIG_DM_GPIO is not set +CONFIG_DEFAULT_DEVICE_TREE="versal-mini-ospi-single" +CONFIG_SYS_PROMPT="Versal> " +CONFIG_SYS_MEM_RSVD_FOR_MMU=y +CONFIG_VERSAL_NO_DDR=y +# CONFIG_PSCI_RESET is not set +CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFE0000 +# CONFIG_EXPERT is not set +# CONFIG_AUTOBOOT is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_BOARD_LATE_INIT is not set +# CONFIG_CMDLINE_EDITING is not set +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_SYS_LONGHELP is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_NET is not set +# CONFIG_DM_WARN is not set +# CONFIG_DM_DEVICE_REMOVE is not set +# CONFIG_MMC is not set +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=30000000 +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_ARM_DCC=y +CONFIG_SOC_XILINX_VERSAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_HAS_CQSPI_REF_CLK=y +CONFIG_CQSPI_REF_CLK=200000000 +CONFIG_CADENCE_OSPI_VERSAL=y +# CONFIG_LMB is not set