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firmware: scmi: smt: Interrupt communication enable

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i.MX95 System Manager uses interrupt driven communication which requires
the caller to set Bit[0] of channel flags to 1. When transmission
completes and the previous general purpose interrupt has been processed
by the other core, i.MX95 System Manager will set General Purpose
Interrupt Control Register (GCR). U-Boot polls General-purpose Status
(GSR) to check if the operation is finished.

Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Viorel Suman 2025-04-01 15:56:35 +08:00 committed by Fabio Estevam
parent a3139fe057
commit 51eed1caca
1 changed files with 13 additions and 0 deletions
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13
drivers/firmware/scmi/smt.c
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@ -20,6 +20,16 @@
#include "smt.h"
static void scmi_smt_enable_intr(struct scmi_smt *smt, bool enable)
{
struct scmi_smt_header *hdr = (void *)smt->buf;
if (enable)
hdr->flags |= SCMI_SHMEM_FLAG_INTR_ENABLED;
else
hdr->flags &= ~SCMI_SHMEM_FLAG_INTR_ENABLED;
}
/**
* Get shared memory configuration defined by the referred DT phandle
* Return with a errno compliant value.
@ -48,6 +58,9 @@ int scmi_dt_get_smt_buffer(struct udevice *dev, struct scmi_smt *smt)
if (!smt->buf)
return -ENOMEM;
if (device_is_compatible(dev, "arm,scmi") && ofnode_has_property(dev_ofnode(dev), "mboxes"))
scmi_smt_enable_intr(smt, true);
#ifdef CONFIG_ARM
if (dcache_status())
mmu_set_region_dcache_behaviour(ALIGN_DOWN((uintptr_t)smt->buf, MMU_SECTION_SIZE),