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ddr: altera: soc64: Fix dram size calculation in clamshell mode

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Fix wrong memory size calculation in clamshell mode

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
This commit is contained in:
Tingting Meng 2025-08-03 18:24:58 -07:00 committed by Tien Fong Chee
parent e5bc1aee5e
commit 4face059c1
2 changed files with 20 additions and 1 deletions
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16
drivers/ddr/altera/sdram_soc64.c
View File

@ -29,6 +29,9 @@
#define PGTABLE_OFF 0x4000
#define SINGLE_RANK_CLAMSHELL 0xc3c3
#define DUAL_RANK_CLAMSHELL 0xa5a5
#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) && !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)
u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg)
{
@ -258,8 +261,19 @@ phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat)
{
u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
u32 reg_ctrlcfg6_value = hmc_readl(plat, CTRLCFG6);
u32 cs_rank = CTRLCFG6_CFG_CS_CHIP(reg_ctrlcfg6_value);
u32 cs_addr_width;
if (cs_rank == SINGLE_RANK_CLAMSHELL)
cs_addr_width = 0;
else if (cs_rank == DUAL_RANK_CLAMSHELL)
cs_addr_width = 1;
else
cs_addr_width = DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw);
phys_size_t size = (phys_size_t)1 <<
(DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
(cs_addr_width +
DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +

5
drivers/ddr/altera/sdram_soc64.h
View File

@ -88,6 +88,8 @@ struct altera_sdram_plat {
#define CTRLCFG0 0x28
#define CTRLCFG1 0x2c
#define CTRLCFG3 0x34
#define CTRLCFG5 0x3c
#define CTRLCFG6 0x40
#define DRAMTIMING0 0x50
#define CALTIMING0 0x7c
#define CALTIMING1 0x80
@ -128,6 +130,9 @@ struct altera_sdram_plat {
#define CTRLCFG1_CFG_CTRL_EN_ECC(x) \
(((x) >> 7) & 0x1)
#define CTRLCFG6_CFG_CS_CHIP(x) \
((x) & 0xFFFF)
#define DRAMTIMING0_CFG_TCL(x) \
((x) & 0x7f)