mirrors/u-boot
1
0
Fork 0
mirror of https://source.denx.de/u-boot/u-boot.git synced 2026-05-05 20:56:12 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity

arm: agilex5: Enable eMMC HS200 and HS400 mode support

Browse Source 
Enable high-speed eMMC modes on Agilex5 SoC development kit for
improved storage performance.

Defconfig changes:
- Enable CONFIG_MMC_HS400_SUPPORT and CONFIG_SPL_MMC_HS400_SUPPORT

Device tree changes:
- Add mmc-hs200-1_8v and mmc-hs400-1_8v capabilities
- Add sdhci-caps-mask to mask SDHCI_CLOCK_V3_BASE_MASK bits
- Add sdhci-caps to set 200MHz base clock and 8-bit bus width
- Add PHY and controller timing configuration for HS200 mode
- Add PHY and controller timing configuration for HS400 mode

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Acked-by: Tien Fong Chee <tien.fong.chee@altera.com>
This commit is contained in:
Tanmay Kathpalia 2026-02-01 07:13:43 -08:00 committed by Tom Rini
parent d60ff5ab9e
commit 4f116c8263
2 changed files with 28 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
arch/arm/dts/socfpga_agilex5_socdk_emmc.dts
View File

@ -25,11 +25,14 @@
disable-wp;
non-removable;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
vmmc-supply = <&sd_emmc_power>;
vqmmc-supply = <&emmc_io_1v8_reg>;
max-frequency = <200000000>;
sdhci-caps = <0x00000000 0x0004c800>; /* SDHCI_CAN_DO_8BIT */
sdhci-caps-mask = <0x00000000 0x0000ff00>;
/* eMMC legacy mode timing configuration */
cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>;
@ -46,4 +49,26 @@
cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-sdr = <0x30000>;
cdns,ctrl-hrs16-slave-ctrl-emmc-sdr = <0x101>;
cdns,ctrl-hrs07-timing-delay-emmc-sdr = <0xA0001>;
/* eMMC HS200 mode timing configuration */
cdns,phy-dqs-timing-delay-emmc-hs200 = <0x780004>;
cdns,phy-gate-lpbk-ctrl-delay-emmc-hs200 = <0x81a40040>;
cdns,phy-dll-slave-ctrl-emmc-hs200 = <0x4d4d00>;
cdns,phy-dq-timing-delay-emmc-hs200 = <0x10000001>;
cdns,phy-dll-master-ctrl-emmc-hs200 = <0x4>;
cdns,ctrl-hrs09-timing-delay-emmc-hs200 = <0xf1c18000>;
cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-hs200 = <0x90000>;
cdns,ctrl-hrs16-slave-ctrl-emmc-hs200 = <0x101>;
cdns,ctrl-hrs07-timing-delay-emmc-hs200 = <0xa0001>;
/* eMMC HS400 mode timing configuration */
cdns,phy-dqs-timing-delay-emmc-hs400 = <0x680004>;
cdns,phy-gate-lpbk-ctrl-delay-emmc-hs400 = <0x81a40040>;
cdns,phy-dll-slave-ctrl-emmc-hs400 = <0x4d4b40>;
cdns,phy-dq-timing-delay-emmc-hs400 = <0x10000001>;
cdns,phy-dll-master-ctrl-emmc-hs400 = <0x4>;
cdns,ctrl-hrs09-timing-delay-emmc-hs400 = <0xf1c18000>;
cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-hs400 = <0x80000>;
cdns,ctrl-hrs16-slave-ctrl-emmc-hs400 = <0x11000001>;
cdns,ctrl-hrs07-timing-delay-emmc-hs400 = <0x90001>;
};

2
configs/socfpga_agilex5_emmc_defconfig
View File

@ -4,3 +4,5 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk_emmc"
# CONFIG_SPL_DM_REGULATOR_GPIO is not set
# CONFIG_DM_REGULATOR_GPIO is not set
# CONFIG_SPL_DWAPB_GPIO is not set
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_SPL_MMC_HS400_SUPPORT=y