From aff236f30d51eee12eba86b49877ea643f374cd5 Mon Sep 17 00:00:00 2001 From: Pegorer Massimo Date: Sat, 15 Jul 2023 10:19:28 +0000 Subject: [PATCH 01/45] rockchip: rk3308: fix board_debug_uart_init Definition of function board_debug_uart_init() must be under CONFIG_DEBUG_UART_BOARD_INIT and not under CONFIG_DEBUG_UART, as it was: see debug_uart.h. In this way the debug uart can be used but its board-specific initialization skipped by configuration, if useless. Signed-off-by: Massimo Pegorer Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3308/rk3308.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c index dd9109b7c3d..5763604dc3e 100644 --- a/arch/arm/mach-rockchip/rk3308/rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/rk3308.c @@ -174,7 +174,7 @@ int rk_board_init(void) return 0; } -#if defined(CONFIG_DEBUG_UART) +#ifdef CONFIG_DEBUG_UART_BOARD_INIT __weak void board_debug_uart_init(void) { static struct rk3308_grf * const grf = (void *)GRF_BASE; From 9f2c7349e516a082b13ded4ae0efd3ce448c8970 Mon Sep 17 00:00:00 2001 From: Pegorer Massimo Date: Sat, 15 Jul 2023 10:19:34 +0000 Subject: [PATCH 02/45] rockchip: rk3308: no DEBUG_UART_BOARD_INIT for ROCK Pi S Call to board_debug_uart_init() is useless, as mainline U-Boot can not build TPL for rk3308, and proprietary ddr.bin to be used as TPL is responsible to init debug uart. Moreover current implementation of board_debug_uart_init() is not compatible with ROCK Pi S, as it sets pins for UART2 channel 1 breaking access to sdmmc due to pinmux conflict. Debug uart for ROCK Pi S is UART0. Thus, avoid ROCKCHIP_RK3308 to select DEBUG_UART_BOARD_INIT and allow to deselct it in rock-pi-s-rk3308_defconfig. The DEBUG_UART_BOARD_INIT is already implied by ARCH_ROCKCHIP, therefore other boards based on rk3308 chip are not affected by change. Signed-off-by: Massimo Pegorer Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 1 - configs/rock-pi-s-rk3308_defconfig | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 07b5595dac8..49da93d54b4 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -153,7 +153,6 @@ config ROCKCHIP_RK3288 config ROCKCHIP_RK3308 bool "Support Rockchip RK3308" select ARM64 - select DEBUG_UART_BOARD_INIT select SUPPORT_SPL select SUPPORT_TPL select SPL diff --git a/configs/rock-pi-s-rk3308_defconfig b/configs/rock-pi-s-rk3308_defconfig index c6fae07913e..d306b58b8e2 100644 --- a/configs/rock-pi-s-rk3308_defconfig +++ b/configs/rock-pi-s-rk3308_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_STACK_R_ADDR=0xc00000 CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF0A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +# CONFIG_DEBUG_UART_BOARD_INIT is not set CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_DEBUG_UART=y CONFIG_ANDROID_BOOT_IMAGE=y From 1d7e1d09cac5f01867a5c25009baa4ddd63559ab Mon Sep 17 00:00:00 2001 From: Pegorer Massimo Date: Sat, 15 Jul 2023 10:19:40 +0000 Subject: [PATCH 03/45] rockchip: rk3308: add support for sdmmc boot Some ROCK Pi S SKU/models are not equipped with SD-NAND (eMMC), therefore SPL needs access to sdmmc: add it to rk3308-u-boot.dtsi with bootph-all property. Signed-off-by: Massimo Pegorer Reviewed-by: Kever Yang --- arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi | 2 +- arch/arm/dts/rk3308-u-boot.dtsi | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi index a27a3adc082..09694b41e53 100644 --- a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi +++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi @@ -6,7 +6,7 @@ / { chosen { - u-boot,spl-boot-order = "same-as-spl", &emmc; + u-boot,spl-boot-order = "same-as-spl", &emmc, &sdmmc; }; }; diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi index c8451b24758..db2c20a7055 100644 --- a/arch/arm/dts/rk3308-u-boot.dtsi +++ b/arch/arm/dts/rk3308-u-boot.dtsi @@ -26,6 +26,11 @@ bootph-all; }; +&sdmmc { + bootph-all; + u-boot,spl-fifo-mode; +}; + &grf { bootph-all; }; From ffd41939feaa0a83f825e0e94b8ebedab7db914c Mon Sep 17 00:00:00 2001 From: Pegorer Massimo Date: Sat, 15 Jul 2023 10:19:46 +0000 Subject: [PATCH 04/45] rockchip: rk3308: fix same-as-spl boot order Boot devices defined in rk3308.c and in rk3308.dtsi do not match, causing 'same-as-spl' feature not to work. Update DTS definitions, aligning to Linux kernel DTS and to other Rockchip DTS files, i.e. from dwmmc to mmc. Add rk3308-rock-pi-s.dtb in dtb-y targets for CONFIG_ROCKCHIP_RK3308. Signed-off-by: Massimo Pegorer Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 3 ++- arch/arm/dts/rk3308.dtsi | 6 +++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index bd5887bf750..4379d9726f9 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -119,7 +119,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ rk3308-evb.dtb \ - rk3308-roc-cc.dtb + rk3308-roc-cc.dtb \ + rk3308-rock-pi-s.dtb dtb-$(CONFIG_ROCKCHIP_RK3328) += \ rk3328-evb.dtb \ diff --git a/arch/arm/dts/rk3308.dtsi b/arch/arm/dts/rk3308.dtsi index a5c0b72ae05..9a152a8a907 100644 --- a/arch/arm/dts/rk3308.dtsi +++ b/arch/arm/dts/rk3308.dtsi @@ -584,7 +584,7 @@ status = "disabled"; }; - sdmmc: dwmmc@ff480000 { + sdmmc: mmc@ff480000 { compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff480000 0x0 0x4000>; max-frequency = <150000000>; @@ -599,7 +599,7 @@ status = "disabled"; }; - emmc: dwmmc@ff490000 { + emmc: mmc@ff490000 { compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff490000 0x0 0x4000>; max-frequency = <150000000>; @@ -612,7 +612,7 @@ status = "disabled"; }; - sdio: dwmmc@ff4a0000 { + sdio: mmc@ff4a0000 { compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff4a0000 0x0 0x4000>; max-frequency = <150000000>; From 6d79d8a7435a438e07660149707daefdb05de8ce Mon Sep 17 00:00:00 2001 From: Pegorer Massimo Date: Sun, 16 Jul 2023 16:53:58 +0000 Subject: [PATCH 05/45] configs: rockchip: drop useless DEBUG_UART_SKIP_INIT DEBUG_UART_SKIP_INIT feature is implemented only by s5p (DEBUG_UART_S5P) and pl01x (DEBUG_UART_PL010 or DEBUG_UART_PL011) serial drivers, but all ARCH_ROCKCHIP configs rely on default DEBUG_UART_NS16550. The ns16550 serial driver does not depends on DEBUG_UART_SKIP_INIT, so drop it from rockchip configs. Signed-off-by: Massimo Pegorer Reviewed-by: Kever Yang --- configs/evb-px30_defconfig | 1 - configs/evb-px5_defconfig | 1 - configs/evb-rk3308_defconfig | 1 - configs/evb-rk3328_defconfig | 1 - configs/firefly-px30_defconfig | 1 - configs/geekbox_defconfig | 1 - configs/lion-rk3368_defconfig | 1 - configs/odroid-go2_defconfig | 1 - configs/px30-core-ctouch2-of10-px30_defconfig | 1 - configs/px30-core-ctouch2-px30_defconfig | 1 - configs/px30-core-edimm2.2-px30_defconfig | 1 - configs/ringneck-px30_defconfig | 1 - configs/roc-cc-rk3308_defconfig | 1 - configs/rock-pi-e-rk3328_defconfig | 1 - configs/rock-pi-s-rk3308_defconfig | 1 - configs/sheep-rk3368_defconfig | 1 - 16 files changed, 16 deletions(-) diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index 4ac161683cc..d75329d3851 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -100,7 +100,6 @@ CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig index 29f7516e75a..5f32c926745 100644 --- a/configs/evb-px5_defconfig +++ b/configs/evb-px5_defconfig @@ -76,7 +76,6 @@ CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_PANIC_HANG=y diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig index 6950b5ba060..a13a809c1ef 100644 --- a/configs/evb-rk3308_defconfig +++ b/configs/evb-rk3308_defconfig @@ -73,7 +73,6 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 580ee502dc9..9bfb8f1df2b 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -87,7 +87,6 @@ CONFIG_TPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig index 47c924c3df3..11a3baa7a37 100644 --- a/configs/firefly-px30_defconfig +++ b/configs/firefly-px30_defconfig @@ -99,7 +99,6 @@ CONFIG_TPL_RAM=y CONFIG_ROCKCHIP_SDRAM_COMMON=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig index fdd01b64949..8f4be79831a 100644 --- a/configs/geekbox_defconfig +++ b/configs/geekbox_defconfig @@ -26,7 +26,6 @@ CONFIG_PINCTRL=y CONFIG_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_ERRNO_STR=y diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig index 2a180609b29..7c55b3be0d2 100644 --- a/configs/lion-rk3368_defconfig +++ b/configs/lion-rk3368_defconfig @@ -95,7 +95,6 @@ CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSINFO=y diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig index bdc2288af66..eb759e00738 100644 --- a/configs/odroid-go2_defconfig +++ b/configs/odroid-go2_defconfig @@ -104,7 +104,6 @@ CONFIG_TPL_RAM=y CONFIG_ROCKCHIP_SDRAM_COMMON=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig index abe6cfbd57d..d96fd14b36d 100644 --- a/configs/px30-core-ctouch2-of10-px30_defconfig +++ b/configs/px30-core-ctouch2-of10-px30_defconfig @@ -99,7 +99,6 @@ CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig index e839dcb5f62..ac2af6d8cbb 100644 --- a/configs/px30-core-ctouch2-px30_defconfig +++ b/configs/px30-core-ctouch2-px30_defconfig @@ -99,7 +99,6 @@ CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig index 92540e73bec..a49bb4072d2 100644 --- a/configs/px30-core-edimm2.2-px30_defconfig +++ b/configs/px30-core-edimm2.2-px30_defconfig @@ -99,7 +99,6 @@ CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index e9234efc2a0..cdec0c52e6a 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -111,7 +111,6 @@ CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig index 8eafd52a6b0..9a789b212f1 100644 --- a/configs/roc-cc-rk3308_defconfig +++ b/configs/roc-cc-rk3308_defconfig @@ -73,7 +73,6 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index 9c67d0c5fe1..68357fed07e 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -95,7 +95,6 @@ CONFIG_TPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y diff --git a/configs/rock-pi-s-rk3308_defconfig b/configs/rock-pi-s-rk3308_defconfig index d306b58b8e2..cc3274a98b3 100644 --- a/configs/rock-pi-s-rk3308_defconfig +++ b/configs/rock-pi-s-rk3308_defconfig @@ -74,7 +74,6 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/sheep-rk3368_defconfig b/configs/sheep-rk3368_defconfig index 044e1060a5d..a591b2741dd 100644 --- a/configs/sheep-rk3368_defconfig +++ b/configs/sheep-rk3368_defconfig @@ -28,7 +28,6 @@ CONFIG_PINCTRL=y CONFIG_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_ERRNO_STR=y From cbe7322d17b780f24d03f2a4b592aab8e956ddc0 Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak Date: Fri, 7 Jul 2023 22:16:35 +0300 Subject: [PATCH 06/45] rockchip: veyron: Enable RESET driver Commit 70e351bdfeee ("rockchip: jerry: Enable RESET driver") enables DM_RESET for chromebook_jerry to fix its display as required by changes to the Rockchip video drivers. Enable it for other veyron boards as well. Fixes: cd529f7ad62 ("rockchip: video: edp: Add missing reset support") Fixes: 9749d2ea29e ("rockchip: video: vop: Add reset support") Signed-off-by: Alper Nebi Yasak Reviewed-by: Simon Glass Tested-by: Simon Glass # chromebook_jerry Reviewed-by: Kever Yang --- configs/chromebit_mickey_defconfig | 1 + configs/chromebook_minnie_defconfig | 1 + configs/chromebook_speedy_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 253ef99f993..e0ecf1ec33b 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -10,6 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey" CONFIG_SPL_TEXT_BASE=0xff704000 +CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=614400 CONFIG_ROCKCHIP_RK3288=y # CONFIG_SPL_MMC is not set diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 25a56f45fe6..b0baf57794b 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -10,6 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie" CONFIG_SPL_TEXT_BASE=0xff704000 +CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=614400 CONFIG_ROCKCHIP_RK3288=y # CONFIG_SPL_MMC is not set diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index ff2a12b25c3..0295610ab8a 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -10,6 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy" CONFIG_SPL_TEXT_BASE=0xff704000 +CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=614400 CONFIG_ROCKCHIP_RK3288=y # CONFIG_SPL_MMC is not set From 871c40dcbe13e4cae823944362b79ab2b3cf9f23 Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak Date: Fri, 7 Jul 2023 22:16:36 +0300 Subject: [PATCH 07/45] rockchip: veyron: Enable building SPI ROM images Commit 9b312e26fc77 ("rockchip: Enable building a SPI ROM image on jerry") produces a u-boot.rom file for chromebook_jerry, intended to be written to SPI flash. Build this file for other veyron boards as well, especially because they are already configured only to boot from SPI. Signed-off-by: Alper Nebi Yasak Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3288/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index ea94ad11424..69a5614b449 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -16,7 +16,9 @@ config TARGET_CHROMEBOOK_JERRY config TARGET_CHROMEBIT_MICKEY bool "Google/Rockchip Veyron-Mickey Chromebit" + select HAS_ROM select BOARD_LATE_INIT + select ROCKCHIP_SPI_IMAGE help Mickey is a small RK3288-based device with one USB 3.0 port, HDMI and WiFi. It has a separate power port and is designed to connect @@ -26,7 +28,9 @@ config TARGET_CHROMEBIT_MICKEY config TARGET_CHROMEBOOK_MINNIE bool "Google/Rockchip Veyron-Minnie Chromebook" + select HAS_ROM select BOARD_LATE_INIT + select ROCKCHIP_SPI_IMAGE help Minnie is a RK3288-based convertible clamshell device with 2 USB 3.0 ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card, @@ -37,7 +41,9 @@ config TARGET_CHROMEBOOK_MINNIE config TARGET_CHROMEBOOK_SPEEDY bool "Google/Rockchip Veyron-Speedy Chromebook" + select HAS_ROM select BOARD_LATE_INIT + select ROCKCHIP_SPI_IMAGE help Speedy is a RK3288-based clamshell device with 2 USB 2.0 ports, micro HDMI, an 11.6 inch display, micro-SD card, From b73b6558a18f36b78ec648ad28f51a7f87c98854 Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak Date: Fri, 7 Jul 2023 22:16:37 +0300 Subject: [PATCH 08/45] rockchip: veyron: Unify u-boot.dtsi bootph-all fragments The rk3288-veyron-speedy-u-boot.dtsi file duplicates the bootphase dts fragments from rk3288-veyron-u-boot.dtsi even though it #inclues that. Deduplicate these into the latter file, which should also make the eMMC available to the other veyron boards' SPL. Signed-off-by: Alper Nebi Yasak Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi | 16 ---------------- arch/arm/dts/rk3288-veyron-u-boot.dtsi | 4 ++++ 2 files changed, 4 insertions(+), 16 deletions(-) diff --git a/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi index 90ce9e1395d..2a4ba44e0bf 100644 --- a/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi +++ b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi @@ -15,19 +15,3 @@ 0x0 0xc3 0x6 0x1>; rockchip,sdram-params = <0x20D266A4 0x5B6 6 533000000 6 13 0>; }; - -&sdmmc { - bootph-all; -}; - -&emmc { - bootph-all; -}; - -&uart2 { - bootph-all; -}; - -&pinctrl { - bootph-all; -}; diff --git a/arch/arm/dts/rk3288-veyron-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-u-boot.dtsi index ab564e73ed0..4f9c59c6757 100644 --- a/arch/arm/dts/rk3288-veyron-u-boot.dtsi +++ b/arch/arm/dts/rk3288-veyron-u-boot.dtsi @@ -31,6 +31,10 @@ >; }; +&emmc { + bootph-all; +}; + &gpio3 { bootph-all; }; From d25b34751b1b375fc7d6dcb4e28dc39bb7dad74f Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak Date: Fri, 7 Jul 2023 22:16:38 +0300 Subject: [PATCH 09/45] rockchip: veyron: Add serial, logging, silent console support Commit eba768c54587 ("rockchip: jerry: Add serial support") enables ROCKCHIP_SERIAL for chromebook_jerry to make the serial console work correctly. Enable it also for other veyron boards. Also enable logging and disable scrolling multiple lines at once as in chromebook_jerry, and enable silent console as chromebook_minnie does. Signed-off-by: Alper Nebi Yasak Reviewed-by: Simon Glass Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- configs/chromebit_mickey_defconfig | 3 +++ configs/chromebook_minnie_defconfig | 3 ++- configs/chromebook_speedy_defconfig | 1 + 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index e0ecf1ec33b..33c0eece9a8 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -26,6 +26,8 @@ CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb" +CONFIG_SILENT_CONSOLE=y +CONFIG_LOG=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_R=y @@ -97,6 +99,7 @@ CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SERIAL=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index b0baf57794b..02a78f2478e 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -27,6 +27,7 @@ CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb" CONFIG_SILENT_CONSOLE=y +CONFIG_LOG=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_R=y @@ -99,6 +100,7 @@ CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SERIAL=y CONFIG_SOUND=y CONFIG_I2S=y CONFIG_I2S_ROCKCHIP=y @@ -115,7 +117,6 @@ CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_EDP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_SPL_TINY_MEMSET=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index 0295610ab8a..6c7eb424edd 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -27,6 +27,7 @@ CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb" CONFIG_SILENT_CONSOLE=y +CONFIG_LOG=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_R=y From 7bd46bf4c6946d006dcb9eb9f029884cb98af49e Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak Date: Fri, 7 Jul 2023 22:16:39 +0300 Subject: [PATCH 10/45] rockchip: veyron: Use TrueType fonts Commit 815ed79d8338 ("video: rockchip: Use TrueType fonts with jerry") enables makes chromebook_jerry use TrueType fonts. Make other veyron boards switch to it as well. Signed-off-by: Alper Nebi Yasak Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- configs/chromebit_mickey_defconfig | 2 ++ configs/chromebook_minnie_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 33c0eece9a8..ce46dd5d942 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -108,9 +108,11 @@ CONFIG_USB_DWC2=y CONFIG_ROCKCHIP_USB2_PHY=y CONFIG_VIDEO=y # CONFIG_VIDEO_BPP8 is not set +CONFIG_CONSOLE_TRUETYPE=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y +# CONFIG_USE_PRIVATE_LIBGCC is not set CONFIG_SPL_TINY_MEMSET=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 02a78f2478e..52e0fa3039f 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -113,10 +113,12 @@ CONFIG_USB_DWC2=y CONFIG_ROCKCHIP_USB2_PHY=y CONFIG_VIDEO=y # CONFIG_VIDEO_BPP8 is not set +CONFIG_CONSOLE_TRUETYPE=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_EDP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y +# CONFIG_USE_PRIVATE_LIBGCC is not set CONFIG_SPL_TINY_MEMSET=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y From 5c6e387e46cf408793f6b2ad940e55604f05149f Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak Date: Fri, 7 Jul 2023 22:16:40 +0300 Subject: [PATCH 11/45] rockchip: chromebook_jerry: Re-enable MAX98090 codec driver Sound support for chromebook_jerry needs the MAX98090 codec driver. This was enabled in commit 2d0c01b8f0ad ("sound: rockchip: Add sound support for jerry"), but apparently lost in commit 7ae2729401bb ("configs: Resync with savedefconfig"). Enable it again. Signed-off-by: Alper Nebi Yasak Reviewed-by: Simon Glass Tested-by: Simon Glass # chromebook_jerry Reviewed-by: Kever Yang --- configs/chromebook_jerry_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 3172f04a264..1a9d633f328 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -103,6 +103,7 @@ CONFIG_ROCKCHIP_SERIAL=y CONFIG_SOUND=y CONFIG_I2S=y CONFIG_I2S_ROCKCHIP=y +CONFIG_SOUND_MAX98090=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y From 42cb8f0112b122ca1720343ee30319e8f7635853 Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak Date: Fri, 7 Jul 2023 22:16:41 +0300 Subject: [PATCH 12/45] rockchip: chromebook_speedy: Enable sound Commit ec107f04b619 ("rockchip: chromebook_minnie: Enable sound") and commit 2d0c01b8f0ad ("sound: rockchip: Add sound support for jerry") enable audio support for chromebook_minnie and chromebook_jerry. Enable it for chromebook_speedy as well, but put the non-upstream sound node in the board -u-boot.dtsi instead. Signed-off-by: Alper Nebi Yasak Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi | 14 ++++++++++++++ configs/chromebook_speedy_defconfig | 5 +++++ 2 files changed, 19 insertions(+) diff --git a/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi index 2a4ba44e0bf..6bfa84906e3 100644 --- a/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi +++ b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi @@ -5,6 +5,20 @@ #include "rk3288-veyron-u-boot.dtsi" +/ { + sound { + compatible = "rockchip,audio-max98090-jerry"; + + cpu { + sound-dai = <&i2s 0>; + }; + + codec { + sound-dai = <&max98090 0>; + }; + }; +}; + &dmc { rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index 6c7eb424edd..b82f70b30f2 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -52,6 +52,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y +CONFIG_CMD_SOUND=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set @@ -100,6 +101,10 @@ CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SERIAL=y +CONFIG_SOUND=y +CONFIG_I2S=y +CONFIG_I2S_ROCKCHIP=y +CONFIG_SOUND_MAX98090=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y From bec51f3fb316b5a5ccedd7deb2e58ae6d7443cfa Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 30 Jul 2023 22:59:54 +0000 Subject: [PATCH 13/45] Revert "arm: dts: rockchip: radxa-cm3-io, rock-3a: enable regulators for usb" Remove regulator-boot-on prop from regulators now that the phy core has support for phy-supply after the commit c57e0dcd9384 ("phy: add support for phy-supply"). This reverts commit 7911f409ff20dce5995cc1b703a6e30c94022f6b. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 4 ---- arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 8 -------- 2 files changed, 12 deletions(-) diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi index f91740c1c0c..57b77151c57 100644 --- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi +++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi @@ -77,7 +77,3 @@ bootph-all; status = "okay"; }; - -&vcc5v0_usb30 { - regulator-boot-on; -}; diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi index 9ee7b494ee2..a6cee5609df 100644 --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi @@ -124,11 +124,3 @@ bootph-all; status = "okay"; }; - -&vcc5v0_usb_host { - regulator-boot-on; -}; - -&vcc5v0_usb_hub { - regulator-boot-on; -}; From 4412a2bf0b674d7438821531a0a19bbcd4b80eda Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 30 Jul 2023 22:59:55 +0000 Subject: [PATCH 14/45] usb: dwc3-generic: Return early when there is no child node The current error check for device_find_first_child is not working as expected, the documentation for device_find_first_child mention: @devp: Returns first child device, or NULL if none Return: 0 Change to return early when there is no child node to avoid any possible null pointer dereference. Signed-off-by: Jonas Karlman Reviewed-by: Marek Vasut Reviewed-by: Kever Yang --- drivers/usb/dwc3/dwc3-generic.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 35e4b36a695..4d5d500aefa 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -558,9 +558,9 @@ int dwc3_glue_probe(struct udevice *dev) return ret; } - ret = device_find_first_child(dev, &child); - if (ret) - return ret; + device_find_first_child(dev, &child); + if (!child) + return 0; if (glue->clks.count == 0) { ret = dwc3_glue_clk_init(child, glue); From 6913c30516022f86104c9fbe315499e43eee4ed6 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 30 Jul 2023 22:59:56 +0000 Subject: [PATCH 15/45] usb: dwc3-generic: Relax unsupported dr_mode check When dr_mode is peripheral or otg and U-Boot has not been built with DM_USB_GADGET support, booting such device may end up with: dwc3_glue_bind_common: subnode name: usb@fcc00000 Error binding driver 'dwc3-generic-wrapper': -6 Some drivers failed to bind initcall sequence 00000000effbca08 failed at call 0000000000a217c8 (err=-6) ### ERROR ### Please RESET the board ### Instead fail gracfully with ENODEV to allow board continue booting. dwc3_glue_bind_common: subnode name: usb@fcc00000 dwc3_glue_bind_common: unsupported dr_mode 3 Also use CONFIG_IS_ENABLED(USB_HOST) and change switch to if statements to improve readability of the code. Fixes: 446e3a205b87 ("dwc3-generic: Handle the PHYs, the clocks and the reset lines") Signed-off-by: Jonas Karlman Reviewed-by: Marek Vasut --- drivers/usb/dwc3/dwc3-generic.c | 27 ++++++++------------------- 1 file changed, 8 insertions(+), 19 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 4d5d500aefa..2331ac45313 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -226,8 +226,7 @@ U_BOOT_DRIVER(dwc3_generic_peripheral) = { }; #endif -#if defined(CONFIG_SPL_USB_HOST) || \ - !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_HOST) +#if CONFIG_IS_ENABLED(USB_HOST) static int dwc3_generic_host_probe(struct udevice *dev) { struct xhci_hcor *hcor; @@ -409,7 +408,7 @@ struct dwc3_glue_ops ti_ops = { static int dwc3_glue_bind_common(struct udevice *parent, ofnode node) { const char *name = ofnode_get_name(node); - const char *driver = NULL; + const char *driver; enum usb_dr_mode dr_mode; struct udevice *dev; int ret; @@ -421,27 +420,17 @@ static int dwc3_glue_bind_common(struct udevice *parent, ofnode node) if (!dr_mode) dr_mode = usb_get_dr_mode(node); - switch (dr_mode) { - case USB_DR_MODE_PERIPHERAL: - case USB_DR_MODE_OTG: -#if CONFIG_IS_ENABLED(DM_USB_GADGET) + if (CONFIG_IS_ENABLED(DM_USB_GADGET) && + (dr_mode == USB_DR_MODE_PERIPHERAL || dr_mode == USB_DR_MODE_OTG)) { debug("%s: dr_mode: OTG or Peripheral\n", __func__); driver = "dwc3-generic-peripheral"; -#endif - break; -#if defined(CONFIG_SPL_USB_HOST) || !defined(CONFIG_SPL_BUILD) - case USB_DR_MODE_HOST: + } else if (CONFIG_IS_ENABLED(USB_HOST) && dr_mode == USB_DR_MODE_HOST) { debug("%s: dr_mode: HOST\n", __func__); driver = "dwc3-generic-host"; - break; -#endif - default: - debug("%s: unsupported dr_mode\n", __func__); + } else { + debug("%s: unsupported dr_mode %d\n", __func__, dr_mode); return -ENODEV; - }; - - if (!driver) - return -ENXIO; + } ret = device_bind_driver_to_node(parent, driver, name, node, &dev); From caaeac88466f4152bd126e2342765a4b740955ae Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 30 Jul 2023 22:59:57 +0000 Subject: [PATCH 16/45] usb: dwc3-generic: Add rk3568 support RK3568 share glue and ctrl in a single node. Use glue_get_ctrl_dev to return the glue node as the ctrl node. Signed-off-by: Jonas Karlman Reviewed-by: Jagan Teki Reviewed-by: Marek Vasut --- drivers/usb/dwc3/dwc3-generic.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 2331ac45313..79203f82041 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -405,6 +405,19 @@ struct dwc3_glue_ops ti_ops = { .glue_configure = dwc3_ti_glue_configure, }; +static int dwc3_rk_glue_get_ctrl_dev(struct udevice *dev, ofnode *node) +{ + *node = dev_ofnode(dev); + if (!ofnode_valid(*node)) + return -EINVAL; + + return 0; +} + +struct dwc3_glue_ops rk_ops = { + .glue_get_ctrl_dev = dwc3_rk_glue_get_ctrl_dev, +}; + static int dwc3_glue_bind_common(struct udevice *parent, ofnode node) { const char *name = ofnode_get_name(node); @@ -596,6 +609,7 @@ static const struct udevice_id dwc3_glue_ids[] = { { .compatible = "ti,am654-dwc3" }, { .compatible = "rockchip,rk3328-dwc3" }, { .compatible = "rockchip,rk3399-dwc3" }, + { .compatible = "rockchip,rk3568-dwc3", .data = (ulong)&rk_ops }, { .compatible = "qcom,dwc3" }, { .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops }, { .compatible = "fsl,imx8mq-dwc3" }, From f8a2d1c108da37fd5202d717c3e428e3dfc12f01 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 30 Jul 2023 22:59:59 +0000 Subject: [PATCH 17/45] rockchip: rk3568: Use dwc3-generic driver Change RK3568 devices to use the newer dwc3-generic driver instead of the old xhci-dwc3 driver for USB 3.0 support. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- configs/nanopi-r5c-rk3568_defconfig | 3 +-- configs/nanopi-r5s-rk3568_defconfig | 3 +-- configs/radxa-cm3-io-rk3566_defconfig | 2 +- configs/rock-3a-rk3568_defconfig | 2 +- 4 files changed, 4 insertions(+), 6 deletions(-) diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig index b913ad4494c..201b21ad77e 100644 --- a/configs/nanopi-r5c-rk3568_defconfig +++ b/configs/nanopi-r5c-rk3568_defconfig @@ -13,7 +13,6 @@ CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_TARGET_EVB_RK3568=y CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 @@ -76,10 +75,10 @@ CONFIG_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_ERRNO_STR=y diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig index 0a298c65a76..67b28430709 100644 --- a/configs/nanopi-r5s-rk3568_defconfig +++ b/configs/nanopi-r5s-rk3568_defconfig @@ -13,7 +13,6 @@ CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_TARGET_EVB_RK3568=y CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 @@ -76,10 +75,10 @@ CONFIG_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_ERRNO_STR=y diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig index 488723dfaa3..f89777184ce 100644 --- a/configs/radxa-cm3-io-rk3566_defconfig +++ b/configs/radxa-cm3-io-rk3566_defconfig @@ -75,8 +75,8 @@ CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_ERRNO_STR=y diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig index 8e3fe0a25e1..1e8256e6025 100644 --- a/configs/rock-3a-rk3568_defconfig +++ b/configs/rock-3a-rk3568_defconfig @@ -94,10 +94,10 @@ CONFIG_ROCKCHIP_SFC=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_ERRNO_STR=y From 9c1b5d163eec247091ed8dbb4493906f315bfff9 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 30 Jul 2023 12:26:42 +0000 Subject: [PATCH 18/45] board: rockchip: Add Pine64 Quartz64-A Board The Pine64 Quartz64 Model A is a single-board computer based on the Rockchip RK3566 SoC. The board features USB3, SATA, PCIe, HDMI, USB2.0, CSI, DSI, eDP, eMMC, SD, and an e-paper parallel port, as well as a 20 pin GPIO header. Features tested on a Quartz64-A 8GB v2.0 2021-04-27: - SD-card boot - eMMC boot - PCIe/NVMe/AHCI - USB host Device tree is imported from linux v6.4. Co-developed-by: Nicolas Frattaroli Signed-off-by: Nicolas Frattaroli Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 51 ++ arch/arm/dts/rk3566-quartz64-a.dts | 839 ++++++++++++++++++ arch/arm/mach-rockchip/rk3568/Kconfig | 6 + board/pine64/quartz64_rk3566/Kconfig | 15 + board/pine64/quartz64_rk3566/MAINTAINERS | 9 + board/pine64/quartz64_rk3566/Makefile | 3 + .../pine64/quartz64_rk3566/quartz64-rk3566.c | 1 + configs/quartz64-a-rk3566_defconfig | 110 +++ doc/board/rockchip/rockchip.rst | 1 + include/configs/quartz64_rk3566.h | 10 + 11 files changed, 1046 insertions(+) create mode 100644 arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-quartz64-a.dts create mode 100644 board/pine64/quartz64_rk3566/Kconfig create mode 100644 board/pine64/quartz64_rk3566/MAINTAINERS create mode 100644 board/pine64/quartz64_rk3566/Makefile create mode 100644 board/pine64/quartz64_rk3566/quartz64-rk3566.c create mode 100644 configs/quartz64-a-rk3566_defconfig create mode 100644 include/configs/quartz64_rk3566.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 4379d9726f9..d52bc0b9db2 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-anbernic-rgxx3.dtb \ + rk3566-quartz64-a.dtb \ rk3566-radxa-cm3-io.dtb \ rk3568-evb.dtb \ rk3568-nanopi-r5c.dtb \ diff --git a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi new file mode 100644 index 00000000000..06cc15ed21b --- /dev/null +++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; +}; + +&gpio0 { + bootph-all; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-ddr-1_8v; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; +}; + +&sfc { + bootph-pre-ram; + u-boot,spl-sfc-no-dma; + + flash@0 { + bootph-pre-ram; + }; +}; + +&uart2 { + bootph-all; + clock-frequency = <24000000>; + status = "okay"; +}; + +/* + * U-Boot does not support multiple regulators using the same gpio, + * use vcc5v0_usb20_host to fix use of USB 2.0 port + */ +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb20_host>; +}; + +&vcc3v3_sd { + bootph-pre-ram; +}; + +&vcc_sd_h { + bootph-all; +}; diff --git a/arch/arm/dts/rk3566-quartz64-a.dts b/arch/arm/dts/rk3566-quartz64-a.dts new file mode 100644 index 00000000000..25a8c781f4e --- /dev/null +++ b/arch/arm/dts/rk3566-quartz64-a.dts @@ -0,0 +1,839 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include "rk3566.dtsi" + +/ { + model = "Pine64 RK3566 Quartz64-A Board"; + compatible = "pine64,quartz64-a", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdmmc0; + mmc1 = &sdhci; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + + fan: gpio_fan { + compatible = "gpio-fan"; + gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0 + 4500 1>; + pinctrl-names = "default"; + pinctrl-0 = <&fan_en_h>; + #cooling-cells = <2>; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-work { + label = "work-led"; + default-state = "off"; + gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&work_led_enable_h>; + retain-state-suspended; + }; + + led-diy { + label = "diy-led"; + default-state = "on"; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&diy_led_enable_h>; + retain-state-suspended; + }; + }; + + rk817-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK817"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk817>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <5000000>; + reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; + }; + + spdif_dit: spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_sound: spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_dit>; + }; + }; + + vcc12v_dcin: vcc12v_dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + /* vbus feeds the rk817 usb input. + * With no battery attached, also feeds vcc_bat+ + * via ON/OFF_BAT jumper + */ + vbus: vbus { + compatible = "regulator-fixed"; + regulator-name = "vbus"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_pcie_p: vcc3v3-pcie-p-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_enable_h>; + regulator-name = "vcc3v3_pcie_p"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + vcc5v0_usb: vcc5v0_usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + /* all four ports are controlled by one gpio + * the host ports are sourced from vcc5v0_usb + * the otg port is sourced from vcc5v0_midu + */ + vcc5v0_usb20_host: vcc5v0_usb20_host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb20_host_en>; + regulator-name = "vcc5v0_usb20_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_usb20_otg: vcc5v0_usb20_otg { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc5v0_usb20_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dcdc_boost>; + }; + + vcc3v3_sd: vcc3v3_sd { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_sd_h>; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + /* sourced from vbus and vcc_bat+ via rk817 sw5 */ + vcc_sys: vcc_sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4400000>; + regulator-max-microvolt = <4400000>; + vin-supply = <&vbus>; + }; + + /* sourced from vcc_sys, sdio module operates internally at 3.3v */ + vcc_wl: vcc_wl { + compatible = "regulator-fixed"; + regulator-name = "vcc_wl"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_thermal { + trips { + cpu_hot: cpu_hot { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&cpu_hot>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_3v3>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_clkinout + &gmac1m0_rgmii_bus>; + snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x30>; + rx_delay = <0x10>; + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda_0v9>; + avdd-1v8-supply = <&vcc_1v8>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; + rockchip,system-power-controller; + #sound-dai-cells = <0>; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&dcdc_boost>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +/* i2c3 is exposed on con40 + * pin 3 - i2c3_sda_m0, pullup to vcc_3v3 + * pin 5 - i2c3_scl_m0, pullup to vcc_3v3 + */ +&i2c3 { + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie_p>; + status = "okay"; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + fan { + fan_en_h: fan-en-h { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + work_led_enable_h: work-led-enable-h { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + diy_led_enable_h: diy-led-enable-h { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_enable_h: pcie-enable-h { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_reset_h: pcie-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + vcc5v0_usb20_host_en: vcc5v0-usb20-host-en { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc_sd { + vcc_sd_h: vcc-sd-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc1v8_dvp>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_wl>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sfc { + pinctrl-0 = <&fspi_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <24000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +/* spdif is exposed on con40 pin 18 */ +&spdif { + status = "okay"; +}; + +/* spi1 is exposed on con40 + * pin 11 - spi1_mosi_m1 + * pin 13 - spi1_miso_m1 + * pin 15 - spi1_clk_m1 + * pin 17 - spi1_cs0_m1 + */ +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +/* uart0 is exposed on con40 + * pin 12 - uart0_tx + * pin 14 - uart0_rx + */ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + status = "okay"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk817 1>; + clock-names = "lpo"; + host-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc_sys>; + vddio-supply = <&vcca1v8_pmu>; + max-speed = <3000000>; + }; +}; + +/* uart2 is exposed on con40 + * pin 8 - uart2_tx_m0_debug + * pin 10 - uart2_rx_m0_debug + */ +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +/* usb3 controller is muxed with sata1 */ +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb20_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb20_otg>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb20_host>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb20_host>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index f46be3d081f..baa51349f4b 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -22,6 +22,11 @@ config TARGET_ODROID_M1_RK3568 help Hardkernel ODROID-M1 single board computer with a RK3568B2 SoC. +config TARGET_QUARTZ64_RK3566 + bool "Pine64 Quartz64" + help + Pine64 Quartz64 single board computer with a RK3566 SoC. + endchoice config ROCKCHIP_BOOT_MODE_REG @@ -39,5 +44,6 @@ config SYS_MALLOC_F_LEN source "board/rockchip/evb_rk3568/Kconfig" source "board/anbernic/rgxx3_rk3566/Kconfig" source "board/hardkernel/odroid_m1/Kconfig" +source "board/pine64/quartz64_rk3566/Kconfig" endif diff --git a/board/pine64/quartz64_rk3566/Kconfig b/board/pine64/quartz64_rk3566/Kconfig new file mode 100644 index 00000000000..3de1d8f7a99 --- /dev/null +++ b/board/pine64/quartz64_rk3566/Kconfig @@ -0,0 +1,15 @@ +if TARGET_QUARTZ64_RK3566 + +config SYS_BOARD + default "quartz64_rk3566" + +config SYS_VENDOR + default "pine64" + +config SYS_CONFIG_NAME + default "quartz64_rk3566" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/pine64/quartz64_rk3566/MAINTAINERS b/board/pine64/quartz64_rk3566/MAINTAINERS new file mode 100644 index 00000000000..dbc0dfbd978 --- /dev/null +++ b/board/pine64/quartz64_rk3566/MAINTAINERS @@ -0,0 +1,9 @@ +QUARTZ64-RK3566 +M: Nicolas Frattaroli +R: Jonas Karlman +S: Maintained +F: board/pine64/quartz64_rk3566/ +F: include/configs/quartz64_rk3566.h +F: configs/quartz64-a-rk3566_defconfig +F: arch/arm/dts/rk3566-quartz64-a.dts +F: arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi diff --git a/board/pine64/quartz64_rk3566/Makefile b/board/pine64/quartz64_rk3566/Makefile new file mode 100644 index 00000000000..c24a40e724d --- /dev/null +++ b/board/pine64/quartz64_rk3566/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += quartz64-rk3566.o diff --git a/board/pine64/quartz64_rk3566/quartz64-rk3566.c b/board/pine64/quartz64_rk3566/quartz64-rk3566.c new file mode 100644 index 00000000000..4c027f2a7af --- /dev/null +++ b/board/pine64/quartz64_rk3566/quartz64-rk3566.c @@ -0,0 +1 @@ +// SPDX-License-Identifier: GPL-2.0+ diff --git a/configs/quartz64-a-rk3566_defconfig b/configs/quartz64-a-rk3566_defconfig new file mode 100644 index 00000000000..d55b224feac --- /dev/null +++ b/configs/quartz64-a-rk3566_defconfig @@ -0,0 +1,110 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-a" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_QUARTZ64_RK3566=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-a.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_POWER=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=4 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index dfbc27a86d6..123486ac7f3 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -96,6 +96,7 @@ List of mainline supported Rockchip boards: * rk3568 - Rockchip Evb-RK3568 (evb-rk3568) - Hardkernel ODROID-M1 (odroid-m1-rk3568) + - Pine64 Quartz64-A Board (quartz64-a-rk3566_defconfig) * rk3588 - Rockchip EVB (evb-rk3588) diff --git a/include/configs/quartz64_rk3566.h b/include/configs/quartz64_rk3566.h new file mode 100644 index 00000000000..dfe0fee94cd --- /dev/null +++ b/include/configs/quartz64_rk3566.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __QUARTZ64_RK3566_H +#define __QUARTZ64_RK3566_H + +#define ROCKCHIP_DEVICE_SETTINGS + +#include + +#endif From f52452bbeaf59e3bbeb376b9657d46b981445a19 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 30 Jul 2023 12:26:44 +0000 Subject: [PATCH 19/45] board: rockchip: Add Pine64 Quartz64-B Board The Pine64 Quartz64 Model B is a credit-card sized single-board computer based on the Rockchip RK3566 SoC. The board features an M.2 PCIe slot, USB3, USB2, eMMC, SD, ethernet, HDMI, analog audio out, a 40 pin GPIO header and a DSI and CSI port, as well as on-board Wi-Fi. Features tested on a Quartz64-B 4GB v1.4 2022-06-06: - SD-card boot - eMMC boot - SPI Flash boot - PCIe/NVMe - USB host Device tree is imported from linux v6.4. Co-developed-by: Nicolas Frattaroli Signed-off-by: Nicolas Frattaroli Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi | 43 ++ arch/arm/dts/rk3566-quartz64-b.dts | 739 +++++++++++++++++++++ board/pine64/quartz64_rk3566/MAINTAINERS | 3 + configs/quartz64-b-rk3566_defconfig | 106 +++ doc/board/rockchip/rockchip.rst | 1 + 6 files changed, 893 insertions(+) create mode 100644 arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-quartz64-b.dts create mode 100644 configs/quartz64-b-rk3566_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d52bc0b9db2..294d585c102 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -172,6 +172,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-anbernic-rgxx3.dtb \ rk3566-quartz64-a.dtb \ + rk3566-quartz64-b.dtb \ rk3566-radxa-cm3-io.dtb \ rk3568-evb.dtb \ rk3568-nanopi-r5c.dtb \ diff --git a/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi new file mode 100644 index 00000000000..3c2c54e9418 --- /dev/null +++ b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-ddr-1_8v; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; +}; + +&sfc { + bootph-pre-ram; + u-boot,spl-sfc-no-dma; + + flash@0 { + bootph-pre-ram; + }; +}; + +&uart2 { + bootph-all; + clock-frequency = <24000000>; + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; +}; + +&vcc5v0_usb30_host { + /delete-property/ regulator-always-on; +}; + +&vcc5v0_usb_otg { + /delete-property/ regulator-always-on; +}; diff --git a/arch/arm/dts/rk3566-quartz64-b.dts b/arch/arm/dts/rk3566-quartz64-b.dts new file mode 100644 index 00000000000..b276eb0810c --- /dev/null +++ b/arch/arm/dts/rk3566-quartz64-b.dts @@ -0,0 +1,739 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include "rk3566.dtsi" + +/ { + model = "Pine64 RK3566 Quartz64-B Board"; + compatible = "pine64,quartz64-b", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdmmc0; + mmc1 = &sdhci; + mmc2 = &sdmmc1; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-user { + label = "user-led"; + default-state = "on"; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led_enable_h>; + retain-state-suspended; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK809"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + status = "okay"; + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <5000000>; + }; + + vcc3v3_pcie_p: vcc3v3-pcie-p-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_enable_h>; + regulator-name = "vcc3v3_pcie_p"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + vcc5v0_in: vcc5v0-in-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_in"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_in>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb30_host: vcc5v0-usb30-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb30_host"; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb30_host_en_h>; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_otg"; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en_h>; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + clock_in_out = "input"; + phy-mode = "rgmii"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_clkinout + &gmac1m1_rgmii_bus>; + snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f, also works well here */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x4f>; + rx_delay = <0x24>; + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; + rockchip,system-power-controller; + #sound-dai-cells = <0>; + wakeup-source; + #clock-cells = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-boot-on; + regulator-name = "vcc_3v3"; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + }; + }; + }; +}; + +/* i2c2_m1 exposed on csi port, pulled up to vcc_3v3 */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + status = "okay"; +}; + +/* i2c3_m1 exposed on dsi port, pulled up to vcc_3v3 */ +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m1_xfer>; + status = "okay"; +}; + +/* + * i2c4_m0 is exposed on PI40, pulled up to vcc_3v3 + * pin 27 - i2c4_sda_m0 + * pin 28 - i2c4_scl_m0 + */ +&i2c4 { + status = "okay"; +}; + +/* + * i2c5_m0 is exposed on PI40 + * pin 29 - i2c5_scl_m0 + * pin 31 - i2c5_sda_m0 + */ +&i2c5 { + status = "disabled"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie_p>; + status = "okay"; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + user_led_enable_h: user-led-enable-h { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_enable_h: pcie-enable-h { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_reset_h: pcie-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcca1v8_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcca1v8_pmu>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr50; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcca1v8_pmu>; + status = "okay"; +}; + +&sfc { + pinctrl-0 = <&fspi_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <24000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&tsadc { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + status = "okay"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcca1v8_pmu>; + }; +}; + +/* + * uart2_m0 is exposed on PI40 + * pin 8 - uart2_tx_m0 + * pin 10 - uart2_rx_m0 + */ +&uart2 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb30_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb30_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/board/pine64/quartz64_rk3566/MAINTAINERS b/board/pine64/quartz64_rk3566/MAINTAINERS index dbc0dfbd978..2e637bf51ba 100644 --- a/board/pine64/quartz64_rk3566/MAINTAINERS +++ b/board/pine64/quartz64_rk3566/MAINTAINERS @@ -5,5 +5,8 @@ S: Maintained F: board/pine64/quartz64_rk3566/ F: include/configs/quartz64_rk3566.h F: configs/quartz64-a-rk3566_defconfig +F: configs/quartz64-b-rk3566_defconfig F: arch/arm/dts/rk3566-quartz64-a.dts F: arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi +F: arch/arm/dts/rk3566-quartz64-b.dts +F: arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi diff --git a/configs/quartz64-b-rk3566_defconfig b/configs/quartz64-b-rk3566_defconfig new file mode 100644 index 00000000000..b98c81f9dce --- /dev/null +++ b/configs/quartz64-b-rk3566_defconfig @@ -0,0 +1,106 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-b" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_QUARTZ64_RK3566=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-b.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=4 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 123486ac7f3..9fff5fc3f5e 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -97,6 +97,7 @@ List of mainline supported Rockchip boards: - Rockchip Evb-RK3568 (evb-rk3568) - Hardkernel ODROID-M1 (odroid-m1-rk3568) - Pine64 Quartz64-A Board (quartz64-a-rk3566_defconfig) + - Pine64 Quartz64-B Board (quartz64-b-rk3566_defconfig) * rk3588 - Rockchip EVB (evb-rk3588) From 651492bfb210317e39ab12358b5e94719033a703 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 30 Jul 2023 12:26:45 +0000 Subject: [PATCH 20/45] board: rockchip: Add Pine64 SOQuartz on Model A The Pine64 SOQuartz Model A board is a carrier board for the SOQuartz CM4-compatible compute module. It exposes PCIe, ethernet, USB, HDMI, CSI, DSI, eDP and a 40 pin GPIO header, and is powered by 12V DC. Features tested with a SOQuartz 4GB v1.1 2022-07-11: - SD-card boot - eMMC boot - PCIe/NVMe/AHCI - USB host Device tree is imported from linux v6.4. Co-developed-by: Nicolas Frattaroli Signed-off-by: Nicolas Frattaroli Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 1 + .../dts/rk3566-soquartz-model-a-u-boot.dtsi | 3 + arch/arm/dts/rk3566-soquartz-model-a.dts | 232 ++++++ arch/arm/dts/rk3566-soquartz-u-boot.dtsi | 26 + arch/arm/dts/rk3566-soquartz.dtsi | 688 ++++++++++++++++++ board/pine64/quartz64_rk3566/MAINTAINERS | 5 + configs/soquartz-model-a-rk3566_defconfig | 90 +++ doc/board/rockchip/rockchip.rst | 1 + 8 files changed, 1046 insertions(+) create mode 100644 arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz-model-a.dts create mode 100644 arch/arm/dts/rk3566-soquartz-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz.dtsi create mode 100644 configs/soquartz-model-a-rk3566_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 294d585c102..d93ba18266c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -174,6 +174,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-quartz64-a.dtb \ rk3566-quartz64-b.dtb \ rk3566-radxa-cm3-io.dtb \ + rk3566-soquartz-model-a.dtb \ rk3568-evb.dtb \ rk3568-nanopi-r5c.dtb \ rk3568-nanopi-r5s.dtb \ diff --git a/arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi b/arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi new file mode 100644 index 00000000000..0e662eafa4c --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3566-soquartz-u-boot.dtsi" diff --git a/arch/arm/dts/rk3566-soquartz-model-a.dts b/arch/arm/dts/rk3566-soquartz-model-a.dts new file mode 100644 index 00000000000..2208dbfb7f0 --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz-model-a.dts @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-soquartz.dtsi" + +/ { + model = "PINE64 RK3566 SOQuartz on Model A carrier board"; + compatible = "pine64,soquartz-model-a", "pine64,soquartz", "rockchip,rk3566"; + + /* labeled DCIN_12V in schematic */ + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + /* + * Labelled VCC3V0_SD in schematic to not conflict with PMIC + * regulator, it's 3.3v in actuality + */ + vcc3v0_sd: vcc3v0-sd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v0_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc12v_pcie: vcc12v-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_pcie"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +/* phy for pcie */ +&combphy2 { + phy-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +&gmac1 { + status = "okay"; +}; + +/* + * i2c1 is exposed on CM1 / Module1A + * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu + * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu + */ +&i2c1 { + status = "okay"; + + /* + * the rtc interrupt is tied to PMIC_PWRON, + * it will force reset the board if triggered. + */ + pcf85063: rtc@51 { + compatible = "nxp,pcf85063"; + reg = <0x51>; + }; +}; + +/* + * i2c2 is exposed on CM1 / Module1A - to PI40 + * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch + * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3 + */ +&i2c2 { + status = "disabled"; +}; + +/* + * i2c3 is exposed on CM1 / Module1A - to PI40 + * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3 + * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3 + */ +&i2c3 { + status = "disabled"; +}; + +/* + * i2c4 is exposed on CM2 / Module1B - to PI40 + * pin 45 - GPIO24 - i2c4_scl_m1 + * pin 47 - GPIO23 - i2c4_sda_m1 + */ +&i2c4 { + status = "disabled"; +}; + +/* + * i2s1_8ch is exposed on CM1 / Module1A - to PI40 + * pin 24 - GPIO26 - i2s1_sdi1_m1 + * pin 25 - GPIO21 - i2s1_sdo0_m1 + * pin 26 - GPIO19 - i2s1_lrck_tx_m1 + * pin 27 - GPIO20 - i2s1_sdi0_m1 + * pin 29 - GPIO16 - i2s1_sdi3_m1 + * pin 30 - GPIO6 - i2s1_sdi2_m1 + * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3 + * pin 41 - GPIO25 - i2s1_sdo2_m1 + * pin 49 - GPIO18 - i2s1_sclk_tx_m1 + * pin 50 - GPIO17 - i2s1_mclk_m1 + * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2 + */ +&i2s1_8ch { + status = "disabled"; +}; + +&led_diy { + status = "okay"; +}; + +&led_work { + status = "okay"; +}; + +&pcie2x1 { + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&rgmii_phy1 { + status = "okay"; +}; + +&rgmii_phy1 { + status = "okay"; +}; + +/* + * saradc is exposed on CM1 / Module1A - to J2 + * pin 94 - AIN1 - saradc_vin3 + * pin 96 - AIN0 - saradc_vin2 + */ +&saradc { + status = "disabled"; +}; + +/* + * vmmc-supply is vcc3v3_sd on v1.0 and vcc3v0_sd on v1.1+ + * the soquartz SoM has SDMMC_PWR (CM1 pin 75) hardwired to vcc3v3_sys, + * so we use vcc3v3_sd here to ensure the regulator is enabled on older boards. + */ +&sdmmc0 { + vmmc-supply = <&vcc3v3_sd>; + status = "okay"; +}; + +/* + * spi3 is exposed on CM1 / Module1A - to PI40 + * pin 37 - GPIO7 - spi3_cs1_m0 + * pin 38 - GPIO11 - spi3_clk_m0 + * pin 39 - GPIO8 - spi3_cs0_m0 + * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch + * pin 44 - GPIO10 - spi3_mosi_m0 + */ +&spi3 { + status = "disabled"; +}; + +/* + * uart2 is exposed on CM1 / Module1A - to PI40 + * pin 51 - GPIO15 - uart2_rx_m0 + * pin 55 - GPIO14 - uart2_tx_m0 + */ +&uart2 { + status = "okay"; +}; + +/* + * uart7 is exposed on CM1 / Module1A - to PI40 + * pin 46 - GPIO22 - uart7_tx_m2 + * pin 47 - GPIO23 - uart7_rx_m2 + */ +&uart7 { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb>; + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&vbus { + vin-supply = <&vcc5v0_usb>; +}; + +&vcc3v3_sd { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3566-soquartz-u-boot.dtsi b/arch/arm/dts/rk3566-soquartz-u-boot.dtsi new file mode 100644 index 00000000000..793cca2ceac --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz-u-boot.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-ddr-1_8v; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; +}; + +&uart2 { + bootph-all; + clock-frequency = <24000000>; + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; +}; diff --git a/arch/arm/dts/rk3566-soquartz.dtsi b/arch/arm/dts/rk3566-soquartz.dtsi new file mode 100644 index 00000000000..31aa2b8efe3 --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz.dtsi @@ -0,0 +1,688 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include "rk3566.dtsi" + +/ { + model = "Pine64 RK3566 SoQuartz SOM"; + compatible = "pine64,soquartz", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdmmc0; + mmc1 = &sdhci; + mmc2 = &sdmmc1; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_diy: led-diy { + label = "diy-led"; + default-state = "on"; + gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&diy_led_enable_h>; + retain-state-suspended; + status = "disabled"; + }; + + led_work: led-work { + label = "work-led"; + default-state = "off"; + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&work_led_enable_h>; + retain-state-suspended; + status = "disabled"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + status = "okay"; + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; + }; + + vbus: vbus-regulator { + compatible = "regulator-fixed"; + regulator-name = "vbus"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + /* sourced from vbus, vbus is provided by the carrier board */ + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vbus>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_3v3>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_clkinout + &gmac1m0_rgmii_bus>; + snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f, also works well here */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x30>; + rx_delay = <0x10>; + phy-handle = <&rgmii_phy1>; + status = "disabled"; +}; + +&gpio0 { + nextrst-hog { + gpio-hog; + /* + * GPIO_ACTIVE_LOW + output-low here means that the pin is set + * to high, because output-low decides the value pre-inversion. + */ + gpios = ; + line-name = "nEXTRST"; + output-low; + }; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + status = "disabled"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + }; + }; +}; + +/* + * i2c1 is exposed on CM1 / Module1A + * pin 80 - i2c1_scl_m0, pullup to vcc3v3_pmu + * pin 82 - i2c1_sda_m0, pullup to vcc3v3_pmu + */ +&i2c1 { + status = "disabled"; +}; + +/* + * i2c2 is exposed on CM1 / Module1A + * pin 56 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch + * pin 58 - i2c2_sda_m1, pullup to vcc_3v3 + */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + status = "disabled"; +}; + +/* + * i2c3 is exposed on CM1 / Module1A + * pin 35 - i2c3_scl_m0, pullup to vcc_3v3 + * pin 36 - i2c3_sda_m0, pullup to vcc_3v3 + */ +&i2c3 { + status = "disabled"; +}; + +/* + * i2c4 is exposed on CM2 / Module1B + * pin 45 - i2c4_scl_m1 + * pin 47 - i2c4_sda_m1 + */ +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + status = "disabled"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +/* + * i2s1_8ch is exposed on CM1 / Module1A + * pin 24 - i2s1_sdi1_m1 + * pin 25 - i2s1_sdo0_m1 + * pin 26 - i2s1_lrck_tx_m1 + * pin 27 - i2s1_sdi0_m1 + * pin 29 - i2s1_sdi3_m1 + * pin 30 - i2s1_sdi2_m1 + * pin 40 - i2s1_sdo1_m1, shared with spi3 + * pin 41 - i2s1_sdo2_m1 + * pin 49 - i2s1_sclk_tx_m1 + * pin 50 - i2s1_mclk_m1 + * pin 56 - i2s1_sdo3_m1, shared with i2c2 + */ +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m1_sclktx &i2s1m1_sclkrx + &i2s1m1_lrcktx &i2s1m1_lrckrx + &i2s1m1_sdi0 &i2s1m1_sdi1 + &i2s1m1_sdi2 &i2s1m1_sdi3 + &i2s1m1_sdo0 &i2s1m1_sdo1 + &i2s1m1_sdo2 &i2s1m1_sdo3>; + status = "disabled"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + status = "disabled"; + }; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + work_led_enable_h: work-led-enable-h { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + diy_led_enable_h: diy-led-enable-h { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_clkreq_h: pcie-clkreq-h { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + pcie_reset_h: pcie-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +/* + * saradc is exposed on CM1 / Module1A + * pin 94 - saradc_vin3 + * pin 96 - saradc_vin2 + */ +&saradc { + vref-supply = <&vcca_1v8>; + status = "disabled"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + broken-cd; + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + vqmmc-supply = <&vccio_sd>; + status = "disabled"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr50; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +/* + * spi3 is exposed on CM1 / Module1A + * pin 37 - spi3_cs1_m0 + * pin 38 - spi3_clk_m0 + * pin 39 - spi3_cs0_m0 + * pin 40 - spi3_miso_m0, shared with i2s1_8ch + * pin 44 - spi3_mosi_m0 + */ +&spi3 { + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcca1v8_pmu>; + }; +}; + +/* + * uart2 is exposed on CM1 / Module1A + * pin 51 - uart2_rx_m0 + * pin 55 - uart2_tx_m0 + */ +&uart2 { + status = "disabled"; +}; + +/* + * uart7 is exposed on CM1 / Module1A + * pin 46 - uart7_tx_m2 + * pin 47 - uart7_rx_m2 + */ +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7m2_xfer>; + status = "disabled"; +}; + +/* dwc3_otg is the only usb port available */ +&usb2phy0 { + status = "disabled"; +}; + +&usb2phy0_otg { + status = "disabled"; +}; + +&usb_host0_xhci { + status = "disabled"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/board/pine64/quartz64_rk3566/MAINTAINERS b/board/pine64/quartz64_rk3566/MAINTAINERS index 2e637bf51ba..748ff5033d9 100644 --- a/board/pine64/quartz64_rk3566/MAINTAINERS +++ b/board/pine64/quartz64_rk3566/MAINTAINERS @@ -6,7 +6,12 @@ F: board/pine64/quartz64_rk3566/ F: include/configs/quartz64_rk3566.h F: configs/quartz64-a-rk3566_defconfig F: configs/quartz64-b-rk3566_defconfig +F: configs/soquartz-model-a-rk3566_defconfig F: arch/arm/dts/rk3566-quartz64-a.dts F: arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi F: arch/arm/dts/rk3566-quartz64-b.dts F: arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi +F: arch/arm/dts/rk3566-soquartz.dtsi +F: arch/arm/dts/rk3566-soquartz-u-boot.dtsi +F: arch/arm/dts/rk3566-soquartz-model-a.dts +F: arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi diff --git a/configs/soquartz-model-a-rk3566_defconfig b/configs/soquartz-model-a-rk3566_defconfig new file mode 100644 index 00000000000..c3958579db7 --- /dev/null +++ b/configs/soquartz-model-a-rk3566_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-model-a" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_QUARTZ64_RK3566=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-soquartz-model-a.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_CLK=y +CONFIG_GPIO_HOG=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 9fff5fc3f5e..3d2ca19d609 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -98,6 +98,7 @@ List of mainline supported Rockchip boards: - Hardkernel ODROID-M1 (odroid-m1-rk3568) - Pine64 Quartz64-A Board (quartz64-a-rk3566_defconfig) - Pine64 Quartz64-B Board (quartz64-b-rk3566_defconfig) + - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566_defconfig) * rk3588 - Rockchip EVB (evb-rk3588) From d0026e5908723b6639cace72a7f99b02efab2370 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 30 Jul 2023 12:26:47 +0000 Subject: [PATCH 21/45] board: rockchip: Add Pine64 SOQuartz on Blade The Pine64 SOQuartz Blade board is a carrier board for the SOQuartz CM4-compatible compute module. It features PoE, an M.2 slot, an SD card slot, HDMI, USB, serial and ethernet. Features tested with a SOQuartz 4GB v1.1 2022-07-11: - SD-card boot - eMMC boot - PCIe/NVMe - USB host Device tree is imported from linux v6.4. Co-developed-by: Nicolas Frattaroli Signed-off-by: Nicolas Frattaroli Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 1 + .../arm/dts/rk3566-soquartz-blade-u-boot.dtsi | 3 + arch/arm/dts/rk3566-soquartz-blade.dts | 194 ++++++++++++++++++ board/pine64/quartz64_rk3566/MAINTAINERS | 3 + configs/soquartz-blade-rk3566_defconfig | 90 ++++++++ doc/board/rockchip/rockchip.rst | 1 + 6 files changed, 292 insertions(+) create mode 100644 arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz-blade.dts create mode 100644 configs/soquartz-blade-rk3566_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d93ba18266c..916de092c55 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -174,6 +174,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-quartz64-a.dtb \ rk3566-quartz64-b.dtb \ rk3566-radxa-cm3-io.dtb \ + rk3566-soquartz-blade.dtb \ rk3566-soquartz-model-a.dtb \ rk3568-evb.dtb \ rk3568-nanopi-r5c.dtb \ diff --git a/arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi b/arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi new file mode 100644 index 00000000000..0e662eafa4c --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3566-soquartz-u-boot.dtsi" diff --git a/arch/arm/dts/rk3566-soquartz-blade.dts b/arch/arm/dts/rk3566-soquartz-blade.dts new file mode 100644 index 00000000000..4e49bebf548 --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz-blade.dts @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include + +#include "rk3566-soquartz.dtsi" + +/ { + model = "PINE64 RK3566 SOQuartz on Blade carrier board"; + compatible = "pine64,soquartz-blade", "pine64,soquartz", "rockchip,rk3566"; + + /* labeled VCC3V0_SD in schematic to not conflict with PMIC regulator */ + vcc3v0_sd: vcc3v0-sd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v0_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + /* labeled VCC_SSD in schematic */ + vcc3v3_pcie_p: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie_p"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vbus>; + }; + + vcc5v_dcin: vcc5v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&combphy2 { + phy-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +&gmac1 { + status = "okay"; +}; + +/* + * i2c1 is exposed on CM1 / Module1A + * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu + * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu + */ +&i2c1 { + status = "okay"; + +}; + +/* + * i2c2 is exposed on CM1 / Module1A - to PI40 + * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch + * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3 + */ +&i2c2 { + status = "disabled"; +}; + +/* + * i2c3 is exposed on CM1 / Module1A - to PI40 + * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3 + * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3 + */ +&i2c3 { + status = "disabled"; +}; + +/* + * i2c4 is exposed on CM2 / Module1B - to PI40 + * pin 45 - GPIO24 - i2c4_scl_m1 + * pin 47 - GPIO23 - i2c4_sda_m1 + */ +&i2c4 { + status = "disabled"; +}; + +/* + * i2s1_8ch is exposed on CM1 / Module1A - to PI40 + * pin 24 - GPIO26 - i2s1_sdi1_m1 + * pin 25 - GPIO21 - i2s1_sdo0_m1 + * pin 26 - GPIO19 - i2s1_lrck_tx_m1 + * pin 27 - GPIO20 - i2s1_sdi0_m1 + * pin 29 - GPIO16 - i2s1_sdi3_m1 + * pin 30 - GPIO6 - i2s1_sdi2_m1 + * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3 + * pin 41 - GPIO25 - i2s1_sdo2_m1 + * pin 49 - GPIO18 - i2s1_sclk_tx_m1 + * pin 50 - GPIO17 - i2s1_mclk_m1 + * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2 + */ +&i2s1_8ch { + status = "disabled"; +}; + +&led_diy { + color = ; + function = LED_FUNCTION_DISK_ACTIVITY; + linux,default-trigger = "disk-activity"; + status = "okay"; +}; + +&led_work { + color = ; + function = LED_FUNCTION_STATUS; + linux,default-trigger = "heartbeat"; + status = "okay"; +}; + +&pcie2x1 { + vpcie3v3-supply = <&vcc3v3_pcie_p>; + status = "okay"; +}; + +&rgmii_phy1 { + status = "okay"; +}; + +/* + * saradc is exposed on CM1 / Module1A - to J2 + * pin 94 - AIN1 - saradc_vin3 + * pin 96 - AIN0 - saradc_vin2 + */ +&saradc { + status = "disabled"; +}; + +&sdmmc0 { + vmmc-supply = <&vcc3v0_sd>; + status = "okay"; +}; + +/* + * spi3 is exposed on CM1 / Module1A - to PI40 + * pin 37 - GPIO7 - spi3_cs1_m0 + * pin 38 - GPIO11 - spi3_clk_m0 + * pin 39 - GPIO8 - spi3_cs0_m0 + * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch + * pin 44 - GPIO10 - spi3_mosi_m0 + */ +&spi3 { + status = "disabled"; +}; + +/* + * uart2 is exposed on CM1 / Module1A - to PI40 + * pin 51 - GPIO15 - uart2_rx_m0 + * pin 55 - GPIO14 - uart2_tx_m0 + */ +&uart2 { + status = "okay"; +}; + +/* + * uart7 is exposed on CM1 / Module1A - to PI40 + * pin 46 - GPIO22 - uart7_tx_m2 + * pin 47 - GPIO23 - uart7_rx_m2 + */ +&uart7 { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vbus>; + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&vbus { + vin-supply = <&vcc5v_dcin>; +}; diff --git a/board/pine64/quartz64_rk3566/MAINTAINERS b/board/pine64/quartz64_rk3566/MAINTAINERS index 748ff5033d9..603d2ee9d5e 100644 --- a/board/pine64/quartz64_rk3566/MAINTAINERS +++ b/board/pine64/quartz64_rk3566/MAINTAINERS @@ -6,6 +6,7 @@ F: board/pine64/quartz64_rk3566/ F: include/configs/quartz64_rk3566.h F: configs/quartz64-a-rk3566_defconfig F: configs/quartz64-b-rk3566_defconfig +F: configs/soquartz-blade-rk3566_defconfig F: configs/soquartz-model-a-rk3566_defconfig F: arch/arm/dts/rk3566-quartz64-a.dts F: arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi @@ -13,5 +14,7 @@ F: arch/arm/dts/rk3566-quartz64-b.dts F: arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi F: arch/arm/dts/rk3566-soquartz.dtsi F: arch/arm/dts/rk3566-soquartz-u-boot.dtsi +F: arch/arm/dts/rk3566-soquartz-blade.dts +F: arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi F: arch/arm/dts/rk3566-soquartz-model-a.dts F: arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi diff --git a/configs/soquartz-blade-rk3566_defconfig b/configs/soquartz-blade-rk3566_defconfig new file mode 100644 index 00000000000..181c284e73e --- /dev/null +++ b/configs/soquartz-blade-rk3566_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-blade" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_QUARTZ64_RK3566=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-soquartz-blade.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_CLK=y +CONFIG_GPIO_HOG=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 3d2ca19d609..5b4d0285d87 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -98,6 +98,7 @@ List of mainline supported Rockchip boards: - Hardkernel ODROID-M1 (odroid-m1-rk3568) - Pine64 Quartz64-A Board (quartz64-a-rk3566_defconfig) - Pine64 Quartz64-B Board (quartz64-b-rk3566_defconfig) + - Pine64 SOQuartz on Blade (soquartz-blade-rk3566_defconfig) - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566_defconfig) * rk3588 From 6855fa625ca5549ef8d27a89cc125c43676b46b6 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 30 Jul 2023 12:26:48 +0000 Subject: [PATCH 22/45] board: rockchip: Add Pine64 SOQuartz on CM4-IO The Pine64 SOQuartz compute module is mostly pin-compatible with the RPi CM4 form factor. Therefore, it can slot into the official Raspberry Pi CM4 IO carrier board. Add this configuration to U-Boot. Features tested with a SOQuartz 4GB v1.1 2022-07-11: - SD-card boot - eMMC boot - USB host Device tree is imported from linux v6.4. Co-developed-by: Nicolas Frattaroli Signed-off-by: Nicolas Frattaroli Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi | 3 + arch/arm/dts/rk3566-soquartz-cm4.dts | 192 +++++++++++++++++++ board/pine64/quartz64_rk3566/MAINTAINERS | 3 + configs/soquartz-cm4-rk3566_defconfig | 90 +++++++++ doc/board/rockchip/rockchip.rst | 1 + 6 files changed, 290 insertions(+) create mode 100644 arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz-cm4.dts create mode 100644 configs/soquartz-cm4-rk3566_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 916de092c55..bb4d63577e8 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -175,6 +175,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-quartz64-b.dtb \ rk3566-radxa-cm3-io.dtb \ rk3566-soquartz-blade.dtb \ + rk3566-soquartz-cm4.dtb \ rk3566-soquartz-model-a.dtb \ rk3568-evb.dtb \ rk3568-nanopi-r5c.dtb \ diff --git a/arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi b/arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi new file mode 100644 index 00000000000..0e662eafa4c --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3566-soquartz-u-boot.dtsi" diff --git a/arch/arm/dts/rk3566-soquartz-cm4.dts b/arch/arm/dts/rk3566-soquartz-cm4.dts new file mode 100644 index 00000000000..cddf6cd2fec --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz-cm4.dts @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-soquartz.dtsi" + +/ { + model = "Pine64 RK3566 SoQuartz with CM4-IO Carrier Board"; + compatible = "pine64,soquartz-cm4io", "pine64,soquartz", "rockchip,rk3566"; + + /* labeled +12v in schematic */ + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + /* labeled +5v in schematic */ + vcc_5v: vcc-5v-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_sd_pwr: vcc-sd-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sd_pwr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; +}; + +/* phy for pcie */ +&combphy2 { + phy-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +&gmac1 { + status = "okay"; +}; + +/* + * i2c1 is exposed on CM1 / Module1A + * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu + * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu + */ +&i2c1 { + status = "okay"; + + /* + * the rtc interrupt is tied to PMIC_PWRON, + * it will force reset the board if triggered. + */ + pcf85063: rtc@51 { + compatible = "nxp,pcf85063"; + reg = <0x51>; + }; +}; + +/* + * i2c2 is exposed on CM1 / Module1A - to PI40 + * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch + * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3 + */ +&i2c2 { + status = "disabled"; +}; + +/* + * i2c3 is exposed on CM1 / Module1A - to PI40 + * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3 + * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3 + */ +&i2c3 { + status = "disabled"; +}; + +/* + * i2c4 is exposed on CM2 / Module1B - to PI40 + * pin 45 - GPIO24 - i2c4_scl_m1 + * pin 47 - GPIO23 - i2c4_sda_m1 + */ +&i2c4 { + status = "disabled"; +}; + +/* + * i2s1_8ch is exposed on CM1 / Module1A - to PI40 + * pin 24 - GPIO26 - i2s1_sdi1_m1 + * pin 25 - GPIO21 - i2s1_sdo0_m1 + * pin 26 - GPIO19 - i2s1_lrck_tx_m1 + * pin 27 - GPIO20 - i2s1_sdi0_m1 + * pin 29 - GPIO16 - i2s1_sdi3_m1 + * pin 30 - GPIO6 - i2s1_sdi2_m1 + * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3 + * pin 41 - GPIO25 - i2s1_sdo2_m1 + * pin 49 - GPIO18 - i2s1_sclk_tx_m1 + * pin 50 - GPIO17 - i2s1_mclk_m1 + * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2 + */ +&i2s1_8ch { + status = "disabled"; +}; + +&led_diy { + status = "okay"; +}; + +&led_work { + status = "okay"; +}; + +&pcie2x1 { + vpcie3v3-supply = <&vcc_3v3>; + status = "okay"; +}; + +&rgmii_phy1 { + status = "okay"; +}; + +/* + * saradc is exposed on CM1 / Module1A - to J2 + * pin 94 - AIN1 - saradc_vin3 + * pin 96 - AIN0 - saradc_vin2 + */ +&saradc { + status = "disabled"; +}; + +&sdmmc0 { + vmmc-supply = <&vcc_sd_pwr>; + status = "okay"; +}; + +/* + * spi3 is exposed on CM1 / Module1A - to PI40 + * pin 37 - GPIO7 - spi3_cs1_m0 + * pin 38 - GPIO11 - spi3_clk_m0 + * pin 39 - GPIO8 - spi3_cs0_m0 + * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch + * pin 44 - GPIO10 - spi3_mosi_m0 + */ +&spi3 { + status = "disabled"; +}; + +/* + * uart2 is exposed on CM1 / Module1A - to PI40 + * pin 51 - GPIO15 - uart2_rx_m0 + * pin 55 - GPIO14 - uart2_tx_m0 + */ +&uart2 { + status = "okay"; +}; + +/* + * uart7 is exposed on CM1 / Module1A - to PI40 + * pin 46 - GPIO22 - uart7_tx_m2 + * pin 47 - GPIO23 - uart7_rx_m2 + */ +&uart7 { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc_5v>; + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&vbus { + vin-supply = <&vcc_5v>; +}; diff --git a/board/pine64/quartz64_rk3566/MAINTAINERS b/board/pine64/quartz64_rk3566/MAINTAINERS index 603d2ee9d5e..6b75b35a124 100644 --- a/board/pine64/quartz64_rk3566/MAINTAINERS +++ b/board/pine64/quartz64_rk3566/MAINTAINERS @@ -7,6 +7,7 @@ F: include/configs/quartz64_rk3566.h F: configs/quartz64-a-rk3566_defconfig F: configs/quartz64-b-rk3566_defconfig F: configs/soquartz-blade-rk3566_defconfig +F: configs/soquartz-cm4-rk3566_defconfig F: configs/soquartz-model-a-rk3566_defconfig F: arch/arm/dts/rk3566-quartz64-a.dts F: arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi @@ -16,5 +17,7 @@ F: arch/arm/dts/rk3566-soquartz.dtsi F: arch/arm/dts/rk3566-soquartz-u-boot.dtsi F: arch/arm/dts/rk3566-soquartz-blade.dts F: arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi +F: arch/arm/dts/rk3566-soquartz-cm4.dts +F: arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi F: arch/arm/dts/rk3566-soquartz-model-a.dts F: arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi diff --git a/configs/soquartz-cm4-rk3566_defconfig b/configs/soquartz-cm4-rk3566_defconfig new file mode 100644 index 00000000000..7e290351477 --- /dev/null +++ b/configs/soquartz-cm4-rk3566_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-cm4" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_QUARTZ64_RK3566=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-soquartz-cm4.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_CLK=y +CONFIG_GPIO_HOG=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 5b4d0285d87..10fc051cf28 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -99,6 +99,7 @@ List of mainline supported Rockchip boards: - Pine64 Quartz64-A Board (quartz64-a-rk3566_defconfig) - Pine64 Quartz64-B Board (quartz64-b-rk3566_defconfig) - Pine64 SOQuartz on Blade (soquartz-blade-rk3566_defconfig) + - Pine64 SOQuartz on CM4-IO (soquartz-cm4-rk3566_defconfig) - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566_defconfig) * rk3588 From 0e3480c1f72f18f80690f8012404eacb67a61151 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 28 Jul 2023 11:53:05 +0000 Subject: [PATCH 23/45] rockchip: rk356x: Sync dtsi from linux v6.4 Sync rk356x.dtsi from linux v6.4. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3568-pinctrl.dtsi | 94 ++++++++++++++++++++++++++++++++ arch/arm/dts/rk356x.dtsi | 14 +++-- 2 files changed, 102 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/rk3568-pinctrl.dtsi b/arch/arm/dts/rk3568-pinctrl.dtsi index 8f90c66dd9e..0a979bfb63d 100644 --- a/arch/arm/dts/rk3568-pinctrl.dtsi +++ b/arch/arm/dts/rk3568-pinctrl.dtsi @@ -3117,4 +3117,98 @@ <0 RK_PA1 0 &pcfg_pull_none>; }; }; + + lcdc { + /omit-if-no-ref/ + lcdc_clock: lcdc-clock { + rockchip,pins = + /* lcdc_clk */ + <3 RK_PA0 1 &pcfg_pull_none>, + /* lcdc_den */ + <3 RK_PC3 1 &pcfg_pull_none>, + /* lcdc_hsync */ + <3 RK_PC1 1 &pcfg_pull_none>, + /* lcdc_vsync */ + <3 RK_PC2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + lcdc_data16: lcdc-data16 { + rockchip,pins = + /* lcdc_d3 */ + <2 RK_PD3 1 &pcfg_pull_none>, + /* lcdc_d4 */ + <2 RK_PD4 1 &pcfg_pull_none>, + /* lcdc_d5 */ + <2 RK_PD5 1 &pcfg_pull_none>, + /* lcdc_d6 */ + <2 RK_PD6 1 &pcfg_pull_none>, + /* lcdc_d7 */ + <2 RK_PD7 1 &pcfg_pull_none>, + /* lcdc_d10 */ + <3 RK_PA3 1 &pcfg_pull_none>, + /* lcdc_d11 */ + <3 RK_PA4 1 &pcfg_pull_none>, + /* lcdc_d12 */ + <3 RK_PA5 1 &pcfg_pull_none>, + /* lcdc_d13 */ + <3 RK_PA6 1 &pcfg_pull_none>, + /* lcdc_d14 */ + <3 RK_PA7 1 &pcfg_pull_none>, + /* lcdc_d15 */ + <3 RK_PB0 1 &pcfg_pull_none>, + /* lcdc_d19 */ + <3 RK_PB4 1 &pcfg_pull_none>, + /* lcdc_d20 */ + <3 RK_PB5 1 &pcfg_pull_none>, + /* lcdc_d21 */ + <3 RK_PB6 1 &pcfg_pull_none>, + /* lcdc_d22 */ + <3 RK_PB7 1 &pcfg_pull_none>, + /* lcdc_d23 */ + <3 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + lcdc_data18: lcdc-data18 { + rockchip,pins = + /* lcdc_d2 */ + <2 RK_PD2 1 &pcfg_pull_none>, + /* lcdc_d3 */ + <2 RK_PD3 1 &pcfg_pull_none>, + /* lcdc_d4 */ + <2 RK_PD4 1 &pcfg_pull_none>, + /* lcdc_d5 */ + <2 RK_PD5 1 &pcfg_pull_none>, + /* lcdc_d6 */ + <2 RK_PD6 1 &pcfg_pull_none>, + /* lcdc_d7 */ + <2 RK_PD7 1 &pcfg_pull_none>, + /* lcdc_d10 */ + <3 RK_PA3 1 &pcfg_pull_none>, + /* lcdc_d11 */ + <3 RK_PA4 1 &pcfg_pull_none>, + /* lcdc_d12 */ + <3 RK_PA5 1 &pcfg_pull_none>, + /* lcdc_d13 */ + <3 RK_PA6 1 &pcfg_pull_none>, + /* lcdc_d14 */ + <3 RK_PA7 1 &pcfg_pull_none>, + /* lcdc_d15 */ + <3 RK_PB0 1 &pcfg_pull_none>, + /* lcdc_d18 */ + <3 RK_PB3 1 &pcfg_pull_none>, + /* lcdc_d19 */ + <3 RK_PB4 1 &pcfg_pull_none>, + /* lcdc_d20 */ + <3 RK_PB5 1 &pcfg_pull_none>, + /* lcdc_d21 */ + <3 RK_PB6 1 &pcfg_pull_none>, + /* lcdc_d22 */ + <3 RK_PB7 1 &pcfg_pull_none>, + /* lcdc_d23 */ + <3 RK_PC0 1 &pcfg_pull_none>; + }; + }; + }; diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi index e0591c194be..61680c7ac48 100644 --- a/arch/arm/dts/rk356x.dtsi +++ b/arch/arm/dts/rk356x.dtsi @@ -422,8 +422,9 @@ clock-names = "xin24m"; #clock-cells = <1>; #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; - assigned-clock-rates = <1200000000>, <200000000>; + assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; + assigned-clock-rates = <32768>, <1200000000>, <200000000>; + assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; rockchip,grf = <&grf>; }; @@ -743,8 +744,8 @@ compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x00 0xfe060000 0x00 0x10000>; interrupts = ; - clock-names = "pclk", "hclk"; - clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>; + clock-names = "pclk"; + clocks = <&cru PCLK_DSITX_0>; phy-names = "dphy"; phys = <&dsi_dphy0>; power-domains = <&power RK3568_PD_VO>; @@ -771,8 +772,8 @@ compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xfe070000 0x0 0x10000>; interrupts = ; - clock-names = "pclk", "hclk"; - clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>; + clock-names = "pclk"; + clocks = <&cru PCLK_DSITX_1>; phy-names = "dphy"; phys = <&dsi_dphy1>; power-domains = <&power RK3568_PD_VO>; @@ -966,6 +967,7 @@ clock-names = "aclk_mst", "aclk_slv", "aclk_dbi", "pclk", "aux"; device_type = "pci"; + #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie_intc 0>, <0 0 0 2 &pcie_intc 1>, From 23ad80a360e70b7e2d8de852328f058fd8dca70d Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 28 Jul 2023 11:53:06 +0000 Subject: [PATCH 24/45] rockchip: rk3566-radxa-cm3-io: Sync dts from linux v6.4 Sync rk3566-radxa-cm3-io.dts from linux v6.4. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3566-radxa-cm3-io.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/rk3566-radxa-cm3-io.dts b/arch/arm/dts/rk3566-radxa-cm3-io.dts index d89d5263cb5..5e4236af4fc 100644 --- a/arch/arm/dts/rk3566-radxa-cm3-io.dts +++ b/arch/arm/dts/rk3566-radxa-cm3-io.dts @@ -254,6 +254,14 @@ status = "okay"; }; +&usb2phy0_otg { + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + &vop { assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; From a3ef37a08df3c6aa463ad794e1f788d8a24b129c Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 28 Jul 2023 11:53:07 +0000 Subject: [PATCH 25/45] rockchip: rk356x-u-boot: Add bootph-all to common pinctrl nodes Add bootph-all prop to common pinctrl nodes for eMMC, FSPI, SD-card and UART2 that are typically used by multiple boards. Unreferenced nodes are removed from the SPL device tree during a normal build. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 56 ----------------- arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 54 ----------------- arch/arm/dts/rk356x-u-boot.dtsi | 64 ++++++++++++++++++++ 3 files changed, 64 insertions(+), 110 deletions(-) diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi index 57b77151c57..c925439f71c 100644 --- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi +++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi @@ -11,67 +11,11 @@ }; }; -&emmc_bus8 { - bootph-all; -}; - -&emmc_clk { - bootph-all; -}; - -&emmc_cmd { - bootph-all; -}; - -&emmc_datastrobe { - bootph-all; -}; - -&pinctrl { - bootph-all; -}; - -&pcfg_pull_none { - bootph-all; -}; - -&pcfg_pull_up_drv_level_2 { - bootph-all; -}; - -&pcfg_pull_up { - bootph-all; -}; - -&sdmmc0_bus4 { - bootph-all; -}; - -&sdmmc0_clk { - bootph-all; -}; - -&sdmmc0_cmd { - bootph-all; -}; - -&sdmmc0_det { - bootph-all; -}; - -&sdmmc0_pwren { - bootph-all; -}; - &sdhci { cap-mmc-highspeed; mmc-ddr-1_8v; }; -&uart2m0_xfer { - bootph-all; -}; - &uart2 { clock-frequency = <24000000>; bootph-all; diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi index a6cee5609df..45e06a91b86 100644 --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi @@ -16,26 +16,6 @@ }; }; -&emmc_bus8 { - bootph-all; -}; - -&emmc_clk { - bootph-all; -}; - -&emmc_cmd { - bootph-all; -}; - -&emmc_datastrobe { - bootph-all; -}; - -&fspi_pins { - bootph-all; -}; - &pcie2x1 { pinctrl-0 = <&pcie20m1_pins &pcie_reset_h>; }; @@ -45,8 +25,6 @@ }; &pinctrl { - bootph-all; - pcie { pcie3x2_reset_h: pcie3x2-reset-h { rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; @@ -54,34 +32,6 @@ }; }; -&pcfg_pull_none { - bootph-all; -}; - -&pcfg_pull_up_drv_level_2 { - bootph-all; -}; - -&pcfg_pull_up { - bootph-all; -}; - -&sdmmc0_bus4 { - bootph-all; -}; - -&sdmmc0_clk { - bootph-all; -}; - -&sdmmc0_cmd { - bootph-all; -}; - -&sdmmc0_det { - bootph-all; -}; - &sdhci { cap-mmc-highspeed; mmc-ddr-1_8v; @@ -115,10 +65,6 @@ status = "disabled"; }; -&uart2m0_xfer { - bootph-all; -}; - &uart2 { clock-frequency = <24000000>; bootph-all; diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index c340c2bba6f..89c0d830b63 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -59,6 +59,70 @@ status = "okay"; }; +&pinctrl { + bootph-all; +}; + +&pcfg_pull_none { + bootph-all; +}; + +&pcfg_pull_up_drv_level_2 { + bootph-all; +}; + +&pcfg_pull_up { + bootph-all; +}; + +&emmc_bus8 { + bootph-all; +}; + +&emmc_clk { + bootph-all; +}; + +&emmc_cmd { + bootph-all; +}; + +&emmc_datastrobe { + bootph-all; +}; + +&emmc_rstnout { + bootph-all; +}; + +&fspi_pins { + bootph-all; +}; + +&sdmmc0_bus4 { + bootph-all; +}; + +&sdmmc0_clk { + bootph-all; +}; + +&sdmmc0_cmd { + bootph-all; +}; + +&sdmmc0_det { + bootph-all; +}; + +&sdmmc0_pwren { + bootph-all; +}; + +&uart2m0_xfer { + bootph-all; +}; + &sdhci { bootph-pre-ram; status = "okay"; From f40dcc7d1e74ff5aa5f709918e26cb31277dcea0 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 28 Jul 2023 11:53:08 +0000 Subject: [PATCH 26/45] rockchip: rk356x-u-boot: Use relaxed u-boot,spl-boot-order BootRom will try to load TPL+SPL from media in the following order: - SPI NOR Flash - SPI NAND Flash - NAND Flash - eMMC - SDMMC SPL will try to load FIT from media in the order defined in the device tree u-boot,spl-boot-order property. Change the default order to load FIT from to: - same media as TPL+SPL - SDMMC - eMMC Boards with strict load order requirements should override the u-boot,spl-boot-order property in the board specific u-boot.dtsi. Fixes: 42f67fb51cb4 ("rockchip: rk3568: Fix boot device detection") Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk356x-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index 89c0d830b63..5644f78ec77 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -12,7 +12,7 @@ }; chosen { - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc0; + u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; }; dmc: dmc { From ada63287386e618190c644b25961dae15d4e79f5 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 28 Jul 2023 11:38:34 +0000 Subject: [PATCH 27/45] rockchip: rk3399-rockpro64: Fix SPL max size and SPI flash payload offset TPL max size is limited to 184 KB, SPL is loaded to 0x0 and TF-A is loaded to 0x40000, this limit SPL max size to 256 KB. With BootRom only reading first 2 KB per 4 KB page of SPI flash, 880 KB may be needed for TPL+SPL in a worst-case scenario. (184 KB + 256 KB) x 2 = 880 KB Use 0xE0000 (896 KB) as the payload offset in SPI flash, this allows for a payload of 3168 KB before env offset start to overlap. Also remove CONFIG_LTO=y now that there is sufficient space for SPL in SPI flash, and to fix a build issue reported by Peter Robinson. Fixes: 5713135ecc75 ("rockchip: rockpro64: Build u-boot-rockchip-spi.bin") Reported-by: Peter Robinson Signed-off-by: Jonas Karlman Reviewed-by: Quentin Schulz Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 4 ---- configs/rockpro64-rk3399_defconfig | 5 ++--- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi index bd864d06701..732727d9b03 100644 --- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi @@ -9,10 +9,6 @@ chosen { u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdmmc, &sdhci; }; - - config { - u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */ - }; }; &sdhci { diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 62daad27a6f..4cd6b76665b 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -21,7 +21,6 @@ CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y -CONFIG_LTO=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_BOOTSTAGE=y @@ -30,7 +29,7 @@ CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x400000 @@ -40,7 +39,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y From cc11d5c4ba27271de615497bdf2785fe3620e30d Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 28 Jul 2023 11:38:35 +0000 Subject: [PATCH 28/45] rockchip: rk3399-pinebook-pro: Fix SPL max size and SPI flash payload offset TPL max size is limited to 184 KB, SPL is loaded to 0x0 and TF-A is loaded to 0x40000, this limit SPL max size to 256 KB. With BootRom only reading first 2 KB per 4 KB page of SPI flash, 880 KB may be needed for TPL+SPL in a worst-case scenario. (184 KB + 256 KB) x 2 = 880 KB Use 0xE0000 (896 KB) as the payload offset in SPI flash, this allows for a payload of 3168 KB before env offset start to overlap. Also add CONFIG_ROCKCHIP_SPI_IMAGE=y to build a bootable SPI flash image, u-boot-rockchip-spi.bin. Signed-off-by: Jonas Karlman Reviewed-by: Quentin Schulz Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 4 ---- configs/pinebook-pro-rk3399_defconfig | 4 +++- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi index ea7a5a17ae0..88a77cad8d4 100644 --- a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi @@ -10,10 +10,6 @@ chosen { u-boot,spl-boot-order = "same-as-spl", &sdhci, &spiflash, &sdmmc; }; - - config { - u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */ - }; }; &edp { diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index 5d493c910ee..ae3211bbe9c 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -12,6 +12,7 @@ CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_PINEBOOK_PRO_RK3399=y CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -26,7 +27,7 @@ CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinebook-pro.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x400000 @@ -36,6 +37,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y From 263f81d3a509e09289c3eba2f7cd0b49eb9f5145 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 28 Jul 2023 11:38:37 +0000 Subject: [PATCH 29/45] rockchip: rk3399-pinephone-pro: Fix SPL max size and SPI flash payload offset TPL max size is limited to 184 KB, SPL is loaded to 0x0 and TF-A is loaded to 0x40000, this limit SPL max size to 256 KB. With BootRom only reading first 2 KB per 4 KB page of SPI flash, 880 KB may be needed for TPL+SPL in a worst-case scenario. (184 KB + 256 KB) x 2 = 880 KB Use 0xE0000 (896 KB) as the payload offset in SPI flash, this allows for a payload of 3168 KB before env offset start to overlap. Also add CONFIG_ROCKCHIP_SPI_IMAGE=y to build a bootable SPI flash image, u-boot-rockchip-spi.bin. Signed-off-by: Jonas Karlman Reviewed-by: Quentin Schulz Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 4 ---- configs/pinephone-pro-rk3399_defconfig | 4 +++- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi index 347243fe479..cabf0a9dae8 100644 --- a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi @@ -10,10 +10,6 @@ chosen { u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; }; - - config { - u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */ - }; }; &rng { diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig index f97a4003bba..11243bc5c19 100644 --- a/configs/pinephone-pro-rk3399_defconfig +++ b/configs/pinephone-pro-rk3399_defconfig @@ -12,6 +12,7 @@ CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_PINEPHONE_PRO_RK3399=y CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -25,7 +26,7 @@ CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinephone-pro.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x400000 @@ -35,6 +36,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y From ee75f168680669180b1e2eb14de71b8c6e3f7973 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 28 Jul 2023 11:38:38 +0000 Subject: [PATCH 30/45] rockchip: rk3399-roc-pc: Fix SPL max size and SPI flash payload offset TPL max size is limited to 184 KB, SPL is loaded to 0x0 and TF-A is loaded to 0x40000, this limit SPL max size to 256 KB. With BootRom only reading first 2 KB per 4 KB page of SPI flash, 880 KB may be needed for TPL+SPL in a worst-case scenario. (184 KB + 256 KB) x 2 = 880 KB Use 0xE0000 (896 KB) as the payload offset in SPI flash, this allows for a payload of 3168 KB before env offset start to overlap. Also add CONFIG_ROCKCHIP_SPI_IMAGE=y to build a bootable SPI flash image, u-boot-rockchip-spi.bin. Signed-off-by: Jonas Karlman Reviewed-by: Quentin Schulz Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 4 ---- configs/roc-pc-mezzanine-rk3399_defconfig | 4 +++- configs/roc-pc-rk3399_defconfig | 4 +++- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi index f85e7b62d9a..c8f4418a738 100644 --- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi +++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi @@ -11,10 +11,6 @@ u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdhci, &sdmmc; }; - config { - u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */ - }; - vcc_hub_en: vcc_hub_en-regulator { compatible = "regulator-fixed"; enable-active-high; diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index 0d113c764f6..06d97c3e1a2 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -13,6 +13,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc-mezzanine" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_ROC_PC_RK3399=y CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -26,7 +27,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x400000 @@ -37,6 +38,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 7e5db741951..c53e8622431 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -14,6 +14,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_ROC_PC_RK3399=y CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -27,7 +28,7 @@ CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x400000 @@ -38,6 +39,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y From 6ed39520a70e76dd9b3f374d62a60de986f051c0 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 28 Jul 2023 11:38:40 +0000 Subject: [PATCH 31/45] doc: rockchip: Update SPI flashing instruction Update documentation on how to write a bootable u-boot-rockchip-spi.bin image into SPI flash. This removes the reference to a hardcoded and now obsolete 0x60000 payload offset. Also remove an obsolete reference to pad_cat. Signed-off-by: Jonas Karlman Reviewed-by: Quentin Schulz Reviewed-by: Kever Yang --- doc/board/rockchip/rockchip.rst | 26 +++++--------------------- 1 file changed, 5 insertions(+), 21 deletions(-) diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 10fc051cf28..e23237e453f 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -218,7 +218,7 @@ SD Card ^^^^^^^ All Rockchip platforms (except rk3128 which doesn't use SPL) are now -supporting a single boot image using binman and pad_cat. +supporting a single boot image using binman. To write an image that boots from a SD card (assumed to be /dev/sda): @@ -269,31 +269,15 @@ is u-boot-dtb.img SPI ^^^ -The SPI boot method requires the generation of idbloader.img with help of the mkimage tool. +Write u-boot-rockchip-spi.bin to offset 0 of SPI flash. -SPL-alone SPI boot image: - -.. code-block:: bash - - ./tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin idbloader.img - -TPL+SPL SPI boot image: - -.. code-block:: bash - - ./tools/mkimage -n rk3399 -T rkspi -d tpl/u-boot-tpl.bin:spl/u-boot-spl.bin idbloader.img - -Copy SPI boot images into SD card and boot from SD: +Copy u-boot-rockchip-spi.bin into SD card and boot from SD: .. code-block:: bash sf probe - load mmc 1:1 $kernel_addr_r idbloader.img - sf erase 0 +$filesize - sf write $kernel_addr_r 0 ${filesize} - load mmc 1:1 ${kernel_addr_r} u-boot.itb - sf erase 0x60000 +$filesize - sf write $kernel_addr_r 0x60000 ${filesize} + load mmc 1:1 $kernel_addr_r u-boot-rockchip-spi.bin + sf update $fileaddr 0 $filesize 2. Package the image with Rockchip miniloader --------------------------------------------- From 52f6b96d27c8aabca697ac395e86a3481f1c53b7 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 28 Jul 2023 12:05:40 +0000 Subject: [PATCH 32/45] rockchip: rk3568-rock-3a: Fix SPI Flash alias The commit 64f79f88a751 ("rockchip: rk3568-rock-3a: Enable boot from SPI NOR flash") enabled SPI flash support by overriding the spi0 alias. Correct this by adding a new spi4 alias in rk356x-u-boot.dtsi and SF_DEFAULT_BUS=4 and SPL_DM_SEQ_ALIAS=y in defconfig. Also enabled support for parsing and auto discovery of parameters, SFDP. Fixes: 64f79f88a751 ("rockchip: rk3568-rock-3a: Enable boot from SPI NOR flash") Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 4 ---- arch/arm/dts/rk356x-u-boot.dtsi | 1 + configs/rock-3a-rk3568_defconfig | 3 +++ 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi index 45e06a91b86..a36a329f59c 100644 --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi @@ -7,10 +7,6 @@ #include "rk356x-u-boot.dtsi" / { - aliases { - spi0 = &sfc; - }; - chosen { stdout-path = &uart2; }; diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index 5644f78ec77..d21b1820522 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -9,6 +9,7 @@ aliases { mmc0 = &sdhci; mmc1 = &sdmmc0; + spi4 = &sfc; }; chosen { diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig index 1e8256e6025..44ff054df66 100644 --- a/configs/rock-3a-rk3568_defconfig +++ b/configs/rock-3a-rk3568_defconfig @@ -57,6 +57,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SCSI_AHCI=y @@ -71,6 +72,8 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=4 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_XTX=y CONFIG_ETH_DESIGNWARE=y From 747f9f26633835bb1f80efac2270d075666cccf1 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 28 Jul 2023 12:05:41 +0000 Subject: [PATCH 33/45] rockchip: rk3588-rock-5b: Fix SPI Flash alias The commit fd6e425be243 ("rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash") enabled SPI flash support by adding a spi0 alias. Correct this by adding spi0-spi5 aliases in rk3588s-u-boot.dtsi and SF_DEFAULT_BUS=5 and SPL_DM_SEQ_ALIAS=y in defconfig. Also enabled support for parsing and auto discovery of parameters, SFDP. Fixes: fd6e425be243 ("rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash") Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 1 - arch/arm/dts/rk3588s-u-boot.dtsi | 9 +++++++++ configs/rock5b-rk3588_defconfig | 3 +++ 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 5a329269964..549b242be0a 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -12,7 +12,6 @@ / { aliases { mmc1 = &sdmmc; - spi0 = &sfc; }; chosen { diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index acb1cfe2006..489c5edd624 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -7,6 +7,15 @@ #include / { + aliases { + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + spi4 = &spi4; + spi5 = &sfc; + }; + dmc { compatible = "rockchip,rk3588-dmc"; bootph-all; diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 3976a6c0f05..3fa65cbf9b0 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -60,6 +60,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y @@ -73,6 +74,8 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_XTX=y CONFIG_ETH_DESIGNWARE=y From def50c66ccc839da8df8e31a4e3a7decaaaa2b17 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 31 Jul 2023 04:28:34 +0000 Subject: [PATCH 34/45] rockchip: rk3568-rock-3a: Fix pcie2x1 and pcie3x2 pinctrl override The pcie pinctrl override added in the commit a76aa6ffa6cd ("rockchip: rk3568-rock-3a: Enable PCIe and NVMe support") is causing a pinmux issue on linux when using a EFI boot flow. The pcie reset-gpios must however be configured with gpio function, or the device will freeze running pci enum and nothing is connected. Adjust the pinctrl override in u-boot.dtsi to fix this issue. PCIe/NVMe continues to work in both U-Boot and linux after this change. Also revert disable of sdmmc2 and uart1 to fix use of wifi in linux when using a EFI boot flow. Fixes: a76aa6ffa6cd ("rockchip: rk3568-rock-3a: Enable PCIe and NVMe support") Fixes: 073d911ae64a ("rockchip: rk3568-rock-3a: Sync device tree from linux") Signed-off-by: Jonas Karlman --- arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi index a36a329f59c..b05b7151e6c 100644 --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi @@ -12,12 +12,8 @@ }; }; -&pcie2x1 { - pinctrl-0 = <&pcie20m1_pins &pcie_reset_h>; -}; - &pcie3x2 { - pinctrl-0 = <&pcie30x2m1_pins &pcie3x2_reset_h>; + pinctrl-0 = <&pcie3x2_reset_h>; }; &pinctrl { @@ -53,14 +49,6 @@ }; }; -&sdmmc2 { - status = "disabled"; -}; - -&uart1 { - status = "disabled"; -}; - &uart2 { clock-frequency = <24000000>; bootph-all; From 7031224000a03e62ae4ae4f8228cbdd10339f5a7 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Tue, 4 Jul 2023 22:05:11 +0300 Subject: [PATCH 35/45] ARM: dts: rockchip: rk3588: Move bootph-all props to common file Move bootph-all prop to common SoC dt file, because they are typically used by multiple boards. Unreferenced nodes are removed from the SPL device tree during a normal build. Suggested-by: Jonas Karlman Signed-off-by: Eugen Hristev Reviewed-by: Kever Yang --- arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 54 ------------------------ arch/arm/dts/rk3588s-u-boot.dtsi | 56 +++++++++++++++++++++++++ 2 files changed, 56 insertions(+), 54 deletions(-) diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 549b242be0a..1b2fcbb0bb1 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -76,26 +76,6 @@ status = "okay"; }; -&emmc_bus8 { - bootph-all; -}; - -&emmc_clk { - bootph-all; -}; - -&emmc_cmd { - bootph-all; -}; - -&emmc_data_strobe { - bootph-all; -}; - -&emmc_rstnout { - bootph-all; -}; - &fspim2_pins { bootph-all; }; @@ -108,8 +88,6 @@ }; &pinctrl { - bootph-all; - pcie { pcie_reset_h: pcie-reset-h { rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; @@ -138,39 +116,11 @@ }; }; -&pcfg_pull_none { - bootph-all; -}; - -&pcfg_pull_up_drv_level_2 { - bootph-all; -}; - -&pcfg_pull_up { - bootph-all; -}; - &sdmmc { bus-width = <4>; status = "okay"; }; -&sdmmc_bus4 { - bootph-all; -}; - -&sdmmc_clk { - bootph-all; -}; - -&sdmmc_cmd { - bootph-all; -}; - -&sdmmc_det { - bootph-all; -}; - &sdhci { cap-mmc-highspeed; mmc-ddr-1_8v; @@ -198,10 +148,6 @@ }; }; -&uart2m0_xfer { - bootph-all; -}; - &usb_host0_ehci { companion = <&usb_host0_ohci>; phys = <&u2phy2_host>; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index 489c5edd624..245bc8b27c3 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -311,6 +311,42 @@ }; }; +&emmc_bus8 { + bootph-all; +}; + +&emmc_clk { + bootph-all; +}; + +&emmc_cmd { + bootph-all; +}; + +&emmc_data_strobe { + bootph-all; +}; + +&emmc_rstnout { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&pcfg_pull_none { + bootph-all; +}; + +&pcfg_pull_up_drv_level_2 { + bootph-all; +}; + +&pcfg_pull_up { + bootph-all; +}; + &xin24m { bootph-all; status = "okay"; @@ -344,12 +380,32 @@ u-boot,spl-fifo-mode; }; +&sdmmc_bus4 { + bootph-all; +}; + +&sdmmc_clk { + bootph-all; +}; + +&sdmmc_cmd { + bootph-all; +}; + +&sdmmc_det { + bootph-all; +}; + &uart2 { clock-frequency = <24000000>; bootph-pre-ram; status = "okay"; }; +&uart2m0_xfer { + bootph-all; +}; + &ioc { bootph-pre-ram; }; From b8fc65473ae74776e7cac47c793a5ac295dea928 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Tue, 4 Jul 2023 22:05:12 +0300 Subject: [PATCH 36/45] board: rockchip: add Radxa ROCK5A Rk3588 board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ROCK 5A is a Rockchip RK3588S based SBC (Single Board Computer) by Radxa. There are tree variants depending on the DRAM size : 4G, 8G and 16G. Specifications: Rockchip Rk3588S SoC 4x ARM Cortex-A76, 4x ARM Cortex-A55 4/8/16GB memory LPDDR4x Mali G610MC4 GPU MIPI CSI 2 multiple lanes connector 4-lane MIPI DSI connector Audio – 3.5mm earphone jack eMMC module connector uSD slot (up to 128GB) 2x USB 2.0, 2x USB 3.0 2x micro HDMI 2.1 ports, one up to 8Kp60, the other up to 4Kp60 Gigabit Ethernet RJ45 with optional PoE support 40-pin IO header including UART, SPI, I2C and 5V DC power in USB PD over USB Type-C Size: 85mm x 56mm (Raspberry Pi 4 form factor) Kernel commits: d1824cf95799 ("arm64: dts: rockchip: Add rock-5a board") 991f136c9f8d ("arm64: dts: rockchip: Update sdhci alias for rock-5a") 304c8a759953 ("arm64: dts: rockchip: Remove empty line from rock-5a") cda0c2ea65a0 ("arm64: dts: rockchip: Fix RX delay for ethernet phy on rk3588s-rock5a") Signed-off-by: Eugen Hristev Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi | 34 ++++++++++ arch/arm/dts/rk3588s-rock-5a.dts | 73 +++++++++++++++++++++ arch/arm/mach-rockchip/rk3588/Kconfig | 29 +++++++- board/radxa/rock5a-rk3588s/Kconfig | 15 +++++ board/radxa/rock5a-rk3588s/MAINTAINERS | 6 ++ board/radxa/rock5a-rk3588s/Makefile | 6 ++ board/radxa/rock5a-rk3588s/rock5a-rk3588s.c | 39 +++++++++++ configs/rock5a-rk3588s_defconfig | 72 ++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + include/configs/rock5a-rk3588s.h | 15 +++++ 11 files changed, 290 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi create mode 100644 arch/arm/dts/rk3588s-rock-5a.dts create mode 100644 board/radxa/rock5a-rk3588s/Kconfig create mode 100644 board/radxa/rock5a-rk3588s/MAINTAINERS create mode 100644 board/radxa/rock5a-rk3588s/Makefile create mode 100644 board/radxa/rock5a-rk3588s/rock5a-rk3588s.c create mode 100644 configs/rock5a-rk3588s_defconfig create mode 100644 include/configs/rock5a-rk3588s.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index bb4d63577e8..edf9608620c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -187,6 +187,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \ rk3588-edgeble-neu6a-io.dtb \ rk3588-edgeble-neu6b-io.dtb \ rk3588-evb1-v10.dtb \ + rk3588s-rock-5a.dtb \ rk3588-rock-5b.dtb dtb-$(CONFIG_ROCKCHIP_RV1108) += \ diff --git a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi new file mode 100644 index 00000000000..9bb0e4f89e1 --- /dev/null +++ b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Collabora Ltd. + */ + +#include "rk3588s-u-boot.dtsi" +#include +#include +#include +#include + +/ { + aliases { + mmc1 = &sdmmc; + }; + + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; + }; +}; + +&sdmmc { + bus-width = <4>; + status = "okay"; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>; +}; + diff --git a/arch/arm/dts/rk3588s-rock-5a.dts b/arch/arm/dts/rk3588s-rock-5a.dts new file mode 100644 index 00000000000..901825514f9 --- /dev/null +++ b/arch/arm/dts/rk3588s-rock-5a.dts @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include "rk3588s.dtsi" + +/ { + model = "Radxa ROCK 5 Model A"; + compatible = "radxa,rock-5a", "rockchip,rk3588s"; + + aliases { + mmc0 = &sdhci; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + pinctrl-names = "default"; + tx_delay = <0x3a>; + rx_delay = <0x3e>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + rtl8211f { + rtl8211f_rst: rtl8211f-rst { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index d72ef92f2ef..79fcc99b898 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -28,7 +28,33 @@ config TARGET_RK3588_NEU6 IO board and Neu6a needs to mount on top of this IO board in order to create complete Edgeble Neural Compute Module 6B(Neu6B) IO platform. -config TARGET_ROCK5B_RK3588 +config TARGET_ROCK5A_RK3588 + bool "Radxa ROCK5A RK3588 board" + select BOARD_LATE_INIT + help + Radxa ROCK5A is a Rockchip RK3588S based SBC (Single Board Computer) + by Radxa. + + There are tree variants depending on the DRAM size : 4G, 8G and 16G. + + Specification: + + Rockchip Rk3588S SoC + 4x ARM Cortex-A76, 4x ARM Cortex-A55 + 4/8/16GB memory LPDDR4x + Mali G610MC4 GPU + MIPI CSI 2 multiple lanes connector + 4-lane MIPI DSI connector + Audio – 3.5mm earphone jack + eMMC module connector + uSD slot (up to 128GB) + 2x USB 2.0, 2x USB 3.0 + 2x micro HDMI 2.1 ports, one up to 8Kp60, the other up to 4Kp60 + Gigabit Ethernet RJ45 with optional PoE support + 40-pin IO header including UART, SPI, I2C and 5V DC power in + USB PD over USB Type-C + Size: 85mm x 56mm (Raspberry Pi 4 form factor) + config TARGET_ROCK5B_RK3588 bool "Radxa ROCK5B RK3588 board" select BOARD_LATE_INIT @@ -68,6 +94,7 @@ config SYS_MALLOC_F_LEN source board/edgeble/neural-compute-module-6/Kconfig source board/rockchip/evb_rk3588/Kconfig +source board/radxa/rock5a-rk3588s/Kconfig source board/radxa/rock5b-rk3588/Kconfig endif diff --git a/board/radxa/rock5a-rk3588s/Kconfig b/board/radxa/rock5a-rk3588s/Kconfig new file mode 100644 index 00000000000..2d7fc85df4f --- /dev/null +++ b/board/radxa/rock5a-rk3588s/Kconfig @@ -0,0 +1,15 @@ +if TARGET_ROCK5A_RK3588 + +config SYS_BOARD + default "rock5a-rk3588s" + +config SYS_VENDOR + default "radxa" + +config SYS_CONFIG_NAME + default "rock5a-rk3588s" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/radxa/rock5a-rk3588s/MAINTAINERS b/board/radxa/rock5a-rk3588s/MAINTAINERS new file mode 100644 index 00000000000..26e0ed93386 --- /dev/null +++ b/board/radxa/rock5a-rk3588s/MAINTAINERS @@ -0,0 +1,6 @@ +ROCK5A-RK3588 +M: Eugen Hristev +S: Maintained +F: board/radxa/rock5a-rk3588s +F: include/configs/rock5a-rk3588.h +F: configs/rock5a-rk3588_defconfig diff --git a/board/radxa/rock5a-rk3588s/Makefile b/board/radxa/rock5a-rk3588s/Makefile new file mode 100644 index 00000000000..48dd5124550 --- /dev/null +++ b/board/radxa/rock5a-rk3588s/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2023 Collabora Ltd. +# + +obj-y += rock5a-rk3588s.o diff --git a/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c b/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c new file mode 100644 index 00000000000..2d7a8c07dc5 --- /dev/null +++ b/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2023 Collabora Ltd. + */ + +#include +#include + +#ifdef CONFIG_OF_BOARD_SETUP +int rock5a_add_reserved_memory_fdt_nodes(void *new_blob) +{ + struct fdt_memory gap1 = { + .start = 0x3fc000000, + .end = 0x3fc4fffff, + }; + struct fdt_memory gap2 = { + .start = 0x3fff00000, + .end = 0x3ffffffff, + }; + unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP; + unsigned int ret; + + /* + * Inject the reserved-memory nodes into the DTS + */ + ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0, + NULL, flags); + if (ret) + return ret; + + return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0, + NULL, flags); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return rock5a_add_reserved_memory_fdt_nodes(blob); +} +#endif diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig new file mode 100644 index 00000000000..6cbd9817c52 --- /dev/null +++ b/configs/rock5a-rk3588s_defconfig @@ -0,0 +1,72 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3588s-rock-5a" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x1000000 +CONFIG_TARGET_ROCK5A_RK3588=y +CONFIG_SPL_STACK=0x1000000 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5a.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_SPL_PINCTRL=y +CONFIG_REGULATOR_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index e23237e453f..39e9532dd4d 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -106,6 +106,7 @@ List of mainline supported Rockchip boards: - Rockchip EVB (evb-rk3588) - Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588) - Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588) + - Radxa ROCK 5A (rock5a-rk3588s) - Radxa ROCK 5B (rock5b-rk3588) * rv1108 diff --git a/include/configs/rock5a-rk3588s.h b/include/configs/rock5a-rk3588s.h new file mode 100644 index 00000000000..9a2d3ee9f53 --- /dev/null +++ b/include/configs/rock5a-rk3588s.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2023 Collabora Ltd. + */ + +#ifndef __ROCK5A_RK3588_H +#define __ROCK5A_RK3588_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include + +#endif /* __ROCK5A_RK3588_H */ From fea7a29cc8d86a0bbcb4bcf740d47924839b1f81 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 2 Jul 2023 12:41:15 +0000 Subject: [PATCH 37/45] power: regulator: rk8xx: Add 500us delay after LDO regulator is enabled A quick power cycle of a LDO regulator during dw-mmc signal voltage change has shown that SD-card does not always get recognized. Linux driver use an enable_time of 400us for LDO regulators. Apply a 500us delay when a LDO regulator is enabled to fix possible issues. Fixes: 94afc1cb466a ("power: regulator: rk8xx: update the driver for rk808 and rk818") Signed-off-by: Jonas Karlman Reviewed-by: elaine.zhang Reviewed-by: Kever Yang --- drivers/power/regulator/rk8xx.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c index 0ee07ad299d..e95640a39b0 100644 --- a/drivers/power/regulator/rk8xx.c +++ b/drivers/power/regulator/rk8xx.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -616,6 +617,9 @@ static int _ldo_set_enable(struct udevice *pmic, int ldo, bool enable) break; } + if (enable) + udelay(500); + return ret; } From b71f74eab42782199757e146483126aee5e3c271 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 6 Jun 2023 22:39:12 +0530 Subject: [PATCH 38/45] arm64: dts: rockchip: Drop unused rk3328-xhci node rk3328-xhci has been added due to the fact that the upstream dwc3 is unsupported. Moreover, the driver for rk3328-xhci is not added to the code tree. By considering these facts and unsupported rk3328-xhci this patch is dropping all related code from DT. However, the DWC3 is fixed now in dwc3-generic and RK3328 USB 3.0 is functional in upcoming patches. Let's drop it. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3328-evb-u-boot.dtsi | 5 ----- arch/arm/dts/rk3328-roc-cc-u-boot.dtsi | 14 -------------- arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi | 5 ----- arch/arm/dts/rk3328-rock64-u-boot.dtsi | 15 --------------- arch/arm/dts/rk3328-u-boot.dtsi | 11 ----------- 5 files changed, 50 deletions(-) diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi b/arch/arm/dts/rk3328-evb-u-boot.dtsi index 95e497970ee..12b68df1ac6 100644 --- a/arch/arm/dts/rk3328-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi @@ -44,8 +44,3 @@ /* Integrated PHY unsupported by U-Boot */ status = "broken"; }; - -&usb_host0_xhci { - vbus-supply = <&vcc5v0_host_xhci>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi index 27a454f0176..2062f34bf82 100644 --- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi +++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi @@ -48,20 +48,6 @@ bootph-pre-ram; }; -&usb_host0_xhci { - vbus-supply = <&vcc_host1_5v>; - status = "okay"; -}; - -/* - * This makes XHCI responsible for toggling VBUS. This is needed to work - * around an issue where either XHCI only works with USB 2.0 or OTG doesn't - * work, depending on how VBUS is configured. Having USB 3.0 seems better. - */ -&vcc_host1_5v { - /delete-property/ regulator-always-on; -}; - /* Need this and all the pinctrl/gpio stuff above to set pinmux */ &vcc_sd { bootph-pre-ram; diff --git a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi index 088e21c76ab..1f220c6dcd0 100644 --- a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi @@ -45,11 +45,6 @@ bootph-pre-ram; }; -&usb_host0_xhci { - vbus-supply = <&vcc_host_5v>; - status = "okay"; -}; - /* Need this and all the pinctrl/gpio stuff above to set pinmux */ &vcc_sd { bootph-pre-ram; diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index c20a99a620b..849854302ee 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -48,21 +48,6 @@ bootph-pre-ram; }; -&usb_host0_xhci { - vbus-supply = <&vcc_host_5v>; - status = "okay"; -}; - -/* - * This makes XHCI responsible for toggling VBUS. This is needed to work - * around an issue where either XHCI only works with USB 2.0 or OTG doesn't - * work, depending on how VBUS is configured. Having USB 3.0 seems better. - */ -&vcc_host_5v { - /delete-property/ regulator-always-on; - /delete-property/ regulator-boot-on; -}; - /* Need this and all the pinctrl/gpio stuff above to set pinmux */ &vcc_sd { bootph-pre-ram; diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index 668f8ca29d8..ce96ce40a73 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -26,17 +26,6 @@ 0x0 0xff720000 0x0 0x1000 0x0 0xff798000 0x0 0x1000>; }; - - usb_host0_xhci: usb@ff600000 { - compatible = "rockchip,rk3328-xhci"; - reg = <0x0 0xff600000 0x0 0x100000>; - interrupts = ; - snps,dis-enblslpm-quirk; - snps,phyif-utmi-bits = <16>; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-u2-susphy-quirk; - status = "disabled"; - }; }; &cru { From 559911ff2ed09812fc0a87513183a44d9ee100cf Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 6 Jun 2023 22:39:13 +0530 Subject: [PATCH 39/45] configs: Drop unused XHCI_DWC3 for RK3328 boards Driver support for rk3328 is not supported so drop this unused XHCI_DWC3. Cc: Tianling Shen Cc: David Bauer Cc: Loic Devulder Cc: Chen-Yu Tsai Cc: Banglang Huang Cc: Matwey V. Kornilov Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- configs/evb-rk3328_defconfig | 1 - configs/nanopi-r2c-rk3328_defconfig | 1 - configs/nanopi-r2s-rk3328_defconfig | 1 - configs/roc-cc-rk3328_defconfig | 1 - configs/rock-pi-e-rk3328_defconfig | 1 - configs/rock64-rk3328_defconfig | 1 - 6 files changed, 6 deletions(-) diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 9bfb8f1df2b..96336e8ca73 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -92,7 +92,6 @@ CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set CONFIG_USB=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig index 84710c185ba..6af874ca2ce 100644 --- a/configs/nanopi-r2c-rk3328_defconfig +++ b/configs/nanopi-r2c-rk3328_defconfig @@ -97,7 +97,6 @@ CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set CONFIG_USB=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index 21d7a073e29..7b0fadbce9e 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -97,7 +97,6 @@ CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set CONFIG_USB=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index 6b3bc75ae95..477179e80e7 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -102,7 +102,6 @@ CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set CONFIG_USB=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index 68357fed07e..c46c92841ab 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -102,7 +102,6 @@ CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set CONFIG_USB=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 74a9cc0a7de..ae761d08a1d 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -100,7 +100,6 @@ CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set CONFIG_USB=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y From 185571b6ec301cd228cb059326e51fb51e76e816 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 6 Jun 2023 22:39:14 +0530 Subject: [PATCH 40/45] usb: dwc3-generic: Restrict single ctrl node for RK3328 Like Rockchip RK3568, the RK3328 also have single node to represent the glue and ctrl for USB 3.0. So, use the driver data to use single ctrl for RK3328 DWC3. Reviewed-by: Marek Vasut Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/usb/dwc3/dwc3-generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 79203f82041..b3ed728fd84 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -607,7 +607,7 @@ static const struct udevice_id dwc3_glue_ids[] = { { .compatible = "ti,dwc3", .data = (ulong)&ti_ops }, { .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops }, { .compatible = "ti,am654-dwc3" }, - { .compatible = "rockchip,rk3328-dwc3" }, + { .compatible = "rockchip,rk3328-dwc3", .data = (ulong)&rk_ops }, { .compatible = "rockchip,rk3399-dwc3" }, { .compatible = "rockchip,rk3568-dwc3", .data = (ulong)&rk_ops }, { .compatible = "qcom,dwc3" }, From 5d334b70cce1d8299202d247011b609faeb8e583 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 6 Jun 2023 22:39:15 +0530 Subject: [PATCH 41/45] configs: Enable DWC3 USB 3.0 on RK3328 boards Enable USB 3.0 in all RK3328 boards. => usb start starting USB... Bus usb@ff5c0000: ehci_generic usb@ff5c0000: Failed to get clocks (ret=-19) Port not available. Bus usb@ff5d0000: USB OHCI 1.0 Bus usb@ff600000: Register 2000140 NbrPorts 2 Starting the controller USB XHCI 1.10 Bus usb@ff580000: 1 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found => usb tree USB device tree: 1 Hub (12 Mb/s, 0mA) U-Boot Root Hub 1 Hub (5 Gb/s, 0mA) | U-Boot XHCI Host Controller | +-2 Mass Storage (5 Gb/s, 224mA) SanDisk Dual Drive 040130e3ee554b7078843f4eb331646 1 Hub (480 Mb/s, 0mA) U-Boot Root Hub Cc: Tianling Shen Cc: David Bauer Cc: Loic Devulder Cc: Chen-Yu Tsai Cc: Banglang Huang Cc: Matwey V. Kornilov Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- configs/evb-rk3328_defconfig | 2 ++ configs/nanopi-r2c-rk3328_defconfig | 2 ++ configs/nanopi-r2s-rk3328_defconfig | 2 ++ configs/roc-cc-rk3328_defconfig | 2 ++ configs/rock-pi-e-rk3328_defconfig | 2 ++ configs/rock64-rk3328_defconfig | 2 ++ 6 files changed, 12 insertions(+) diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 96336e8ca73..9f948be3328 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -69,6 +69,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_ETH_DESIGNWARE=y @@ -99,6 +100,7 @@ CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_SPL_TINY_MEMSET=y diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig index 6af874ca2ce..fb0b8719fb3 100644 --- a/configs/nanopi-r2c-rk3328_defconfig +++ b/configs/nanopi-r2c-rk3328_defconfig @@ -71,6 +71,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_ETH_DESIGNWARE=y @@ -104,6 +105,7 @@ CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_SPL_TINY_MEMSET=y diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index 7b0fadbce9e..79cb17d7513 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -71,6 +71,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_ETH_DESIGNWARE=y @@ -104,6 +105,7 @@ CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_SPL_TINY_MEMSET=y diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index 477179e80e7..f5912ceca93 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -72,6 +72,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PHY_REALTEK=y @@ -109,6 +110,7 @@ CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_SPL_TINY_MEMSET=y diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index c46c92841ab..0a8b17dab89 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -73,6 +73,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_ETH_DESIGNWARE=y @@ -100,6 +101,7 @@ CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set +CONFIG_USB_DWC3_GENERIC=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index ae761d08a1d..4acbca0140d 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -71,6 +71,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_SPI_FLASH_GIGADEVICE=y @@ -107,6 +108,7 @@ CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_SPL_TINY_MEMSET=y From 9aa93d84038bb47bcd4e9ac4287ef63e1b022971 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 6 Jun 2023 22:39:16 +0530 Subject: [PATCH 42/45] phy: rockchip-inno-usb2: Add USB2 PHY for RK3328 USB2.0 Host and OTG controllers in RK3328 are using USB2PHY. Add support for it. Signed-off-by: Jagan Teki Reviewed-by: Xavier Drudis Ferran Reviewed-by: Kever Yang --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 8d6f27735c2..70e61eccb79 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -345,6 +345,36 @@ bind_fail: return ret; } +static const struct rockchip_usb2phy_cfg rk3328_usb2phy_cfgs[] = { + { + .reg = 0x100, + .clkout_ctl = { 0x108, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 }, + .bvalid_det_en = { 0x0110, 3, 2, 0, 3 }, + .bvalid_det_st = { 0x0114, 3, 2, 0, 3 }, + .bvalid_det_clr = { 0x0118, 3, 2, 0, 3 }, + .ls_det_en = { 0x0110, 0, 0, 0, 1 }, + .ls_det_st = { 0x0114, 0, 0, 0, 1 }, + .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, + .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, + .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, + .utmi_ls = { 0x0120, 5, 4, 0, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x104, 15, 0, 0, 0x1d1 }, + .ls_det_en = { 0x110, 1, 1, 0, 1 }, + .ls_det_st = { 0x114, 1, 1, 0, 1 }, + .ls_det_clr = { 0x118, 1, 1, 0, 1 }, + .utmi_ls = { 0x120, 17, 16, 0, 1 }, + .utmi_hstdet = { 0x120, 19, 19, 0, 1 } + } + }, + }, + { /* sentinel */ } +}; + static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = { { .reg = 0xe450, @@ -498,6 +528,10 @@ static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = { }; static const struct udevice_id rockchip_usb2phy_ids[] = { + { + .compatible = "rockchip,rk3328-usb2phy", + .data = (ulong)&rk3328_usb2phy_cfgs, + }, { .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_usb2phy_cfgs, From c0165258582078c206faca352b0f63ccdf535ce7 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 6 Jun 2023 22:39:17 +0530 Subject: [PATCH 43/45] clk: rockchip: rk3328: Handle usb480m phy clock Handle USB480M clock ID in set_rate() and set_parent() to allow the dt assigned-clocks and assigned-clock-parents work on rk3328.dtsi Cc: Lukasz Majewski Cc: Sean Anderson Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3328.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 969b7a8581e..ef97381f0ed 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -681,6 +681,7 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) case ACLK_GMAC: case PCLK_GMAC: case SCLK_USB3OTG_SUSPEND: + case USB480M: return 0; default: return -ENOENT; @@ -771,6 +772,7 @@ static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent) case SCLK_MAC2IO_EXT: return rk3328_gmac2io_ext_set_parent(clk, parent); case DCLK_LCDC: + case USB480M: case SCLK_PDM: case SCLK_RTC32K: case SCLK_UART0: From b6fd3c63f4c5ba8cad518fa34e6a3289a6976f2e Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 6 Jun 2023 22:39:18 +0530 Subject: [PATCH 44/45] configs: rockchip: Enable USB2PHY for RK3328 boards Enable USB2PHY for all RK3328 boards. => usb start starting USB... Bus usb@ff5c0000: USB EHCI 1.00 Bus usb@ff5d0000: USB OHCI 1.0 Bus usb@ff600000: generic_phy_get_bulk : no phys property Register 2000140 NbrPorts 2 Starting the controller USB XHCI 1.10 Bus usb@ff580000: USB DWC2 scanning bus usb@ff5c0000 for devices... 2 USB Device(s) found scanning bus usb@ff5d0000 for devices... 1 USB Device(s) found scanning bus usb@ff600000 for devices... 2 USB Device(s) found scanning bus usb@ff580000 for devices... 2 USB Device(s) found scanning usb for storage devices... 2 Storage Device(s) found => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) | u-boot EHCI Host Controller | +-2 Mass Storage (480 Mb/s, 500mA) TS-RDF5A Transcend 000000000009 1 Hub (12 Mb/s, 0mA) U-Boot Root Hub 1 Hub (5 Gb/s, 0mA) | U-Boot XHCI Host Controller | +-2 Mass Storage (5 Gb/s, 224mA) SanDisk Dual Drive 040130e3ee554b7078843f4eb331646 1 Hub (480 Mb/s, 0mA) | U-Boot Root Hub | +-2 Human Interface (12 Mb/s, 98mA) Logitech USB Receiver => dm tree -s Class Index Probed Driver Name ----------------------------------------------------------- syscon 1 [ + ] syscon |-- syscon@ff450000 phy 0 [ + ] rockchip_usb2phy | `-- usb2phy@100 clk 2 [ + ] rockchip_usb2phy_clo | |-- usb480m_phy phy 1 [ + ] rockchip_usb2phy_por | |-- otg-port phy 2 [ + ] rockchip_usb2phy_por | `-- host-port sysinfo 0 [ + ] sysinfo_smbios |-- smbios usb 3 [ + ] dwc2_usb |-- usb@ff580000 usb_hub 3 [ + ] usb_hub | `-- usb_hub usb_dev_ge 0 [ + ] usb_dev_generic_drv | `-- generic_bus_3_dev_2 usb 0 [ + ] ehci_generic |-- usb@ff5c0000 usb_hub 0 [ + ] usb_hub | `-- usb_hub usb_mass_s 0 [ + ] usb_mass_storage | `-- usb_mass_storage blk 2 [ + ] usb_storage_blk | |-- usb_mass_storage.lun0 partition 4 [ + ] blk_partition | | |-- usb_mass_storage.lun0:1 partition 5 [ + ] blk_partition | | `-- usb_mass_storage.lun0:2 bootdev 3 [ ] usb_bootdev | `-- usb_mass_storage.lun0.bootdev usb 1 [ + ] ohci_generic `-- usb@ff5d0000 usb_hub 1 [ + ] usb_hub `-- usb_hub Cc: Tianling Shen Cc: David Bauer Cc: Loic Devulder Cc: Chen-Yu Tsai Cc: Banglang Huang Cc: Matwey V. Kornilov Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- configs/evb-rk3328_defconfig | 1 + configs/nanopi-r2c-rk3328_defconfig | 1 + configs/nanopi-r2s-rk3328_defconfig | 1 + configs/roc-cc-rk3328_defconfig | 1 + configs/rock-pi-e-rk3328_defconfig | 1 + configs/rock64-rk3328_defconfig | 1 + 6 files changed, 6 insertions(+) diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 9f948be3328..b9c541a92a1 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -74,6 +74,7 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig index fb0b8719fb3..583179d7c54 100644 --- a/configs/nanopi-r2c-rk3328_defconfig +++ b/configs/nanopi-r2c-rk3328_defconfig @@ -76,6 +76,7 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index 79cb17d7513..f7ed71e4122 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -76,6 +76,7 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index f5912ceca93..4ac3c9403b0 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -79,6 +79,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index 0a8b17dab89..82098f2954c 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -78,6 +78,7 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 4acbca0140d..5e36612bb80 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -77,6 +77,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y From 1f54f71b182e3515f72870a75ce2ba769b00b1f3 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 30 Jul 2023 12:30:26 +0000 Subject: [PATCH 45/45] board: rockchip: Add Radxa E25 Carrier Board Radxa E25 is a network application carrier board for the Radxa CM3I SoM with a RK3568 SoC. It features dual 2.5G ethernet, mini PCIe, M.2 B Key, USB3, eMMC, SD, nano SIM card slot and a 26-pin GPIO header. Features tested on a Radxa E25 v1.4: - SD-card boot - eMMC boot - USB host - PCIe/Ethernet adapters is detected - SATA Device tree is imported from linux next-20230728. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Tested-by: FUKAUMI Naoki --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3568-radxa-cm3i.dtsi | 415 ++++++++++++++++++++++ arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 32 ++ arch/arm/dts/rk3568-radxa-e25.dts | 236 ++++++++++++ board/rockchip/evb_rk3568/MAINTAINERS | 8 + configs/radxa-e25-rk3568_defconfig | 94 +++++ doc/board/rockchip/rockchip.rst | 1 + 7 files changed, 787 insertions(+) create mode 100644 arch/arm/dts/rk3568-radxa-cm3i.dtsi create mode 100644 arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-radxa-e25.dts create mode 100644 configs/radxa-e25-rk3568_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index edf9608620c..e66c32e2689 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -181,6 +181,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3568-nanopi-r5c.dtb \ rk3568-nanopi-r5s.dtb \ rk3568-odroid-m1.dtb \ + rk3568-radxa-e25.dtb \ rk3568-rock-3a.dtb dtb-$(CONFIG_ROCKCHIP_RK3588) += \ diff --git a/arch/arm/dts/rk3568-radxa-cm3i.dtsi b/arch/arm/dts/rk3568-radxa-cm3i.dtsi new file mode 100644 index 00000000000..c50fbdd4868 --- /dev/null +++ b/arch/arm/dts/rk3568-radxa-cm3i.dtsi @@ -0,0 +1,415 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include +#include +#include +#include "rk3568.dtsi" + +/ { + compatible = "radxa,cm3i", "rockchip,rk3568"; + + aliases { + mmc0 = &sdhci; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led_user: led-0 { + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + color = ; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_user_en>; + }; + }; + + pcie30_avdd0v9: pcie30-avdd0v9-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v_input>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_input>; + }; + + /* labeled +5v_input in schematic */ + vcc5v_input: vcc5v-input-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v_input"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&display_subsystem { + status = "disabled"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v_input>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&pinctrl { + leds { + led_user_en: led_user_en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy0>; +}; diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi new file mode 100644 index 00000000000..572bdc5665b --- /dev/null +++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; +}; + +/* PCIe PHY driver in U-Boot does not support bifurcation */ +&pcie3x1 { + status = "disabled"; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&uart2 { + bootph-all; + clock-frequency = <24000000>; + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; +}; diff --git a/arch/arm/dts/rk3568-radxa-e25.dts b/arch/arm/dts/rk3568-radxa-e25.dts new file mode 100644 index 00000000000..72ad74c38a2 --- /dev/null +++ b/arch/arm/dts/rk3568-radxa-e25.dts @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include "rk3568-radxa-cm3i.dtsi" + +/ { + model = "Radxa E25 Carrier Board"; + compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568"; + + aliases { + mmc1 = &sdmmc0; + }; + + pwm-leds { + compatible = "pwm-leds-multicolor"; + + multi-led { + color = ; + max-brightness = <255>; + + led-red { + color = ; + pwms = <&pwm1 0 1000000 0>; + }; + + led-green { + color = ; + pwms = <&pwm2 0 1000000 0>; + }; + + led-blue { + color = ; + pwms = <&pwm12 0 1000000 0>; + }; + }; + }; + + vbus_typec: vbus-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vbus_typec_en>; + regulator-name = "vbus_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + /* actually fed by vcc5v0_sys, dependent + * on pi6c clock generator + */ + vcc3v3_minipcie: vcc3v3-minipcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&minipcie_enable_h>; + regulator-name = "vcc3v3_minipcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_pi6c_05>; + }; + + vcc3v3_ngff: vcc3v3-ngff-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&ngffpcie_enable_h>; + regulator-name = "vcc3v3_ngff"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x1_enable_h>; + regulator-name = "vcc3v3_pcie30x1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_enable_h>; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy1 { + phy-supply = <&vcc3v3_pcie30x1>; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pi6c_05>; + status = "okay"; +}; + +&pcie30phy { + data-lanes = <1 2>; + status = "okay"; +}; + +&pcie3x1 { + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x1m0_pins>; + reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_minipcie>; + status = "okay"; +}; + +&pcie3x2 { + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x2_reset_h>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pi6c_05>; + status = "okay"; +}; + +&pinctrl { + pcie { + pcie20_reset_h: pcie20-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x1_enable_h: pcie30x1-enable-h { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x2_reset_h: pcie30x2-reset-h { + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_enable_h: pcie-enable-h { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + minipcie_enable_h: minipcie-enable-h { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + ngffpcie_enable_h: ngffpcie-enable-h { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vbus_typec_en: vbus_typec_en { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm12 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm12m1_pins>; + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + /* Also used in pcie30x1_clkreqnm0 */ + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vbus_typec>; + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc3v3_minipcie>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc3v3_ngff>; + status = "okay"; +}; diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS index a8ed2508a16..82a92b89fa6 100644 --- a/board/rockchip/evb_rk3568/MAINTAINERS +++ b/board/rockchip/evb_rk3568/MAINTAINERS @@ -27,6 +27,14 @@ M: Jagan Teki S: Maintained F: configs/radxa-cm3-io-rk3566_defconfig +RADXA-E25 +M: Jonas Karlman +S: Maintained +F: configs/radxa-e25-rk3568_defconfig +F: arch/arm/dts/rk3568-radxa-cm3i.dtsi +F: arch/arm/dts/rk3568-radxa-e25.dts +F: arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi + ROCK-3A M: Akash Gajjar S: Maintained diff --git a/configs/radxa-e25-rk3568_defconfig b/configs/radxa-e25-rk3568_defconfig new file mode 100644 index 00000000000..a905100a794 --- /dev/null +++ b/configs/radxa-e25-rk3568_defconfig @@ -0,0 +1,94 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-radxa-e25" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-radxa-e25.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_RTL8169=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 39e9532dd4d..49a0c5797ad 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -101,6 +101,7 @@ List of mainline supported Rockchip boards: - Pine64 SOQuartz on Blade (soquartz-blade-rk3566_defconfig) - Pine64 SOQuartz on CM4-IO (soquartz-cm4-rk3566_defconfig) - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566_defconfig) + - Radxa E25 Carrier Board (radxa-e25-rk3568_defconfig) * rk3588 - Rockchip EVB (evb-rk3588)