From 69c6d268a29cf6d61e096d815abf5abf24136f45 Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Fri, 10 Jul 2009 18:37:15 +0000 Subject: [PATCH 001/208] Blackfin: use +(filesize) to make sure we are only doing what is necessary Signed-off-by: Robin Getz Signed-off-by: Mike Frysinger --- include/configs/bfin_adi_common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index 1ca2e514205..ceb130c813d 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -160,8 +160,8 @@ "nand write $(loadaddr) 0 0x40000" # else # define UBOOT_ENV_UPDATE \ - "protect off 0x20000000 0x2003FFFF;" \ - "erase 0x20000000 0x2003FFFF;" \ + "protect off 0x20000000 +$(filesize);" \ + "erase 0x20000000 +$(filesize);" \ "cp.b $(loadaddr) 0x20000000 $(filesize)" # endif # define NETWORK_ENV_SETTINGS \ From aa7b248a05323d4720969227603e39a22777ed95 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Thu, 18 Jun 2009 09:12:50 +0000 Subject: [PATCH 002/208] Blackfin: bf537-stamp: comment CF-Flash Card Support better Signed-off-by: Michael Hennerich Signed-off-by: Mike Frysinger --- include/configs/bf537-stamp.h | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index 98300db7b52..74b9ecd0b0a 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -178,9 +178,28 @@ /* * CF-CARD IDE-HDD Support */ -/* #define CONFIG_BFIN_TRUE_IDE */ /* Add CF flash card support */ -/* #define CONFIG_BFIN_CF_IDE */ /* Add CF flash card support */ -/* #define CONFIG_BFIN_HDD_IDE */ /* Add IDE Disk Drive (HDD) support */ + +/* + * Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card) + * Strange address mapping Blackfin A13 connects to CF_A0 + */ + +/* #define CONFIG_BFIN_TRUE_IDE */ + +/* + * Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card) + * This should be the preferred mode + */ + +/* #define CONFIG_BFIN_CF_IDE */ + +/* + * Add IDE Disk Drive (HDD) support + * See example interface here: + * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin + */ + +/* #define CONFIG_BFIN_HDD_IDE */ #if defined(CONFIG_BFIN_CF_IDE) || \ defined(CONFIG_BFIN_HDD_IDE) || \ @@ -218,7 +237,7 @@ #define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */ #define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */ #define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */ -#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */ +#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A13 */ #elif defined(CONFIG_BFIN_CF_IDE) #define CONFIG_SYS_ATA_BASE_ADDR 0x20211800 @@ -226,7 +245,7 @@ #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* data I/O */ #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* normal register accesses */ #define CONFIG_SYS_ATA_ALT_OFFSET 0x000E /* alternate registers */ -#define CONFIG_SYS_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */ +#define CONFIG_SYS_ATA_STRIDE 1 /* CF_A0=0, with /CE1 /CE2 odd/even byte selects */ #elif defined(CONFIG_BFIN_HDD_IDE) #define CONFIG_SYS_ATA_BASE_ADDR 0x20314000 From 574b70df03fba0ea635e2fe71fbd7b97d19b706a Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Tue, 11 Aug 2009 14:20:13 +0000 Subject: [PATCH 003/208] Blackfin: enable more network commands for ADI dev boards Add dns and ntp to default networking commands, and ask for more dhcp options to better configure the network environment. Signed-off-by: Robin Getz Signed-off-by: Mike Frysinger --- include/configs/bfin_adi_common.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index ceb130c813d..b615c79c846 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -12,6 +12,13 @@ # include # if ADI_CMDS_NETWORK # define CONFIG_CMD_DHCP +# define CONFIG_BOOTP_SUBNETMASK +# define CONFIG_BOOTP_GATEWAY +# define CONFIG_BOOTP_DNS +# define CONFIG_BOOTP_NTPSERVER +# define CONFIG_BOOTP_RANDOM_DELAY +# define CONFIG_KEEP_SERVERADDR +# define CONFIG_CMD_DNS # define CONFIG_CMD_PING # ifdef CONFIG_BFIN_MAC # define CONFIG_CMD_MII @@ -46,6 +53,9 @@ # endif # ifdef CONFIG_RTC_BFIN # define CONFIG_CMD_DATE +# if ADI_CMDS_NETWORK +# define CONFIG_CMD_SNTP +# endif # endif # ifdef CONFIG_SPI # define CONFIG_CMD_EEPROM From c4db335c2e0805e1ce4c33d278b77492c0812353 Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Mon, 17 Aug 2009 15:23:02 +0000 Subject: [PATCH 004/208] Blackfin: change global data register from P5 to P3 Since the Blackfin ABI favors higher scratch registers by default, use the last scratch register (P3) for global data rather than the first (P5). This allows the compiler's register allocator to use higher number scratch P registers, which in turn better matches the Blackfin instruction set, which reduces the size of U-Boot by more than 1024 bytes... Signed-off-by: Robin Getz Signed-off-by: Mike Frysinger --- README | 4 ++-- doc/README.standalone | 2 +- examples/standalone/stubs.c | 4 ++-- include/asm-blackfin/global_data.h | 2 +- lib_blackfin/config.mk | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/README b/README index 246ae2badca..c90f6ee2d9d 100644 --- a/README +++ b/README @@ -3912,10 +3912,10 @@ For PowerPC, the following registers have specific use: average for all boards 752 bytes for the whole U-Boot image, 624 text + 127 data). -On Blackfin, the normal C ABI (except for P5) is followed as documented here: +On Blackfin, the normal C ABI (except for P3) is followed as documented here: http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface - ==> U-Boot will use P5 to hold a pointer to the global data + ==> U-Boot will use P3 to hold a pointer to the global data On ARM, the following registers are used: diff --git a/doc/README.standalone b/doc/README.standalone index 81b949a0aaa..885c92fb3a2 100644 --- a/doc/README.standalone +++ b/doc/README.standalone @@ -21,7 +21,7 @@ Design Notes on Exporting U-Boot Functions to Standalone Applications: 2. The pointer to the jump table is passed to the application in a machine-dependent way. PowerPC, ARM, MIPS and Blackfin architectures use a dedicated register to hold the pointer to the 'global_data' - structure: r2 on PowerPC, r8 on ARM, k0 on MIPS, and P5 on Blackfin. + structure: r2 on PowerPC, r8 on ARM, k0 on MIPS, and P3 on Blackfin. The x86 architecture does not use such a register; instead, the pointer to the 'global_data' structure is passed as 'argv[-1]' pointer. diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c index a8cb9542821..339bbf9b56d 100644 --- a/examples/standalone/stubs.c +++ b/examples/standalone/stubs.c @@ -127,14 +127,14 @@ gd_t *global_data; : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r5"); #elif defined(CONFIG_BLACKFIN) /* - * P5 holds the pointer to the global_data, P0 is a call-clobbered + * P3 holds the pointer to the global_data, P0 is a call-clobbered * register */ #define EXPORT_FUNC(x) \ asm volatile ( \ " .globl _" #x "\n_" \ #x ":\n" \ -" P0 = [P5 + %0]\n" \ +" P0 = [P3 + %0]\n" \ " P0 = [P0 + %1]\n" \ " JUMP (P0)\n" \ : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "P0"); diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h index 5c9903bb150..3194b72a537 100644 --- a/include/asm-blackfin/global_data.h +++ b/include/asm-blackfin/global_data.h @@ -66,6 +66,6 @@ typedef struct global_data { #define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */ #define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ -#define DECLARE_GLOBAL_DATA_PTR register gd_t * volatile gd asm ("P5") +#define DECLARE_GLOBAL_DATA_PTR register gd_t * volatile gd asm ("P3") #endif diff --git a/lib_blackfin/config.mk b/lib_blackfin/config.mk index a7e3658c3ef..34b53e6903b 100644 --- a/lib_blackfin/config.mk +++ b/lib_blackfin/config.mk @@ -28,7 +28,7 @@ CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE))) CONFIG_ENV_OFFSET := $(strip $(subst ",,$(CONFIG_ENV_OFFSET))) CONFIG_ENV_SIZE := $(strip $(subst ",,$(CONFIG_ENV_SIZE))) -PLATFORM_RELFLAGS += -ffixed-P5 -fomit-frame-pointer -mno-fdpic +PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN LDFLAGS += --gc-sections From 4640c2b8699bcdd2346a2c633486f07f061a2939 Mon Sep 17 00:00:00 2001 From: Harald Krapfenbauer Date: Thu, 20 Aug 2009 19:20:41 -0400 Subject: [PATCH 005/208] Blackfin: cm-bf537u: new board port The CM-BF537U is similar to the CM-BF537E module, but enough to need its own board port. Signed-off-by: Harald Krapfenbauer Signed-off-by: Mike Frysinger --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 2 +- board/cm-bf537u/Makefile | 54 +++++++++++ board/cm-bf537u/cm-bf537u.c | 66 ++++++++++++++ board/cm-bf537u/config.mk | 34 +++++++ board/cm-bf537u/flash.c | 34 +++++++ board/cm-bf537u/gpio_cfi_flash.c | 60 +++++++++++++ board/cm-bf537u/gpio_cfi_flash.h | 10 +++ include/configs/cm-bf537u.h | 150 +++++++++++++++++++++++++++++++ 10 files changed, 411 insertions(+), 1 deletion(-) create mode 100644 board/cm-bf537u/Makefile create mode 100644 board/cm-bf537u/cm-bf537u.c create mode 100644 board/cm-bf537u/config.mk create mode 100644 board/cm-bf537u/flash.c create mode 100644 board/cm-bf537u/gpio_cfi_flash.c create mode 100644 board/cm-bf537u/gpio_cfi_flash.h create mode 100644 include/configs/cm-bf537u.h diff --git a/MAINTAINERS b/MAINTAINERS index f99eae596c1..d6747534c1f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -917,6 +917,7 @@ Blackfin Team CM-BF527 BF527 CM-BF533 BF533 CM-BF537E BF537 + CM-BF537U BF537 CM-BF548 BF548 CM-BF561 BF561 TCM-BF537 BF537 diff --git a/MAKEALL b/MAKEALL index c8a1f37d1d0..85f99ef6d82 100755 --- a/MAKEALL +++ b/MAKEALL @@ -838,6 +838,7 @@ LIST_blackfin=" \ cm-bf527 \ cm-bf533 \ cm-bf537e \ + cm-bf537u \ cm-bf548 \ cm-bf561 \ ibf-dsp561 \ diff --git a/Makefile b/Makefile index c9727f8dab6..dd01b664255 100644 --- a/Makefile +++ b/Makefile @@ -3525,7 +3525,7 @@ BFIN_BOARDS = bf518f-ezbrd bf526-ezbrd bf527-ezkit bf533-ezkit bf533-stamp \ bf537-pnav bf537-stamp bf538f-ezkit bf548-ezkit bf561-ezkit # Bluetechnix tinyboards -BFIN_BOARDS += cm-bf527 cm-bf533 cm-bf537e cm-bf548 cm-bf561 tcm-bf537 +BFIN_BOARDS += cm-bf527 cm-bf533 cm-bf537e cm-bf537u cm-bf548 cm-bf561 tcm-bf537 # Misc third party boards BFIN_BOARDS += bf537-minotaur bf537-srv1 blackstamp diff --git a/board/cm-bf537u/Makefile b/board/cm-bf537u/Makefile new file mode 100644 index 00000000000..3812ba1e721 --- /dev/null +++ b/board/cm-bf537u/Makefile @@ -0,0 +1,54 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o flash.o gpio_cfi_flash.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/cm-bf537u/cm-bf537u.c b/board/cm-bf537u/cm-bf537u.c new file mode 100644 index 00000000000..9628e0f949a --- /dev/null +++ b/board/cm-bf537u/cm-bf537u.c @@ -0,0 +1,66 @@ +/* + * U-boot - main board file + * + * Copyright (c) 2005-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "gpio_cfi_flash.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + printf("Board: Bluetechnix CM-BF537U board\n"); + printf(" Support: http://www.bluetechnix.at/\n"); + return 0; +} + +phys_size_t initdram(int board_type) +{ + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; + return gd->bd->bi_memsize; +} + +#ifdef CONFIG_BFIN_MAC +static void board_init_enetaddr(uchar *mac_addr) +{ + puts("Warning: Generating 'random' MAC address\n"); + bfin_gen_rand_mac(mac_addr); + eth_setenv_enetaddr("ethaddr", mac_addr); +} + +int board_eth_init(bd_t *bis) +{ + return bfin_EMAC_initialize(bis); +} +#endif + +#ifdef CONFIG_SMC911X +int board_eth_init(bd_t *bis) +{ + return smc911x_initialize(0, CONFIG_SMC911X_BASE); +} +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_BFIN_MAC + uchar enetaddr[6]; + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + board_init_enetaddr(enetaddr); +#endif + + gpio_cfi_flash_init(); + + return 0; +} diff --git a/board/cm-bf537u/config.mk b/board/cm-bf537u/config.mk new file mode 100644 index 00000000000..3c0b46f7214 --- /dev/null +++ b/board/cm-bf537u/config.mk @@ -0,0 +1,34 @@ +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 + +# Set some default LDR flags based on boot mode. +LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/cm-bf537u/flash.c b/board/cm-bf537u/flash.c new file mode 100644 index 00000000000..ebe17b65318 --- /dev/null +++ b/board/cm-bf537u/flash.c @@ -0,0 +1,34 @@ +/* + * flash.c - helper commands for working with GPIO-assisted flash + * + * Copyright (c) 2005-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include +#include +#include +#include "gpio_cfi_flash.h" + +int do_ph(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong faddr = CONFIG_SYS_FLASH_BASE; + ushort data; + ulong dflg; + + if (argc > 1) { + dflg = simple_strtoul(argv[1], NULL, 16); + faddr |= (dflg << 21); + gpio_cfi_flash_swizzle((void *)faddr); + } else { + data = bfin_read_PORTHIO(); + printf("Port H data %04x (PH0:%i)\n", data, !!(data & PH0)); + } + + return 0; +} + +U_BOOT_CMD(ph, 3, 0, do_ph, + "set/clear PH0 GPIO flash bank switch\n", + " - set PH0 GPIO pin state\n"); diff --git a/board/cm-bf537u/gpio_cfi_flash.c b/board/cm-bf537u/gpio_cfi_flash.c new file mode 100644 index 00000000000..68633ec78d9 --- /dev/null +++ b/board/cm-bf537u/gpio_cfi_flash.c @@ -0,0 +1,60 @@ +/* + * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support + * + * Copyright (c) 2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include +#include +#include +#include "gpio_cfi_flash.h" + +#define GPIO_PIN_1 PH0 +#define GPIO_MASK_1 (1 << 21) +#define GPIO_MASK (GPIO_MASK_1) + +void *gpio_cfi_flash_swizzle(void *vaddr) +{ + unsigned long addr = (unsigned long)vaddr; + + if (addr & GPIO_MASK_1) + bfin_write_PORTHIO_SET(GPIO_PIN_1); + else + bfin_write_PORTHIO_CLEAR(GPIO_PIN_1); + +#ifdef GPIO_MASK_2 + if (addr & GPIO_MASK_2) + bfin_write_PORTGIO_SET(GPIO_PIN_2); + else + bfin_write_PORTGIO_CLEAR(GPIO_PIN_2); +#endif + + SSYNC(); + + return (void *)(addr & ~GPIO_MASK); +} + +#define __raw_writeq(value, addr) *(volatile u64 *)addr = value +#define __raw_readq(addr) *(volatile u64 *)addr + +#define MAKE_FLASH(size, sfx) \ +void flash_write##size(u##size value, void *addr) \ +{ \ + __raw_write##sfx(value, gpio_cfi_flash_swizzle(addr)); \ +} \ +u##size flash_read##size(void *addr) \ +{ \ + return __raw_read##sfx(gpio_cfi_flash_swizzle(addr)); \ +} +MAKE_FLASH(8, b) /* flash_write8() flash_read8() */ +MAKE_FLASH(16, w) /* flash_write16() flash_read16() */ +MAKE_FLASH(32, l) /* flash_write32() flash_read32() */ +MAKE_FLASH(64, q) /* flash_write64() flash_read64() */ + +void gpio_cfi_flash_init(void) +{ + bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() | GPIO_PIN_1); + gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE); +} diff --git a/board/cm-bf537u/gpio_cfi_flash.h b/board/cm-bf537u/gpio_cfi_flash.h new file mode 100644 index 00000000000..5211e972ad2 --- /dev/null +++ b/board/cm-bf537u/gpio_cfi_flash.h @@ -0,0 +1,10 @@ +/* + * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support + * + * Copyright (c) 2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +void *gpio_cfi_flash_swizzle(void *vaddr); +void gpio_cfi_flash_init(void); diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h new file mode 100644 index 00000000000..d1870a8963f --- /dev/null +++ b/include/configs/cm-bf537u.h @@ -0,0 +1,150 @@ +/* + * U-boot - Configuration file for CM-BF537U board + */ + +#ifndef __CONFIG_CM_BF537U_H__ +#define __CONFIG_CM_BF537U_H__ + +#include + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf537-0.2 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 30000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 18 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 +/* Core voltage */ +#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000) + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 9 +#define CONFIG_MEM_SIZE 32 + +#define CONFIG_EBIU_SDRRC_VAL 0x3f8 +#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd + +#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) +#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) +#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + + +/* + * Network Settings + */ +#ifndef __ADSPBF534__ +#define ADI_CMDS_NETWORK 1 +#define CONFIG_NET_MULTI +/* The next 3 lines are for use with SMSC on EXT-BF5xx-USB-ETH2 */ +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_BASE 0x24000000 +#define CONFIG_SMC911X_16_BIT +#endif +#define CONFIG_HOSTNAME cm-bf537u +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ + + +/* + * Flash Settings + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 35 + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x4000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) +#define ENV_IS_EMBEDDED +#else +#define ENV_IS_EMBEDDED_CUSTOM +#endif +#ifdef ENV_IS_EMBEDDED +/* WARNING - the following is hand-optimized to fit within + * the sector before the environment sector. If it throws + * an error during compilation remove an object here to get + * it linked after the configuration sector. + */ +# define LDS_BOARD_TEXT \ + cpu/blackfin/traps.o (.text .text.*); \ + cpu/blackfin/interrupt.o (.text .text.*); \ + cpu/blackfin/serial.o (.text .text.*); \ + common/dlmalloc.o (.text .text.*); \ + lib_generic/crc32.o (.text .text.*); \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text .text.*); +#endif + + +/* + * I2C Settings + */ +#define CONFIG_BFIN_TWI_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 + + +/* + * Misc Settings + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_MISC_INIT_R +#define CONFIG_RTC_BFIN +#define CONFIG_UART_CONSOLE 0 + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include + +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "run flashboot" + +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + NAND_ENV_SETTINGS \ + NETWORK_ENV_SETTINGS \ + "flashboot=flread 20040000 1000000 280000; bootm 0x1000000\0" + +#endif From f541e1d6d99c22bbd4bc8c84fdb02baad0277847 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 24 Aug 2009 19:03:18 -0400 Subject: [PATCH 006/208] Blackfin: fix debug printf modifiers The display_global_data() function generated warnings with pretty much every variable. Signed-off-by: Mike Frysinger --- lib_blackfin/board.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c index b957a9d8b9a..5b9efde7a23 100644 --- a/lib_blackfin/board.c +++ b/lib_blackfin/board.c @@ -93,25 +93,25 @@ static void display_global_data(void) #ifdef CONFIG_DEBUG_EARLY_SERIAL bd_t *bd; bd = gd->bd; - printf(" gd: %x\n", gd); - printf(" |-flags: %x\n", gd->flags); - printf(" |-board_type: %x\n", gd->board_type); - printf(" |-baudrate: %i\n", gd->baudrate); - printf(" |-have_console: %x\n", gd->have_console); - printf(" |-ram_size: %x\n", gd->ram_size); - printf(" |-reloc_off: %x\n", gd->reloc_off); - printf(" |-env_addr: %x\n", gd->env_addr); - printf(" |-env_valid: %x\n", gd->env_valid); - printf(" |-jt(%x): %x\n", gd->jt, *(gd->jt)); - printf(" \\-bd: %x\n", gd->bd); + printf(" gd: %p\n", gd); + printf(" |-flags: %lx\n", gd->flags); + printf(" |-board_type: %lx\n", gd->board_type); + printf(" |-baudrate: %lu\n", gd->baudrate); + printf(" |-have_console: %lx\n", gd->have_console); + printf(" |-ram_size: %lx\n", gd->ram_size); + printf(" |-reloc_off: %lx\n", gd->reloc_off); + printf(" |-env_addr: %lx\n", gd->env_addr); + printf(" |-env_valid: %lx\n", gd->env_valid); + printf(" |-jt(%p): %p\n", gd->jt, *(gd->jt)); + printf(" \\-bd: %p\n", gd->bd); printf(" |-bi_baudrate: %x\n", bd->bi_baudrate); - printf(" |-bi_ip_addr: %x\n", bd->bi_ip_addr); - printf(" |-bi_boot_params: %x\n", bd->bi_boot_params); - printf(" |-bi_memstart: %x\n", bd->bi_memstart); - printf(" |-bi_memsize: %x\n", bd->bi_memsize); - printf(" |-bi_flashstart: %x\n", bd->bi_flashstart); - printf(" |-bi_flashsize: %x\n", bd->bi_flashsize); - printf(" \\-bi_flashoffset: %x\n", bd->bi_flashoffset); + printf(" |-bi_ip_addr: %lx\n", bd->bi_ip_addr); + printf(" |-bi_boot_params: %lx\n", bd->bi_boot_params); + printf(" |-bi_memstart: %lx\n", bd->bi_memstart); + printf(" |-bi_memsize: %lx\n", bd->bi_memsize); + printf(" |-bi_flashstart: %lx\n", bd->bi_flashstart); + printf(" |-bi_flashsize: %lx\n", bd->bi_flashsize); + printf(" \\-bi_flashoffset: %lx\n", bd->bi_flashoffset); #endif } From 69a25ce3578f34c8accb476f70089f3a44b78ed9 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 24 Aug 2009 20:36:25 -0400 Subject: [PATCH 007/208] Blackfin: increase default console size The default console size indirectly applies to length of env vars, so a smaller length makes it hard to pass longer command lines to kernels. Signed-off-by: Mike Frysinger --- include/asm-blackfin/config.h | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/include/asm-blackfin/config.h b/include/asm-blackfin/config.h index 6623fb7ae10..5739b1377c0 100644 --- a/include/asm-blackfin/config.h +++ b/include/asm-blackfin/config.h @@ -120,11 +120,7 @@ # define CONFIG_SYS_PROMPT "bfin> " #endif #ifndef CONFIG_SYS_CBSIZE -# ifdef CONFIG_CMD_KGDB -# define CONFIG_SYS_CBSIZE 1024 -# else -# define CONFIG_SYS_CBSIZE 256 -# endif +# define CONFIG_SYS_CBSIZE 1024 #endif #ifndef CONFIG_SYS_BARGSIZE # define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE From 9c46e71af2b03ccd721c56b1dc906ead702d6fb5 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 24 Aug 2009 20:48:04 -0400 Subject: [PATCH 008/208] Blackfin: use scratch pad for exception stack If the memory layout pushes the stack out of the default DCPLB coverage, the exception handler may trigger a double fault by trying to push onto the uncovered stack. So handle the exception stack similar to the kernel by using the top of the scratch pad SRAM. Signed-off-by: Mike Frysinger --- cpu/blackfin/interrupt.S | 5 +++++ include/asm-blackfin/config.h | 4 ++++ 2 files changed, 9 insertions(+) diff --git a/cpu/blackfin/interrupt.S b/cpu/blackfin/interrupt.S index dd2cc5320c0..71e0fc67088 100644 --- a/cpu/blackfin/interrupt.S +++ b/cpu/blackfin/interrupt.S @@ -5,6 +5,7 @@ * Licensed under the GPL-2 or later. */ +#include #include #include @@ -12,12 +13,16 @@ /* default entry point for exceptions */ ENTRY(_trap) + CONFIG_BFIN_SCRATCH_REG = sp; + sp.l = LO(L1_SRAM_SCRATCH_END - 20); + sp.h = HI(L1_SRAM_SCRATCH_END - 20); SAVE_ALL_SYS r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ sp += -12; call _trap_c; sp += 12; RESTORE_ALL_SYS + sp = CONFIG_BFIN_SCRATCH_REG; rtx; ENDPROC(_trap) diff --git a/include/asm-blackfin/config.h b/include/asm-blackfin/config.h index 5739b1377c0..25794dd4bf0 100644 --- a/include/asm-blackfin/config.h +++ b/include/asm-blackfin/config.h @@ -14,6 +14,10 @@ # error CONFIG_BFIN_CPU: your board config needs to define this #endif +#ifndef CONFIG_BFIN_SCRATCH_REG +# define CONFIG_BFIN_SCRATCH_REG retn +#endif + /* Make sure the structure is properly aligned */ #if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR) # error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned From c7bcdde46a7ef78628f0f09fdc6cb61bb1bd7e79 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 2 Sep 2009 04:21:16 -0400 Subject: [PATCH 009/208] Blackfin: enable 64bit printf for nand Since the NAND code now uses 64bit code, make sure we enable support for ADI Blackfin boards in printf to avoid the warning: nand_util.c:45:2: warning: #warning Please define CONFIG_SYS_64BIT_VSPRINTF for correct output! Signed-off-by: Mike Frysinger --- include/configs/bfin_adi_common.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index b615c79c846..00bfc6e90bc 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -87,6 +87,9 @@ # define CONFIG_CMD_SPIBOOTLDR # endif #endif +#ifdef CONFIG_CMD_NAND +# define CONFIG_SYS_64BIT_VSPRINTF +#endif /* * Console Settings From cb95c7a935ab9b52dac5d08e5ba4007c5a480f97 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 2 Sep 2009 05:52:37 -0400 Subject: [PATCH 010/208] Blackfin: cm-bf548: fix device->stdio_dev fallout The recent 52cb4d4fb348 commit which renamed device to stdio_dev missed the cm-bf548's video board. Signed-off-by: Mike Frysinger --- board/cm-bf548/video.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c index 49dbe77da5e..078734269d7 100644 --- a/board/cm-bf548/video.c +++ b/board/cm-bf548/video.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include int gunzip(void *, int, unsigned char *, unsigned long *); @@ -291,7 +291,7 @@ void video_puts(const char *s) int drv_video_init(void) { int error, devices = 1; - device_t videodev; + struct stdio_dev videodev; u8 *dst; u32 fbmem_size = @@ -331,7 +331,7 @@ int drv_video_init(void) videodev.putc = video_putc; /* 'putc' function */ videodev.puts = video_puts; /* 'puts' function */ - error = device_register(&videodev); + error = stdio_register(&videodev); return (error == 0) ? devices : error; } From 65f6f07b72a71b83d775c4d20d7ebcd6b2d2086d Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 23 Jul 2009 16:37:03 -0400 Subject: [PATCH 011/208] atmel_df_pow2: standalone to convert dataflashes to pow2 Atmel DataFlashes by default operate with pages that are slightly bigger than normal binary sizes (i.e. many are 1056 byte pages rather than 1024 bytes). However, they also have a "power of 2" mode where the pages show up with the normal binary size. The latter mode is required in order to boot with a Blackfin processor, so many people wish to convert their DataFlashes on their development systems to this mode. This standalone application does just that. Signed-off-by: Mike Frysinger --- examples/standalone/.gitignore | 1 + examples/standalone/Makefile | 4 + examples/standalone/atmel_df_pow2.c | 209 ++++++++++++++++++++++++++++ 3 files changed, 214 insertions(+) create mode 100644 examples/standalone/atmel_df_pow2.c diff --git a/examples/standalone/.gitignore b/examples/standalone/.gitignore index 0d1864cc28c..7b783fc2134 100644 --- a/examples/standalone/.gitignore +++ b/examples/standalone/.gitignore @@ -1,4 +1,5 @@ /82559_eeprom +/atmel_df_pow2 /hello_world /interrupt /mem_to_mem_idma2intr diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index d2e811a8b50..9a9b6c38eff 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -86,6 +86,10 @@ ELF = hello_world SREC = hello_world.srec BIN = hello_world.bin +ELF += atmel_df_pow2 +SREC += atmel_df_pow2.srec +BIN += atmel_df_pow2.bin + ifeq ($(CPU),mpc8xx) ELF += test_burst SREC += test_burst.srec diff --git a/examples/standalone/atmel_df_pow2.c b/examples/standalone/atmel_df_pow2.c new file mode 100644 index 00000000000..db0cd693a99 --- /dev/null +++ b/examples/standalone/atmel_df_pow2.c @@ -0,0 +1,209 @@ +/* + * atmel_df_pow2.c - convert Atmel Dataflashes to Power of 2 mode + * + * Copyright 2009 Analog Devices Inc. + * + * Licensed under the 2-clause BSD. + */ + +#include +#include + +#define CMD_ID 0x9f +#define CMD_STAT 0xd7 +#define CMD_CFG 0x3d + +static int flash_cmd(struct spi_slave *slave, uchar cmd, uchar *buf, int len) +{ + buf[0] = cmd; + return spi_xfer(slave, 8 * len, buf, buf, SPI_XFER_BEGIN | SPI_XFER_END); +} + +static int flash_status(struct spi_slave *slave) +{ + uchar buf[2]; + if (flash_cmd(slave, CMD_STAT, buf, sizeof(buf))) + return -1; + return buf[1]; +} + +static int flash_set_pow2(struct spi_slave *slave) +{ + int ret; + uchar buf[4]; + + buf[1] = 0x2a; + buf[2] = 0x80; + buf[3] = 0xa6; + + ret = flash_cmd(slave, CMD_CFG, buf, sizeof(buf)); + if (ret) + return ret; + + /* wait Tp, or 6 msec */ + udelay(6000); + + ret = flash_status(slave); + if (ret == -1) + return 1; + + return ret & 0x1 ? 0 : 1; +} + +static int flash_check(struct spi_slave *slave) +{ + int ret; + uchar buf[4]; + + ret = flash_cmd(slave, CMD_ID, buf, sizeof(buf)); + if (ret) + return ret; + + if (buf[1] != 0x1F) { + printf("atmel flash not found (id[0] = %#x)\n", buf[1]); + return 1; + } + + if ((buf[2] >> 5) != 0x1) { + printf("AT45 flash not found (id[0] = %#x)\n", buf[2]); + return 2; + } + + return 0; +} + +static char *getline(void) +{ + static char buffer[100]; + char c; + size_t i; + + i = 0; + while (1) { + buffer[i] = '\0'; + + c = getc(); + + switch (c) { + case '\r': /* Enter/Return key */ + case '\n': + puts("\n"); + return buffer; + + case 0x03: /* ^C - break */ + return NULL; + + case 0x5F: + case 0x08: /* ^H - backspace */ + case 0x7F: /* DEL - backspace */ + if (i) { + puts("\b \b"); + i--; + } + break; + + default: + /* Ignore control characters */ + if (c < 0x20) + break; + /* Queue up all other characters */ + buffer[i++] = c; + printf("%c", c); + break; + } + } +} + +int atmel_df_pow2(int argc, char *argv[]) +{ + /* Print the ABI version */ + app_startup(argv); + if (XF_VERSION != get_version()) { + printf("Expects ABI version %d\n", XF_VERSION); + printf("Actual U-Boot ABI version %lu\n", get_version()); + printf("Can't run\n\n"); + return 1; + } + + spi_init(); + + while (1) { + struct spi_slave *slave; + char *line, *p; + int bus, cs, status; + + puts("\nenter the [BUS:]CS of the SPI flash: "); + line = getline(); + + /* CTRL+C */ + if (!line) + return 0; + if (line[0] == '\0') + continue; + + bus = cs = simple_strtoul(line, &p, 10); + if (*p) { + if (*p == ':') { + ++p; + cs = simple_strtoul(p, &p, 10); + } + if (*p) { + puts("invalid format, please try again\n"); + continue; + } + } else + bus = 0; + + printf("\ngoing to work with dataflash at %i:%i\n", bus, cs); + + /* use a low speed -- it'll work with all devices, and + * speed here doesn't really matter. + */ + slave = spi_setup_slave(bus, cs, 1000, SPI_MODE_3); + if (!slave) { + puts("unable to setup slave\n"); + continue; + } + + if (spi_claim_bus(slave)) { + spi_free_slave(slave); + continue; + } + + if (flash_check(slave)) { + puts("no flash found\n"); + goto done; + } + + status = flash_status(slave); + if (status == -1) { + puts("unable to read status register\n"); + goto done; + } + if (status & 0x1) { + puts("flash is already in power-of-2 mode!\n"); + goto done; + } + + puts("are you sure you wish to set power-of-2 mode?\n"); + puts("this operation is permanent and irreversible\n"); + printf("enter YES to continue: "); + line = getline(); + if (!line || strcmp(line, "YES")) + goto done; + + if (flash_set_pow2(slave)) { + puts("setting pow2 mode failed\n"); + goto done; + } + + puts( + "Configuration should be updated now. You will have to\n" + "power cycle the part in order to finish the conversion.\n" + ); + + done: + spi_release_bus(slave); + spi_free_slave(slave); + } +} From 5e93bd1c9aaea886c5e5c7c1b6114ab36c30668f Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 21 Aug 2009 23:05:19 -0500 Subject: [PATCH 012/208] Consolidate arch-specific sbrk() implementations Signed-off-by: Peter Tyser --- common/dlmalloc.c | 18 +++++++++++++++++- include/malloc.h | 6 ++++++ lib_arm/board.c | 20 -------------------- lib_avr32/board.c | 19 ------------------- lib_blackfin/board.c | 20 +++----------------- lib_i386/board.c | 21 --------------------- lib_m68k/board.c | 20 -------------------- lib_microblaze/board.c | 19 ------------------- lib_mips/board.c | 19 ------------------- lib_nios/board.c | 20 +------------------- lib_nios2/board.c | 20 +------------------- lib_ppc/board.c | 19 ------------------- lib_sh/board.c | 18 ------------------ lib_sparc/board.c | 19 ------------------- 14 files changed, 28 insertions(+), 230 deletions(-) diff --git a/common/dlmalloc.c b/common/dlmalloc.c index 4a185620f98..f3bced463fd 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -1502,7 +1502,23 @@ void malloc_bin_reloc (void) *p++ += gd->reloc_off; } } - + +ulong mem_malloc_start = 0; +ulong mem_malloc_end = 0; +ulong mem_malloc_brk = 0; + +void *sbrk(ptrdiff_t increment) +{ + ulong old = mem_malloc_brk; + ulong new = old + increment; + + if ((new < mem_malloc_start) || (new > mem_malloc_end)) + return NULL; + + mem_malloc_brk = new; + + return (void *)old; +} /* field-extraction macros */ diff --git a/include/malloc.h b/include/malloc.h index a38464e6291..0382169b6a0 100644 --- a/include/malloc.h +++ b/include/malloc.h @@ -937,6 +937,12 @@ int mALLOPt(); struct mallinfo mALLINFo(); #endif +/* + * Begin and End of memory area for malloc(), and current "brk" + */ +extern ulong mem_malloc_start; +extern ulong mem_malloc_end; +extern ulong mem_malloc_brk; #ifdef __cplusplus }; /* end of extern "C" */ diff --git a/lib_arm/board.c b/lib_arm/board.c index fa87d513731..62b78744372 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -82,13 +82,6 @@ extern void rtl8019_get_enetaddr (uchar * addr); #include #endif -/* - * Begin and End of memory area for malloc(), and current "brk" - */ -static ulong mem_malloc_start = 0; -static ulong mem_malloc_end = 0; -static ulong mem_malloc_brk = 0; - static void mem_malloc_init (ulong dest_addr) { @@ -100,19 +93,6 @@ void mem_malloc_init (ulong dest_addr) mem_malloc_end - mem_malloc_start); } -void *sbrk (ptrdiff_t increment) -{ - ulong old = mem_malloc_brk; - ulong new = old + increment; - - if ((new < mem_malloc_start) || (new > mem_malloc_end)) { - return (NULL); - } - mem_malloc_brk = new; - - return ((void *) old); -} - /************************************************************************ * Coloured LED functionality diff --git a/lib_avr32/board.c b/lib_avr32/board.c index e2b0a2e1a2e..03a520cddc3 100644 --- a/lib_avr32/board.c +++ b/lib_avr32/board.c @@ -41,13 +41,6 @@ const char version_string[] = unsigned long monitor_flash_len; -/* - * Begin and end of memory area for malloc(), and current "brk" - */ -static unsigned long mem_malloc_start = 0; -static unsigned long mem_malloc_end = 0; -static unsigned long mem_malloc_brk = 0; - /* Weak aliases for optional board functions */ static int __do_nothing(void) { @@ -73,18 +66,6 @@ static void mem_malloc_init(void) mem_malloc_end - mem_malloc_start); } -void *sbrk(ptrdiff_t increment) -{ - unsigned long old = mem_malloc_brk; - unsigned long new = old + increment; - - if ((new < mem_malloc_start) || (new > mem_malloc_end)) - return NULL; - - mem_malloc_brk = new; - return ((void *)old); -} - #ifdef CONFIG_SYS_DMA_ALLOC_LEN #include #include diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c index 5b9efde7a23..9c405ba4bd6 100644 --- a/lib_blackfin/board.c +++ b/lib_blackfin/board.c @@ -44,27 +44,13 @@ static inline void serial_early_puts(const char *s) #endif } -static void *mem_malloc_start, *mem_malloc_end, *mem_malloc_brk; - static void mem_malloc_init(void) { - mem_malloc_start = (void *)CONFIG_SYS_MALLOC_BASE; - mem_malloc_end = (void *)(CONFIG_SYS_MALLOC_BASE + CONFIG_SYS_MALLOC_LEN); + mem_malloc_start = (ulong)CONFIG_SYS_MALLOC_BASE; + mem_malloc_end = (ulong)(CONFIG_SYS_MALLOC_BASE + CONFIG_SYS_MALLOC_LEN); mem_malloc_brk = mem_malloc_start; - memset(mem_malloc_start, 0, mem_malloc_end - mem_malloc_start); -} -void *sbrk(ptrdiff_t increment) -{ - void *old = mem_malloc_brk; - void *new = old + increment; - - if (new < mem_malloc_start || new > mem_malloc_end) - return NULL; - - mem_malloc_brk = new; - - return old; + memset((void*)mem_malloc_start, 0, mem_malloc_end - mem_malloc_start); } static int display_banner(void) diff --git a/lib_i386/board.c b/lib_i386/board.c index 54ef6e75a83..0262b5e2cb8 100644 --- a/lib_i386/board.c +++ b/lib_i386/board.c @@ -73,14 +73,6 @@ ulong i386boot_bios_size = (ulong)&_i386boot_bios_size; /* size of BIOS const char version_string[] = U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")"; - -/* - * Begin and End of memory area for malloc(), and current "brk" - */ -static ulong mem_malloc_start = 0; -static ulong mem_malloc_end = 0; -static ulong mem_malloc_brk = 0; - static int mem_malloc_init(void) { /* start malloc area right after the stack */ @@ -96,19 +88,6 @@ static int mem_malloc_init(void) return 0; } -void *sbrk (ptrdiff_t increment) -{ - ulong old = mem_malloc_brk; - ulong new = old + increment; - - if ((new < mem_malloc_start) || (new > mem_malloc_end)) { - return (NULL); - } - mem_malloc_brk = new; - - return ((void *) old); -} - /************************************************************************ * Init Utilities * ************************************************************************ diff --git a/lib_m68k/board.c b/lib_m68k/board.c index 483c9b6df89..4392bccdbae 100644 --- a/lib_m68k/board.c +++ b/lib_m68k/board.c @@ -101,13 +101,6 @@ extern int watchdog_disable(void); ulong monitor_flash_len; -/* - * Begin and End of memory area for malloc(), and current "brk" - */ -static ulong mem_malloc_start = 0; -static ulong mem_malloc_end = 0; -static ulong mem_malloc_brk = 0; - /************************************************************************ * Utilities * ************************************************************************ @@ -129,19 +122,6 @@ static void mem_malloc_init (void) mem_malloc_end - mem_malloc_start); } -void *sbrk (ptrdiff_t increment) -{ - ulong old = mem_malloc_brk; - ulong new = old + increment; - - if ((new < mem_malloc_start) || - (new > mem_malloc_end) ) { - return (NULL); - } - mem_malloc_brk = new; - return ((void *)old); -} - /* * All attempts to come up with a "common" initialization sequence * that works for all boards and architectures failed: some of the diff --git a/lib_microblaze/board.c b/lib_microblaze/board.c index cfed5fefcd7..fc25a753052 100644 --- a/lib_microblaze/board.c +++ b/lib_microblaze/board.c @@ -46,13 +46,6 @@ extern int eth_init (bd_t * bis); extern int getenv_IPaddr (char *); #endif -/* - * Begin and End of memory area for malloc(), and current "brk" - */ -static ulong mem_malloc_start; -static ulong mem_malloc_end; -static ulong mem_malloc_brk; - /* * The Malloc area is immediately below the monitor copy in DRAM * aka CONFIG_SYS_MONITOR_BASE - Note there is no need for reloc_off @@ -66,18 +59,6 @@ static void mem_malloc_init (void) memset ((void *)mem_malloc_start, 0, mem_malloc_end - mem_malloc_start); } -void *sbrk (ptrdiff_t increment) -{ - ulong old = mem_malloc_brk; - ulong new = old + increment; - - if ((new < mem_malloc_start) || (new > mem_malloc_end)) { - return (NULL); - } - mem_malloc_brk = new; - return ((void *)old); -} - /* * All attempts to come up with a "common" initialization sequence * that works for all boards and architectures failed: some of the diff --git a/lib_mips/board.c b/lib_mips/board.c index aa5b1295ce2..68a3697f740 100644 --- a/lib_mips/board.c +++ b/lib_mips/board.c @@ -59,13 +59,6 @@ const char version_string[] = static char *failed = "*** failed ***\n"; -/* - * Begin and End of memory area for malloc(), and current "brk" - */ -static ulong mem_malloc_start; -static ulong mem_malloc_end; -static ulong mem_malloc_brk; - /* * mips_io_port_base is the begin of the address space to which x86 style * I/O ports are mapped. @@ -97,18 +90,6 @@ static void mem_malloc_init (void) mem_malloc_end - mem_malloc_start); } -void *sbrk (ptrdiff_t increment) -{ - ulong old = mem_malloc_brk; - ulong new = old + increment; - - if ((new < mem_malloc_start) || (new > mem_malloc_end)) { - return (NULL); - } - mem_malloc_brk = new; - return ((void *) old); -} - static int init_func_ram (void) { diff --git a/lib_nios/board.c b/lib_nios/board.c index cd234578b74..30cdb477cf0 100644 --- a/lib_nios/board.c +++ b/lib_nios/board.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #ifdef CONFIG_STATUS_LED #include @@ -51,13 +52,6 @@ DECLARE_GLOBAL_DATA_PTR; extern void malloc_bin_reloc (void); typedef int (init_fnc_t) (void); -/* - * Begin and End of memory area for malloc(), and current "brk" - */ -static ulong mem_malloc_start = 0; -static ulong mem_malloc_end = 0; -static ulong mem_malloc_brk = 0; - /* * The Malloc area is immediately below the monitor copy in RAM */ @@ -71,18 +65,6 @@ static void mem_malloc_init (void) mem_malloc_end - mem_malloc_start); } -void *sbrk (ptrdiff_t increment) -{ - ulong old = mem_malloc_brk; - ulong new = old + increment; - - if ((new < mem_malloc_start) || (new > mem_malloc_end)) { - return (NULL); - } - mem_malloc_brk = new; - return ((void *) old); -} - /************************************************************************ * Initialization sequence * diff --git a/lib_nios2/board.c b/lib_nios2/board.c index b142c596137..e5a8d54069e 100644 --- a/lib_nios2/board.c +++ b/lib_nios2/board.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #ifdef CONFIG_STATUS_LED #include @@ -54,13 +55,6 @@ DECLARE_GLOBAL_DATA_PTR; extern void malloc_bin_reloc (void); typedef int (init_fnc_t) (void); -/* - * Begin and End of memory area for malloc(), and current "brk" - */ -static ulong mem_malloc_start = 0; -static ulong mem_malloc_end = 0; -static ulong mem_malloc_brk = 0; - /* * The Malloc area is immediately below the monitor copy in RAM */ @@ -74,18 +68,6 @@ static void mem_malloc_init (void) mem_malloc_end - mem_malloc_start); } -void *sbrk (ptrdiff_t increment) -{ - ulong old = mem_malloc_brk; - ulong new = old + increment; - - if ((new < mem_malloc_start) || (new > mem_malloc_end)) { - return (NULL); - } - mem_malloc_brk = new; - return ((void *) old); -} - /************************************************************************ * Initialization sequence * diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 9faf7f2a0b4..f0cc3ce8d85 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -136,13 +136,6 @@ ulong monitor_flash_len; #include #endif -/* - * Begin and End of memory area for malloc(), and current "brk" - */ -static ulong mem_malloc_start = 0; -static ulong mem_malloc_end = 0; -static ulong mem_malloc_brk = 0; - /************************************************************************ * Utilities * ************************************************************************ @@ -164,18 +157,6 @@ static void mem_malloc_init (void) mem_malloc_end - mem_malloc_start); } -void *sbrk (ptrdiff_t increment) -{ - ulong old = mem_malloc_brk; - ulong new = old + increment; - - if ((new < mem_malloc_start) || (new > mem_malloc_end)) { - return (NULL); - } - mem_malloc_brk = new; - return ((void *) old); -} - /* * All attempts to come up with a "common" initialization sequence * that works for all boards and architectures failed: some of the diff --git a/lib_sh/board.c b/lib_sh/board.c index 829455d8b12..001e89c7143 100644 --- a/lib_sh/board.c +++ b/lib_sh/board.c @@ -38,10 +38,6 @@ const char version_string[] = U_BOOT_VERSION" ("U_BOOT_DATE" - "U_BOOT_TIME")"; unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; -static unsigned long mem_malloc_start; -static unsigned long mem_malloc_end; -static unsigned long mem_malloc_brk; - static void mem_malloc_init(void) { @@ -52,20 +48,6 @@ static void mem_malloc_init(void) (mem_malloc_end - mem_malloc_start)); } -void *sbrk(ptrdiff_t increment) -{ - unsigned long old = mem_malloc_brk; - unsigned long new = old + increment; - - if ((new < mem_malloc_start) || - (new > mem_malloc_end)) { - return NULL; - } - - mem_malloc_brk = new; - return (void *) old; -} - static int sh_flash_init(void) { DECLARE_GLOBAL_DATA_PTR; diff --git a/lib_sparc/board.c b/lib_sparc/board.c index d40834b7b02..37b7c0a5946 100644 --- a/lib_sparc/board.c +++ b/lib_sparc/board.c @@ -74,13 +74,6 @@ static char *failed = "*** failed ***\n"; ulong monitor_flash_len; -/* - * Begin and End of memory area for malloc(), and current "brk" - */ -static ulong mem_malloc_start = 0; -static ulong mem_malloc_end = 0; -static ulong mem_malloc_brk = 0; - /************************************************************************ * Utilities * ************************************************************************ @@ -97,18 +90,6 @@ static void mem_malloc_init(void) memset((void *)mem_malloc_start, 0, mem_malloc_end - mem_malloc_start); } -void *sbrk(ptrdiff_t increment) -{ - ulong old = mem_malloc_brk; - ulong new = old + increment; - - if ((new < mem_malloc_start) || (new > mem_malloc_end)) { - return (NULL); - } - mem_malloc_brk = new; - return ((void *)old); -} - /***********************************************************************/ /************************************************************************ From a483a167bc8d808145ca1224a2c238cda90aa60c Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 21 Aug 2009 23:05:20 -0500 Subject: [PATCH 013/208] Standardize mem_malloc_init() implementation This lays the groundwork to allow architectures to share a common mem_malloc_init(). Note that the x86 implementation was not modified as it did not fit the mold of all other architectures. Signed-off-by: Peter Tyser --- lib_arm/board.c | 14 +++++++------- lib_avr32/board.c | 17 +++++++---------- lib_blackfin/board.c | 12 ++++++------ lib_m68k/board.c | 17 +++++++---------- lib_microblaze/board.c | 13 +++++++------ lib_mips/board.c | 17 +++++++---------- lib_nios/board.c | 15 +++++++-------- lib_nios2/board.c | 13 ++++++------- lib_ppc/board.c | 21 ++++++++++----------- lib_sh/board.c | 14 +++++++------- lib_sparc/board.c | 14 ++++++++------ 11 files changed, 79 insertions(+), 88 deletions(-) diff --git a/lib_arm/board.c b/lib_arm/board.c index 62b78744372..904ea89c2d2 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -83,14 +83,13 @@ extern void rtl8019_get_enetaddr (uchar * addr); #endif static -void mem_malloc_init (ulong dest_addr) +void mem_malloc_init (ulong start, ulong size) { - mem_malloc_start = dest_addr; - mem_malloc_end = dest_addr + CONFIG_SYS_MALLOC_LEN; - mem_malloc_brk = mem_malloc_start; + mem_malloc_start = start; + mem_malloc_end = start + size; + mem_malloc_brk = start; - memset ((void *) mem_malloc_start, 0, - mem_malloc_end - mem_malloc_start); + memset ((void *)mem_malloc_start, 0, size); } @@ -300,7 +299,8 @@ void start_armboot (void) } /* armboot_start is defined in the board-specific linker script */ - mem_malloc_init (_armboot_start - CONFIG_SYS_MALLOC_LEN); + mem_malloc_init (_armboot_start - CONFIG_SYS_MALLOC_LEN, + CONFIG_SYS_MALLOC_LEN); #ifndef CONFIG_SYS_NO_FLASH /* configure available FLASH banks */ diff --git a/lib_avr32/board.c b/lib_avr32/board.c index 03a520cddc3..ca1bd6fd329 100644 --- a/lib_avr32/board.c +++ b/lib_avr32/board.c @@ -50,20 +50,16 @@ int board_postclk_init(void) __attribute__((weak, alias("__do_nothing"))); int board_early_init_r(void) __attribute__((weak, alias("__do_nothing"))); /* The malloc area is right below the monitor image in RAM */ -static void mem_malloc_init(void) +static void mem_malloc_init(ulong start, ulong size) { - unsigned long monitor_addr; - - monitor_addr = CONFIG_SYS_MONITOR_BASE + gd->reloc_off; - mem_malloc_end = monitor_addr; - mem_malloc_start = mem_malloc_end - CONFIG_SYS_MALLOC_LEN; - mem_malloc_brk = mem_malloc_start; + mem_malloc_start = start; + mem_malloc_end = start + size; + mem_malloc_brk = start; printf("malloc: Using memory from 0x%08lx to 0x%08lx\n", mem_malloc_start, mem_malloc_end); - memset ((void *)mem_malloc_start, 0, - mem_malloc_end - mem_malloc_start); + memset((void *)mem_malloc_start, 0, size); } #ifdef CONFIG_SYS_DMA_ALLOC_LEN @@ -312,7 +308,8 @@ void board_init_r(gd_t *new_gd, ulong dest_addr) #endif timer_init(); - mem_malloc_init(); + mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off - + CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN); malloc_bin_reloc(); dma_alloc_init(); diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c index 9c405ba4bd6..17681f6f8ea 100644 --- a/lib_blackfin/board.c +++ b/lib_blackfin/board.c @@ -44,13 +44,13 @@ static inline void serial_early_puts(const char *s) #endif } -static void mem_malloc_init(void) +static void mem_malloc_init(ulong start, ulong size) { - mem_malloc_start = (ulong)CONFIG_SYS_MALLOC_BASE; - mem_malloc_end = (ulong)(CONFIG_SYS_MALLOC_BASE + CONFIG_SYS_MALLOC_LEN); - mem_malloc_brk = mem_malloc_start; + mem_malloc_start = start; + mem_malloc_end = start + size; + mem_malloc_brk = start; - memset((void*)mem_malloc_start, 0, mem_malloc_end - mem_malloc_start); + memset((void*)mem_malloc_start, 0, size); } static int display_banner(void) @@ -311,7 +311,7 @@ void board_init_r(gd_t * id, ulong dest_addr) #endif /* initialize malloc() area */ - mem_malloc_init(); + mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN); malloc_bin_reloc(); #if !defined(CONFIG_SYS_NO_FLASH) diff --git a/lib_m68k/board.c b/lib_m68k/board.c index 4392bccdbae..cbc6b50258a 100644 --- a/lib_m68k/board.c +++ b/lib_m68k/board.c @@ -109,17 +109,13 @@ ulong monitor_flash_len; /* * The Malloc area is immediately below the monitor copy in DRAM */ -static void mem_malloc_init (void) +static void mem_malloc_init(ulong start, ulong size) { - ulong dest_addr = CONFIG_SYS_MONITOR_BASE + gd->reloc_off; + mem_malloc_start = start; + mem_malloc_end = start + size; + mem_malloc_brk = start; - mem_malloc_end = dest_addr; - mem_malloc_start = dest_addr - TOTAL_MALLOC_LEN; - mem_malloc_brk = mem_malloc_start; - - memset ((void *) mem_malloc_start, - 0, - mem_malloc_end - mem_malloc_start); + memset ((void *)mem_malloc_start, 0, size); } /* @@ -499,7 +495,8 @@ void board_init_r (gd_t *id, ulong dest_addr) trap_init (CONFIG_SYS_SDRAM_BASE); /* initialize malloc() area */ - mem_malloc_init (); + mem_malloc_init (CONFIG_SYS_MONITOR_BASE + gd->reloc_off - + TOTAL_MALLOC_LEN, TOTAL_MALLOC_LEN); malloc_bin_reloc (); #if !defined(CONFIG_SYS_NO_FLASH) diff --git a/lib_microblaze/board.c b/lib_microblaze/board.c index fc25a753052..a5d924a1f33 100644 --- a/lib_microblaze/board.c +++ b/lib_microblaze/board.c @@ -51,12 +51,13 @@ extern int getenv_IPaddr (char *); * aka CONFIG_SYS_MONITOR_BASE - Note there is no need for reloc_off * as our monitory code is run from SDRAM */ -static void mem_malloc_init (void) +static void mem_malloc_init(ulong start, ulong size) { - mem_malloc_end = (CONFIG_SYS_MALLOC_BASE + CONFIG_SYS_MALLOC_LEN); - mem_malloc_start = CONFIG_SYS_MALLOC_BASE; - mem_malloc_brk = mem_malloc_start; - memset ((void *)mem_malloc_start, 0, mem_malloc_end - mem_malloc_start); + mem_malloc_start = start; + mem_malloc_end = start + size; + mem_malloc_brk = start; + + memset ((void *)mem_malloc_start, 0, size); } /* @@ -104,7 +105,7 @@ void board_init (void) gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ /* Initialise malloc() area */ - mem_malloc_init (); + mem_malloc_init (CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN); for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { WATCHDOG_RESET (); diff --git a/lib_mips/board.c b/lib_mips/board.c index 68a3697f740..b233a6c8a95 100644 --- a/lib_mips/board.c +++ b/lib_mips/board.c @@ -77,17 +77,13 @@ int board_early_init_f(void) __attribute__((weak, alias("__board_early_init_f")) /* * The Malloc area is immediately below the monitor copy in DRAM */ -static void mem_malloc_init (void) +static void mem_malloc_init(ulong start, ulong size) { - ulong dest_addr = CONFIG_SYS_MONITOR_BASE + gd->reloc_off; + mem_malloc_start = start; + mem_malloc_end = start + size; + mem_malloc_brk = start; - mem_malloc_end = dest_addr; - mem_malloc_start = dest_addr - TOTAL_MALLOC_LEN; - mem_malloc_brk = mem_malloc_start; - - memset ((void *) mem_malloc_start, - 0, - mem_malloc_end - mem_malloc_start); + memset ((void *)mem_malloc_start, 0, size); } @@ -352,7 +348,8 @@ void board_init_r (gd_t *id, ulong dest_addr) bd = gd->bd; /* initialize malloc() area */ - mem_malloc_init(); + mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off - + TOTAL_MALLOC_LEN, TOTAL_MALLOC_LEN); malloc_bin_reloc(); #ifndef CONFIG_SYS_NO_FLASH diff --git a/lib_nios/board.c b/lib_nios/board.c index 30cdb477cf0..745e0a4d983 100644 --- a/lib_nios/board.c +++ b/lib_nios/board.c @@ -55,14 +55,13 @@ typedef int (init_fnc_t) (void); /* * The Malloc area is immediately below the monitor copy in RAM */ -static void mem_malloc_init (void) +static void mem_malloc_init(ulong start, ulong size) { - mem_malloc_start = CONFIG_SYS_MALLOC_BASE; - mem_malloc_end = mem_malloc_start + CONFIG_SYS_MALLOC_LEN; - mem_malloc_brk = mem_malloc_start; - memset ((void *) mem_malloc_start, - 0, - mem_malloc_end - mem_malloc_start); + mem_malloc_start = start; + mem_malloc_end = start + size; + mem_malloc_brk = start; + + memset ((void *)mem_malloc_start, 0, size); } @@ -125,7 +124,7 @@ void board_init (void) } WATCHDOG_RESET (); - mem_malloc_init(); + mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN); malloc_bin_reloc(); WATCHDOG_RESET (); diff --git a/lib_nios2/board.c b/lib_nios2/board.c index e5a8d54069e..2c470dd9f41 100644 --- a/lib_nios2/board.c +++ b/lib_nios2/board.c @@ -60,12 +60,11 @@ typedef int (init_fnc_t) (void); */ static void mem_malloc_init (void) { - mem_malloc_start = CONFIG_SYS_MALLOC_BASE; - mem_malloc_end = mem_malloc_start + CONFIG_SYS_MALLOC_LEN; - mem_malloc_brk = mem_malloc_start; - memset ((void *) mem_malloc_start, - 0, - mem_malloc_end - mem_malloc_start); + mem_malloc_start = start; + mem_malloc_end = start + size; + mem_malloc_brk = start + + memset((void *)mem_malloc_start, 0, size); } @@ -131,7 +130,7 @@ void board_init (void) } WATCHDOG_RESET (); - mem_malloc_init(); + mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN); malloc_bin_reloc(); WATCHDOG_RESET (); diff --git a/lib_ppc/board.c b/lib_ppc/board.c index f0cc3ce8d85..6cf77300951 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -144,17 +144,13 @@ ulong monitor_flash_len; /* * The Malloc area is immediately below the monitor copy in DRAM */ -static void mem_malloc_init (void) +static void mem_malloc_init(ulong start, ulong size) { -#if !defined(CONFIG_RELOC_FIXUP_WORKS) - mem_malloc_end = CONFIG_SYS_MONITOR_BASE + gd->reloc_off; -#endif - mem_malloc_start = mem_malloc_end - TOTAL_MALLOC_LEN; - mem_malloc_brk = mem_malloc_start; + mem_malloc_start = start; + mem_malloc_end = start + size; + mem_malloc_brk = start; - memset ((void *) mem_malloc_start, - 0, - mem_malloc_end - mem_malloc_start); + memset ((void *)mem_malloc_start, 0, size); } /* @@ -650,6 +646,7 @@ void board_init_r (gd_t *id, ulong dest_addr) #ifndef CONFIG_ENV_IS_NOWHERE extern char * env_name_spec; #endif + ulong malloc_start; #ifndef CONFIG_SYS_NO_FLASH ulong flash_size; @@ -662,9 +659,11 @@ void board_init_r (gd_t *id, ulong dest_addr) #if defined(CONFIG_RELOC_FIXUP_WORKS) gd->reloc_off = 0; - mem_malloc_end = dest_addr; + malloc_start = dest_addr - TOTAL_MALLOC_LEN; #else gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE; + malloc_start = CONFIG_SYS_MONITOR_BASE + gd->reloc_off - + TOTAL_MALLOC_LEN; #endif #ifdef CONFIG_SERIAL_MULTI @@ -760,7 +759,7 @@ void board_init_r (gd_t *id, ulong dest_addr) asm ("sync ; isync"); /* initialize malloc() area */ - mem_malloc_init (); + mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN); malloc_bin_reloc (); #if !defined(CONFIG_SYS_NO_FLASH) diff --git a/lib_sh/board.c b/lib_sh/board.c index 001e89c7143..26913160463 100644 --- a/lib_sh/board.c +++ b/lib_sh/board.c @@ -38,14 +38,13 @@ const char version_string[] = U_BOOT_VERSION" ("U_BOOT_DATE" - "U_BOOT_TIME")"; unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; -static void mem_malloc_init(void) +static void mem_malloc_init(ulong start, ulong size) { + mem_malloc_start = start; + mem_malloc_end = start + size; + mem_malloc_brk = start; - mem_malloc_start = (TEXT_BASE - CONFIG_SYS_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN); - mem_malloc_end = (mem_malloc_start + CONFIG_SYS_MALLOC_LEN - 16); - mem_malloc_brk = mem_malloc_start; - memset((void *) mem_malloc_start, 0, - (mem_malloc_end - mem_malloc_start)); + memset((void *)mem_malloc_start, 0, size); } static int sh_flash_init(void) @@ -96,7 +95,8 @@ static int sh_pci_init(void) static int sh_mem_env_init(void) { - mem_malloc_init(); + mem_malloc_init(TEXT_BASE - CONFIG_SYS_GBL_DATA_SIZE - + CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN - 16); malloc_bin_reloc(); env_relocate(); jumptable_init(); diff --git a/lib_sparc/board.c b/lib_sparc/board.c index 37b7c0a5946..e69431f8b89 100644 --- a/lib_sparc/board.c +++ b/lib_sparc/board.c @@ -82,12 +82,13 @@ ulong monitor_flash_len; /* * The Malloc area is immediately below the monitor copy in RAM */ -static void mem_malloc_init(void) +static void mem_malloc_init(ulong start, ulong size) { - mem_malloc_start = CONFIG_SYS_MALLOC_BASE; - mem_malloc_end = CONFIG_SYS_MALLOC_END; - mem_malloc_brk = mem_malloc_start; - memset((void *)mem_malloc_start, 0, mem_malloc_end - mem_malloc_start); + mem_malloc_start = start; + mem_malloc_end = start + size; + mem_malloc_brk = start + + memset((void *)mem_malloc_start, 0, size); } /***********************************************************************/ @@ -313,7 +314,8 @@ void board_init_f(ulong bootflag) interrupt_init(); /* initialize malloc() area */ - mem_malloc_init(); + mem_malloc_init(CONFIG_SYS_MALLOC_BASE, + CONFIG_SYS_MALLOC_END - CONFIG_SYS_MALLOC_BASE); malloc_bin_reloc(); #if !defined(CONFIG_SYS_NO_FLASH) From d4e8ada0f6d51e0e3b80790fb9375ac8910f5352 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 21 Aug 2009 23:05:21 -0500 Subject: [PATCH 014/208] Consolidate arch-specific mem_malloc_init() implementations Signed-off-by: Peter Tyser --- common/dlmalloc.c | 15 +++++++++++++++ include/malloc.h | 2 ++ lib_arm/board.c | 10 ---------- lib_avr32/board.c | 15 ++------------- lib_blackfin/board.c | 9 --------- lib_m68k/board.c | 14 +------------- lib_microblaze/board.c | 20 +++++--------------- lib_mips/board.c | 14 +------------- lib_nios/board.c | 14 ++------------ lib_nios2/board.c | 14 ++------------ lib_ppc/board.c | 14 +------------- lib_sh/board.c | 9 --------- lib_sparc/board.c | 21 +-------------------- 13 files changed, 32 insertions(+), 139 deletions(-) diff --git a/common/dlmalloc.c b/common/dlmalloc.c index f3bced463fd..241db8cd3e0 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -1520,6 +1520,21 @@ void *sbrk(ptrdiff_t increment) return (void *)old; } +#ifndef CONFIG_X86 +/* + * x86 boards use a slightly different init sequence thus they implement + * their own version of mem_malloc_init() + */ +void mem_malloc_init(ulong start, ulong size) +{ + mem_malloc_start = start; + mem_malloc_end = start + size; + mem_malloc_brk = start; + + memset((void *)mem_malloc_start, 0, size); +} +#endif + /* field-extraction macros */ #define first(b) ((b)->fd) diff --git a/include/malloc.h b/include/malloc.h index 0382169b6a0..3e145ad11c3 100644 --- a/include/malloc.h +++ b/include/malloc.h @@ -944,6 +944,8 @@ extern ulong mem_malloc_start; extern ulong mem_malloc_end; extern ulong mem_malloc_brk; +void mem_malloc_init(ulong start, ulong size); + #ifdef __cplusplus }; /* end of extern "C" */ #endif diff --git a/lib_arm/board.c b/lib_arm/board.c index 904ea89c2d2..a0e56d5ae8f 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -82,16 +82,6 @@ extern void rtl8019_get_enetaddr (uchar * addr); #include #endif -static -void mem_malloc_init (ulong start, ulong size) -{ - mem_malloc_start = start; - mem_malloc_end = start + size; - mem_malloc_brk = start; - - memset ((void *)mem_malloc_start, 0, size); -} - /************************************************************************ * Coloured LED functionality diff --git a/lib_avr32/board.c b/lib_avr32/board.c index ca1bd6fd329..29999d86359 100644 --- a/lib_avr32/board.c +++ b/lib_avr32/board.c @@ -49,19 +49,6 @@ static int __do_nothing(void) int board_postclk_init(void) __attribute__((weak, alias("__do_nothing"))); int board_early_init_r(void) __attribute__((weak, alias("__do_nothing"))); -/* The malloc area is right below the monitor image in RAM */ -static void mem_malloc_init(ulong start, ulong size) -{ - mem_malloc_start = start; - mem_malloc_end = start + size; - mem_malloc_brk = start; - - printf("malloc: Using memory from 0x%08lx to 0x%08lx\n", - mem_malloc_start, mem_malloc_end); - - memset((void *)mem_malloc_start, 0, size); -} - #ifdef CONFIG_SYS_DMA_ALLOC_LEN #include #include @@ -308,6 +295,8 @@ void board_init_r(gd_t *new_gd, ulong dest_addr) #endif timer_init(); + + /* The malloc area is right below the monitor image in RAM */ mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off - CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN); malloc_bin_reloc(); diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c index 17681f6f8ea..1053f694cb4 100644 --- a/lib_blackfin/board.c +++ b/lib_blackfin/board.c @@ -44,15 +44,6 @@ static inline void serial_early_puts(const char *s) #endif } -static void mem_malloc_init(ulong start, ulong size) -{ - mem_malloc_start = start; - mem_malloc_end = start + size; - mem_malloc_brk = start; - - memset((void*)mem_malloc_start, 0, size); -} - static int display_banner(void) { printf("\n\n%s\n\n", version_string); diff --git a/lib_m68k/board.c b/lib_m68k/board.c index cbc6b50258a..3d885306e21 100644 --- a/lib_m68k/board.c +++ b/lib_m68k/board.c @@ -106,18 +106,6 @@ ulong monitor_flash_len; ************************************************************************ */ -/* - * The Malloc area is immediately below the monitor copy in DRAM - */ -static void mem_malloc_init(ulong start, ulong size) -{ - mem_malloc_start = start; - mem_malloc_end = start + size; - mem_malloc_brk = start; - - memset ((void *)mem_malloc_start, 0, size); -} - /* * All attempts to come up with a "common" initialization sequence * that works for all boards and architectures failed: some of the @@ -494,7 +482,7 @@ void board_init_r (gd_t *id, ulong dest_addr) */ trap_init (CONFIG_SYS_SDRAM_BASE); - /* initialize malloc() area */ + /* The Malloc area is immediately below the monitor copy in DRAM */ mem_malloc_init (CONFIG_SYS_MONITOR_BASE + gd->reloc_off - TOTAL_MALLOC_LEN, TOTAL_MALLOC_LEN); malloc_bin_reloc (); diff --git a/lib_microblaze/board.c b/lib_microblaze/board.c index a5d924a1f33..200ea5dd701 100644 --- a/lib_microblaze/board.c +++ b/lib_microblaze/board.c @@ -46,20 +46,6 @@ extern int eth_init (bd_t * bis); extern int getenv_IPaddr (char *); #endif -/* - * The Malloc area is immediately below the monitor copy in DRAM - * aka CONFIG_SYS_MONITOR_BASE - Note there is no need for reloc_off - * as our monitory code is run from SDRAM - */ -static void mem_malloc_init(ulong start, ulong size) -{ - mem_malloc_start = start; - mem_malloc_end = start + size; - mem_malloc_brk = start; - - memset ((void *)mem_malloc_start, 0, size); -} - /* * All attempts to come up with a "common" initialization sequence * that works for all boards and architectures failed: some of the @@ -104,7 +90,11 @@ void board_init (void) bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ - /* Initialise malloc() area */ + /* + * The Malloc area is immediately below the monitor copy in DRAM + * aka CONFIG_SYS_MONITOR_BASE - Note there is no need for reloc_off + * as our monitory code is run from SDRAM + */ mem_malloc_init (CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN); for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { diff --git a/lib_mips/board.c b/lib_mips/board.c index b233a6c8a95..f62a46a1726 100644 --- a/lib_mips/board.c +++ b/lib_mips/board.c @@ -74,18 +74,6 @@ int __board_early_init_f(void) } int board_early_init_f(void) __attribute__((weak, alias("__board_early_init_f"))); -/* - * The Malloc area is immediately below the monitor copy in DRAM - */ -static void mem_malloc_init(ulong start, ulong size) -{ - mem_malloc_start = start; - mem_malloc_end = start + size; - mem_malloc_brk = start; - - memset ((void *)mem_malloc_start, 0, size); -} - static int init_func_ram (void) { @@ -347,7 +335,7 @@ void board_init_r (gd_t *id, ulong dest_addr) bd = gd->bd; - /* initialize malloc() area */ + /* The Malloc area is immediately below the monitor copy in DRAM */ mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off - TOTAL_MALLOC_LEN, TOTAL_MALLOC_LEN); malloc_bin_reloc(); diff --git a/lib_nios/board.c b/lib_nios/board.c index 745e0a4d983..72713a8fec7 100644 --- a/lib_nios/board.c +++ b/lib_nios/board.c @@ -52,18 +52,6 @@ DECLARE_GLOBAL_DATA_PTR; extern void malloc_bin_reloc (void); typedef int (init_fnc_t) (void); -/* - * The Malloc area is immediately below the monitor copy in RAM - */ -static void mem_malloc_init(ulong start, ulong size) -{ - mem_malloc_start = start; - mem_malloc_end = start + size; - mem_malloc_brk = start; - - memset ((void *)mem_malloc_start, 0, size); -} - /************************************************************************ * Initialization sequence * @@ -124,6 +112,8 @@ void board_init (void) } WATCHDOG_RESET (); + + /* The Malloc area is immediately below the monitor copy in RAM */ mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN); malloc_bin_reloc(); diff --git a/lib_nios2/board.c b/lib_nios2/board.c index 2c470dd9f41..c6b36f4a2ef 100644 --- a/lib_nios2/board.c +++ b/lib_nios2/board.c @@ -55,18 +55,6 @@ DECLARE_GLOBAL_DATA_PTR; extern void malloc_bin_reloc (void); typedef int (init_fnc_t) (void); -/* - * The Malloc area is immediately below the monitor copy in RAM - */ -static void mem_malloc_init (void) -{ - mem_malloc_start = start; - mem_malloc_end = start + size; - mem_malloc_brk = start - - memset((void *)mem_malloc_start, 0, size); -} - /************************************************************************ * Initialization sequence * @@ -130,6 +118,8 @@ void board_init (void) } WATCHDOG_RESET (); + + /* The Malloc area is immediately below the monitor copy in RAM */ mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN); malloc_bin_reloc(); diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 6cf77300951..d9a12a12413 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -141,18 +141,6 @@ ulong monitor_flash_len; ************************************************************************ */ -/* - * The Malloc area is immediately below the monitor copy in DRAM - */ -static void mem_malloc_init(ulong start, ulong size) -{ - mem_malloc_start = start; - mem_malloc_end = start + size; - mem_malloc_brk = start; - - memset ((void *)mem_malloc_start, 0, size); -} - /* * All attempts to come up with a "common" initialization sequence * that works for all boards and architectures failed: some of the @@ -657,6 +645,7 @@ void board_init_r (gd_t *id, ulong dest_addr) gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ + /* The Malloc area is immediately below the monitor copy in DRAM */ #if defined(CONFIG_RELOC_FIXUP_WORKS) gd->reloc_off = 0; malloc_start = dest_addr - TOTAL_MALLOC_LEN; @@ -758,7 +747,6 @@ void board_init_r (gd_t *id, ulong dest_addr) asm ("sync ; isync"); - /* initialize malloc() area */ mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN); malloc_bin_reloc (); diff --git a/lib_sh/board.c b/lib_sh/board.c index 26913160463..5d61f0d74fe 100644 --- a/lib_sh/board.c +++ b/lib_sh/board.c @@ -38,15 +38,6 @@ const char version_string[] = U_BOOT_VERSION" ("U_BOOT_DATE" - "U_BOOT_TIME")"; unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; -static void mem_malloc_init(ulong start, ulong size) -{ - mem_malloc_start = start; - mem_malloc_end = start + size; - mem_malloc_brk = start; - - memset((void *)mem_malloc_start, 0, size); -} - static int sh_flash_init(void) { DECLARE_GLOBAL_DATA_PTR; diff --git a/lib_sparc/board.c b/lib_sparc/board.c index e69431f8b89..6aadb56f63c 100644 --- a/lib_sparc/board.c +++ b/lib_sparc/board.c @@ -74,25 +74,6 @@ static char *failed = "*** failed ***\n"; ulong monitor_flash_len; -/************************************************************************ - * Utilities * - ************************************************************************ - */ - -/* - * The Malloc area is immediately below the monitor copy in RAM - */ -static void mem_malloc_init(ulong start, ulong size) -{ - mem_malloc_start = start; - mem_malloc_end = start + size; - mem_malloc_brk = start - - memset((void *)mem_malloc_start, 0, size); -} - -/***********************************************************************/ - /************************************************************************ * Init Utilities * ************************************************************************ @@ -313,7 +294,7 @@ void board_init_f(ulong bootflag) */ interrupt_init(); - /* initialize malloc() area */ + /* The Malloc area is immediately below the monitor copy in RAM */ mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_END - CONFIG_SYS_MALLOC_BASE); malloc_bin_reloc(); From a3ab8caee696a1d53fc82fa321e2b2f179970168 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:45 +1000 Subject: [PATCH 015/208] i386: Add errno.h Signed-off-by: Graeme Russ --- include/asm-i386/errno.h | 1 + 1 file changed, 1 insertion(+) create mode 100644 include/asm-i386/errno.h diff --git a/include/asm-i386/errno.h b/include/asm-i386/errno.h new file mode 100644 index 00000000000..4c82b503d92 --- /dev/null +++ b/include/asm-i386/errno.h @@ -0,0 +1 @@ +#include From cfb3a736ffcff3e3753b902cad536f22fcf8961d Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:46 +1000 Subject: [PATCH 016/208] i386: Change inline asm global symbols to local gcc 4.3.2 optimiser creates multiple copies of inline asm (who knows why) Remove use of global names for labels to prevent 'symbol already defined' errors Signed-off-by: Graeme Russ --- board/eNET/eNET.c | 4 ++-- cpu/i386/sc520/sc520.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index 57dd6359e78..27dabaa9651 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -51,9 +51,9 @@ void init_sc520_enet (void) /* wait at least one millisecond */ asm("movl $0x2000,%%ecx\n" - "wait_loop: pushl %%ecx\n" + "0: pushl %%ecx\n" "popl %%ecx\n" - "loop wait_loop\n": : : "ecx"); + "loop 0b\n": : : "ecx"); /* turn on the SDRAM write buffer */ write_mmcr_byte(SC520_DBCTL, 0x11); diff --git a/cpu/i386/sc520/sc520.c b/cpu/i386/sc520/sc520.c index ae3b50007f2..1d79210a62f 100644 --- a/cpu/i386/sc520/sc520.c +++ b/cpu/i386/sc520/sc520.c @@ -109,9 +109,9 @@ void init_sc520(void) /* wait at least one millisecond */ asm("movl $0x2000,%%ecx\n" - "wait_loop: pushl %%ecx\n" + "0: pushl %%ecx\n" "popl %%ecx\n" - "loop wait_loop\n": : : "ecx"); + "loop 0b\n": : : "ecx"); /* turn on the SDRAM write buffer */ write_mmcr_byte(SC520_DBCTL, 0x11); From ea0c37798c3823fdd77edfffd27b20191f8ca1f0 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:47 +1000 Subject: [PATCH 017/208] i386: Fix regression introduced by commit 8c63d47651f7 A local variable was deleted that should not have been Signed-off-by: Graeme Russ --- lib_i386/pcat_timer.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/lib_i386/pcat_timer.c b/lib_i386/pcat_timer.c index e282f649acf..c351b23b633 100644 --- a/lib_i386/pcat_timer.c +++ b/lib_i386/pcat_timer.c @@ -25,10 +25,13 @@ #include #include #include +#include #define TIMER0_VALUE 0x04aa /* 1kHz 1.9318MHz / 1000 */ #define TIMER2_VALUE 0x0a8e /* 440Hz */ +static int timer_init_done = 0; + int timer_init(void) { /* initialize timer 0 and 2 @@ -52,6 +55,8 @@ int timer_init(void) irq_install_handler (0, timer_isr, NULL); unmask_irq (0); + timer_init_done = 1; + return 0; } From f3a8d6b29b1cd01fdd940e8ff7a62b1df0ebbf82 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:48 +1000 Subject: [PATCH 018/208] Fix environment configuration for eNET board The current configuration of the Environment has the redundant copy of the environment in the Boot Flash - This was never the intent. The Environment should instead be in the first two sectors of the first Strata Flash Signed-off-by: Graeme Russ --- include/configs/eNET.h | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/include/configs/eNET.h b/include/configs/eNET.h index dde4c832130..43567142323 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -188,14 +188,13 @@ * Environment configuration */ #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE_1 + \ - CONFIG_ENV_OFFSET) -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1 +/* Redundant Copy */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \ CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SECT_SIZE /*----------------------------------------------------------------------- From 04ff9ab158714d43cdf2f4f6f0235c3ea9d241a2 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:49 +1000 Subject: [PATCH 019/208] Fix sc520 timer interrupt generation The current implementation has the timer being started before the interrupt handler is installed. It the interrupt occurs before the handler is installed, the timer interrupt is never reset and the timer stops Signed-off-by: Graeme Russ --- cpu/i386/sc520/sc520_timer.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/cpu/i386/sc520/sc520_timer.c b/cpu/i386/sc520/sc520_timer.c index 2cb8656ebd5..2a3425b6167 100644 --- a/cpu/i386/sc520/sc520_timer.c +++ b/cpu/i386/sc520/sc520_timer.c @@ -54,9 +54,6 @@ int timer_init(void) write_mmcr_word (SC520_GPTMR1MAXCMPA, 100); write_mmcr_word (SC520_GPTMR1CTL, 0xe009); - /* Clear the GP Timers status register */ - write_mmcr_byte (SC520_GPTMRSTA, 0x07); - /* Register the SC520 specific timer interrupt handler */ register_timer_isr (sc520_timer_isr); @@ -64,6 +61,9 @@ int timer_init(void) irq_install_handler (0, timer_isr, NULL); unmask_irq (0); + /* Clear the GP Timer 1 status register to get the show rolling*/ + write_mmcr_byte (SC520_GPTMRSTA, 0x02); + return 0; } From d7549024098af093785151261266a02be19af633 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:50 +1000 Subject: [PATCH 020/208] i386: Misc PCI fixups Change PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY (Originally done in commit ff4e66e93c1a, regressed by commit 6d7f610b09f8) Cast PCI_ROM_ADDRESS_MASK to u32 Wrap probe_pci_video() call inside #ifdef CONFIG_VIDEO Change call to pci_find_class() to pci_find_devices(). This is based on a patch submitted on 1st March 2007 (Patch that fixes the compilation errors for sc520_cdp board) by mushtaq_k This patch requires that PCI_VIDEO_VENDOR_ID and PCI_VIDEO_DEVICE_ID be specified in the board config file. Dummy values have been added for the SC520 CDP board to enable compilation, but since I do not have one of these, I do know what the values should be Signed-off-by: Graeme Russ --- board/sc520_cdp/sc520_cdp.c | 1 + cpu/i386/sc520/sc520_pci.c | 2 +- include/configs/sc520_cdp.h | 2 ++ lib_i386/pci.c | 2 +- lib_i386/video_bios.c | 18 +++++++++--------- 5 files changed, 14 insertions(+), 11 deletions(-) diff --git a/board/sc520_cdp/sc520_cdp.c b/board/sc520_cdp/sc520_cdp.c index 830ec37dd76..9cbe63efbc6 100644 --- a/board/sc520_cdp/sc520_cdp.c +++ b/board/sc520_cdp/sc520_cdp.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/cpu/i386/sc520/sc520_pci.c b/cpu/i386/sc520/sc520_pci.c index 38b837e81ce..871ad0a7361 100644 --- a/cpu/i386/sc520/sc520_pci.c +++ b/cpu/i386/sc520/sc520_pci.c @@ -124,7 +124,7 @@ void pci_sc520_init(struct pci_controller *hose) SC520_PCI_MEMORY_BUS, SC520_PCI_MEMORY_PHYS, SC520_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); /* PCI memory space */ pci_set_region(hose->regions + 1, diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h index 3e2bb02a462..36e1224e57a 100644 --- a/include/configs/sc520_cdp.h +++ b/include/configs/sc520_cdp.h @@ -206,6 +206,8 @@ ************************************************************/ #ifndef GRUSS_TESTING #define CONFIG_VIDEO /* To enable video controller support */ +#define PCI_VIDEO_VENDOR_ID 0 /*Use the appropriate vendor ID*/ +#define PCI_VIDEO_DEVICE_ID 0 /*Use the appropriate Device ID*/ #else #undef CONFIG_VIDEO #endif diff --git a/lib_i386/pci.c b/lib_i386/pci.c index 4331b04418c..f366bdc6724 100644 --- a/lib_i386/pci.c +++ b/lib_i386/pci.c @@ -60,7 +60,7 @@ int pci_shadow_rom(pci_dev_t dev, unsigned char *dest) vendor, device, class_code); #endif /* Enable the rom addess decoder */ - pci_write_config_dword(dev, PCI_ROM_ADDRESS, PCI_ROM_ADDRESS_MASK); + pci_write_config_dword(dev, PCI_ROM_ADDRESS, (u32)PCI_ROM_ADDRESS_MASK); pci_read_config_dword(dev, PCI_ROM_ADDRESS, &addr_reg); if (!addr_reg) { diff --git a/lib_i386/video_bios.c b/lib_i386/video_bios.c index ce96a3e058f..c8060e60a77 100644 --- a/lib_i386/video_bios.c +++ b/lib_i386/video_bios.c @@ -76,18 +76,22 @@ void print_bios_bios_stat(void) } #endif +#ifdef CONFIG_VIDEO + #define PCI_CLASS_VIDEO 3 #define PCI_CLASS_VIDEO_STD 0 #define PCI_CLASS_VIDEO_PROG_IF_VGA 0 +static struct pci_device_id supported[] = { + {PCI_VIDEO_VENDOR_ID, PCI_VIDEO_DEVICE_ID}, + {} +}; static u32 probe_pci_video(void) { pci_dev_t devbusfn; - if ((devbusfn = pci_find_class(PCI_CLASS_VIDEO, - PCI_CLASS_VIDEO_STD, - PCI_CLASS_VIDEO_PROG_IF_VGA, 0)) != -1) { + if ((devbusfn = pci_find_devices(supported, 0) != -1)) { u32 old; u32 addr; @@ -103,7 +107,7 @@ static u32 probe_pci_video(void) /* Test the ROM decoder, do the device support a rom? */ pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &old); - pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, PCI_ROM_ADDRESS_MASK); + pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, (u32)PCI_ROM_ADDRESS_MASK); pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &addr); pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, old); @@ -133,11 +137,6 @@ static u32 probe_pci_video(void) return 0; } - -#endif - -#ifdef CONFIG_VIDEO - static int probe_isa_video(void) { u32 ptr; @@ -220,3 +219,4 @@ int video_bios_init(void) } #endif +#endif From 31b9ab33d93d88ff89f3046aa45c68667a378a56 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:51 +1000 Subject: [PATCH 021/208] Misc SATA fixups Cast first parameter to sata_cpy() In /drivers/block/ata_piix.h, ata_id_has_lba48(), ata_id_has_lba(), ata_id_has_dma(), ata_id_u32(), ata_id_u64() are all defined in include/libata.h which is included in ata.h which is included by all files which include ata_piix.h (only ata_piix.c) so these definitions are supurflous to (and conlict with) this in libata.h. Interestingly, my compiler complains about ata_id_u64 already being defined, but not ata_id_u32 ata_dump_id() is defined in include/libata.h and should not be static (maybe should even use ata_dump_id() in libata.c Signed-off-by: Graeme Russ --- drivers/block/ata_piix.c | 10 +++++----- drivers/block/ata_piix.h | 15 +-------------- 2 files changed, 6 insertions(+), 19 deletions(-) diff --git a/drivers/block/ata_piix.c b/drivers/block/ata_piix.c index 549de31235b..c81d11a6ce3 100644 --- a/drivers/block/ata_piix.c +++ b/drivers/block/ata_piix.c @@ -310,7 +310,7 @@ sata_bus_softreset (int num) } if (status & ATA_BUSY) - printf ("ata%u is slow to respond,plz be patient\n", port); + printf ("ata%u is slow to respond,plz be patient\n", num); while ((status & ATA_BUSY)) { msleep (100); @@ -318,7 +318,7 @@ sata_bus_softreset (int num) } if (status & ATA_BUSY) { - printf ("ata%u failed to respond : ", port); + printf ("ata%u failed to respond : ", num); printf ("bus reset failed\n"); return 1; } @@ -389,11 +389,11 @@ sata_identify (int num, int dev) return; } - sata_cpy (sata_dev_desc[devno].revision, iop->fw_rev, + sata_cpy ((unsigned char *)sata_dev_desc[devno].revision, iop->fw_rev, sizeof (sata_dev_desc[devno].revision)); - sata_cpy (sata_dev_desc[devno].vendor, iop->model, + sata_cpy ((unsigned char *)sata_dev_desc[devno].vendor, iop->model, sizeof (sata_dev_desc[devno].vendor)); - sata_cpy (sata_dev_desc[devno].product, iop->serial_no, + sata_cpy ((unsigned char *)sata_dev_desc[devno].product, iop->serial_no, sizeof (sata_dev_desc[devno].product)); strswab (sata_dev_desc[devno].revision); strswab (sata_dev_desc[devno].vendor); diff --git a/drivers/block/ata_piix.h b/drivers/block/ata_piix.h index 11885af20e9..9157cf82c0b 100644 --- a/drivers/block/ata_piix.h +++ b/drivers/block/ata_piix.h @@ -37,20 +37,7 @@ struct sata_port { /***********SATA LIBRARY SPECIFIC DEFINITIONS AND DECLARATIONS**************/ #ifdef SATA_DECL /*SATA library specific declarations */ -#define ata_id_has_lba48(id) ((id)[83] & (1 << 10)) -#define ata_id_has_lba(id) ((id)[49] & (1 << 9)) -#define ata_id_has_dma(id) ((id)[49] & (1 << 8)) -#define ata_id_u32(id,n) \ - (((u32) (id)[(n) + 1] << 16) | ((u32) (id)[(n)])) -#define ata_id_u64(id,n) \ - (((u64) (id)[(n) + 3] << 48) | \ - ((u64) (id)[(n) + 2] << 32) | \ - ((u64) (id)[(n) + 1] << 16) | \ - ((u64) (id)[(n) + 0]) ) -#endif - -#ifdef SATA_DECL /*SATA library specific declarations */ -static inline void +inline void ata_dump_id (u16 * id) { PRINTF ("49 = 0x%04x " From a92510e7fae523145b58765cdc46110f1162260d Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:52 +1000 Subject: [PATCH 022/208] Misc ti_pci1410a fixups Removed do_pinit() - now declared in cmd_pcmcia.c Added #define CONFIG_CMD_PCMCIA around pcmcia_off() in line with other PCMCIA drivers signed/unsigned type fixups Added semi-colon after default: label as required by newer gcc The only board that appears to use this driver is the sc520_spunk which is very old and very likely very broken anyway. I do not have one to test whether this patch breaks anything functionaly, I have can only check that it compiles without warning or error Signed-off-by: Graeme Russ --- drivers/pcmcia/ti_pci1410a.c | 62 +++++++++++------------------------- 1 file changed, 18 insertions(+), 44 deletions(-) diff --git a/drivers/pcmcia/ti_pci1410a.c b/drivers/pcmcia/ti_pci1410a.c index 6ab97597f7b..4ac2e0fd092 100644 --- a/drivers/pcmcia/ti_pci1410a.c +++ b/drivers/pcmcia/ti_pci1410a.c @@ -68,13 +68,12 @@ int pcmcia_on(int ide_base_bus); -static int pcmcia_off(void); static int hardware_disable(int slot); static int hardware_enable(int slot); static int voltage_set(int slot, int vcc, int vpp); static void print_funcid(int func); -static void print_fixed(volatile uchar *p); -static int identify(volatile uchar *p); +static void print_fixed(volatile char *p); +static int identify(volatile char *p); static int check_ide_device(int slot, int ide_base_bus); @@ -86,33 +85,6 @@ const char *indent = "\t "; /* ------------------------------------------------------------------------- */ -int do_pinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ -#ifndef CONFIG_SYS_FIRST_PCMCIA_BUS -# define CONFIG_SYS_FIRST_PCMCIA_BUS 0 -#endif - - int rcode = 0; - - if (argc != 2) { - printf ("Usage: pinit {on | off}\n"); - return 1; - } - if (strcmp(argv[1],"on") == 0) { - rcode = pcmcia_on(CONFIG_SYS_FIRST_PCMCIA_BUS); - } else if (strcmp(argv[1],"off") == 0) { - rcode = pcmcia_off(); - } else { - printf ("Usage: pinit {on | off}\n"); - return 1; - } - - return rcode; -} - -/* ------------------------------------------------------------------------- */ - - static struct pci_device_id supported[] = { { PCI_VENDOR_ID_TI, 0xac50 }, /* Ti PCI1410A */ { PCI_VENDOR_ID_TI, 0xac56 }, /* Ti PCI1510 */ @@ -245,7 +217,8 @@ int pcmcia_on(int ide_base_bus) /* ------------------------------------------------------------------------- */ -static int pcmcia_off (void) +#if defined(CONFIG_CMD_PCMCIA) +int pcmcia_off (void) { int slot = 0; @@ -285,6 +258,7 @@ static int pcmcia_off (void) return 0; } +#endif /* ------------------------------------------------------------------------- */ @@ -294,9 +268,9 @@ static int pcmcia_off (void) int ide_devices_found; static int check_ide_device(int slot, int ide_base_bus) { - volatile uchar *ident = NULL; - volatile uchar *feature_p[MAX_FEATURES]; - volatile uchar *p, *start; + volatile char *ident = NULL; + volatile char *feature_p[MAX_FEATURES]; + volatile char *p, *start; int n_features = 0; uchar func_id = ~0; uchar code, len; @@ -314,7 +288,7 @@ static int check_ide_device(int slot, int ide_base_bus) return 1; } - start = p = (volatile uchar *) pcmcia_cis_ptr; + start = p = (volatile char *) pcmcia_cis_ptr; while ((p - start) < MAX_TUPEL_SZ) { @@ -417,7 +391,7 @@ static int voltage_set(int slot, int vcc, int vpp) socket_control |= 0x30; break; case 0: - default: + default: ; } switch (vpp) { @@ -431,7 +405,7 @@ static int voltage_set(int slot, int vcc, int vpp) socket_control |= 0x3; break; case 0: - default: + default: ; } writel(socket_control, reg); @@ -537,7 +511,7 @@ static void print_funcid(int func) /* ------------------------------------------------------------------------- */ -static void print_fixed(volatile uchar *p) +static void print_fixed(volatile char *p) { if (p == NULL) return; @@ -605,17 +579,17 @@ static void print_fixed(volatile uchar *p) #define MAX_IDENT_CHARS 64 #define MAX_IDENT_FIELDS 4 -static uchar *known_cards[] = { +static char *known_cards[] = { "ARGOSY PnPIDE D5", NULL }; -static int identify(volatile uchar *p) +static int identify(volatile char *p) { - uchar id_str[MAX_IDENT_CHARS]; - uchar data; - uchar *t; - uchar **card; + char id_str[MAX_IDENT_CHARS]; + char data; + char *t; + char **card; int i, done; if (p == NULL) From 8907b8dbc5805094f1316d64737d3428b3863693 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:53 +1000 Subject: [PATCH 023/208] Misc ds1722 fixups This patch is based on a patch submitted by Jean-Christophe PLAGNIOL-VILLARD on 18th May 2008 as part of a general i386 / sc520 fixup which was never applied Signed-off-by: Graeme Russ --- drivers/hwmon/ds1722.c | 3 ++- include/ds1722.h | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 1 deletion(-) create mode 100644 include/ds1722.h diff --git a/drivers/hwmon/ds1722.c b/drivers/hwmon/ds1722.c index 7e2f1ed4fb0..a46cd4dfb5a 100644 --- a/drivers/hwmon/ds1722.c +++ b/drivers/hwmon/ds1722.c @@ -1,6 +1,7 @@ #include -#include +#include +#include static void ds1722_select(int dev) { diff --git a/include/ds1722.h b/include/ds1722.h new file mode 100644 index 00000000000..44f0830c0b7 --- /dev/null +++ b/include/ds1722.h @@ -0,0 +1,32 @@ +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _DS1722_H_ +#define _DS1722_H_ + +#define DS1722_RESOLUTION_8BIT 0x0 +#define DS1722_RESOLUTION_9BIT 0x1 +#define DS1722_RESOLUTION_10BIT 0x2 +#define DS1722_RESOLUTION_11BIT 0x3 +#define DS1722_RESOLUTION_12BIT 0x4 + +int ds1722_probe(int dev); + +#endif /* _DS1722_H_ */ From 91ee4e183cb7ac5f86e7673ead51400f19906635 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:54 +1000 Subject: [PATCH 024/208] Fixup sc520_spunk board Primary intent is to resolve build errors for this board which has been neglected for a very long time. I do not have one of these boards, so I cannot test functionality Signed-off-by: Graeme Russ --- board/sc520_spunk/sc520_spunk.c | 33 +++++++++++++++++++++++++++++++-- include/configs/sc520_spunk.h | 2 ++ 2 files changed, 33 insertions(+), 2 deletions(-) diff --git a/board/sc520_spunk/sc520_spunk.c b/board/sc520_spunk/sc520_spunk.c index d3bd8693065..36a0a8ecfc5 100644 --- a/board/sc520_spunk/sc520_spunk.c +++ b/board/sc520_spunk/sc520_spunk.c @@ -24,11 +24,13 @@ #include #include -#include #include +#include #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -112,7 +114,7 @@ static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev }; static int next_irq_index=0; - char tmp_pin; + uchar tmp_pin; int pin; pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin); @@ -637,6 +639,33 @@ void ssi_chip_select(int dev) } } +void spi_eeprom_probe(int x) +{ +} + +int spi_eeprom_read(int x, int offset, uchar *buffer, int len) +{ + return 0; +} + +int spi_eeprom_write(int x, int offset, uchar *buffer, int len) +{ + return 0; +} + +void mw_eeprom_probe(int x) +{ +} + +int mw_eeprom_read(int x, int offset, uchar *buffer, int len) +{ + return 0; +} + +int mw_eeprom_write(int x, int offset, uchar *buffer, int len) +{ + return 0; +} void spi_init_f(void) { diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h index d42ef842167..f3fc9602ada 100644 --- a/include/configs/sc520_spunk.h +++ b/include/configs/sc520_spunk.h @@ -37,6 +37,7 @@ #define CONFIG_X86 1 /* This is a X86 CPU */ #define CONFIG_SYS_SC520 1 /* Include support for AMD SC520 */ +#define CONFIG_SYS_SC520_SSI #define CONFIG_SYS_SDRAM_PRECHARGE_DELAY 6 /* 6T */ #define CONFIG_SYS_SDRAM_REFRESH_RATE 78 /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */ @@ -218,6 +219,7 @@ #define CONFIG_SYS_PCMCIA_CIS_WIN_SIZE 0x00100000 #define CONFIG_SYS_PCMCIA_IO_WIN 0xe000 #define CONFIG_SYS_PCMCIA_IO_WIN_SIZE 16 +#define CONFIG_PCMCIA_SLOT_A /* TODO: Check this */ /************************************************************ * DISK Partition support From 9b32f96b5b92ba13fdb4b5eb637734752235f260 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:55 +1000 Subject: [PATCH 025/208] Misc sc520 cdp fixups Now that the PCI, SATA et al compile problems have been resolved, the cludge that was applied to avoid them can be removed Signed-off-by: Graeme Russ --- include/configs/sc520_cdp.h | 22 ---------------------- 1 file changed, 22 deletions(-) diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h index 36e1224e57a..214a9af356e 100644 --- a/include/configs/sc520_cdp.h +++ b/include/configs/sc520_cdp.h @@ -30,7 +30,6 @@ #define CONFIG_SKIP_RELOCATE_UBOOT -#define GRUSS_TESTING /* * High Level Configuration Options * (easy to change) @@ -85,11 +84,7 @@ #include #define CONFIG_CMD_PCI -#ifndef GRUSS_TESTING #define CONFIG_CMD_SATA -#else -#undef CONFIG_CMD_SATA -#endif #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NET #define CONFIG_CMD_EEPROM @@ -181,17 +176,10 @@ /************************************************************ *SATA/Native Stuff ************************************************************/ -#ifndef GRUSS_TESTING #define CONFIG_SYS_SATA_MAXBUS 2 /*Max Sata buses supported */ #define CONFIG_SYS_SATA_DEVS_PER_BUS 2 /*Max no. of devices per bus/port */ #define CONFIG_SYS_SATA_MAX_DEVICE (CONFIG_SYS_SATA_MAXBUS* CONFIG_SYS_SATA_DEVS_PER_BUS) #define CONFIG_ATA_PIIX 1 /*Supports ata_piix driver */ -#else -#undef CONFIG_SYS_SATA_MAXBUS -#undef CONFIG_SYS_SATA_DEVS_PER_BUS -#undef CONFIG_SYS_SATA_MAX_DEVICE -#undef CONFIG_ATA_PIIX -#endif /************************************************************ @@ -204,13 +192,9 @@ /************************************************************ * Video/Keyboard support ************************************************************/ -#ifndef GRUSS_TESTING #define CONFIG_VIDEO /* To enable video controller support */ #define PCI_VIDEO_VENDOR_ID 0 /*Use the appropriate vendor ID*/ #define PCI_VIDEO_DEVICE_ID 0 /*Use the appropriate Device ID*/ -#else -#undef CONFIG_VIDEO -#endif #define CONFIG_I8042_KBD #define CONFIG_SYS_ISA_IO 0 @@ -223,7 +207,6 @@ /* * PCI stuff */ -#ifndef GRUSS_TESTING #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_PNP /* pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW @@ -232,11 +215,6 @@ #define CONFIG_SYS_SECOND_PCI_IRQ 9 #define CONFIG_SYS_THIRD_PCI_IRQ 11 #define CONFIG_SYS_FORTH_PCI_IRQ 15 -#else -#undef CONFIG_PCI -#undef CONFIG_PCI_PNP -#undef CONFIG_PCI_SCAN_SHOW -#endif #endif /* __CONFIG_H */ From ed7a1b681de1e31d18d5b92e2767ae8df3241687 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:56 +1000 Subject: [PATCH 026/208] i386: Replace [read, write]_mmcr_[byte, word, long] with memory mapped structure Signed-off-by: Graeme Russ --- board/eNET/eNET.c | 80 +++--- board/sc520_cdp/flash.c | 14 +- board/sc520_cdp/sc520_cdp.c | 165 +++++++------ board/sc520_spunk/sc520_spunk.c | 203 ++++++++-------- cpu/i386/sc520/sc520.c | 71 ++---- cpu/i386/sc520/sc520_pci.c | 64 ++--- cpu/i386/sc520/sc520_ssi.c | 28 ++- cpu/i386/sc520/sc520_timer.c | 31 +-- include/asm-i386/ic/sc520.h | 417 ++++++++++++++++++-------------- 9 files changed, 539 insertions(+), 534 deletions(-) diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index 27dabaa9651..29cf29518a0 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -46,7 +46,7 @@ unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; void init_sc520_enet (void) { /* Set CPU Speed to 100MHz */ - write_mmcr_byte(SC520_CPUCTL, 1); + sc520_mmcr->cpuctl = 0x01; gd->cpu_clk = 100000000; /* wait at least one millisecond */ @@ -56,7 +56,7 @@ void init_sc520_enet (void) "loop 0b\n": : : "ecx"); /* turn on the SDRAM write buffer */ - write_mmcr_byte(SC520_DBCTL, 0x11); + sc520_mmcr->dbctl = 0x11; /* turn on the cache and disable write through */ asm("movl %%cr0, %%eax\n" @@ -71,51 +71,51 @@ int board_init(void) { init_sc520_enet(); - write_mmcr_byte(SC520_GPCSRT, 0x01); /* GP Chip Select Recovery Time */ - write_mmcr_byte(SC520_GPCSPW, 0x07); /* GP Chip Select Pulse Width */ - write_mmcr_byte(SC520_GPCSOFF, 0x00); /* GP Chip Select Offset */ - write_mmcr_byte(SC520_GPRDW, 0x05); /* GP Read pulse width */ - write_mmcr_byte(SC520_GPRDOFF, 0x01); /* GP Read offset */ - write_mmcr_byte(SC520_GPWRW, 0x05); /* GP Write pulse width */ - write_mmcr_byte(SC520_GPWROFF, 0x01); /* GP Write offset */ + sc520_mmcr->gpcsrt = 0x01; /* GP Chip Select Recovery Time */ + sc520_mmcr->gpcspw = 0x07; /* GP Chip Select Pulse Width */ + sc520_mmcr->gpcsoff = 0x00; /* GP Chip Select Offset */ + sc520_mmcr->gprdw = 0x05; /* GP Read pulse width */ + sc520_mmcr->gprdoff = 0x01; /* GP Read offset */ + sc520_mmcr->gpwrw = 0x05; /* GP Write pulse width */ + sc520_mmcr->gpwroff = 0x01; /* GP Write offset */ - write_mmcr_word(SC520_PIODATA15_0, 0x0630); /* PIO15_PIO0 Data */ - write_mmcr_word(SC520_PIODATA31_16, 0x2000); /* PIO31_PIO16 Data */ - write_mmcr_word(SC520_PIODIR31_16, 0x2000); /* GPIO Direction */ - write_mmcr_word(SC520_PIODIR15_0, 0x87b5); /* GPIO Direction */ - write_mmcr_word(SC520_PIOPFS31_16, 0x0dfe); /* GPIO pin function 31-16 reg */ - write_mmcr_word(SC520_PIOPFS15_0, 0x200a); /* GPIO pin function 15-0 reg */ - write_mmcr_byte(SC520_CSPFS, 0x00f8); /* Chip Select Pin Function Select */ + sc520_mmcr->piodata15_0 = 0x0630; /* PIO15_PIO0 Data */ + sc520_mmcr->piodata31_16 = 0x2000; /* PIO31_PIO16 Data */ + sc520_mmcr->piodir31_16 = 0x2000; /* GPIO Direction */ + sc520_mmcr->piodir15_0 = 0x87b5; /* GPIO Direction */ + sc520_mmcr->piopfs31_16 = 0x0dfe; /* GPIO pin function 31-16 reg */ + sc520_mmcr->piopfs15_0 = 0x200a; /* GPIO pin function 15-0 reg */ + sc520_mmcr->cspfs = 0x00f8; /* Chip Select Pin Function Select */ - write_mmcr_long(SC520_PAR2, 0x200713f8); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */ - write_mmcr_long(SC520_PAR3, 0x2c0712f8); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */ - write_mmcr_long(SC520_PAR4, 0x300711f8); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */ - write_mmcr_long(SC520_PAR5, 0x340710f8); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */ - write_mmcr_long(SC520_PAR6, 0xe3ffc000); /* SDRAM (0x00000000, 128MB) */ - write_mmcr_long(SC520_PAR7, 0xaa3fd000); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */ - write_mmcr_long(SC520_PAR8, 0xca3fd100); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */ - write_mmcr_long(SC520_PAR9, 0x4203d900); /* SRAM (GPCS0, 0x19000000, 1MB) */ - write_mmcr_long(SC520_PAR10, 0x4e03d910); /* SRAM (GPCS3, 0x19100000, 1MB) */ - write_mmcr_long(SC520_PAR11, 0x50018100); /* DP-RAM (GPCS4, 0x18100000, 4kB) */ - write_mmcr_long(SC520_PAR12, 0x54020000); /* CFLASH1 (0x200000000, 4kB) */ - write_mmcr_long(SC520_PAR13, 0x5c020001); /* CFLASH2 (0x200010000, 4kB) */ -/* write_mmcr_long(SC520_PAR14, 0x8bfff800); */ /* BOOTCS at 0x18000000 */ -/* write_mmcr_long(SC520_PAR15, 0x38201000); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */ + sc520_mmcr->par[2] = 0x200713f8; /* Uart A (GPCS0, 0x013f8, 8 Bytes) */ + sc520_mmcr->par[3] = 0x2c0712f8; /* Uart B (GPCS3, 0x012f8, 8 Bytes) */ + sc520_mmcr->par[4] = 0x300711f8; /* Uart C (GPCS4, 0x011f8, 8 Bytes) */ + sc520_mmcr->par[5] = 0x340710f8; /* Uart D (GPCS5, 0x010f8, 8 Bytes) */ + sc520_mmcr->par[6] = 0xe3ffc000; /* SDRAM (0x00000000, 128MB) */ + sc520_mmcr->par[7] = 0xaa3fd000; /* StrataFlash (ROMCS1, 0x10000000, 16MB) */ + sc520_mmcr->par[8] = 0xca3fd100; /* StrataFlash (ROMCS2, 0x11000000, 16MB) */ + sc520_mmcr->par[9] = 0x4203d900; /* SRAM (GPCS0, 0x19000000, 1MB) */ + sc520_mmcr->par[10] = 0x4e03d910; /* SRAM (GPCS3, 0x19100000, 1MB) */ + sc520_mmcr->par[11] = 0x50018100; /* DP-RAM (GPCS4, 0x18100000, 4kB) */ + sc520_mmcr->par[12] = 0x54020000; /* CFLASH1 (0x200000000, 4kB) */ + sc520_mmcr->par[13] = 0x5c020001; /* CFLASH2 (0x200010000, 4kB) */ +/* sc520_mmcr->par14 = 0x8bfff800; */ /* BOOTCS at 0x18000000 */ +/* sc520_mmcr->par15 = 0x38201000; */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */ /* Disable Watchdog */ - write_mmcr_word(0x0cb0, 0x3333); - write_mmcr_word(0x0cb0, 0xcccc); - write_mmcr_word(0x0cb0, 0x0000); + sc520_mmcr->wdtmrctl = 0x3333; + sc520_mmcr->wdtmrctl = 0xcccc; + sc520_mmcr->wdtmrctl = 0x0000; /* Chip Select Configuration */ - write_mmcr_word(SC520_BOOTCSCTL, 0x0033); - write_mmcr_word(SC520_ROMCS1CTL, 0x0615); - write_mmcr_word(SC520_ROMCS2CTL, 0x0615); + sc520_mmcr->bootcsctl = 0x0033; + sc520_mmcr->romcs1ctl = 0x0615; + sc520_mmcr->romcs2ctl = 0x0615; - write_mmcr_byte(SC520_ADDDECCTL, 0x02); - write_mmcr_byte(SC520_UART1CTL, 0x07); - write_mmcr_byte(SC520_SYSARBCTL,0x06); - write_mmcr_word(SC520_SYSARBMENB, 0x0003); + sc520_mmcr->adddecctl = 0x02; + sc520_mmcr->uart1ctl = 0x07; + sc520_mmcr->sysarbctl = 0x06; + sc520_mmcr->sysarbmenb = 0x0003; /* Crystal is 33.000MHz */ gd->bus_clk = 33000000; diff --git a/board/sc520_cdp/flash.c b/board/sc520_cdp/flash.c index dcb8c57e817..64831b7edaa 100644 --- a/board/sc520_cdp/flash.c +++ b/board/sc520_cdp/flash.c @@ -337,12 +337,12 @@ done: ; unsigned micro; \ unsigned milli=0; \ \ - micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \ + micro = sc520_mmcr->swtmrmilli; \ \ for (;;) { \ \ - milli += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \ - micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMICRO); \ + milli += sc520_mmcr->swtmrmilli; \ + micro = sc520_mmcr->swtmrmicro; \ \ if ((delay) <= (micro + (milli * 1000))) { \ break; \ @@ -364,12 +364,12 @@ static u32 _amd_erase_flash(u32 addr, u32 sector) /* Sector erase command comes last */ *(volatile u32*)(addr + sector) = 0x30303030; - elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */ + elapsed = sc520_mmcr->swtmrmilli; /* dummy read */ elapsed = 0; __udelay(50); while (((*(volatile u32*)(addr + sector)) & 0x80808080) != 0x80808080) { - elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); + elapsed += sc520_mmcr->swtmrmilli; if (elapsed > ((CONFIG_SYS_FLASH_ERASE_TOUT/CONFIG_SYS_HZ) * 1000)) { *(volatile u32*)(addr) = 0xf0f0f0f0; return 1; @@ -487,12 +487,12 @@ static int _amd_write_word(unsigned start, unsigned dest, unsigned data) dest2[0] = data; - elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */ + elapsed = sc520_mmcr->swtmrmilli; /* dummy read */ elapsed = 0; /* data polling for D7 */ while ((dest2[0] & 0x80808080) != (data2[0] & 0x80808080)) { - elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); + elapsed += sc520_mmcr->swtmrmilli; if (elapsed > ((CONFIG_SYS_FLASH_WRITE_TOUT/CONFIG_SYS_HZ) * 1000)) { addr2[0] = 0xf0f0f0f0; return 1; diff --git a/board/sc520_cdp/sc520_cdp.c b/board/sc520_cdp/sc520_cdp.c index 9cbe63efbc6..9312f4f1d37 100644 --- a/board/sc520_cdp/sc520_cdp.c +++ b/board/sc520_cdp/sc520_cdp.c @@ -58,61 +58,60 @@ DECLARE_GLOBAL_DATA_PTR; static void irq_init(void) { /* disable global interrupt mode */ - write_mmcr_byte(SC520_PICICR, 0x40); + sc520_mmcr->picicr = 0x40; /* set all irqs to edge */ - write_mmcr_byte(SC520_MPICMODE, 0x00); - write_mmcr_byte(SC520_SL1PICMODE, 0x00); - write_mmcr_byte(SC520_SL2PICMODE, 0x00); + sc520_mmcr->pic_mode[0] = 0x00; + sc520_mmcr->pic_mode[1] = 0x00; + sc520_mmcr->pic_mode[2] = 0x00; /* active low polarity on PIC interrupt pins, * active high polarity on all other irq pins */ - write_mmcr_word(SC520_INTPINPOL, 0x0000); + sc520_mmcr->intpinpol = 0x0000; /* set irq number mapping */ - write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED); /* disable GP timer 0 INT */ - write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED); /* disable GP timer 1 INT */ - write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED); /* disable GP timer 2 INT */ - write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0); /* Set PIT timer 0 INT to IRQ0 */ - write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED); /* disable PIT timer 1 INT */ - write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED); /* disable PIT timer 2 INT */ - write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED); /* disable PCI INT A */ - write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED); /* disable PCI INT B */ - write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED); /* disable PCI INT C */ - write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED); /* disable PCI INT D */ - write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */ - write_mmcr_byte(SC520_SSIMAP, SC520_IRQ_DISABLED); /* disable Synchronius serial INT */ - write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED); /* disable Watchdog INT */ - write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8); /* Set RTC int to 8 */ - write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED); /* disable write protect INT */ - write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1); /* Set ICE Debug Serielport INT to IRQ1 */ - write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13); /* Set FP error INT to IRQ13 */ + sc520_mmcr->gp_tmr_int_map[0] = SC520_IRQ_DISABLED; /* disable GP timer 0 INT */ + sc520_mmcr->gp_tmr_int_map[1] = SC520_IRQ_DISABLED; /* disable GP timer 1 INT */ + sc520_mmcr->gp_tmr_int_map[2] = SC520_IRQ_DISABLED; /* disable GP timer 2 INT */ + sc520_mmcr->pit_int_map[0] = SC520_IRQ0; /* Set PIT timer 0 INT to IRQ0 */ + sc520_mmcr->pit_int_map[1] = SC520_IRQ_DISABLED; /* disable PIT timer 1 INT */ + sc520_mmcr->pit_int_map[2] = SC520_IRQ_DISABLED; /* disable PIT timer 2 INT */ + sc520_mmcr->pci_int_map[0] = SC520_IRQ_DISABLED; /* disable PCI INT A */ + sc520_mmcr->pci_int_map[1] = SC520_IRQ_DISABLED; /* disable PCI INT B */ + sc520_mmcr->pci_int_map[2] = SC520_IRQ_DISABLED; /* disable PCI INT C */ + sc520_mmcr->pci_int_map[3] = SC520_IRQ_DISABLED; /* disable PCI INT D */ + sc520_mmcr->dmabcintmap = SC520_IRQ_DISABLED; /* disable DMA INT */ + sc520_mmcr->ssimap = SC520_IRQ_DISABLED; /* disable Synchronius serial INT */ + sc520_mmcr->wdtmap = SC520_IRQ_DISABLED; /* disable Watchdog INT */ + sc520_mmcr->rtcmap = SC520_IRQ8; /* Set RTC int to 8 */ + sc520_mmcr->wpvmap = SC520_IRQ_DISABLED; /* disable write protect INT */ + sc520_mmcr->icemap = SC520_IRQ1; /* Set ICE Debug Serielport INT to IRQ1 */ + sc520_mmcr->ferrmap = SC520_IRQ13; /* Set FP error INT to IRQ13 */ if (CONFIG_SYS_USE_SIO_UART) { - write_mmcr_byte(SC520_UART1MAP, SC520_IRQ_DISABLED); /* disable internal UART1 INT */ - write_mmcr_byte(SC520_UART2MAP, SC520_IRQ_DISABLED); /* disable internal UART2 INT */ - write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ3); /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */ - write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ4); /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */ + sc520_mmcr->uart_int_map[0] = SC520_IRQ_DISABLED; /* disable internal UART1 INT */ + sc520_mmcr->uart_int_map[1] = SC520_IRQ_DISABLED; /* disable internal UART2 INT */ + sc520_mmcr->gp_int_map[3] = SC520_IRQ3; /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */ + sc520_mmcr->gp_int_map[4] = SC520_IRQ4; /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */ } else { - write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4); /* Set internal UART2 INT to IRQ4 */ - write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3); /* Set internal UART2 INT to IRQ3 */ - write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ3 (ISA IRQ3) */ - write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ4 (ISA IRQ4) */ + sc520_mmcr->uart_int_map[0] = SC520_IRQ4; /* Set internal UART2 INT to IRQ4 */ + sc520_mmcr->uart_int_map[1] = SC520_IRQ3; /* Set internal UART2 INT to IRQ3 */ + sc520_mmcr->gp_int_map[3] = SC520_IRQ_DISABLED; /* disable GPIRQ3 (ISA IRQ3) */ + sc520_mmcr->gp_int_map[4] = SC520_IRQ_DISABLED; /* disable GPIRQ4 (ISA IRQ4) */ } - write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ1); /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */ - write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ5); /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */ - write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ6); /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */ - write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ7); /* Set GPIRQ7 (ISA IRQ7) to IRQ7 */ - write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ8); /* Set GPIRQ8 (SIO IRQ8) to IRQ8 */ - write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ9); /* Set GPIRQ9 (ISA IRQ2) to IRQ9 */ - write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ11); /* Set GPIRQ0 (ISA IRQ11) to IRQ10 */ - write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ12); /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */ - write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ14); /* Set GPIRQ10 (ISA IRQ14) to IRQ14 */ - - write_mmcr_word(SC520_PCIHOSTMAP, 0x11f); /* Map PCI hostbridge INT to NMI */ - write_mmcr_word(SC520_ECCMAP, 0x100); /* Map SDRAM ECC failure INT to NMI */ + sc520_mmcr->gp_int_map[1] = SC520_IRQ1; /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */ + sc520_mmcr->gp_int_map[5] = SC520_IRQ5; /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */ + sc520_mmcr->gp_int_map[6] = SC520_IRQ6; /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */ + sc520_mmcr->gp_int_map[7] = SC520_IRQ7; /* Set GPIRQ7 (ISA IRQ7) to IRQ7 */ + sc520_mmcr->gp_int_map[8] = SC520_IRQ8; /* Set GPIRQ8 (SIO IRQ8) to IRQ8 */ + sc520_mmcr->gp_int_map[9] = SC520_IRQ9; /* Set GPIRQ9 (ISA IRQ2) to IRQ9 */ + sc520_mmcr->gp_int_map[0] = SC520_IRQ11; /* Set GPIRQ0 (ISA IRQ11) to IRQ10 */ + sc520_mmcr->gp_int_map[2] = SC520_IRQ12; /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */ + sc520_mmcr->gp_int_map[10] = SC520_IRQ14; /* Set GPIRQ10 (ISA IRQ14) to IRQ14 */ + sc520_mmcr->pcihostmap = 0x11f; /* Map PCI hostbridge INT to NMI */ + sc520_mmcr->eccmap = 0x100; /* Map SDRAM ECC failure INT to NMI */ } #ifdef CONFIG_PCI @@ -235,23 +234,22 @@ static void bus_init(void) { /* set up the GP IO pins */ - write_mmcr_word(SC520_PIOPFS31_16, 0xf7ff); /* set the GPIO pin function 31-16 reg */ - write_mmcr_word(SC520_PIOPFS15_0, 0xffff); /* set the GPIO pin function 15-0 reg */ - write_mmcr_byte(SC520_CSPFS, 0xf8); /* set the CS pin function reg */ - write_mmcr_byte(SC520_CLKSEL, 0x70); + sc520_mmcr->piopfs31_16 = 0xf7ff; /* set the GPIO pin function 31-16 reg */ + sc520_mmcr->piopfs15_0 = 0xffff; /* set the GPIO pin function 15-0 reg */ + sc520_mmcr->cspfs = 0xf8; /* set the CS pin function reg */ + sc520_mmcr->clksel = 0x70; + sc520_mmcr->gpcsrt = 1; /* set the GP CS offset */ + sc520_mmcr->gpcspw = 3; /* set the GP CS pulse width */ + sc520_mmcr->gpcsoff = 1; /* set the GP CS offset */ + sc520_mmcr->gprdw = 3; /* set the RD pulse width */ + sc520_mmcr->gprdoff = 1; /* set the GP RD offset */ + sc520_mmcr->gpwrw = 3; /* set the GP WR pulse width */ + sc520_mmcr->gpwroff = 1; /* set the GP WR offset */ - write_mmcr_byte(SC520_GPCSRT, 1); /* set the GP CS offset */ - write_mmcr_byte(SC520_GPCSPW, 3); /* set the GP CS pulse width */ - write_mmcr_byte(SC520_GPCSOFF, 1); /* set the GP CS offset */ - write_mmcr_byte(SC520_GPRDW, 3); /* set the RD pulse width */ - write_mmcr_byte(SC520_GPRDOFF, 1); /* set the GP RD offset */ - write_mmcr_byte(SC520_GPWRW, 3); /* set the GP WR pulse width */ - write_mmcr_byte(SC520_GPWROFF, 1); /* set the GP WR offset */ - - write_mmcr_word(SC520_BOOTCSCTL, 0x1823); /* set up timing of BOOTCS */ - write_mmcr_word(SC520_ROMCS1CTL, 0x1823); /* set up timing of ROMCS1 */ - write_mmcr_word(SC520_ROMCS2CTL, 0x1823); /* set up timing of ROMCS2 */ + sc520_mmcr->bootcsctl = 0x1823; /* set up timing of BOOTCS */ + sc520_mmcr->romcs1ctl = 0x1823; /* set up timing of ROMCS1 */ + sc520_mmcr->romcs2ctl = 0x1823; /* set up timing of ROMCS2 */ /* adjust the memory map: * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM @@ -260,31 +258,31 @@ static void bus_init(void) /* SRAM = GPCS3 128k @ d0000-effff*/ - write_mmcr_long(SC520_PAR2, 0x4e00400d); + sc520_mmcr->par[2] = 0x4e00400d; /* IDE0 = GPCS6 1f0-1f7 */ - write_mmcr_long(SC520_PAR3, 0x380801f0); + sc520_mmcr->par[3] = 0x380801f0; /* IDE1 = GPCS7 3f6 */ - write_mmcr_long(SC520_PAR4, 0x3c0003f6); + sc520_mmcr->par[4] = 0x3c0003f6; /* bootcs */ - write_mmcr_long(SC520_PAR12, 0x8bffe800); + sc520_mmcr->par[12] = 0x8bffe800; /* romcs2 */ - write_mmcr_long(SC520_PAR13, 0xcbfff000); + sc520_mmcr->par[13] = 0xcbfff000; /* romcs1 */ - write_mmcr_long(SC520_PAR14, 0xabfff800); + sc520_mmcr->par[14] = 0xabfff800; /* 680 LEDS */ - write_mmcr_long(SC520_PAR15, 0x30000640); + sc520_mmcr->par[15] = 0x30000640; - write_mmcr_byte(SC520_ADDDECCTL, 0); + sc520_mmcr->adddecctl = 0; asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */ if (CONFIG_SYS_USE_SIO_UART) { - write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) | UART2_DIS|UART1_DIS); + sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | UART2_DIS | UART1_DIS; setup_ali_sio(1); } else { - write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS)); + sc520_mmcr->adddecctl = sc520_mmcr->adddecctl & ~(UART2_DIS|UART1_DIS); setup_ali_sio(0); silence_uart(0x3e8); silence_uart(0x2e8); @@ -352,7 +350,7 @@ u32 isa_map_rom(u32 bus_addr, int size) PRINTF ("setting PAR11 to %x\n", par); /* Map rom 0x10000 with PAR1 */ - write_mmcr_long(SC520_PAR11, par); + sc520_mmcr->par[11] = par; return bus_addr; } @@ -364,8 +362,8 @@ u32 isa_map_rom(u32 bus_addr, int size) void isa_unmap_rom(u32 addr) { PRINTF("isa_unmap_rom asked to unmap %x", addr); - if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) { - write_mmcr_long(SC520_PAR11, 0); + if ((addr>>12) == (sc520_mmcr->par[11] & 0x3ffff)) { + sc520_mmcr->par[11] = 0; PRINTF(" done\n"); return; } @@ -401,7 +399,7 @@ u32 pci_get_rom_window(struct pci_controller *hose, int size) PRINTF ("setting PAR1 to %x\n", par); /* Map rom 0x10000 with PAR1 */ - write_mmcr_long(SC520_PAR1, par); + sc520_mmcr->par[1] = par; return PCI_ROM_TEMP_SPACE; } @@ -414,7 +412,7 @@ void pci_remove_rom_window(struct pci_controller *hose, u32 addr) { PRINTF("pci_remove_rom_window: %x", addr); if (addr == PCI_ROM_TEMP_SPACE) { - write_mmcr_long(SC520_PAR1, 0); + sc520_mmcr->par[1] = 0; PRINTF(" done\n"); return; } @@ -432,11 +430,10 @@ void pci_remove_rom_window(struct pci_controller *hose, u32 addr) int pci_enable_legacy_video_ports(struct pci_controller *hose) { /* Map video memory to 0xa0000*/ - write_mmcr_long(SC520_PAR0, 0x7200400a); + sc520_mmcr->par[0] = 0x7200400a; /* forward all I/O accesses to PCI */ - write_mmcr_byte(SC520_ADDDECCTL, - read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI); + sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | IO_HOLE_DEST_PCI; /* so we map away all io ports to pci (only way to access pci io @@ -446,32 +443,32 @@ int pci_enable_legacy_video_ports(struct pci_controller *hose) */ /* bring 0x100 - 0x1ef back to ISA using PAR5 */ - write_mmcr_long(SC520_PAR5, 0x30ef0100); + sc520_mmcr->par[5] = 0x30ef0100; /* IDE use 1f0-1f7 */ /* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */ - write_mmcr_long(SC520_PAR6, 0x30ff01f8); + sc520_mmcr->par[6] = 0x30ff01f8; /* com2 use 2f8-2ff */ /* bring 0x300 - 0x3af back to ISA using PAR7 */ - write_mmcr_long(SC520_PAR7, 0x30af0300); + sc520_mmcr->par[7] = 0x30af0300; /* vga use 3b0-3bb */ /* bring 0x3bc - 0x3bf back to ISA using PAR8 */ - write_mmcr_long(SC520_PAR8, 0x300303bc); + sc520_mmcr->par[8] = 0x300303bc; /* vga use 3c0-3df */ /* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */ - write_mmcr_long(SC520_PAR9, 0x301503e0); + sc520_mmcr->par[9] = 0x301503e0; /* ide use 3f6 */ /* bring 0x3f7 back to ISA using PAR10 */ - write_mmcr_long(SC520_PAR10, 0x300003f7); + sc520_mmcr->par[10] = 0x300003f7; /* com1 use 3f8-3ff */ @@ -490,12 +487,12 @@ int board_init(void) irq_init(); /* max drive current on SDRAM */ - write_mmcr_word(SC520_DSCTL, 0x0100); + sc520_mmcr->dsctl = 0x0100; /* enter debug mode after next reset (only if jumper is also set) */ - write_mmcr_byte(SC520_RESCFG, 0x08); + sc520_mmcr->rescfg = 0x08; /* configure the software timer to 33.333MHz */ - write_mmcr_byte(SC520_SWTMRCFG, 0); + sc520_mmcr->swtmrcfg = 0; gd->bus_clk = 33333000; return 0; diff --git a/board/sc520_spunk/sc520_spunk.c b/board/sc520_spunk/sc520_spunk.c index 36a0a8ecfc5..dbb5c48d683 100644 --- a/board/sc520_spunk/sc520_spunk.c +++ b/board/sc520_spunk/sc520_spunk.c @@ -47,53 +47,54 @@ DECLARE_GLOBAL_DATA_PTR; static void irq_init(void) { /* disable global interrupt mode */ - write_mmcr_byte(SC520_PICICR, 0x40); + sc520_mmcr->picicr = 0x40; /* set all irqs to edge */ - write_mmcr_byte(SC520_MPICMODE, 0x00); - write_mmcr_byte(SC520_SL1PICMODE, 0x00); - write_mmcr_byte(SC520_SL2PICMODE, 0x00); + sc520_mmcr->pic_mode[0] = 0x00; + sc520_mmcr->pic_mode[1] = 0x00; + sc520_mmcr->pic_mode[2] = 0x00; /* active low polarity on PIC interrupt pins, * active high polarity on all other irq pins */ - write_mmcr_word(SC520_INTPINPOL, 0x0000); + sc520_mmcr->intpinpol = 0x0000; /* set irq number mapping */ - write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED); /* disable GP timer 0 INT */ - write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED); /* disable GP timer 1 INT */ - write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED); /* disable GP timer 2 INT */ - write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0); /* Set PIT timer 0 INT to IRQ0 */ - write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED); /* disable PIT timer 1 INT */ - write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED); /* disable PIT timer 2 INT */ - write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED); /* disable PCI INT A */ - write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED); /* disable PCI INT B */ - write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED); /* disable PCI INT C */ - write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED); /* disable PCI INT D */ - write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */ - write_mmcr_byte(SC520_SSIMAP, SC520_IRQ6); /* Set Synchronius serial INT to IRQ6*/ - write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED); /* disable Watchdog INT */ - write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8); /* Set RTC int to 8 */ - write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED); /* disable write protect INT */ - write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1); /* Set ICE Debug Serielport INT to IRQ1 */ - write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13); /* Set FP error INT to IRQ13 */ + sc520_mmcr->gp_tmr_int_map[0] = SC520_IRQ_DISABLED; /* disable GP timer 0 INT */ + sc520_mmcr->gp_tmr_int_map[1] = SC520_IRQ_DISABLED; /* disable GP timer 1 INT */ + sc520_mmcr->gp_tmr_int_map[2] = SC520_IRQ_DISABLED; /* disable GP timer 2 INT */ + sc520_mmcr->pit_int_map[0] = SC520_IRQ0; /* Set PIT timer 0 INT to IRQ0 */ + sc520_mmcr->pit_int_map[1] = SC520_IRQ_DISABLED; /* disable PIT timer 1 INT */ + sc520_mmcr->pit_int_map[2] = SC520_IRQ_DISABLED; /* disable PIT timer 2 INT */ + sc520_mmcr->pci_int_map[0] = SC520_IRQ_DISABLED; /* disable PCI INT A */ + sc520_mmcr->pci_int_map[1] = SC520_IRQ_DISABLED; /* disable PCI INT B */ + sc520_mmcr->pci_int_map[2] = SC520_IRQ_DISABLED; /* disable PCI INT C */ + sc520_mmcr->pci_int_map[3] = SC520_IRQ_DISABLED; /* disable PCI INT D */ + sc520_mmcr->dmabcintmap = SC520_IRQ_DISABLED; /* disable DMA INT */ + sc520_mmcr->ssimap = SC520_IRQ6; /* Set Synchronius serial INT to IRQ6*/ + sc520_mmcr->wdtmap = SC520_IRQ_DISABLED; /* disable Watchdog INT */ + sc520_mmcr->rtcmap = SC520_IRQ8; /* Set RTC int to 8 */ + sc520_mmcr->wpvmap = SC520_IRQ_DISABLED; /* disable write protect INT */ + sc520_mmcr->icemap = SC520_IRQ1; /* Set ICE Debug Serielport INT to IRQ1 */ + sc520_mmcr->ferrmap = SC520_IRQ13; /* Set FP error INT to IRQ13 */ - write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4); /* Set internal UART2 INT to IRQ4 */ - write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3); /* Set internal UART2 INT to IRQ3 */ - write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ7); /* Set GPIRQ0 (PC-Card AUX IRQ) to IRQ7 */ - write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ14); /* Set GPIRQ1 (CF IRQ) to IRQ14 */ - write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ5); /* Set GPIRQ3 ( CAN IRQ ) ti IRQ5 */ - write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED); /* disbale GIRQ4 ( IRR IRQ ) */ - write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ5 */ - write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ6 */ - write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ7 */ - write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ8 */ - write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ9 */ - write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ2 */ - write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ_DISABLED); /* disable GPIRQ10 */ + sc520_mmcr->uart_int_map[0] = SC520_IRQ4; /* Set internal UART1 INT to IRQ4 */ + sc520_mmcr->uart_int_map[1] = SC520_IRQ3; /* Set internal UART2 INT to IRQ3 */ - write_mmcr_word(SC520_PCIHOSTMAP, 0x11f); /* Map PCI hostbridge INT to NMI */ - write_mmcr_word(SC520_ECCMAP, 0x100); /* Map SDRAM ECC failure INT to NMI */ + sc520_mmcr->gp_int_map[0] = SC520_IRQ7; /* Set GPIRQ0 (PC-Card AUX IRQ) to IRQ7 */ + sc520_mmcr->gp_int_map[1] = SC520_IRQ14; /* Set GPIRQ1 (CF IRQ) to IRQ14 */ + sc520_mmcr->gp_int_map[3] = SC520_IRQ5; /* Set GPIRQ3 ( CAN IRQ ) ti IRQ5 */ + sc520_mmcr->gp_int_map[4] = SC520_IRQ_DISABLED; /* disbale GIRQ4 ( IRR IRQ ) */ + sc520_mmcr->gp_int_map[5] = SC520_IRQ_DISABLED; /* disable GPIRQ5 */ + sc520_mmcr->gp_int_map[6] = SC520_IRQ_DISABLED; /* disable GPIRQ6 */ + sc520_mmcr->gp_int_map[7] = SC520_IRQ_DISABLED; /* disable GPIRQ7 */ + sc520_mmcr->gp_int_map[8] = SC520_IRQ_DISABLED; /* disable GPIRQ8 */ + sc520_mmcr->gp_int_map[9] = SC520_IRQ_DISABLED; /* disable GPIRQ9 */ + sc520_mmcr->gp_int_map[2] = SC520_IRQ_DISABLED; /* disable GPIRQ2 */ + sc520_mmcr->gp_int_map[10] = SC520_IRQ_DISABLED; /* disable GPIRQ10 */ + + sc520_mmcr->pcihostmap = 0x11f; /* Map PCI hostbridge INT to NMI */ + sc520_mmcr->eccmap = 0x100; /* Map SDRAM ECC failure INT to NMI */ } @@ -101,7 +102,7 @@ static void irq_init(void) /* PCI stuff */ static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev) { - int version = read_mmcr_byte(SC520_SYSINFO); + int version = sc520_mmcr->sysinfo; /* a configurable lists of irqs to steal * when we need one (a board with more pci interrupt pins @@ -255,41 +256,41 @@ static void bus_init(void) * ?? Hyglo version 0.97 (small board) * 10 Spunk board */ - int version = read_mmcr_byte(SC520_SYSINFO); + int version = sc520_mmcr->sysinfo; if (version) { /* set up the GP IO pins (for the Spunk board) */ - write_mmcr_word(SC520_PIOPFS31_16, 0xfff0); /* set the GPIO pin function 31-16 reg */ - write_mmcr_word(SC520_PIOPFS15_0, 0x000f); /* set the GPIO pin function 15-0 reg */ - write_mmcr_word(SC520_PIODIR31_16, 0x000f); /* set the GPIO direction 31-16 reg */ - write_mmcr_word(SC520_PIODIR15_0, 0x1ff0); /* set the GPIO direction 15-0 reg */ - write_mmcr_byte(SC520_CSPFS, 0xc0); /* set the CS pin function reg */ - write_mmcr_byte(SC520_CLKSEL, 0x70); + sc520_mmcr->piopfs31_16 = 0xfff0; /* set the GPIO pin function 31-16 reg */ + sc520_mmcr->piopfs15_0 = 0x000f; /* set the GPIO pin function 15-0 reg */ + sc520_mmcr->piodir31_16 = 0x000f; /* set the GPIO direction 31-16 reg */ + sc520_mmcr->piodir15_0 = 0x1ff0; /* set the GPIO direction 15-0 reg */ + sc520_mmcr->cspfs = 0xc0; /* set the CS pin function reg */ + sc520_mmcr->clksel = 0x70; - write_mmcr_word(SC520_PIOCLR31_16, 0x0003); /* reset SSI chip-selects */ - write_mmcr_word(SC520_PIOSET31_16, 0x000c); + sc520_mmcr->pioclr31_16 = 0x0003; /* reset SSI chip-selects */ + sc520_mmcr->pioset31_16 = 0x000c; } else { /* set up the GP IO pins (for the Hyglo board) */ - write_mmcr_word(SC520_PIOPFS31_16, 0xffc0); /* set the GPIO pin function 31-16 reg */ - write_mmcr_word(SC520_PIOPFS15_0, 0x1e7f); /* set the GPIO pin function 15-0 reg */ - write_mmcr_word(SC520_PIODIR31_16, 0x003f); /* set the GPIO direction 31-16 reg */ - write_mmcr_word(SC520_PIODIR15_0, 0xe180); /* set the GPIO direction 15-0 reg */ - write_mmcr_byte(SC520_CSPFS, 0x00); /* set the CS pin function reg */ - write_mmcr_byte(SC520_CLKSEL, 0x70); + sc520_mmcr->piopfs31_16 = 0xffc0; /* set the GPIO pin function 31-16 reg */ + sc520_mmcr->piopfs15_0 = 0x1e7f; /* set the GPIO pin function 15-0 reg */ + sc520_mmcr->piodir31_16 = 0x003f; /* set the GPIO direction 31-16 reg */ + sc520_mmcr->piodir15_0 = 0xe180; /* set the GPIO direction 15-0 reg */ + sc520_mmcr->cspfs = 0x00; /* set the CS pin function reg */ + sc520_mmcr->clksel = 0x70; - write_mmcr_word(SC520_PIOCLR15_0, 0x0180); /* reset SSI chip-selects */ + sc520_mmcr->pioclr15_0 = 0x0180; /* reset SSI chip-selects */ } - write_mmcr_byte(SC520_GPCSRT, 1); /* set the GP CS offset */ - write_mmcr_byte(SC520_GPCSPW, 3); /* set the GP CS pulse width */ - write_mmcr_byte(SC520_GPCSOFF, 1); /* set the GP CS offset */ - write_mmcr_byte(SC520_GPRDW, 3); /* set the RD pulse width */ - write_mmcr_byte(SC520_GPRDOFF, 1); /* set the GP RD offset */ - write_mmcr_byte(SC520_GPWRW, 3); /* set the GP WR pulse width */ - write_mmcr_byte(SC520_GPWROFF, 1); /* set the GP WR offset */ + sc520_mmcr->gpcsrt = 1; /* set the GP CS offset */ + sc520_mmcr->gpcspw = 3; /* set the GP CS pulse width */ + sc520_mmcr->gpcsoff = 1; /* set the GP CS offset */ + sc520_mmcr->gprdw = 3; /* set the RD pulse width */ + sc520_mmcr->gprdoff = 1; /* set the GP RD offset */ + sc520_mmcr->gpwrw = 3; /* set the GP WR pulse width */ + sc520_mmcr->gpwroff = 1; /* set the GP WR offset */ - write_mmcr_word(SC520_BOOTCSCTL, 0x0407); /* set up timing of BOOTCS */ + sc520_mmcr->bootcsctl = 0x0407; /* set up timing of BOOTCS */ /* adjust the memory map: * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM @@ -298,17 +299,17 @@ static void bus_init(void) /* bootcs */ - write_mmcr_long(SC520_PAR12, 0x8bffe800); + sc520_mmcr->par[12] = 0x8bffe800; /* IDE0 = GPCS6 1f0-1f7 */ - write_mmcr_long(SC520_PAR3, 0x380801f0); + sc520_mmcr->par[3] = 0x380801f0; /* IDE1 = GPCS7 3f6 */ - write_mmcr_long(SC520_PAR4, 0x3c0003f6); + sc520_mmcr->par[4] = 0x3c0003f6; asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */ - write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS)); + sc520_mmcr->adddecctl = sc520_mmcr->adddecctl & ~(UART2_DIS|UART1_DIS); } @@ -361,7 +362,7 @@ u32 isa_map_rom(u32 bus_addr, int size) printf ("setting PAR11 to %x\n", par); /* Map rom 0x10000 with PAR1 */ - write_mmcr_long(SC520_PAR11, par); + sc520_mmcr->par[11] = par; return bus_addr; } @@ -373,8 +374,8 @@ u32 isa_map_rom(u32 bus_addr, int size) void isa_unmap_rom(u32 addr) { printf("isa_unmap_rom asked to unmap %x", addr); - if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) { - write_mmcr_long(SC520_PAR11, 0); + if ((addr>>12) == (sc520_mmcr->par[11] & 0x3ffff)) { + sc520_mmcr->par[11] = 0; printf(" done\n"); return; } @@ -410,7 +411,7 @@ u32 pci_get_rom_window(struct pci_controller *hose, int size) printf ("setting PAR1 to %x\n", par); /* Map rom 0x10000 with PAR1 */ - write_mmcr_long(SC520_PAR1, par); + sc520_mmcr->par[1] = par; return PCI_ROM_TEMP_SPACE; } @@ -423,7 +424,7 @@ void pci_remove_rom_window(struct pci_controller *hose, u32 addr) { printf("pci_remove_rom_window: %x", addr); if (addr == PCI_ROM_TEMP_SPACE) { - write_mmcr_long(SC520_PAR1, 0); + sc520_mmcr->par[1] = 0; printf(" done\n"); return; } @@ -441,11 +442,10 @@ void pci_remove_rom_window(struct pci_controller *hose, u32 addr) int pci_enable_legacy_video_ports(struct pci_controller *hose) { /* Map video memory to 0xa0000*/ - write_mmcr_long(SC520_PAR0, 0x7200400a); + sc520_mmcr->par[0] = 0x7200400a; /* forward all I/O accesses to PCI */ - write_mmcr_byte(SC520_ADDDECCTL, - read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI); + sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | IO_HOLE_DEST_PCI; /* so we map away all io ports to pci (only way to access pci io @@ -455,22 +455,22 @@ int pci_enable_legacy_video_ports(struct pci_controller *hose) */ /* bring 0x100 - 0x2f7 back to ISA using PAR5 */ - write_mmcr_long(SC520_PAR5, 0x31f70100); + sc520_mmcr->par[5] = 0x31f70100; /* com2 use 2f8-2ff */ /* bring 0x300 - 0x3af back to ISA using PAR7 */ - write_mmcr_long(SC520_PAR7, 0x30af0300); + sc520_mmcr->par[7] = 0x30af0300; /* vga use 3b0-3bb */ /* bring 0x3bc - 0x3bf back to ISA using PAR8 */ - write_mmcr_long(SC520_PAR8, 0x300303bc); + sc520_mmcr->par[8] = 0x300303bc; /* vga use 3c0-3df */ /* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */ - write_mmcr_long(SC520_PAR9, 0x301703e0); + sc520_mmcr->par[9] = 0x301703e0; /* com1 use 3f8-3ff */ @@ -489,12 +489,12 @@ int board_init(void) irq_init(); /* max drive current on SDRAM */ - write_mmcr_word(SC520_DSCTL, 0x0100); + sc520_mmcr->dsctl = 0x0100; /* enter debug mode after next reset (only if jumper is also set) */ - write_mmcr_byte(SC520_RESCFG, 0x08); + sc520_mmcr->rescfg = 0x08; /* configure the software timer to 33.000MHz */ - write_mmcr_byte(SC520_SWTMRCFG, 1); + sc520_mmcr->swtmrcfg = 1; gd->bus_clk = 33000000; return 0; @@ -508,17 +508,15 @@ int dram_init(void) void show_boot_progress(int val) { - int version = read_mmcr_byte(SC520_SYSINFO); + int version = sc520_mmcr->sysinfo; if (val < -32) val = -1; /* let things compatible */ if (version == 0) { /* PIO31-PIO16 Data */ - write_mmcr_word(SC520_PIODATA31_16, - (read_mmcr_word(SC520_PIODATA31_16) & 0xffc0)| ((val&0x7e)>>1)); /* 0x1f8 >> 3 */ + sc520_mmcr->piodata31_16 = (sc520_mmcr->piodata31_16 & 0xffc0) | ((val&0x7e)>>1); /* 0x1f8 >> 3 */ /* PIO0-PIO15 Data */ - write_mmcr_word(SC520_PIODATA15_0, - (read_mmcr_word(SC520_PIODATA15_0) & 0x1fff)| ((val&0x7)<<13)); + sc520_mmcr->piodata15_0 = (sc520_mmcr->piodata15_0 & 0x1fff)| ((val&0x7)<<13); } else { /* newer boards use PIO4-PIO12 */ /* PIO0-PIO15 Data */ @@ -527,8 +525,7 @@ void show_boot_progress(int val) #else val = (val & 0x007) | ((val & 0x07e) << 2); #endif - write_mmcr_word(SC520_PIODATA15_0, - (read_mmcr_word(SC520_PIODATA15_0) & 0xe00f) | ((val&0x01ff)<<4)); + sc520_mmcr->piodata15_0 = (sc520_mmcr->piodata15_0 & 0xe00f) | ((val&0x01ff)<<4); } } @@ -536,7 +533,7 @@ void show_boot_progress(int val) int last_stage_init(void) { - int version = read_mmcr_byte(SC520_SYSINFO); + int version = sc520_mmcr->sysinfo; printf("Omicron Ceti SC520 Spunk revision %x\n", version); @@ -587,30 +584,30 @@ int last_stage_init(void) void ssi_chip_select(int dev) { - int version = read_mmcr_byte(SC520_SYSINFO); + int version = sc520_mmcr->sysinfo; if (version) { /* Spunk board: EEPROM and CAN are actove-low, TEMP and AUX are active high */ switch (dev) { case 1: /* EEPROM */ - write_mmcr_word(SC520_PIOCLR31_16, 0x0004); + sc520_mmcr->pioclr31_16 = 0x0004; break; case 2: /* Temp Probe */ - write_mmcr_word(SC520_PIOSET31_16, 0x0002); + sc520_mmcr->pioset31_16 = 0x0002; break; case 3: /* CAN */ - write_mmcr_word(SC520_PIOCLR31_16, 0x0008); + sc520_mmcr->pioclr31_16 = 0x0008; break; case 4: /* AUX */ - write_mmcr_word(SC520_PIOSET31_16, 0x0001); + sc520_mmcr->pioset31_16 = 0x0001; break; case 0: - write_mmcr_word(SC520_PIOCLR31_16, 0x0003); - write_mmcr_word(SC520_PIOSET31_16, 0x000c); + sc520_mmcr->pioclr31_16 = 0x0003; + sc520_mmcr->pioset31_16 = 0x000c; break; default: @@ -622,15 +619,15 @@ void ssi_chip_select(int dev) switch (dev) { case 1: /* EEPROM */ - write_mmcr_word(SC520_PIOSET15_0, 0x0100); + sc520_mmcr->pioset15_0 = 0x0100; break; case 2: /* Temp Probe */ - write_mmcr_word(SC520_PIOSET15_0, 0x0080); + sc520_mmcr->pioset15_0 = 0x0080; break; case 0: - write_mmcr_word(SC520_PIOCLR15_0, 0x0180); + sc520_mmcr->pioclr15_0 = 0x0180; break; default: @@ -669,9 +666,7 @@ int mw_eeprom_write(int x, int offset, uchar *buffer, int len) void spi_init_f(void) { - read_mmcr_byte(SC520_SYSINFO) ? - spi_eeprom_probe(1) : - mw_eeprom_probe(1); + sc520_mmcr->sysinfo ? spi_eeprom_probe(1) : mw_eeprom_probe(1); } @@ -686,7 +681,7 @@ ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) offset |= addr[i]; } - return read_mmcr_byte(SC520_SYSINFO) ? + return sc520_mmcr->sysinfo ? spi_eeprom_read(1, offset, buffer, len) : mw_eeprom_read(1, offset, buffer, len); } @@ -702,7 +697,7 @@ ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len) offset |= addr[i]; } - return read_mmcr_byte(SC520_SYSINFO) ? + return sc520_mmcr->sysinfo ? spi_eeprom_write(1, offset, buffer, len) : mw_eeprom_write(1, offset, buffer, len); } diff --git a/cpu/i386/sc520/sc520.c b/cpu/i386/sc520/sc520.c index 1d79210a62f..4b566a75ccd 100644 --- a/cpu/i386/sc520/sc520.c +++ b/cpu/i386/sc520/sc520.c @@ -33,75 +33,35 @@ DECLARE_GLOBAL_DATA_PTR; /* * utility functions for boards based on the AMD sc520 * - * void write_mmcr_byte(u16 mmcr, u8 data) - * void write_mmcr_word(u16 mmcr, u16 data) - * void write_mmcr_long(u16 mmcr, u32 data) - * - * u8 read_mmcr_byte(u16 mmcr) - * u16 read_mmcr_word(u16 mmcr) - * u32 read_mmcr_long(u16 mmcr) - * * void init_sc520(void) * unsigned long init_sc520_dram(void) */ -static u32 mmcr_base= 0xfffef000; - -void write_mmcr_byte(u16 mmcr, u8 data) -{ - writeb(data, mmcr+mmcr_base); -} - -void write_mmcr_word(u16 mmcr, u16 data) -{ - writew(data, mmcr+mmcr_base); -} - -void write_mmcr_long(u16 mmcr, u32 data) -{ - writel(data, mmcr+mmcr_base); -} - -u8 read_mmcr_byte(u16 mmcr) -{ - return readb(mmcr+mmcr_base); -} - -u16 read_mmcr_word(u16 mmcr) -{ - return readw(mmcr+mmcr_base); -} - -u32 read_mmcr_long(u16 mmcr) -{ - return readl(mmcr+mmcr_base); -} - +volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000; void init_sc520(void) { /* Set the UARTxCTL register at it's slower, * baud clock giving us a 1.8432 MHz reference */ - write_mmcr_byte(SC520_UART1CTL, 7); - write_mmcr_byte(SC520_UART2CTL, 7); + sc520_mmcr->uart1ctl = 0x07; + sc520_mmcr->uart2ctl = 0x07; /* first set the timer pin mapping */ - write_mmcr_byte(SC520_CLKSEL, 0x72); /* no clock frequency selected, use 1.1892MHz */ + sc520_mmcr->clksel = 0x72; /* no clock frequency selected, use 1.1892MHz */ /* enable PCI bus arbitrer */ - write_mmcr_byte(SC520_SYSARBCTL,0x02); /* enable concurrent mode */ - - write_mmcr_word(SC520_SYSARBMENB,0x1f); /* enable external grants */ - write_mmcr_word(SC520_HBCTL,0x04); /* enable posted-writes */ + sc520_mmcr->sysarbctl = 0x02; /* enable concurrent mode */ + sc520_mmcr->sysarbmenb = 0x1f; /* enable external grants */ + sc520_mmcr->hbctl = 0x04; /* enable posted-writes */ if (CONFIG_SYS_SC520_HIGH_SPEED) { - write_mmcr_byte(SC520_CPUCTL, 0x2); /* set it to 133 MHz and write back */ + sc520_mmcr->cpuctl = 0x02; /* set it to 133 MHz and write back */ gd->cpu_clk = 133000000; printf("## CPU Speed set to 133MHz\n"); } else { - write_mmcr_byte(SC520_CPUCTL, 1); /* set CPU to 100 MHz and write back cache */ + sc520_mmcr->cpuctl = 0x01; /* set it to 100 MHz and write back */ printf("## CPU Speed set to 100MHz\n"); gd->cpu_clk = 100000000; } @@ -114,7 +74,7 @@ void init_sc520(void) "loop 0b\n": : : "ecx"); /* turn on the SDRAM write buffer */ - write_mmcr_byte(SC520_DBCTL, 0x11); + sc520_mmcr->dbctl = 0x11; /* turn on the cache and disable write through */ asm("movl %%cr0, %%eax\n" @@ -156,10 +116,9 @@ unsigned long init_sc520_dram(void) val = 3; /* 62.4us */ } - write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4)); + sc520_mmcr->drcctl = (sc520_mmcr->drcctl & 0xcf) | (val<<4); - val = read_mmcr_byte(SC520_DRCTMCTL); - val &= 0xf0; + val = sc520_mmcr->drctmctl & 0xf0; if (cas_precharge_delay==3) { val |= 0x04; /* 3T */ @@ -174,12 +133,12 @@ unsigned long init_sc520_dram(void) } else { val |= 1; } - write_mmcr_byte(SC520_DRCTMCTL, val); + sc520_mmcr->drctmctl = val; #endif /* We read-back the configuration of the dram * controller that the assembly code wrote */ - dram_ctrl = read_mmcr_long(SC520_DRCBENDADR); + dram_ctrl = sc520_mmcr->drcbendadr; bd->bi_dram[0].start = 0; if (dram_ctrl & 0x80) { @@ -232,7 +191,7 @@ void reset_cpu(ulong addr) { printf("Resetting using SC520 MMCR\n"); /* Write a '1' to the SYS_RST of the RESCFG MMCR */ - write_mmcr_word(SC520_RESCFG, 0x0001); + sc520_mmcr->rescfg = 0x01; /* NOTREACHED */ } diff --git a/cpu/i386/sc520/sc520_pci.c b/cpu/i386/sc520/sc520_pci.c index 871ad0a7361..f446c6d5927 100644 --- a/cpu/i386/sc520/sc520_pci.c +++ b/cpu/i386/sc520/sc520_pci.c @@ -33,23 +33,23 @@ static struct { u16 level_reg; u8 level_bit; } sc520_irq[] = { - { SC520_IRQ0, SC520_MPICMODE, 0x01 }, - { SC520_IRQ1, SC520_MPICMODE, 0x02 }, - { SC520_IRQ2, SC520_SL1PICMODE, 0x02 }, - { SC520_IRQ3, SC520_MPICMODE, 0x08 }, - { SC520_IRQ4, SC520_MPICMODE, 0x10 }, - { SC520_IRQ5, SC520_MPICMODE, 0x20 }, - { SC520_IRQ6, SC520_MPICMODE, 0x40 }, - { SC520_IRQ7, SC520_MPICMODE, 0x80 }, + { SC520_IRQ0, 0, 0x01 }, + { SC520_IRQ1, 0, 0x02 }, + { SC520_IRQ2, 1, 0x02 }, + { SC520_IRQ3, 0, 0x08 }, + { SC520_IRQ4, 0, 0x10 }, + { SC520_IRQ5, 0, 0x20 }, + { SC520_IRQ6, 0, 0x40 }, + { SC520_IRQ7, 0, 0x80 }, - { SC520_IRQ8, SC520_SL1PICMODE, 0x01 }, - { SC520_IRQ9, SC520_SL1PICMODE, 0x02 }, - { SC520_IRQ10, SC520_SL1PICMODE, 0x04 }, - { SC520_IRQ11, SC520_SL1PICMODE, 0x08 }, - { SC520_IRQ12, SC520_SL1PICMODE, 0x10 }, - { SC520_IRQ13, SC520_SL1PICMODE, 0x20 }, - { SC520_IRQ14, SC520_SL1PICMODE, 0x40 }, - { SC520_IRQ15, SC520_SL1PICMODE, 0x80 } + { SC520_IRQ8, 1, 0x01 }, + { SC520_IRQ9, 1, 0x02 }, + { SC520_IRQ10, 1, 0x04 }, + { SC520_IRQ11, 1, 0x08 }, + { SC520_IRQ12, 1, 0x10 }, + { SC520_IRQ13, 1, 0x20 }, + { SC520_IRQ14, 1, 0x40 }, + { SC520_IRQ15, 1, 0x80 } }; @@ -77,34 +77,34 @@ int pci_sc520_set_irq(int pci_pin, int irq) /* first disable any non-pci interrupt source that use * this level */ - for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) { - if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) { - continue; - } - if (read_mmcr_byte(i) == sc520_irq[irq].priority) { - write_mmcr_byte(i, SC520_IRQ_DISABLED); - } + + /* PCI interrupt mapping (A through D)*/ + for (i=0; i<=3 ;i++) { + if (sc520_mmcr->pci_int_map[i] == sc520_irq[irq].priority) + sc520_mmcr->pci_int_map[i] = SC520_IRQ_DISABLED; + } + + /* GP IRQ interrupt mapping */ + for (i=0; i<=10 ;i++) { + if (sc520_mmcr->gp_int_map[i] == sc520_irq[irq].priority) + sc520_mmcr->gp_int_map[i] = SC520_IRQ_DISABLED; } /* Set the trigger to level */ - write_mmcr_byte(sc520_irq[irq].level_reg, - read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit); + sc520_mmcr->pic_mode[sc520_irq[irq].level_reg] = + sc520_mmcr->pic_mode[sc520_irq[irq].level_reg] | sc520_irq[irq].level_bit; if (pci_pin < 4) { /* PCI INTA-INTD */ /* route the interrupt */ - write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority); - - + sc520_mmcr->pci_int_map[pci_pin] = sc520_irq[irq].priority; } else { /* GPIRQ0-GPIRQ10 used for additional PCI INTS */ - write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority); + sc520_mmcr->gp_int_map[pci_pin - 4] = sc520_irq[irq].priority; /* also set the polarity in this case */ - write_mmcr_word(SC520_INTPINPOL, - read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4))); - + sc520_mmcr->intpinpol = sc520_mmcr->intpinpol | (1 << (pci_pin-4)); } /* register the pin */ diff --git a/cpu/i386/sc520/sc520_ssi.c b/cpu/i386/sc520/sc520_ssi.c index dd667ca8cbb..8dbe17aa60e 100644 --- a/cpu/i386/sc520/sc520_ssi.c +++ b/cpu/i386/sc520/sc520_ssi.c @@ -61,32 +61,34 @@ int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase) temp |= PHS_INV_ENB; } - write_mmcr_byte(SC520_SSICTL, temp); + sc520_mmcr->ssictl = temp; return 0; } u8 ssi_txrx_byte(u8 data) { - write_mmcr_byte(SC520_SSIXMIT, data); - while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); - write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMITRCV); - while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); - return read_mmcr_byte(SC520_SSIRCV); + sc520_mmcr->ssixmit = data; + while (sc520_mmcr->ssista & SSISTA_BSY); + sc520_mmcr->ssicmd = SSICMD_CMD_SEL_XMITRCV; + while (sc520_mmcr->ssista & SSISTA_BSY); + + return sc520_mmcr->ssircv; } void ssi_tx_byte(u8 data) { - write_mmcr_byte(SC520_SSIXMIT, data); - while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); - write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMIT); + sc520_mmcr->ssixmit = data; + while (sc520_mmcr->ssista & SSISTA_BSY); + sc520_mmcr->ssicmd = SSICMD_CMD_SEL_XMIT; } u8 ssi_rx_byte(void) { - while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); - write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_RCV); - while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); - return read_mmcr_byte(SC520_SSIRCV); + while (sc520_mmcr->ssista & SSISTA_BSY); + sc520_mmcr->ssicmd = SSICMD_CMD_SEL_RCV; + while (sc520_mmcr->ssista & SSISTA_BSY); + + return sc520_mmcr->ssircv; } diff --git a/cpu/i386/sc520/sc520_timer.c b/cpu/i386/sc520/sc520_timer.c index 2a3425b6167..23de14bdd81 100644 --- a/cpu/i386/sc520/sc520_timer.c +++ b/cpu/i386/sc520/sc520_timer.c @@ -30,29 +30,29 @@ void sc520_timer_isr(void) { /* Ack the GP Timer Interrupt */ - write_mmcr_byte (SC520_GPTMRSTA, 0x02); + sc520_mmcr->gptmrsta = 0x02; } int timer_init(void) { /* Map GP Timer 1 to Master PIC IR0 */ - write_mmcr_byte (SC520_GPTMR1MAP, 0x01); + sc520_mmcr->gp_tmr_int_map[1] = 0x01; /* Disable GP Timers 1 & 2 - Allow configuration writes */ - write_mmcr_word (SC520_GPTMR1CTL, 0x4000); - write_mmcr_word (SC520_GPTMR2CTL, 0x4000); + sc520_mmcr->gptmr1ctl = 0x4000; + sc520_mmcr->gptmr2ctl = 0x4000; /* Reset GP Timers 1 & 2 */ - write_mmcr_word (SC520_GPTMR1CNT, 0x0000); - write_mmcr_word (SC520_GPTMR2CNT, 0x0000); + sc520_mmcr->gptmr1cnt = 0x0000; + sc520_mmcr->gptmr2cnt = 0x0000; /* Setup GP Timer 2 as a 100kHz (10us) prescaler */ - write_mmcr_word (SC520_GPTMR2MAXCMPA, 83); - write_mmcr_word (SC520_GPTMR2CTL, 0xc001); + sc520_mmcr->gptmr2maxcmpa = 83; + sc520_mmcr->gptmr2ctl = 0xc001; /* Setup GP Timer 1 as a 1000 Hz (1ms) interrupt generator */ - write_mmcr_word (SC520_GPTMR1MAXCMPA, 100); - write_mmcr_word (SC520_GPTMR1CTL, 0xe009); + sc520_mmcr->gptmr1maxcmpa = 100; + sc520_mmcr->gptmr1ctl = 0xe009; /* Register the SC520 specific timer interrupt handler */ register_timer_isr (sc520_timer_isr); @@ -62,7 +62,7 @@ int timer_init(void) unmask_irq (0); /* Clear the GP Timer 1 status register to get the show rolling*/ - write_mmcr_byte (SC520_GPTMRSTA, 0x02); + sc520_mmcr->gptmrsta = 0x02; return 0; } @@ -71,12 +71,13 @@ void udelay(unsigned long usec) { int m = 0; long u; + long temp; - read_mmcr_word (SC520_SWTMRMILLI); - read_mmcr_word (SC520_SWTMRMICRO); + temp = sc520_mmcr->swtmrmilli; + temp = sc520_mmcr->swtmrmicro; do { - m += read_mmcr_word (SC520_SWTMRMILLI); - u = read_mmcr_word (SC520_SWTMRMICRO) + (m * 1000); + m += sc520_mmcr->swtmrmilli; + u = sc520_mmcr->swtmrmicro + (m * 1000); } while (u < usec); } diff --git a/include/asm-i386/ic/sc520.h b/include/asm-i386/ic/sc520.h index bf395166512..57c99044224 100644 --- a/include/asm-i386/ic/sc520.h +++ b/include/asm-i386/ic/sc520.h @@ -24,179 +24,243 @@ #ifndef _ASM_IC_SC520_H_ #define _ASM_IC_SC520_H_ 1 -/* Memory mapped configuration registers, MMCR */ -#define SC520_REVID 0x0000 /* ElanSC520 Microcontroller Revision ID Register */ -#define SC520_CPUCTL 0x0002 /* Am5x86 CPU Control Register */ -#define SC520_DRCCTL 0x0010 /* SDRAM Control Register */ -#define SC520_DRCTMCTL 0x0012 /* SDRAM Timing Control Register */ -#define SC520_DRCCFG 0x0014 /* SDRAM Bank Configuration Register*/ -#define SC520_DRCBENDADR 0x0018 /* SDRAM Bank 0-3 Ending Address Register*/ -#define SC520_ECCCTL 0x0020 /* ECC Control Register */ -#define SC520_ECCSTA 0x0021 /* ECC Status Register */ -#define SC520_ECCCKBPOS 0x0022 /* ECC Check Bit Position Register */ -#define SC520_ECCSBADD 0x0024 /* ECC Single-Bit Error Address Register */ +#ifndef __ASSEMBLY__ + +void init_sc520(void); +unsigned long init_sc520_dram(void); + +/* Memory mapped configuration registers */ +typedef struct sc520_mmcr { + u16 revid; /* ElanSC520 microcontroller revision id */ + u8 cpuctl; /* am5x86 CPU control */ + + u8 pad_0x003[0x0d]; + + u8 drcctl; /* SDRAM control */ + u8 pad_0x011[0x01]; + u8 drctmctl; /* SDRAM timing control */ + u8 pad_0x013[0x01]; + u16 drccfg; /* SDRAM bank configuration*/ + u8 pad_0x016[0x02]; + u32 drcbendadr; /* SDRAM bank 0-3 ending address*/ + u8 pad_0x01c[0x04]; + u8 eccctl; /* ECC control */ + u8 eccsta; /* ECC status */ + u8 eccckbpos; /* ECC check bit position */ + u8 ecccktest; /* ECC Check Code Test */ + u32 eccsbadd; /* ECC single-bit error address */ + u32 eccmbadd; /* ECC multi-bit error address */ + + u8 pad_0x02c[0x14]; + + u8 dbctl; /* SDRAM buffer control */ + + u8 pad_0x041[0x0f]; + + u16 bootcsctl; /* /BOOTCS control */ + u8 pad_0x052[0x02]; + u16 romcs1ctl; /* /ROMCS1 control */ + u16 romcs2ctl; /* /ROMCS2 control */ + + u8 pad_0x058[0x08]; + + u16 hbctl; /* host bridge control */ + u16 hbtgtirqctl; /* host bridge target interrupt control */ + u16 hbtgtirqsta; /* host bridge target interrupt status */ + u16 hbmstirqctl; /* host bridge target interrupt control */ + u16 hbmstirqsta; /* host bridge master interrupt status */ + u8 pad_0x06a[0x02]; + u32 mstintadd; /* host bridge master interrupt address */ + + u8 sysarbctl; /* system arbiter control */ + u8 pciarbsta; /* PCI bus arbiter status */ + u16 sysarbmenb; /* system arbiter master enable */ + u32 arbprictl; /* arbiter priority control */ + + u8 pad_0x078[0x08]; + + u8 adddecctl; /* address decode control */ + u8 pad_0x081[0x01]; + u16 wpvsta; /* write-protect violation status */ + u8 pad_0x084[0x04]; + u32 par[16]; /* programmable address regions */ + + u8 pad_0x0c8[0x0b38]; + + u8 gpecho; /* GP echo mode */ + u8 gpcsdw; /* GP chip select data width */ + u16 gpcsqual; /* GP chip select qualification */ + u8 pad_0xc04[0x4]; + u8 gpcsrt; /* GP chip select recovery time */ + u8 gpcspw; /* GP chip select pulse width */ + u8 gpcsoff; /* GP chip select offset */ + u8 gprdw; /* GP read pulse width */ + u8 gprdoff; /* GP read offset */ + u8 gpwrw; /* GP write pulse width */ + u8 gpwroff; /* GP write offset */ + u8 gpalew; /* GP ale pulse width */ + u8 gpaleoff; /* GP ale offset */ + + u8 pad_0xc11[0x0f]; + + u16 piopfs15_0; /* PIO15-PIO0 pin function select */ + u16 piopfs31_16; /* PIO31-PIO16 pin function select */ + u8 cspfs; /* chip select pin function select */ + u8 pad_0xc25[0x01]; + u8 clksel; /* clock select */ + u8 pad_0xc27[0x01]; + u16 dsctl; /* drive strength control */ + u16 piodir15_0; /* PIO15-PIO0 direction */ + u16 piodir31_16; /* PIO31-PIO16 direction */ + u8 pad_0xc2e[0x02]; + u16 piodata15_0 ; /* PIO15-PIO0 data */ + u16 piodata31_16; /* PIO31-PIO16 data */ + u16 pioset15_0; /* PIO15-PIO0 set */ + u16 pioset31_16; /* PIO31-PIO16 set */ + u16 pioclr15_0; /* PIO15-PIO0 clear */ + u16 pioclr31_16; /* PIO31-PIO16 clear */ + + u8 pad_0xc3c[0x24]; + + u16 swtmrmilli; /* software timer millisecond count */ + u16 swtmrmicro; /* software timer microsecond count */ + u8 swtmrcfg; /* software timer configuration */ + + u8 pad_0xc65[0x0b]; + + u8 gptmrsta; /* GP timers status register */ + u8 pad_0xc71; + u16 gptmr0ctl; /* GP timer 0 mode/control */ + u16 gptmr0cnt; /* GP timer 0 count */ + u16 gptmr0maxcmpa; /* GP timer 0 maxcount compare A */ + u16 gptmr0maxcmpb; /* GP timer 0 maxcount compare B */ + u16 gptmr1ctl; /* GP timer 1 mode/control */ + u16 gptmr1cnt; /* GP timer 1 count */ + u16 gptmr1maxcmpa; /* GP timer 1 maxcount compare A */ + u16 gptmr1maxcmpb; /* GP timer 1 maxcount compare B*/ + u16 gptmr2ctl; /* GP timer 2 mode/control */ + u16 gptmr2cnt; /* GP timer 2 count */ + u8 pad_0xc86[0x08]; + u16 gptmr2maxcmpa; /* GP timer 2 maxcount compare A */ + + u8 pad_0xc90[0x20]; + + u16 wdtmrctl; /* watchdog timer control */ + u16 wdtmrcntl; /* watchdog timer count low */ + u16 wdtmrcnth; /* watchdog timer count high */ + + u8 pad_0xcb6[0x0a]; + + u8 uart1ctl; /* UART 1 general control */ + u8 uart1sta; /* UART 1 general status */ + u8 uart1fcrshad; /* UART 1 FIFO control shadow */ + u8 pad_0xcc3[0x01]; + u8 uart2ctl; /* UART 2 general control */ + u8 uart2sta; /* UART 2 general status */ + u8 uart2fcrshad; /* UART 2 FIFO control shadow */ + + u8 pad_0xcc7[0x09]; + + u8 ssictl; /* SSI control */ + u8 ssixmit; /* SSI transmit */ + u8 ssicmd; /* SSI command */ + u8 ssista; /* SSI status */ + u8 ssircv; /* SSI receive */ + + u8 pad_0xcd5[0x2b]; + + u8 picicr; /* interrupt control */ + u8 pad_0xd01[0x01]; + u8 pic_mode[3]; /* PIC interrupt mode */ + u8 pad_0xd05[0x03]; + u16 swint16_1; /* software interrupt 16-1 control */ + u8 swint22_17; /* software interrupt 22-17/NMI control */ + u8 pad_0xd0b[0x05]; + u16 intpinpol; /* interrupt pin polarity */ + u8 pad_0xd12[0x02]; + u16 pcihostmap; /* PCI host bridge interrupt mapping */ + u8 pad_0xd16[0x02]; + u16 eccmap; /* ECC interrupt mapping */ + u8 gp_tmr_int_map[3]; /* GP timer interrupt mapping */ + u8 pad_0xd1d[0x03]; + u8 pit_int_map[3]; /* PIT interrupt mapping */ + u8 pad_0xd23[0x05]; + u8 uart_int_map[2]; /* UART interrupt mapping */ + u8 pad_0xd2a[0x06]; + u8 pci_int_map[4]; /* PCI interrupt mapping (A through D)*/ + u8 pad_0xd34[0x0c]; + u8 dmabcintmap; /* DMA buffer chaining interrupt mapping */ + u8 ssimap; /* SSI interrupt mapping register */ + u8 wdtmap; /* watchdog timer interrupt mapping */ + u8 rtcmap; /* RTC interrupt mapping register */ + u8 wpvmap; /* write-protect interrupt mapping */ + u8 icemap; /* AMDebug JTAG Rx/Tx interrupt mapping */ + u8 ferrmap; /* floating point error interrupt mapping */ + u8 pad_0xd47[0x09]; + u8 gp_int_map[11]; /* GP IRQ interrupt mapping */ + + u8 pad_0xd5b[0x15]; + + u8 sysinfo; /* system board information */ + u8 pad_0xd71[0x01]; + u8 rescfg; /* reset configuration */ + u8 pad_0xd73[0x01]; + u8 ressta; /* reset status */ + + u8 pad_0xd75[0x0b]; + + u8 gpdmactl; /* GP-DMA Control */ + u8 gpdmammio; /* GP-DMA memory-mapped I/O */ + u16 gpdmaextchmapa; /* GP-DMA resource channel map a */ + u16 gpdmaextchmapb; /* GP-DMA resource channel map b */ + u8 gp_dma_ext_pg_0; /* GP-DMA channel extended page 0 */ + u8 gp_dma_ext_pg_1; /* GP-DMA channel extended page 0 */ + u8 gp_dma_ext_pg_2; /* GP-DMA channel extended page 0 */ + u8 gp_dma_ext_pg_3; /* GP-DMA channel extended page 0 */ + u8 gp_dma_ext_pg_5; /* GP-DMA channel extended page 0 */ + u8 gp_dma_ext_pg_6; /* GP-DMA channel extended page 0 */ + u8 gp_dma_ext_pg_7; /* GP-DMA channel extended page 0 */ + u8 pad_0xd8d[0x03]; + u8 gpdmaexttc3; /* GP-DMA channel 3 extender transfer count */ + u8 gpdmaexttc5; /* GP-DMA channel 5 extender transfer count */ + u8 gpdmaexttc6; /* GP-DMA channel 6 extender transfer count */ + u8 gpdmaexttc7; /* GP-DMA channel 7 extender transfer count */ + u8 pad_0xd94[0x4]; + u8 gpdmabcctl; /* buffer chaining control */ + u8 gpdmabcsta; /* buffer chaining status */ + u8 gpdmabsintenb; /* buffer chaining interrupt enable */ + u8 gpdmabcval; /* buffer chaining valid */ + u8 pad_0xd9c[0x04]; + u16 gpdmanxtaddl3; /* GP-DMA channel 3 next address low */ + u16 gpdmanxtaddh3; /* GP-DMA channel 3 next address high */ + u16 gpdmanxtaddl5; /* GP-DMA channel 5 next address low */ + u16 gpdmanxtaddh5; /* GP-DMA channel 5 next address high */ + u16 gpdmanxtaddl6; /* GP-DMA channel 6 next address low */ + u16 gpdmanxtaddh6; /* GP-DMA channel 6 next address high */ + u16 gpdmanxtaddl7; /* GP-DMA channel 7 next address low */ + u16 gpdmanxtaddh7; /* GP-DMA channel 7 next address high */ + u16 gpdmanxttcl3; /* GP-DMA channel 3 next transfer count low */ + u16 gpdmanxttch3; /* GP-DMA channel 3 next transfer count high */ + u16 gpdmanxttcl5; /* GP-DMA channel 5 next transfer count low */ + u16 gpdmanxttch5; /* GP-DMA channel 5 next transfer count high */ + u16 gpdmanxttcl6; /* GP-DMA channel 6 next transfer count low */ + u16 gpdmanxttch6; /* GP-DMA channel 6 next transfer count high */ + u16 gpdmanxttcl7; /* GP-DMA channel 7 next transfer count low */ + u16 gpdmanxttch7; /* GP-DMA channel 7 next transfer count high */ + + u8 pad_0xdc0[0x0240]; +} sc520_mmcr_t; + +extern volatile sc520_mmcr_t *sc520_mmcr; + +#endif + +/* MMCR Offsets (required for assembler code */ #define SC520_DBCTL 0x0040 /* SDRAM Buffer Control Register */ -#define SC520_BOOTCSCTL 0x0050 /* /BOOTCS Control Register */ -#define SC520_ROMCS1CTL 0x0054 /* /ROMCS1 Control Register */ -#define SC520_ROMCS2CTL 0x0056 /* /ROMCS2 Control Register */ -#define SC520_HBCTL 0x0060 /* Host Bridge Control Register */ -#define SC520_HBTGTIRQCTL 0x0062 /* Host Bridge Target Interrupt Control Register */ -#define SC520_HBTGTIRQSTA 0x0064 /* Host Bridge Target Interrupt Status Register */ -#define SC520_HBMSTIRQCTL 0x0066 /* Host Bridge Target Interrupt Control Register */ -#define SC520_HBMSTIRQSTA 0x0068 /* Host Bridge Master Interrupt Status Register */ -#define SC520_MSTINTADD 0x006c /* Host Bridge Master Interrupt Address Register */ -#define SC520_SYSARBCTL 0x0070 /* System Arbiter Control Register */ -#define SC520_PCIARBSTA 0x0071 /* PCI Bus Arbiter Status Register */ -#define SC520_SYSARBMENB 0x0072 /* System Arbiter Master Enable Register */ -#define SC520_ARBPRICTL 0x0074 /* Arbiter Priority Control Register */ -#define SC520_ADDDECCTL 0x0080 /* Address Decode Control Register */ -#define SC520_WPVSTA 0x0082 /* Write-Protect Violation Status Register */ -#define SC520_PAR0 0x0088 /* Programmable Address Region 0 Register */ -#define SC520_PAR1 0x008c /* Programmable Address Region 1 Register */ -#define SC520_PAR2 0x0090 /* Programmable Address Region 2 Register */ -#define SC520_PAR3 0x0094 /* Programmable Address Region 3 Register */ -#define SC520_PAR4 0x0098 /* Programmable Address Region 4 Register */ -#define SC520_PAR5 0x009c /* Programmable Address Region 5 Register */ -#define SC520_PAR6 0x00a0 /* Programmable Address Region 6 Register */ -#define SC520_PAR7 0x00a4 /* Programmable Address Region 7 Register */ -#define SC520_PAR8 0x00a8 /* Programmable Address Region 8 Register */ -#define SC520_PAR9 0x00ac /* Programmable Address Region 9 Register */ -#define SC520_PAR10 0x00b0 /* Programmable Address Region 10 Register */ -#define SC520_PAR11 0x00b4 /* Programmable Address Region 11 Register */ -#define SC520_PAR12 0x00b8 /* Programmable Address Region 12 Register */ -#define SC520_PAR13 0x00bc /* Programmable Address Region 13 Register */ #define SC520_PAR14 0x00c0 /* Programmable Address Region 14 Register */ #define SC520_PAR15 0x00c4 /* Programmable Address Region 15 Register */ -#define SC520_GPECHO 0x0c00 /* GP Echo Mode Register */ -#define SC520_GPCSDW 0x0c01 /* GP Chip Select Data Width Register */ -#define SC520_GPCSQUAL 0x0c02 /* GP Chip Select Qualification Register */ -#define SC520_GPCSRT 0x0c08 /* GP Chip Select Recovery Time Register */ -#define SC520_GPCSPW 0x0c09 /* GP Chip Select Pulse Width Register */ -#define SC520_GPCSOFF 0x0c0a /* GP Chip Select Offset Register */ -#define SC520_GPRDW 0x0c0b /* GP Read Pulse Width Register */ -#define SC520_GPRDOFF 0x0c0c /* GP Read Offset Register */ -#define SC520_GPWRW 0x0c0d /* GP Write Pulse Width Register */ -#define SC520_GPWROFF 0x0c0e /* GP Write Offset Register */ -#define SC520_GPALEW 0x0c0f /* GP ALE Pulse Width Register */ -#define SC520_GPALEOFF 0x0c10 /* GP ALE Offset Register */ -#define SC520_PIOPFS15_0 0x0c20 /* PIO15-PIO0 Pin Function Select */ -#define SC520_PIOPFS31_16 0x0c22 /* PIO31-PIO16 Pin Function Select */ -#define SC520_CSPFS 0x0c24 /* Chip Select Pin Function Select */ -#define SC520_CLKSEL 0x0c26 /* Clock Select */ -#define SC520_DSCTL 0x0c28 /* Drive Strength Control */ -#define SC520_PIODIR15_0 0x0c2a /* PIO15-PIO0 Direction */ -#define SC520_PIODIR31_16 0x0c2c /* PIO31-PIO16 Direction */ -#define SC520_PIODATA15_0 0x0c30 /* PIO15-PIO0 Data */ -#define SC520_PIODATA31_16 0x0c32 /* PIO31-PIO16 Data */ -#define SC520_PIOSET15_0 0x0c34 /* PIO15-PIO0 Set */ -#define SC520_PIOSET31_16 0x0c36 /* PIO31-PIO16 Set */ -#define SC520_PIOCLR15_0 0x0c38 /* PIO15-PIO0 Clear */ -#define SC520_PIOCLR31_16 0x0c3a /* PIO31-PIO16 Clear */ -#define SC520_SWTMRMILLI 0x0c60 /* Software Timer Millisecond Count */ -#define SC520_SWTMRMICRO 0x0c62 /* Software Timer Microsecond Count */ -#define SC520_SWTMRCFG 0x0c64 /* Software Timer Configuration */ -#define SC520_GPTMRSTA 0x0c70 /* GP Timers Status Register */ -#define SC520_GPTMR0CTL 0x0c72 /* GP Timer 0 Mode/Control Register */ -#define SC520_GPTMR0CNT 0x0c74 /* GP Timer 0 Count Register */ -#define SC520_GPTMR0MAXCMPA 0x0c76 /* GP Timer 0 Maxcount Compare A Register */ -#define SC520_GPTMR0MAXCMPB 0x0c78 /* GP Timer 0 Maxcount Compare B Register */ -#define SC520_GPTMR1CTL 0x0c7a /* GP Timer 1 Mode/Control Register */ -#define SC520_GPTMR1CNT 0x0c7c /* GP Timer 1 Count Register */ -#define SC520_GPTMR1MAXCMPA 0x0c7e /* GP Timer 1 Maxcount Compare Register A */ -#define SC520_GPTMR1MAXCMPB 0x0c80 /* GP Timer 1 Maxcount Compare B Register */ -#define SC520_GPTMR2CTL 0x0c82 /* GP Timer 2 Mode/Control Register */ -#define SC520_GPTMR2CNT 0x0c84 /* GP Timer 2 Count Register */ -#define SC520_GPTMR2MAXCMPA 0x0c8e /* GP Timer 2 Maxcount Compare A Register */ -#define SC520_WDTMRCTL 0x0cb0 /* Watchdog Timer Control Register */ -#define SC520_WDTMRCNTL 0x0cb2 /* Watchdog Timer Count Low Register */ -#define SC520_WDTMRCNTH 0x0cb4 /* Watchdog Timer Count High Register */ -#define SC520_UART1CTL 0x0cc0 /* UART 1 General Control Register */ -#define SC520_UART1STA 0x0cc1 /* UART 1 General Status Register */ -#define SC520_UART1FCRSHAD 0x0cc2 /* UART 1 FIFO Control Shadow Register */ -#define SC520_UART2CTL 0x0cc4 /* UART 2 General Control Register */ -#define SC520_UART2STA 0x0cc5 /* UART 2 General Status Register */ -#define SC520_UART2FCRSHAD 0x0cc6 /* UART 2 FIFO Control Shadow Register */ -#define SC520_SSICTL 0x0cd0 /* SSI Control */ -#define SC520_SSIXMIT 0x0cd1 /* SSI Transmit */ -#define SC520_SSICMD 0x0cd2 /* SSI Command */ -#define SC520_SSISTA 0x0cd3 /* SSI Status */ -#define SC520_SSIRCV 0x0cd4 /* SSI Receive */ -#define SC520_PICICR 0x0d00 /* Interrupt Control Register */ -#define SC520_MPICMODE 0x0d02 /* Master PIC Interrupt Mode Register */ -#define SC520_SL1PICMODE 0x0d03 /* Slave 1 PIC Interrupt Mode Register */ -#define SC520_SL2PICMODE 0x0d04 /* Slave 2 PIC Interrupt Mode Register */ -#define SC520_SWINT16_1 0x0d08 /* Software Interrupt 16-1 Control Register */ -#define SC520_SWINT22_17 0x0d0a /* Software Interrupt 22-17/NMI Control Register */ -#define SC520_INTPINPOL 0x0d10 /* Interrupt Pin Polarity Register */ -#define SC520_PCIHOSTMAP 0x0d14 /* PCI Host Bridge Interrupt Mappin Register */ -#define SC520_ECCMAP 0x0d18 /* ECC Interrupt Mapping Register */ -#define SC520_GPTMR0MAP 0x0d1a /* GP Timer 0 Interrupt Mapping Register */ -#define SC520_GPTMR1MAP 0x0d1b /* GP Timer 1 Interrupt Mapping Register */ -#define SC520_GPTMR2MAP 0x0d1c /* GP Timer 2 Interrupt Mapping Register */ -#define SC520_PIT0MAP 0x0d20 /* PIT0 Interrupt Mapping Register */ -#define SC520_PIT1MAP 0x0d21 /* PIT1 Interrupt Mapping Register */ -#define SC520_PIT2MAP 0x0d22 /* PIT2 Interrupt Mapping Register */ -#define SC520_UART1MAP 0x0d28 /* UART 1 Interrupt Mapping Register */ -#define SC520_UART2MAP 0x0d29 /* UART 2 Interrupt Mapping Register */ -#define SC520_PCIINTAMAP 0x0d30 /* PCI Interrupt A Mapping Register */ -#define SC520_PCIINTBMAP 0x0d31 /* PCI Interrupt B Mapping Register */ -#define SC520_PCIINTCMAP 0x0d32 /* PCI Interrupt C Mapping Register */ -#define SC520_PCIINTDMAP 0x0d33 /* PCI Interrupt D Mapping Register */ -#define SC520_DMABCINTMAP 0x0d40 /* DMA Buffer Chaining Interrupt Mapping Register */ -#define SC520_SSIMAP 0x0d41 /* SSI Interrupt Mapping Register */ -#define SC520_WDTMAP 0x0d42 /* Watchdog Timer Interrupt Mapping Register */ -#define SC520_RTCMAP 0x0d43 /* RTC Interrupt Mapping Register */ -#define SC520_WPVMAP 0x0d44 /* Write-Protect Interrupt Mapping Register */ -#define SC520_ICEMAP 0x0d45 /* AMDebug JTAG RX/TX Interrupt Mapping Register */ -#define SC520_FERRMAP 0x0d46 /* Floating Point Error Interrupt Mapping Register */ -#define SC520_GP0IMAP 0x0d50 /* GPIRQ0 Interrupt Mapping Register */ -#define SC520_GP1IMAP 0x0d51 /* GPIRQ1 Interrupt Mapping Register */ -#define SC520_GP2IMAP 0x0d52 /* GPIRQ2 Interrupt Mapping Register */ -#define SC520_GP3IMAP 0x0d53 /* GPIRQ3 Interrupt Mapping Register */ -#define SC520_GP4IMAP 0x0d54 /* GPIRQ4 Interrupt Mapping Register */ -#define SC520_GP5IMAP 0x0d55 /* GPIRQ5 Interrupt Mapping Register */ -#define SC520_GP6IMAP 0x0d56 /* GPIRQ6 Interrupt Mapping Register */ -#define SC520_GP7IMAP 0x0d57 /* GPIRQ7 Interrupt Mapping Register */ -#define SC520_GP8IMAP 0x0d58 /* GPIRQ8 Interrupt Mapping Register */ -#define SC520_GP9IMAP 0x0d59 /* GPIRQ9 Interrupt Mapping Register */ -#define SC520_GP10IMAP 0x0d5a /* GPIRQ10 Interrupt Mapping Register */ -#define SC520_SYSINFO 0x0d70 /* System Board Information Register */ -#define SC520_RESCFG 0x0d72 /* Reset Configuration Register */ -#define SC520_RESSTA 0x0d74 /* Reset Status Register */ -#define SC520_GPDMAMMIO 0x0d81 /* GP-DMA Memory-Mapped I/O Register */ -#define SC520_GPDMAEXTCHMAPA 0x0d82 /* GP-DMA Resource Channel Map A */ -#define SC520_GPDMAEXTCHMAPB 0x0d84 /* GP-DMA Resource Channel Map B */ -#define SC520_GPDMAEXTPG0 0x0d86 /* GP-DMA Channel 0 Extended Page */ -#define SC520_GPDMAEXTPG1 0x0d87 /* GP-DMA Channel 1 Extended Page */ -#define SC520_GPDMAEXTPG2 0x0d88 /* GP-DMA Channel 2 Extended Page */ -#define SC520_GPDMAEXTPG3 0x0d89 /* GP-DMA Channel 3 Extended Page */ -#define SC520_GPDMAEXTPG5 0x0d8a /* GP-DMA Channel 5 Extended Page */ -#define SC520_GPDMAEXTPG6 0x0d8b /* GP-DMA Channel 6 Extended Page */ -#define SC520_GPDMAEXTPG7 0x0d8c /* GP-DMA Channel 7 Extended Page */ -#define SC520_GPDMAEXTTC3 0x0d90 /* GP-DMA Channel 3 Extender Transfer count */ -#define SC520_GPDMAEXTTC5 0x0d91 /* GP-DMA Channel 5 Extender Transfer count */ -#define SC520_GPDMAEXTTC6 0x0d92 /* GP-DMA Channel 6 Extender Transfer count */ -#define SC520_GPDMAEXTTC7 0x0d93 /* GP-DMA Channel 7 Extender Transfer count */ -#define SC520_GPDMABCCTL 0x0d98 /* Buffer Chaining Control */ -#define SC520_GPDMABCSTA 0x0d99 /* Buffer Chaining Status */ -#define SC520_GPDMABSINTENB 0x0d9a /* Buffer Chaining Interrupt Enable */ -#define SC520_GPDMABCVAL 0x0d9b /* Buffer Chaining Valid */ -#define SC520_GPDMANXTADDL3 0x0da0 /* GP-DMA Channel 3 Next Address Low */ -#define SC520_GPDMANXTADDH3 0x0da2 /* GP-DMA Channel 3 Next Address High */ -#define SC520_GPDMANXTADDL5 0x0da4 /* GP-DMA Channel 5 Next Address Low */ -#define SC520_GPDMANXTADDH5 0x0da6 /* GP-DMA Channel 5 Next Address High */ -#define SC520_GPDMANXTADDL6 0x0da8 /* GP-DMA Channel 6 Next Address Low */ -#define SC520_GPDMANXTADDH6 0x0daa /* GP-DMA Channel 6 Next Address High */ -#define SC520_GPDMANXTADDL7 0x0dac /* GP-DMA Channel 7 Next Address Low */ -#define SC520_GPDMANXTADDH7 0x0dae /* GP-DMA Channel 7 Next Address High */ -#define SC520_GPDMANXTTCL3 0x0db0 /* GP-DMA Channel 3 Next Transfer Count Low */ -#define SC520_GPDMANXTTCH3 0x0db2 /* GP-DMA Channel 3 Next Transfer Count High */ -#define SC520_GPDMANXTTCL5 0x0db4 /* GP-DMA Channel 5 Next Transfer Count Low */ -#define SC520_GPDMANXTTCH5 0x0db6 /* GP-DMA Channel 5 Next Transfer Count High */ -#define SC520_GPDMANXTTCL6 0x0db8 /* GP-DMA Channel 6 Next Transfer Count Low */ -#define SC520_GPDMANXTTCH6 0x0dba /* GP-DMA Channel 6 Next Transfer Count High */ -#define SC520_GPDMANXTTCL7 0x0dbc /* GP-DMA Channel 7 Next Transfer Count Low */ -#define SC520_GPDMANXTTCH7 0x0dbe /* GP-DMA Channel 7 Next Transfer Count High */ +#define SC520_SWTMRMILLI 0x0c60 /* Software Timer Millisecond Count */ +#define SC520_SWTMRMICRO 0x0c62 /* Software Timer Microsecond Count */ /* MMCR Register bits (not all of them :) ) */ @@ -221,7 +285,6 @@ #define SSISTA_BSY 0x02 /* SSI Busy */ #define SSISTA_TC_INT 0x01 /* SSI Transaction Complete Interrupt */ - /* BITS for SC520_ADDDECCTL: */ #define WPV_INT_ENB 0x80 /* Write-Protect Violation Interrupt Enable */ #define IO_HOLE_DEST_PCI 0x10 /* I/O Hole Access Destination */ @@ -233,7 +296,6 @@ #define SC520_REG_ADDR 0x00000cf8 #define SC520_REG_DATA 0x00000cfc - #define SC520_ISA_MEM_PHYS 0x00000000 #define SC520_ISA_MEM_BUS 0x00000000 #define SC520_ISA_MEM_SIZE 0x01000000 @@ -282,15 +344,4 @@ #define SC520_IRQ14 9 #define SC520_IRQ15 10 -/* utility functions */ -void write_mmcr_byte(u16 mmcr, u8 data); -void write_mmcr_word(u16 mmcr, u16 data); -void write_mmcr_long(u16 mmcr, u32 data); -u8 read_mmcr_byte(u16 mmcr); -u16 read_mmcr_word(u16 mmcr); -u32 read_mmcr_long(u16 mmcr); - -void init_sc520(void); -unsigned long init_sc520_dram(void); - #endif From f50b619d9cb297b0125fe78dcd6f255eb0d91659 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:57 +1000 Subject: [PATCH 027/208] i386: Moved PCI from #ifdef to conditional compile for sc520 boards Signed-off-by: Graeme Russ --- board/eNET/Makefile | 10 +- board/sc520_cdp/Makefile | 12 +- board/sc520_cdp/sc520_cdp.c | 239 -------------------- board/sc520_cdp/sc520_cdp_pci.c | 271 +++++++++++++++++++++++ board/sc520_spunk/Makefile | 12 +- board/sc520_spunk/sc520_spunk.c | 298 ------------------------- board/sc520_spunk/sc520_spunk_pci.c | 323 ++++++++++++++++++++++++++++ lib_i386/Makefile | 4 +- lib_i386/pci.c | 3 - lib_i386/pci_type1.c | 5 - 10 files changed, 615 insertions(+), 562 deletions(-) create mode 100644 board/sc520_cdp/sc520_cdp_pci.c create mode 100644 board/sc520_spunk/sc520_spunk_pci.c diff --git a/board/eNET/Makefile b/board/eNET/Makefile index 4813b4b53a3..bf5736a7908 100644 --- a/board/eNET/Makefile +++ b/board/eNET/Makefile @@ -31,12 +31,12 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := eNET.o -SOBJS := eNET_start16.o eNET_start.o +COBJS-y += eNET.o +SOBJS-y += eNET_start16.o +SOBJS-y += eNET_start.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) diff --git a/board/sc520_cdp/Makefile b/board/sc520_cdp/Makefile index 0d2800d5e42..7944a01a643 100644 --- a/board/sc520_cdp/Makefile +++ b/board/sc520_cdp/Makefile @@ -28,12 +28,14 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := sc520_cdp.o flash.o -SOBJS := sc520_cdp_asm.o sc520_cdp_asm16.o +COBJS-y += sc520_cdp.o +COBJS-y += flash.o +COBJS-$(CONFIG_PCI) += sc520_cdp_pci.o +SOBJS-y += sc520_cdp_asm.o +SOBJS-y += sc520_cdp_asm16.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) diff --git a/board/sc520_cdp/sc520_cdp.c b/board/sc520_cdp/sc520_cdp.c index 9312f4f1d37..4c44b2414c0 100644 --- a/board/sc520_cdp/sc520_cdp.c +++ b/board/sc520_cdp/sc520_cdp.c @@ -23,11 +23,8 @@ */ #include -#include #include -#include #include -#include #include #include #include @@ -114,87 +111,6 @@ static void irq_init(void) sc520_mmcr->eccmap = 0x100; /* Map SDRAM ECC failure INT to NMI */ } -#ifdef CONFIG_PCI -/* PCI stuff */ -static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - /* a configurable lists of irqs to steal - * when we need one (a board with more pci interrupt pins - * would use a larger table */ - static int irq_list[] = { - CONFIG_SYS_FIRST_PCI_IRQ, - CONFIG_SYS_SECOND_PCI_IRQ, - CONFIG_SYS_THIRD_PCI_IRQ, - CONFIG_SYS_FORTH_PCI_IRQ - }; - static int next_irq_index=0; - - uchar tmp_pin; - int pin; - - pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin); - pin = tmp_pin; - - pin-=1; /* pci config space use 1-based numbering */ - if (-1 == pin) { - return; /* device use no irq */ - } - - - /* map device number + pin to a pin on the sc520 */ - switch (PCI_DEV(dev)) { - case 20: - pin+=SC520_PCI_INTA; - break; - - case 19: - pin+=SC520_PCI_INTB; - break; - - case 18: - pin+=SC520_PCI_INTC; - break; - - case 17: - pin+=SC520_PCI_INTD; - break; - - default: - return; - } - - pin&=3; /* wrap around */ - - if (sc520_pci_ints[pin] == -1) { - /* re-route one interrupt for us */ - if (next_irq_index > 3) { - return; - } - if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { - return; - } - next_irq_index++; - } - - - if (-1 != sc520_pci_ints[pin]) { - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, - sc520_pci_ints[pin]); - } - PRINTF("fixup_irq: device %d pin %c irq %d\n", - PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]); -} - -static struct pci_controller sc520_cdp_hose = { - fixup_irq: pci_sc520_cdp_fixup_irq, -}; - -void pci_init_board(void) -{ - pci_sc520_init(&sc520_cdp_hose); -} -#endif - static void silence_uart(int port) { outb(0, port+1); @@ -321,161 +237,6 @@ static void bus_init(void) * PAR15 Port 0x680 LED display */ -/* - * This function should map a chunk of size bytes - * of the system address space to the ISA bus - * - * The function will return the memory address - * as seen by the host (which may very will be the - * same as the bus address) - */ -u32 isa_map_rom(u32 bus_addr, int size) -{ - u32 par; - - PRINTF("isa_map_rom asked to map %d bytes at %x\n", - size, bus_addr); - - par = size; - if (par < 0x80000) { - par = 0x80000; - } - par >>= 12; - par--; - par&=0x7f; - par <<= 18; - par |= (bus_addr>>12); - par |= 0x50000000; - - PRINTF ("setting PAR11 to %x\n", par); - - /* Map rom 0x10000 with PAR1 */ - sc520_mmcr->par[11] = par; - - return bus_addr; -} - -/* - * this function removed any mapping created - * with pci_get_rom_window() - */ -void isa_unmap_rom(u32 addr) -{ - PRINTF("isa_unmap_rom asked to unmap %x", addr); - if ((addr>>12) == (sc520_mmcr->par[11] & 0x3ffff)) { - sc520_mmcr->par[11] = 0; - PRINTF(" done\n"); - return; - } - PRINTF(" not ours\n"); -} - -#ifdef CONFIG_PCI -#define PCI_ROM_TEMP_SPACE 0x10000 -/* - * This function should map a chunk of size bytes - * of the system address space to the PCI bus, - * suitable to map PCI ROMS (bus address < 16M) - * the function will return the host memory address - * which should be converted into a bus address - * before used to configure the PCI rom address - * decoder - */ -u32 pci_get_rom_window(struct pci_controller *hose, int size) -{ - u32 par; - - par = size; - if (par < 0x80000) { - par = 0x80000; - } - par >>= 16; - par--; - par&=0x7ff; - par <<= 14; - par |= (PCI_ROM_TEMP_SPACE>>16); - par |= 0x72000000; - - PRINTF ("setting PAR1 to %x\n", par); - - /* Map rom 0x10000 with PAR1 */ - sc520_mmcr->par[1] = par; - - return PCI_ROM_TEMP_SPACE; -} - -/* - * this function removed any mapping created - * with pci_get_rom_window() - */ -void pci_remove_rom_window(struct pci_controller *hose, u32 addr) -{ - PRINTF("pci_remove_rom_window: %x", addr); - if (addr == PCI_ROM_TEMP_SPACE) { - sc520_mmcr->par[1] = 0; - PRINTF(" done\n"); - return; - } - PRINTF(" not ours\n"); - -} - -/* - * This function is called in order to provide acces to the - * legacy video I/O ports on the PCI bus. - * After this function accesses to I/O ports 0x3b0-0x3bb and - * 0x3c0-0x3df shuld result in transactions on the PCI bus. - * - */ -int pci_enable_legacy_video_ports(struct pci_controller *hose) -{ - /* Map video memory to 0xa0000*/ - sc520_mmcr->par[0] = 0x7200400a; - - /* forward all I/O accesses to PCI */ - sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | IO_HOLE_DEST_PCI; - - - /* so we map away all io ports to pci (only way to access pci io - * below 0x400. But then we have to map back the portions that we dont - * use so that the generate cycles on the GPIO bus where the sio and - * ISA slots are connected, this requre the use of several PAR registers - */ - - /* bring 0x100 - 0x1ef back to ISA using PAR5 */ - sc520_mmcr->par[5] = 0x30ef0100; - - /* IDE use 1f0-1f7 */ - - /* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */ - sc520_mmcr->par[6] = 0x30ff01f8; - - /* com2 use 2f8-2ff */ - - /* bring 0x300 - 0x3af back to ISA using PAR7 */ - sc520_mmcr->par[7] = 0x30af0300; - - /* vga use 3b0-3bb */ - - /* bring 0x3bc - 0x3bf back to ISA using PAR8 */ - sc520_mmcr->par[8] = 0x300303bc; - - /* vga use 3c0-3df */ - - /* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */ - sc520_mmcr->par[9] = 0x301503e0; - - /* ide use 3f6 */ - - /* bring 0x3f7 back to ISA using PAR10 */ - sc520_mmcr->par[10] = 0x300003f7; - - /* com1 use 3f8-3ff */ - - return 0; -} -#endif - /* * Miscelaneous platform dependent initialisations */ diff --git a/board/sc520_cdp/sc520_cdp_pci.c b/board/sc520_cdp/sc520_cdp_pci.c new file mode 100644 index 00000000000..ccb79888dca --- /dev/null +++ b/board/sc520_cdp/sc520_cdp_pci.c @@ -0,0 +1,271 @@ +/* + * + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB . + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#undef SC520_CDP_DEBUG + +#ifdef SC520_CDP_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + /* a configurable lists of irqs to steal + * when we need one (a board with more pci interrupt pins + * would use a larger table */ + static int irq_list[] = { + CONFIG_SYS_FIRST_PCI_IRQ, + CONFIG_SYS_SECOND_PCI_IRQ, + CONFIG_SYS_THIRD_PCI_IRQ, + CONFIG_SYS_FORTH_PCI_IRQ + }; + static int next_irq_index=0; + + uchar tmp_pin; + int pin; + + pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin); + pin = tmp_pin; + + pin-=1; /* pci config space use 1-based numbering */ + if (-1 == pin) { + return; /* device use no irq */ + } + + + /* map device number + pin to a pin on the sc520 */ + switch (PCI_DEV(dev)) { + case 20: + pin+=SC520_PCI_INTA; + break; + + case 19: + pin+=SC520_PCI_INTB; + break; + + case 18: + pin+=SC520_PCI_INTC; + break; + + case 17: + pin+=SC520_PCI_INTD; + break; + + default: + return; + } + + pin&=3; /* wrap around */ + + if (sc520_pci_ints[pin] == -1) { + /* re-route one interrupt for us */ + if (next_irq_index > 3) { + return; + } + if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { + return; + } + next_irq_index++; + } + + + if (-1 != sc520_pci_ints[pin]) { + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, + sc520_pci_ints[pin]); + } + PRINTF("fixup_irq: device %d pin %c irq %d\n", + PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]); +} + +static struct pci_controller sc520_cdp_hose = { + fixup_irq: pci_sc520_cdp_fixup_irq, +}; + +void pci_init_board(void) +{ + pci_sc520_init(&sc520_cdp_hose); +} + +/* + * This function should map a chunk of size bytes + * of the system address space to the ISA bus + * + * The function will return the memory address + * as seen by the host (which may very will be the + * same as the bus address) + */ +u32 isa_map_rom(u32 bus_addr, int size) +{ + u32 par; + + PRINTF("isa_map_rom asked to map %d bytes at %x\n", + size, bus_addr); + + par = size; + if (par < 0x80000) { + par = 0x80000; + } + par >>= 12; + par--; + par&=0x7f; + par <<= 18; + par |= (bus_addr>>12); + par |= 0x50000000; + + PRINTF ("setting PAR11 to %x\n", par); + + /* Map rom 0x10000 with PAR1 */ + sc520_mmcr->par[11] = par; + + return bus_addr; +} + +/* + * this function removed any mapping created + * with pci_get_rom_window() + */ +void isa_unmap_rom(u32 addr) +{ + PRINTF("isa_unmap_rom asked to unmap %x", addr); + if ((addr>>12) == (sc520_mmcr->par[11] & 0x3ffff)) { + sc520_mmcr->par[11] = 0; + PRINTF(" done\n"); + return; + } + PRINTF(" not ours\n"); +} + +#define PCI_ROM_TEMP_SPACE 0x10000 +/* + * This function should map a chunk of size bytes + * of the system address space to the PCI bus, + * suitable to map PCI ROMS (bus address < 16M) + * the function will return the host memory address + * which should be converted into a bus address + * before used to configure the PCI rom address + * decoder + */ +u32 pci_get_rom_window(struct pci_controller *hose, int size) +{ + u32 par; + + par = size; + if (par < 0x80000) { + par = 0x80000; + } + par >>= 16; + par--; + par&=0x7ff; + par <<= 14; + par |= (PCI_ROM_TEMP_SPACE>>16); + par |= 0x72000000; + + PRINTF ("setting PAR1 to %x\n", par); + + /* Map rom 0x10000 with PAR1 */ + sc520_mmcr->par[1] = par; + + return PCI_ROM_TEMP_SPACE; +} + +/* + * this function removed any mapping created + * with pci_get_rom_window() + */ +void pci_remove_rom_window(struct pci_controller *hose, u32 addr) +{ + PRINTF("pci_remove_rom_window: %x", addr); + if (addr == PCI_ROM_TEMP_SPACE) { + sc520_mmcr->par[1] = 0; + PRINTF(" done\n"); + return; + } + PRINTF(" not ours\n"); + +} + +/* + * This function is called in order to provide acces to the + * legacy video I/O ports on the PCI bus. + * After this function accesses to I/O ports 0x3b0-0x3bb and + * 0x3c0-0x3df shuld result in transactions on the PCI bus. + * + */ +int pci_enable_legacy_video_ports(struct pci_controller *hose) +{ + /* Map video memory to 0xa0000*/ + sc520_mmcr->par[0] = 0x7200400a; + + /* forward all I/O accesses to PCI */ + sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | IO_HOLE_DEST_PCI; + + + /* so we map away all io ports to pci (only way to access pci io + * below 0x400. But then we have to map back the portions that we dont + * use so that the generate cycles on the GPIO bus where the sio and + * ISA slots are connected, this requre the use of several PAR registers + */ + + /* bring 0x100 - 0x1ef back to ISA using PAR5 */ + sc520_mmcr->par[5] = 0x30ef0100; + + /* IDE use 1f0-1f7 */ + + /* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */ + sc520_mmcr->par[6] = 0x30ff01f8; + + /* com2 use 2f8-2ff */ + + /* bring 0x300 - 0x3af back to ISA using PAR7 */ + sc520_mmcr->par[7] = 0x30af0300; + + /* vga use 3b0-3bb */ + + /* bring 0x3bc - 0x3bf back to ISA using PAR8 */ + sc520_mmcr->par[8] = 0x300303bc; + + /* vga use 3c0-3df */ + + /* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */ + sc520_mmcr->par[9] = 0x301503e0; + + /* ide use 3f6 */ + + /* bring 0x3f7 back to ISA using PAR10 */ + sc520_mmcr->par[10] = 0x300003f7; + + /* com1 use 3f8-3ff */ + + return 0; +} diff --git a/board/sc520_spunk/Makefile b/board/sc520_spunk/Makefile index e04172e3b9b..06fa2f3f448 100644 --- a/board/sc520_spunk/Makefile +++ b/board/sc520_spunk/Makefile @@ -28,12 +28,14 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := sc520_spunk.o flash.o -SOBJS := sc520_spunk_asm.o sc520_spunk_asm16.o +COBJS-y += sc520_spunk.o +COBJS-y += flash.o +COBJS-$(CONFIG_PCI) += sc520_spunk_pci.o +SOBJS-y += sc520_spunk_asm.o +SOBJS-y += sc520_spunk_asm16.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) diff --git a/board/sc520_spunk/sc520_spunk.c b/board/sc520_spunk/sc520_spunk.c index dbb5c48d683..09f11bb4f30 100644 --- a/board/sc520_spunk/sc520_spunk.c +++ b/board/sc520_spunk/sc520_spunk.c @@ -23,13 +23,10 @@ */ #include -#include #include #include #include -#include #include -#include #include DECLARE_GLOBAL_DATA_PTR; @@ -98,156 +95,6 @@ static void irq_init(void) } - -/* PCI stuff */ -static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - int version = sc520_mmcr->sysinfo; - - /* a configurable lists of irqs to steal - * when we need one (a board with more pci interrupt pins - * would use a larger table */ - static int irq_list[] = { - CONFIG_SYS_FIRST_PCI_IRQ, - CONFIG_SYS_SECOND_PCI_IRQ, - CONFIG_SYS_THIRD_PCI_IRQ, - CONFIG_SYS_FORTH_PCI_IRQ - }; - static int next_irq_index=0; - - uchar tmp_pin; - int pin; - - pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin); - pin = tmp_pin; - - pin-=1; /* pci config space use 1-based numbering */ - if (-1 == pin) { - return; /* device use no irq */ - } - - - /* map device number + pin to a pin on the sc520 */ - switch (PCI_DEV(dev)) { - case 6: /* ETH0 */ - pin+=SC520_PCI_INTA; - break; - - case 7: /* ETH1 */ - pin+=SC520_PCI_INTB; - break; - - case 8: /* Crypto */ - pin+=SC520_PCI_INTC; - break; - - case 9: /* PMC slot */ - pin+=SC520_PCI_INTD; - break; - - case 10: /* PC-Card */ - - if (version < 10) { - pin+=SC520_PCI_INTD; - } else { - pin+=SC520_PCI_INTC; - } - break; - - default: - return; - } - - pin&=3; /* wrap around */ - - if (sc520_pci_ints[pin] == -1) { - /* re-route one interrupt for us */ - if (next_irq_index > 3) { - return; - } - if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { - return; - } - next_irq_index++; - } - - - if (-1 != sc520_pci_ints[pin]) { - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, - sc520_pci_ints[pin]); - } -#if 0 - printf("fixup_irq: device %d pin %c irq %d\n", - PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]); -#endif -} - - -static void pci_sc520_spunk_configure_cardbus(struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *te) -{ - u32 io_base; - u32 temp; - - pciauto_config_device(hose, dev); - - pci_hose_write_config_word(hose, dev, PCI_COMMAND, 0x07); /* enable device */ - pci_hose_write_config_byte(hose, dev, 0x0c, 0x10); /* cacheline size */ - pci_hose_write_config_byte(hose, dev, 0x0d, 0x40); /* latency timer */ - pci_hose_write_config_byte(hose, dev, 0x1b, 0x40); /* cardbus latency timer */ - pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0040); /* reset cardbus */ - pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0080); /* route interrupts though ExCA */ - pci_hose_write_config_word(hose, dev, 0x44, 0x3e0); /* map legacy I/O port to 0x3e0 */ - - pci_hose_read_config_dword(hose, dev, 0x80, &temp); /* System control */ - pci_hose_write_config_dword(hose, dev, 0x80, temp | 0x60); /* System control: disable clockrun */ - /* route MF0 to ~INT and MF3 to IRQ7 - * reserve all others */ - pci_hose_write_config_dword(hose, dev, 0x8c, 0x00007002); - pci_hose_write_config_byte(hose, dev, 0x91, 0x00); /* card control */ - pci_hose_write_config_byte(hose, dev, 0x92, 0x62); /* device control */ - - if (te->device != 0xac56) { - pci_hose_write_config_byte(hose, dev, 0x93, 0x21); /* async interrupt enable */ - pci_hose_write_config_word(hose, dev, 0xa8, 0x0000); /* reset GPIO */ - pci_hose_write_config_word(hose, dev, 0xac, 0x0000); /* reset GPIO */ - pci_hose_write_config_word(hose, dev, 0xaa, 0x0000); /* reset GPIO */ - pci_hose_write_config_word(hose, dev, 0xae, 0x0000); /* reset GPIO */ - } else { - pci_hose_write_config_byte(hose, dev, 0x93, 0x20); /* */ - } - pci_hose_write_config_word(hose, dev, 0xa4, 0x8000); /* reset power management */ - - - pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &io_base); - io_base &= ~0xfL; - - writeb(0x07, io_base+0x803); /* route CSC irq though ExCA and enable IRQ7 */ - writel(0, io_base+0x10); /* CLKRUN default */ - writel(0, io_base+0x20); /* CLKRUN default */ - -} - - -static struct pci_config_table pci_sc520_spunk_config_table[] = { - { 0x104c, 0xac50, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} }, - { 0x104c, 0xac56, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} }, - { 0, 0, 0, 0, 0, 0, NULL, {0,0,0}} -}; - -static struct pci_controller sc520_spunk_hose = { - fixup_irq: pci_sc520_spunk_fixup_irq, - config_table: pci_sc520_spunk_config_table, - first_busno: 0x00, - last_busno: 0xff, -}; - -void pci_init_board(void) -{ - pci_sc520_init(&sc520_spunk_hose); -} - - /* set up the ISA bus timing and system address mappings */ static void bus_init(void) { @@ -333,151 +180,6 @@ static void bus_init(void) * PAR15 */ -/* - * This function should map a chunk of size bytes - * of the system address space to the ISA bus - * - * The function will return the memory address - * as seen by the host (which may very will be the - * same as the bus address) - */ -u32 isa_map_rom(u32 bus_addr, int size) -{ - u32 par; - - printf("isa_map_rom asked to map %d bytes at %x\n", - size, bus_addr); - - par = size; - if (par < 0x80000) { - par = 0x80000; - } - par >>= 12; - par--; - par&=0x7f; - par <<= 18; - par |= (bus_addr>>12); - par |= 0x50000000; - - printf ("setting PAR11 to %x\n", par); - - /* Map rom 0x10000 with PAR1 */ - sc520_mmcr->par[11] = par; - - return bus_addr; -} - -/* - * this function removed any mapping created - * with pci_get_rom_window() - */ -void isa_unmap_rom(u32 addr) -{ - printf("isa_unmap_rom asked to unmap %x", addr); - if ((addr>>12) == (sc520_mmcr->par[11] & 0x3ffff)) { - sc520_mmcr->par[11] = 0; - printf(" done\n"); - return; - } - printf(" not ours\n"); -} - -#ifdef CONFIG_PCI -#define PCI_ROM_TEMP_SPACE 0x10000 -/* - * This function should map a chunk of size bytes - * of the system address space to the PCI bus, - * suitable to map PCI ROMS (bus address < 16M) - * the function will return the host memory address - * which should be converted into a bus address - * before used to configure the PCI rom address - * decoder - */ -u32 pci_get_rom_window(struct pci_controller *hose, int size) -{ - u32 par; - - par = size; - if (par < 0x80000) { - par = 0x80000; - } - par >>= 16; - par--; - par&=0x7ff; - par <<= 14; - par |= (PCI_ROM_TEMP_SPACE>>16); - par |= 0x72000000; - - printf ("setting PAR1 to %x\n", par); - - /* Map rom 0x10000 with PAR1 */ - sc520_mmcr->par[1] = par; - - return PCI_ROM_TEMP_SPACE; -} - -/* - * this function removed any mapping created - * with pci_get_rom_window() - */ -void pci_remove_rom_window(struct pci_controller *hose, u32 addr) -{ - printf("pci_remove_rom_window: %x", addr); - if (addr == PCI_ROM_TEMP_SPACE) { - sc520_mmcr->par[1] = 0; - printf(" done\n"); - return; - } - printf(" not ours\n"); - -} - -/* - * This function is called in order to provide acces to the - * legacy video I/O ports on the PCI bus. - * After this function accesses to I/O ports 0x3b0-0x3bb and - * 0x3c0-0x3df shuld result in transactions on the PCI bus. - * - */ -int pci_enable_legacy_video_ports(struct pci_controller *hose) -{ - /* Map video memory to 0xa0000*/ - sc520_mmcr->par[0] = 0x7200400a; - - /* forward all I/O accesses to PCI */ - sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | IO_HOLE_DEST_PCI; - - - /* so we map away all io ports to pci (only way to access pci io - * below 0x400. But then we have to map back the portions that we dont - * use so that the generate cycles on the GPIO bus where the sio and - * ISA slots are connected, this requre the use of several PAR registers - */ - - /* bring 0x100 - 0x2f7 back to ISA using PAR5 */ - sc520_mmcr->par[5] = 0x31f70100; - - /* com2 use 2f8-2ff */ - - /* bring 0x300 - 0x3af back to ISA using PAR7 */ - sc520_mmcr->par[7] = 0x30af0300; - - /* vga use 3b0-3bb */ - - /* bring 0x3bc - 0x3bf back to ISA using PAR8 */ - sc520_mmcr->par[8] = 0x300303bc; - - /* vga use 3c0-3df */ - - /* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */ - sc520_mmcr->par[9] = 0x301703e0; - - /* com1 use 3f8-3ff */ - - return 0; -} -#endif - /* * Miscelaneous platform dependent initialisations */ diff --git a/board/sc520_spunk/sc520_spunk_pci.c b/board/sc520_spunk/sc520_spunk_pci.c new file mode 100644 index 00000000000..1b5d0f17f63 --- /dev/null +++ b/board/sc520_spunk/sc520_spunk_pci.c @@ -0,0 +1,323 @@ +/* + * + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB . + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + int version = sc520_mmcr->sysinfo; + + /* a configurable lists of irqs to steal + * when we need one (a board with more pci interrupt pins + * would use a larger table */ + static int irq_list[] = { + CONFIG_SYS_FIRST_PCI_IRQ, + CONFIG_SYS_SECOND_PCI_IRQ, + CONFIG_SYS_THIRD_PCI_IRQ, + CONFIG_SYS_FORTH_PCI_IRQ + }; + static int next_irq_index=0; + + uchar tmp_pin; + int pin; + + pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin); + pin = tmp_pin; + + pin-=1; /* pci config space use 1-based numbering */ + if (-1 == pin) { + return; /* device use no irq */ + } + + + /* map device number + pin to a pin on the sc520 */ + switch (PCI_DEV(dev)) { + case 6: /* ETH0 */ + pin+=SC520_PCI_INTA; + break; + + case 7: /* ETH1 */ + pin+=SC520_PCI_INTB; + break; + + case 8: /* Crypto */ + pin+=SC520_PCI_INTC; + break; + + case 9: /* PMC slot */ + pin+=SC520_PCI_INTD; + break; + + case 10: /* PC-Card */ + + if (version < 10) { + pin+=SC520_PCI_INTD; + } else { + pin+=SC520_PCI_INTC; + } + break; + + default: + return; + } + + pin&=3; /* wrap around */ + + if (sc520_pci_ints[pin] == -1) { + /* re-route one interrupt for us */ + if (next_irq_index > 3) { + return; + } + if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { + return; + } + next_irq_index++; + } + + + if (-1 != sc520_pci_ints[pin]) { + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, + sc520_pci_ints[pin]); + } +#if 0 + printf("fixup_irq: device %d pin %c irq %d\n", + PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]); +#endif +} + + +static void pci_sc520_spunk_configure_cardbus(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *te) +{ + u32 io_base; + u32 temp; + + pciauto_config_device(hose, dev); + + pci_hose_write_config_word(hose, dev, PCI_COMMAND, 0x07); /* enable device */ + pci_hose_write_config_byte(hose, dev, 0x0c, 0x10); /* cacheline size */ + pci_hose_write_config_byte(hose, dev, 0x0d, 0x40); /* latency timer */ + pci_hose_write_config_byte(hose, dev, 0x1b, 0x40); /* cardbus latency timer */ + pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0040); /* reset cardbus */ + pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0080); /* route interrupts though ExCA */ + pci_hose_write_config_word(hose, dev, 0x44, 0x3e0); /* map legacy I/O port to 0x3e0 */ + + pci_hose_read_config_dword(hose, dev, 0x80, &temp); /* System control */ + pci_hose_write_config_dword(hose, dev, 0x80, temp | 0x60); /* System control: disable clockrun */ + /* route MF0 to ~INT and MF3 to IRQ7 + * reserve all others */ + pci_hose_write_config_dword(hose, dev, 0x8c, 0x00007002); + pci_hose_write_config_byte(hose, dev, 0x91, 0x00); /* card control */ + pci_hose_write_config_byte(hose, dev, 0x92, 0x62); /* device control */ + + if (te->device != 0xac56) { + pci_hose_write_config_byte(hose, dev, 0x93, 0x21); /* async interrupt enable */ + pci_hose_write_config_word(hose, dev, 0xa8, 0x0000); /* reset GPIO */ + pci_hose_write_config_word(hose, dev, 0xac, 0x0000); /* reset GPIO */ + pci_hose_write_config_word(hose, dev, 0xaa, 0x0000); /* reset GPIO */ + pci_hose_write_config_word(hose, dev, 0xae, 0x0000); /* reset GPIO */ + } else { + pci_hose_write_config_byte(hose, dev, 0x93, 0x20); /* */ + } + pci_hose_write_config_word(hose, dev, 0xa4, 0x8000); /* reset power management */ + + + pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &io_base); + io_base &= ~0xfL; + + writeb(0x07, io_base+0x803); /* route CSC irq though ExCA and enable IRQ7 */ + writel(0, io_base+0x10); /* CLKRUN default */ + writel(0, io_base+0x20); /* CLKRUN default */ + +} + + +static struct pci_config_table pci_sc520_spunk_config_table[] = { + { 0x104c, 0xac50, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} }, + { 0x104c, 0xac56, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} }, + { 0, 0, 0, 0, 0, 0, NULL, {0,0,0}} +}; + +static struct pci_controller sc520_spunk_hose = { + fixup_irq: pci_sc520_spunk_fixup_irq, + config_table: pci_sc520_spunk_config_table, + first_busno: 0x00, + last_busno: 0xff, +}; + +void pci_init_board(void) +{ + pci_sc520_init(&sc520_spunk_hose); +} + +/* + * This function should map a chunk of size bytes + * of the system address space to the ISA bus + * + * The function will return the memory address + * as seen by the host (which may very will be the + * same as the bus address) + */ +u32 isa_map_rom(u32 bus_addr, int size) +{ + u32 par; + + printf("isa_map_rom asked to map %d bytes at %x\n", + size, bus_addr); + + par = size; + if (par < 0x80000) { + par = 0x80000; + } + par >>= 12; + par--; + par&=0x7f; + par <<= 18; + par |= (bus_addr>>12); + par |= 0x50000000; + + printf ("setting PAR11 to %x\n", par); + + /* Map rom 0x10000 with PAR1 */ + sc520_mmcr->par[11] = par; + + return bus_addr; +} + +/* + * this function removed any mapping created + * with pci_get_rom_window() + */ +void isa_unmap_rom(u32 addr) +{ + printf("isa_unmap_rom asked to unmap %x", addr); + if ((addr>>12) == (sc520_mmcr->par[11] & 0x3ffff)) { + sc520_mmcr->par[11] = 0; + printf(" done\n"); + return; + } + printf(" not ours\n"); +} + +#define PCI_ROM_TEMP_SPACE 0x10000 +/* + * This function should map a chunk of size bytes + * of the system address space to the PCI bus, + * suitable to map PCI ROMS (bus address < 16M) + * the function will return the host memory address + * which should be converted into a bus address + * before used to configure the PCI rom address + * decoder + */ +u32 pci_get_rom_window(struct pci_controller *hose, int size) +{ + u32 par; + + par = size; + if (par < 0x80000) { + par = 0x80000; + } + par >>= 16; + par--; + par&=0x7ff; + par <<= 14; + par |= (PCI_ROM_TEMP_SPACE>>16); + par |= 0x72000000; + + printf ("setting PAR1 to %x\n", par); + + /* Map rom 0x10000 with PAR1 */ + sc520_mmcr->par[1] = par; + + return PCI_ROM_TEMP_SPACE; +} + +/* + * this function removed any mapping created + * with pci_get_rom_window() + */ +void pci_remove_rom_window(struct pci_controller *hose, u32 addr) +{ + printf("pci_remove_rom_window: %x", addr); + if (addr == PCI_ROM_TEMP_SPACE) { + sc520_mmcr->par[1] = 0; + printf(" done\n"); + return; + } + printf(" not ours\n"); + +} + +/* + * This function is called in order to provide acces to the + * legacy video I/O ports on the PCI bus. + * After this function accesses to I/O ports 0x3b0-0x3bb and + * 0x3c0-0x3df shuld result in transactions on the PCI bus. + * + */ +int pci_enable_legacy_video_ports(struct pci_controller *hose) +{ + /* Map video memory to 0xa0000*/ + sc520_mmcr->par[0] = 0x7200400a; + + /* forward all I/O accesses to PCI */ + sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | IO_HOLE_DEST_PCI; + + + /* so we map away all io ports to pci (only way to access pci io + * below 0x400. But then we have to map back the portions that we dont + * use so that the generate cycles on the GPIO bus where the sio and + * ISA slots are connected, this requre the use of several PAR registers + */ + + /* bring 0x100 - 0x2f7 back to ISA using PAR5 */ + sc520_mmcr->par[5] = 0x31f70100; + + /* com2 use 2f8-2ff */ + + /* bring 0x300 - 0x3af back to ISA using PAR7 */ + sc520_mmcr->par[7] = 0x30af0300; + + /* vga use 3b0-3bb */ + + /* bring 0x3bc - 0x3bf back to ISA using PAR8 */ + sc520_mmcr->par[8] = 0x300303bc; + + /* vga use 3c0-3df */ + + /* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */ + sc520_mmcr->par[9] = 0x301703e0; + + /* com1 use 3f8-3ff */ + + return 0; +} diff --git a/lib_i386/Makefile b/lib_i386/Makefile index ec6f2360522..bb9b330ac64 100644 --- a/lib_i386/Makefile +++ b/lib_i386/Makefile @@ -32,8 +32,8 @@ SOBJS-y += realmode_switch.o COBJS-y += bios_setup.o COBJS-y += board.o COBJS-y += bootm.o -COBJS-y += pci.o -COBJS-y += pci_type1.o +COBJS-$(CONFIG_PCI) += pci.o +COBJS-$(CONFIG_PCI) += pci_type1.o COBJS-y += realmode.o COBJS-y += video_bios.o COBJS-y += video.o diff --git a/lib_i386/pci.c b/lib_i386/pci.c index f366bdc6724..9020e7ce764 100644 --- a/lib_i386/pci.c +++ b/lib_i386/pci.c @@ -26,7 +26,6 @@ #include #include -#ifdef CONFIG_PCI #undef PCI_ROM_SCAN_VERBOSE int pci_shadow_rom(pci_dev_t dev, unsigned char *dest) @@ -151,5 +150,3 @@ int pci_shadow_rom(pci_dev_t dev, unsigned char *dest) return res; } - -#endif diff --git a/lib_i386/pci_type1.c b/lib_i386/pci_type1.c index 8da8c1ced75..225ae4a9909 100644 --- a/lib_i386/pci_type1.c +++ b/lib_i386/pci_type1.c @@ -11,9 +11,6 @@ */ #include - -#ifdef CONFIG_PCI - #include #include @@ -52,5 +49,3 @@ void pci_setup_type1(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) hose->cfg_addr = (unsigned int *) cfg_addr; hose->cfg_data = (unsigned char *) cfg_data; } - -#endif From 5b34a296d47b236dafbcaf1c91ae11b5aeb1ef51 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:58 +1000 Subject: [PATCH 028/208] Add PCI support to eNET board Signed-off-by: Graeme Russ --- board/eNET/Makefile | 1 + board/eNET/eNET_pci.c | 95 ++++++++++++++++++++++++++++++++++++++++++ include/configs/eNET.h | 14 +++---- 3 files changed, 103 insertions(+), 7 deletions(-) create mode 100644 board/eNET/eNET_pci.c diff --git a/board/eNET/Makefile b/board/eNET/Makefile index bf5736a7908..588d21d269e 100644 --- a/board/eNET/Makefile +++ b/board/eNET/Makefile @@ -32,6 +32,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a COBJS-y += eNET.o +COBJS-$(CONFIG_PCI) += eNET_pci.o SOBJS-y += eNET_start16.o SOBJS-y += eNET_start.o diff --git a/board/eNET/eNET_pci.c b/board/eNET/eNET_pci.c new file mode 100644 index 00000000000..e80a8feb162 --- /dev/null +++ b/board/eNET/eNET_pci.c @@ -0,0 +1,95 @@ +/* + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + * + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB . + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include + +static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + /* a configurable lists of IRQs to steal when we need one */ + static int irq_list[] = { + CONFIG_SYS_FIRST_PCI_IRQ, + CONFIG_SYS_SECOND_PCI_IRQ, + CONFIG_SYS_THIRD_PCI_IRQ, + CONFIG_SYS_FORTH_PCI_IRQ + }; + static int next_irq_index=0; + + uchar tmp_pin; + int pin; + + pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin); + pin = tmp_pin; + + pin -= 1; /* PCI config space use 1-based numbering */ + if (pin == -1) { + return; /* device use no irq */ + } + + /* map device number + pin to a pin on the sc520 */ + switch (PCI_DEV(dev)) { + case 12: /* First Ethernet Chip */ + pin += SC520_PCI_INTA; + break; + + case 13: /* Second Ethernet Chip */ + pin += SC520_PCI_INTB; + break; + + default: + return; + } + + pin &= 3; /* wrap around */ + + if (sc520_pci_ints[pin] == -1) { + /* re-route one interrupt for us */ + if (next_irq_index > 3) { + return; + } + if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { + return; + } + next_irq_index++; + } + + if (-1 != sc520_pci_ints[pin]) { + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, + sc520_pci_ints[pin]); + } + printf("fixup_irq: device %d pin %c irq %d\n", + PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]); +} + +static struct pci_controller enet_hose = { + fixup_irq: pci_enet_fixup_irq, +}; + +void pci_init_board(void) +{ + pci_sc520_init(&enet_hose); +} diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 43567142323..243a5541785 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -86,6 +86,7 @@ #define CONFIG_CMD_MISC /* Misc functions like sleep etc*/ #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #undef CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_PCI /* PCI support */ #define CONFIG_CMD_RUN /* run command in env variable */ #define CONFIG_CMD_SAVEENV /* saveenv */ #define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ @@ -200,13 +201,12 @@ /*----------------------------------------------------------------------- * PCI configuration */ -#undef CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP /* pci plug-and-play */ -#undef CONFIG_PCI_SCAN_SHOW -#undef CONFIG_SYS_FIRST_PCI_IRQ -#undef CONFIG_SYS_SECOND_PCI_IRQ -#undef CONFIG_SYS_THIRD_PCI_IRQ -#undef CONFIG_SYS_FORTH_PCI_IRQ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* pci plug-and-play */ +#define CONFIG_SYS_FIRST_PCI_IRQ 10 +#define CONFIG_SYS_SECOND_PCI_IRQ 9 +#define CONFIG_SYS_THIRD_PCI_IRQ 11 +#define CONFIG_SYS_FORTH_PCI_IRQ 15 /*----------------------------------------------------------------------- * Hardware watchdog configuration From 9ea005fb4428c922536fa75991ce9972304a02fb Mon Sep 17 00:00:00 2001 From: Roy Zang Date: Sat, 22 Aug 2009 03:49:52 +0800 Subject: [PATCH 029/208] Use different PBA value for E1000 PCI and PCIe cards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Roy Zang Acked-by: André Schwarz --- drivers/net/e1000.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index b8dd9f2fe46..7f9f783c43d 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -50,7 +50,8 @@ tested on both gig copper and gig fiber boards #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) #define mdelay(n) udelay((n)*1000) -#define E1000_DEFAULT_PBA 0x000a0026 +#define E1000_DEFAULT_PCI_PBA 0x00000030 +#define E1000_DEFAULT_PCIE_PBA 0x000a0026 /* NIC specific static variables go here */ @@ -1349,9 +1350,16 @@ e1000_reset_hw(struct e1000_hw *hw) uint32_t ctrl_ext; uint32_t icr; uint32_t manc; + uint32_t pba = 0; DEBUGFUNC(); + /* get the correct pba value for both PCI and PCIe*/ + if (hw->mac_type < e1000_82571) + pba = E1000_DEFAULT_PCI_PBA; + else + pba = E1000_DEFAULT_PCIE_PBA; + /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ if (hw->mac_type == e1000_82542_rev2_0) { DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); @@ -1419,7 +1427,7 @@ e1000_reset_hw(struct e1000_hw *hw) if (hw->mac_type == e1000_82542_rev2_0) { pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); } - E1000_WRITE_REG(hw, PBA, E1000_DEFAULT_PBA); + E1000_WRITE_REG(hw, PBA, pba); } /****************************************************************************** From 3dfad40a0459f63099e177dc15a1df39d048f860 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 27 Aug 2009 08:23:55 -0500 Subject: [PATCH 030/208] Add ability for arch code to make changes before we boot Added a arch_preboot_os() function that cpu specific code can implement to allow for various modifications to the state of the machine right before we boot. This can be useful to setup register state to a specific configuration. Signed-off-by: Kumar Gala --- common/cmd_bootm.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 86c81220d2c..365ceebdf06 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -166,6 +166,13 @@ void __arch_lmb_reserve(struct lmb *lmb) } void arch_lmb_reserve(struct lmb *lmb) __attribute__((weak, alias("__arch_lmb_reserve"))); +/* Allow for arch specific config before we boot */ +void __arch_preboot_os(void) +{ + /* please define platform specific arch_preboot_os() */ +} +void arch_preboot_os(void) __attribute__((weak, alias("__arch_preboot_os"))); + #if defined(__ARM__) #define IH_INITRD_ARCH IH_ARCH_ARM #elif defined(__avr32__) @@ -543,6 +550,7 @@ int do_bootm_subcommand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) break; case BOOTM_STATE_OS_GO: disable_interrupts(); + arch_preboot_os(); boot_fn(BOOTM_STATE_OS_GO, argc, argv, &images); break; } @@ -673,6 +681,8 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } + arch_preboot_os(); + boot_fn(0, argc, argv, &images); show_boot_progress (-9); From 795d246c278e70b4ba9868cc9f2c8fbada49d388 Mon Sep 17 00:00:00 2001 From: Eric Millbrandt Date: Fri, 28 Aug 2009 07:14:04 -0500 Subject: [PATCH 031/208] galaxy5200: Add chip select region for an Epson S1D15313 Signed-off-by: Eric Millbrandt --- include/configs/galaxy5200.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h index 8d530d86aa1..a5b5a03a9a2 100644 --- a/include/configs/galaxy5200.h +++ b/include/configs/galaxy5200.h @@ -211,6 +211,11 @@ #define CONFIG_SYS_CS1_SIZE 0x90000 #define CONFIG_SYS_CS1_CFG 0x0002d900 +/* Chip Select configuration for Epson S1D13513 */ +#define CONFIG_SYS_CS3_START 0x10000000 +#define CONFIG_SYS_CS3_SIZE 0x400000 +#define CONFIG_SYS_CS3_CFG 0xffff3d10 + /* * Ethernet configuration */ From d6281ff0cc2ebb5d6a5c3e1021837334074f92ec Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 1 Sep 2009 11:24:44 -0500 Subject: [PATCH 032/208] ppc: Remove -fno-strict-aliasing -fno-strict-aliasing is hidding warnings. Signed-off-by: Kumar Gala --- board/tqc/tqm5200/Makefile | 2 +- cpu/74xx_7xx/config.mk | 2 +- cpu/mpc824x/config.mk | 2 +- cpu/mpc8xx/config.mk | 2 +- cpu/ppc4xx/config.mk | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/board/tqc/tqm5200/Makefile b/board/tqc/tqm5200/Makefile index ce125e2b960..55c4d99a8f3 100644 --- a/board/tqc/tqm5200/Makefile +++ b/board/tqc/tqm5200/Makefile @@ -41,7 +41,7 @@ distclean: clean rm -f $(LIB) core *.bak $(obj).depend cam5200_flash.o: cam5200_flash.c - $(CC) $(CFLAGS) -fno-strict-aliasing -c -o $@ $< + $(CC) $(CFLAGS) -c -o $@ $< ######################################################################### diff --git a/cpu/74xx_7xx/config.mk b/cpu/74xx_7xx/config.mk index 324f62b836d..d58921079c7 100644 --- a/cpu/74xx_7xx/config.mk +++ b/cpu/74xx_7xx/config.mk @@ -21,6 +21,6 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -mstring diff --git a/cpu/mpc824x/config.mk b/cpu/mpc824x/config.mk index 1bb0487bd3b..b607fee4fdd 100644 --- a/cpu/mpc824x/config.mk +++ b/cpu/mpc824x/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -mstring -mcpu=603e -msoft-float diff --git a/cpu/mpc8xx/config.mk b/cpu/mpc8xx/config.mk index 6031e7f76af..2b3d545cc37 100644 --- a/cpu/mpc8xx/config.mk +++ b/cpu/mpc8xx/config.mk @@ -21,6 +21,6 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_8xx -ffixed-r2 -mstring -mcpu=860 -msoft-float diff --git a/cpu/ppc4xx/config.mk b/cpu/ppc4xx/config.mk index baa97a4122a..00ad39b6027 100644 --- a/cpu/ppc4xx/config.mk +++ b/cpu/ppc4xx/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -mstring -msoft-float cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') From d72871e1387094972569e4b77c25e88020f7b68f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 1 Sep 2009 11:24:45 -0500 Subject: [PATCH 033/208] arm: Remove -fno-strict-aliasing -fno-strict-aliasing is hidding warnings. Signed-off-by: Kumar Gala --- cpu/arm1136/config.mk | 3 +-- cpu/arm1176/config.mk | 3 +-- cpu/arm1176/s3c64xx/config.mk | 3 +-- cpu/arm720t/config.mk | 3 +-- cpu/arm920t/config.mk | 3 +-- cpu/arm925t/config.mk | 3 +-- cpu/arm926ejs/config.mk | 3 +-- cpu/arm926ejs/davinci/config.mk | 3 +-- cpu/arm946es/config.mk | 3 +-- cpu/arm_cortexa8/config.mk | 3 +-- cpu/arm_intcm/config.mk | 3 +-- cpu/ixp/config.mk | 3 +-- cpu/lh7a40x/config.mk | 3 +-- cpu/pxa/config.mk | 3 +-- cpu/s3c44b0/config.mk | 3 +-- cpu/sa1100/config.mk | 3 +-- 16 files changed, 16 insertions(+), 32 deletions(-) diff --git a/cpu/arm1136/config.mk b/cpu/arm1136/config.mk index 61d5a382ed8..3e685354ab7 100644 --- a/cpu/arm1136/config.mk +++ b/cpu/arm1136/config.mk @@ -20,8 +20,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float # Make ARMv5 to allow more compilers to work, even though its v6. PLATFORM_CPPFLAGS += -march=armv5 diff --git a/cpu/arm1176/config.mk b/cpu/arm1176/config.mk index a31c7b0f897..14346cfff3f 100644 --- a/cpu/arm1176/config.mk +++ b/cpu/arm1176/config.mk @@ -20,8 +20,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float # Make ARMv5 to allow more compilers to work, even though its v6. PLATFORM_CPPFLAGS += -march=armv5t diff --git a/cpu/arm1176/s3c64xx/config.mk b/cpu/arm1176/s3c64xx/config.mk index a31c7b0f897..14346cfff3f 100644 --- a/cpu/arm1176/s3c64xx/config.mk +++ b/cpu/arm1176/s3c64xx/config.mk @@ -20,8 +20,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float # Make ARMv5 to allow more compilers to work, even though its v6. PLATFORM_CPPFLAGS += -march=armv5t diff --git a/cpu/arm720t/config.mk b/cpu/arm720t/config.mk index 74d52831ede..3844c626af3 100644 --- a/cpu/arm720t/config.mk +++ b/cpu/arm720t/config.mk @@ -22,8 +22,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi # ========================================================================= diff --git a/cpu/arm920t/config.mk b/cpu/arm920t/config.mk index a43b1567110..8f6c1a354c5 100644 --- a/cpu/arm920t/config.mk +++ b/cpu/arm920t/config.mk @@ -21,8 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float PLATFORM_CPPFLAGS += -march=armv4 # ========================================================================= diff --git a/cpu/arm925t/config.mk b/cpu/arm925t/config.mk index a43b1567110..8f6c1a354c5 100644 --- a/cpu/arm925t/config.mk +++ b/cpu/arm925t/config.mk @@ -21,8 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float PLATFORM_CPPFLAGS += -march=armv4 # ========================================================================= diff --git a/cpu/arm926ejs/config.mk b/cpu/arm926ejs/config.mk index 90eb3c0edec..f8ef90f2d51 100644 --- a/cpu/arm926ejs/config.mk +++ b/cpu/arm926ejs/config.mk @@ -21,8 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float PLATFORM_CPPFLAGS += -march=armv5te # ========================================================================= diff --git a/cpu/arm926ejs/davinci/config.mk b/cpu/arm926ejs/davinci/config.mk index 7757be398ae..565adda11d4 100644 --- a/cpu/arm926ejs/davinci/config.mk +++ b/cpu/arm926ejs/davinci/config.mk @@ -21,8 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float PLATFORM_CPPFLAGS += -march=armv5te # ========================================================================= diff --git a/cpu/arm946es/config.mk b/cpu/arm946es/config.mk index a81321bd3cc..e783f697a10 100644 --- a/cpu/arm946es/config.mk +++ b/cpu/arm946es/config.mk @@ -21,8 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float PLATFORM_CPPFLAGS += -march=armv4 # ========================================================================= diff --git a/cpu/arm_cortexa8/config.mk b/cpu/arm_cortexa8/config.mk index da5ee162c5f..49ac9c74aeb 100644 --- a/cpu/arm_cortexa8/config.mk +++ b/cpu/arm_cortexa8/config.mk @@ -20,8 +20,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float # Make ARMv5 to allow more compilers to work, even though its v7a. PLATFORM_CPPFLAGS += -march=armv5 diff --git a/cpu/arm_intcm/config.mk b/cpu/arm_intcm/config.mk index a81321bd3cc..e783f697a10 100644 --- a/cpu/arm_intcm/config.mk +++ b/cpu/arm_intcm/config.mk @@ -21,8 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float PLATFORM_CPPFLAGS += -march=armv4 # ========================================================================= diff --git a/cpu/ixp/config.mk b/cpu/ixp/config.mk index 2c33b40a2cb..deca3f4d550 100644 --- a/cpu/ixp/config.mk +++ b/cpu/ixp/config.mk @@ -24,8 +24,7 @@ BIG_ENDIAN = y -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float -mbig-endian +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float -mbig-endian PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100 # ========================================================================= diff --git a/cpu/lh7a40x/config.mk b/cpu/lh7a40x/config.mk index 27bc4812606..47b2b7b722d 100644 --- a/cpu/lh7a40x/config.mk +++ b/cpu/lh7a40x/config.mk @@ -21,8 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float PLATFORM_CPPFLAGS += -march=armv4 # ========================================================================= diff --git a/cpu/pxa/config.mk b/cpu/pxa/config.mk index f360478d0c2..a05d69ca270 100644 --- a/cpu/pxa/config.mk +++ b/cpu/pxa/config.mk @@ -22,8 +22,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float PLATFORM_CPPFLAGS += -march=armv5te -mtune=xscale # ========================================================================= diff --git a/cpu/s3c44b0/config.mk b/cpu/s3c44b0/config.mk index 3623f2503e2..7454d728a55 100644 --- a/cpu/s3c44b0/config.mk +++ b/cpu/s3c44b0/config.mk @@ -22,8 +22,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi -msoft-float # ========================================================================= diff --git a/cpu/sa1100/config.mk b/cpu/sa1100/config.mk index 553cd0c9cfc..6f21f410be3 100644 --- a/cpu/sa1100/config.mk +++ b/cpu/sa1100/config.mk @@ -22,8 +22,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100 # ========================================================================= From d8bc55a6fb28876abcbf4a3fc3b6c3ce429c1bb3 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Tue, 1 Sep 2009 20:58:03 +0400 Subject: [PATCH 034/208] Move uninitialized_var() macro from ubi_uboot.h to compiler.h This is needed so that we could use this macro for non-UBI code. Signed-off-by: Anton Vorontsov --- include/compiler.h | 3 +++ include/ubi_uboot.h | 4 +--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/include/compiler.h b/include/compiler.h index 272fd3cf628..e602cce2e9b 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -122,4 +122,7 @@ typedef unsigned int uintptr_t; #endif +/* compiler options */ +#define uninitialized_var(x) x = x + #endif diff --git a/include/ubi_uboot.h b/include/ubi_uboot.h index 74312abf039..60f6a5fb4f5 100644 --- a/include/ubi_uboot.h +++ b/include/ubi_uboot.h @@ -15,6 +15,7 @@ #define __UBOOT_UBI_H #include +#include #include #include #include @@ -51,9 +52,6 @@ do { \ #undef CONFIG_MTD_UBI_DEBUG_MSG_BLD #define CONFIG_MTD_UBI_DEBUG_DISABLE_BGT -/* compiler options */ -#define uninitialized_var(x) x = x - /* build.c */ #define get_device(...) #define put_device(...) From 37daa77f3cafb5ec9a974eff3db2af4a0560a9ef Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 2 Sep 2009 10:21:20 +0200 Subject: [PATCH 035/208] cmd_mtdparts.c: fix compiler warning in debug code Fix warning messages: cmd_mtdparts.c:1429: warning: format '%08lx' expects type 'long unsigned int', but argument 6 has type 'u32' cmd_mtdparts.c:1429: warning: format '%08lx' expects type 'long unsigned int', but argument 7 has type 'u32' Signed-off-by: Wolfgang Denk --- common/cmd_mtdparts.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/cmd_mtdparts.c b/common/cmd_mtdparts.c index 665995d16bf..b375feaad19 100644 --- a/common/cmd_mtdparts.c +++ b/common/cmd_mtdparts.c @@ -1336,7 +1336,7 @@ static int delete_partition(const char *id) if (find_dev_and_part(id, &dev, &pnum, &part) == 0) { - DEBUGF("delete_partition: device = %s%d, partition %d = (%s) 0x%08lx@0x%08lx\n", + DEBUGF("delete_partition: device = %s%d, partition %d = (%s) 0x%08x@0x%08x\n", MTD_DEV_TYPE(dev->id->type), dev->id->num, pnum, part->name, part->size, part->offset); From 46ff6d461321f5b565cc790e02679237ffd9a20f Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 2 Sep 2009 14:57:27 +0200 Subject: [PATCH 036/208] License cleanup: remove unintended "All Rights Reserved" notices. Some files included my old standerd file header which had a "All Rights Reserved" part. As this has never been my intention, I remove these lines to make the files compatible with GPL v.2 and later. Signed-off-by: Wolfgang Denk --- board/lwmon/lwmon.c | 1 - drivers/input/keyboard.c | 1 - drivers/input/pc_keyb.c | 1 - drivers/input/ps2mult.c | 1 - drivers/input/ps2ser.c | 1 - tools/mkimage.c | 1 - tools/mkimage.h | 1 - 7 files changed, 7 deletions(-) diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c index 75b32090d19..8e277789396 100644 --- a/board/lwmon/lwmon.c +++ b/board/lwmon/lwmon.c @@ -7,7 +7,6 @@ M* Content: LWMON specific U-Boot commands. * (C) Copyright 2001, 2002 * DENX Software Engineering * Wolfgang Denk, wd@denx.de - * All rights reserved. * D* Design: wd@denx.de C* Coding: wd@denx.de diff --git a/drivers/input/keyboard.c b/drivers/input/keyboard.c index a5fbd5f5095..614592ef3c1 100644 --- a/drivers/input/keyboard.c +++ b/drivers/input/keyboard.c @@ -3,7 +3,6 @@ * (C) Copyright 2004 * DENX Software Engineering * Wolfgang Denk, wd@denx.de - * All rights reserved. * * Keyboard driver * diff --git a/drivers/input/pc_keyb.c b/drivers/input/pc_keyb.c index 25ad3e40650..1606ab33ff4 100644 --- a/drivers/input/pc_keyb.c +++ b/drivers/input/pc_keyb.c @@ -3,7 +3,6 @@ * (C) Copyright 2004 * DENX Software Engineering * Wolfgang Denk, wd@denx.de - * All rights reserved. * * PS/2 keyboard driver * diff --git a/drivers/input/ps2mult.c b/drivers/input/ps2mult.c index ecd585323f9..ab749336bf5 100644 --- a/drivers/input/ps2mult.c +++ b/drivers/input/ps2mult.c @@ -3,7 +3,6 @@ * (C) Copyright 2004 * DENX Software Engineering * Wolfgang Denk, wd@denx.de - * All rights reserved. * * PS/2 multiplexer driver * diff --git a/drivers/input/ps2ser.c b/drivers/input/ps2ser.c index 1a5e2d43dba..1b20a76c4c3 100644 --- a/drivers/input/ps2ser.c +++ b/drivers/input/ps2ser.c @@ -3,7 +3,6 @@ * (C) Copyright 2004-2009 * DENX Software Engineering * Wolfgang Denk, wd@denx.de - * All rights reserved. * * Simple 16550A serial driver * diff --git a/tools/mkimage.c b/tools/mkimage.c index 02cdb953877..7fd9fd1aeb8 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -4,7 +4,6 @@ * (C) Copyright 2000-2004 * DENX Software Engineering * Wolfgang Denk, wd@denx.de - * All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/tools/mkimage.h b/tools/mkimage.h index 70c53add169..c077dc955ff 100644 --- a/tools/mkimage.h +++ b/tools/mkimage.h @@ -2,7 +2,6 @@ * (C) Copyright 2000-2004 * DENX Software Engineering * Wolfgang Denk, wd@denx.de - * All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as From 001d615681333569c555e6cde07d8d23e2c536fb Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Wed, 2 Sep 2009 17:58:48 +0400 Subject: [PATCH 037/208] mpc83xx/serdes: License cleanup: remove "All Rights Reserved" notice "All Rights Reserved" conflicts with the GPL. Signed-off-by: Anton Vorontsov --- cpu/mpc83xx/serdes.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cpu/mpc83xx/serdes.c b/cpu/mpc83xx/serdes.c index 283cc3f4108..64033fe4c35 100644 --- a/cpu/mpc83xx/serdes.c +++ b/cpu/mpc83xx/serdes.c @@ -2,7 +2,7 @@ * Freescale SerDes initialization routine * * Copyright (C) 2007 Freescale Semicondutor, Inc. - * Copyright (C) 2008 MontaVista Software, Inc. All rights reserved. + * Copyright (C) 2008 MontaVista Software, Inc. * * Author: Li Yang * From cfcbf8c4cf3da96b9e3f652506b664bfd766a520 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Wed, 2 Sep 2009 16:45:31 -0500 Subject: [PATCH 038/208] mxc_nand: Remove Freescale's "All Rights Reserved." Signed-off-by: Scott Wood --- drivers/mtd/nand/mxc_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 647be0b7ef3..eb0323f2130 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2007 Freescale Semiconductor, Inc. * Copyright 2008 Sascha Hauer, kernel@pengutronix.de * Copyright 2009 Ilya Yanok, * From 7662eb2b9d6fbc95ecb1fb3e5b5147215e251e7d Mon Sep 17 00:00:00 2001 From: Giuseppe CONDORELLI Date: Thu, 3 Sep 2009 07:37:46 -0400 Subject: [PATCH 039/208] zlib: fix code when DEBUG is defined Removed stdio.h inclusion and moved trace macros to use printf avoiding to write debug informations to standard error. Signed-off-by: Giuseppe Condorelli --- lib_generic/zlib.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/lib_generic/zlib.c b/lib_generic/zlib.c index 1b6db3214e9..8fe3bd0dd12 100644 --- a/lib_generic/zlib.c +++ b/lib_generic/zlib.c @@ -27,6 +27,7 @@ #define ZLIB_INTERNAL #include "u-boot/zlib.h" +#include /* To avoid a build time warning */ #ifdef STDC #include @@ -83,10 +84,10 @@ typedef unsigned long ulg; /* Diagnostic functions */ #ifdef DEBUG -#include extern int z_verbose; extern void z_error OF((char *m)); #define Assert(cond,msg) {if(!(cond)) z_error(msg);} +#define fprintf(fp,...) printf(__VA_ARGS__) #define Trace(x) {if (z_verbose>=0) fprintf x ;} #define Tracev(x) {if (z_verbose>0) fprintf x ;} #define Tracevv(x) {if (z_verbose>1) fprintf x ;} @@ -2000,7 +2001,7 @@ void z_error (m) char *m; { fprintf(stderr, "%s\n", m); - exit(1); + hang (); } #endif From 262ae0a6193f10b6a94e86d2f752e7f5510416fa Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 3 Sep 2009 23:12:47 -0400 Subject: [PATCH 040/208] push LOAD_ADDR out to arch mk files Rather than maintain/extend the current ifeq($(ARCH)) mess that exists in the standalone Makefile, push the setting up of LOAD_ADDR out to the arch config.mk (and rename to STANDALONE_LOAD_ADDR in the process). This keeps the common code clean and lets the arch do whatever crazy crap it wants in its own area. Signed-off-by: Mike Frysinger --- examples/standalone/Makefile | 65 +----------------------------------- lib_arm/config.mk | 10 ++++++ lib_avr32/config.mk | 2 ++ lib_blackfin/config.mk | 2 ++ lib_i386/config.mk | 2 ++ lib_m68k/config.mk | 3 ++ lib_microblaze/config.mk | 2 ++ lib_mips/config.mk | 2 ++ lib_nios/config.mk | 2 ++ lib_nios2/config.mk | 2 ++ lib_ppc/config.mk | 2 ++ lib_sh/config.mk | 5 +++ lib_sparc/config.mk | 2 ++ 13 files changed, 37 insertions(+), 64 deletions(-) diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index 9a9b6c38eff..bc98120a51f 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -21,65 +21,6 @@ # MA 02111-1307 USA # -ifeq ($(ARCH),ppc) -LOAD_ADDR = 0x40000 -endif - -ifeq ($(ARCH),i386) -LOAD_ADDR = 0x40000 -endif - -ifeq ($(ARCH),arm) -ifeq ($(BOARD),omap2420h4) -LOAD_ADDR = 0x80300000 -else -ifeq ($(SOC),omap3) -LOAD_ADDR = 0x80300000 -else -LOAD_ADDR = 0xc100000 -endif -endif -endif - -ifeq ($(ARCH),mips) -LOAD_ADDR = 0x80200000 -T mips.lds -endif - -ifeq ($(ARCH),nios) -LOAD_ADDR = 0x00800000 -L $(gcclibdir)/m32 -T nios.lds -endif - -ifeq ($(ARCH),nios2) -LOAD_ADDR = 0x02000000 -L $(gcclibdir) -T nios2.lds -endif - -ifeq ($(ARCH),m68k) -LOAD_ADDR = 0x20000 -L $(clibdir) -endif - -ifeq ($(ARCH),microblaze) -LOAD_ADDR = 0x80F00000 -endif - -ifeq ($(ARCH),blackfin) -LOAD_ADDR = 0x1000 -endif - -ifeq ($(ARCH),avr32) -LOAD_ADDR = 0x00000000 -endif - -ifeq ($(ARCH),sh) -LOAD_ADDR = 0x8C000000 -ifeq ($(CPU),sh2) -BIG_ENDIAN=y -endif -endif - -ifeq ($(ARCH),sparc) -LOAD_ADDR = 0x00000000 -L $(gcclibdir) -T sparc.lds -endif - include $(TOPDIR)/config.mk ELF = hello_world @@ -143,9 +84,6 @@ SREC += eepro100_eeprom.srec BIN += eepro100_eeprom.bin endif -ifeq ($(BIG_ENDIAN),y) -EX_LDFLAGS += -EB -endif COBJS := $(SREC:.srec=.o) @@ -168,7 +106,6 @@ BIN := $(addprefix $(obj),$(BIN)) SREC := $(addprefix $(obj),$(SREC)) gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) -clibdir := $(shell dirname `$(CC) $(CFLAGS) -print-file-name=libc.a`) CPPFLAGS += -I.. @@ -180,7 +117,7 @@ $(LIB): $(obj).depend $(LIBOBJS) $(ELF): $(obj)%: $(obj)%.o $(LIB) - $(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \ + $(LD) -g -Ttext $(STANDALONE_LOAD_ADDR) \ -o $@ -e $(SYM_PREFIX)$(notdir $(<:.o=)) $< $(LIB) \ -L$(gcclibdir) -lgcc diff --git a/lib_arm/config.mk b/lib_arm/config.mk index 705dfc306c4..3c078df3c12 100644 --- a/lib_arm/config.mk +++ b/lib_arm/config.mk @@ -23,6 +23,16 @@ CROSS_COMPILE ?= arm-linux- +ifeq ($(BOARD),omap2420h4) +STANDALONE_LOAD_ADDR = 0x80300000 +else +ifeq ($(SOC),omap3) +STANDALONE_LOAD_ADDR = 0x80300000 +else +STANDALONE_LOAD_ADDR = 0xc100000 +endif +endif + PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__ # Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb: diff --git a/lib_avr32/config.mk b/lib_avr32/config.mk index c258b4b55d1..1121ca1cc25 100644 --- a/lib_avr32/config.mk +++ b/lib_avr32/config.mk @@ -23,5 +23,7 @@ CROSS_COMPILE ?= avr32-linux- +STANDALONE_LOAD_ADDR = 0x00000000 + PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax PLATFORM_LDFLAGS += --relax diff --git a/lib_blackfin/config.mk b/lib_blackfin/config.mk index 34b53e6903b..ce2fe6773ed 100644 --- a/lib_blackfin/config.mk +++ b/lib_blackfin/config.mk @@ -23,6 +23,8 @@ CROSS_COMPILE ?= bfin-uclinux- +STANDALONE_LOAD_ADDR = 0x1000 + CONFIG_BFIN_CPU := $(strip $(subst ",,$(CONFIG_BFIN_CPU))) CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE))) CONFIG_ENV_OFFSET := $(strip $(subst ",,$(CONFIG_ENV_OFFSET))) diff --git a/lib_i386/config.mk b/lib_i386/config.mk index 5fe36d5f3c9..4b990e04ef2 100644 --- a/lib_i386/config.mk +++ b/lib_i386/config.mk @@ -23,4 +23,6 @@ CROSS_COMPILE ?= i386-linux- +STANDALONE_LOAD_ADDR = 0x40000 + PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__ diff --git a/lib_m68k/config.mk b/lib_m68k/config.mk index f41d1b3c2aa..749c38968ab 100644 --- a/lib_m68k/config.mk +++ b/lib_m68k/config.mk @@ -23,5 +23,8 @@ CROSS_COMPILE ?= m68k-elf- +clibdir = $(shell dirname `$(CC) $(CFLAGS) -print-file-name=libc.a`) +STANDALONE_LOAD_ADDR = 0x20000 -L $(clibdir) + PLATFORM_CPPFLAGS += -DCONFIG_M68K -D__M68K__ PLATFORM_LDFLAGS += -n diff --git a/lib_microblaze/config.mk b/lib_microblaze/config.mk index 68e7e214bf2..c3c9f958c0b 100644 --- a/lib_microblaze/config.mk +++ b/lib_microblaze/config.mk @@ -26,4 +26,6 @@ CROSS_COMPILE ?= mb- +STANDALONE_LOAD_ADDR = 0x80F00000 + PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__ diff --git a/lib_mips/config.mk b/lib_mips/config.mk index c785677fc85..aa06761ae35 100644 --- a/lib_mips/config.mk +++ b/lib_mips/config.mk @@ -23,6 +23,8 @@ CROSS_COMPILE ?= mips_4KC- +STANDALONE_LOAD_ADDR = 0x80200000 -T mips.lds + PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ # diff --git a/lib_nios/config.mk b/lib_nios/config.mk index 3ed7170b800..d48aa6dfd4e 100644 --- a/lib_nios/config.mk +++ b/lib_nios/config.mk @@ -24,4 +24,6 @@ CROSS_COMPILE ?= nios-elf- +STANDALONE_LOAD_ADDR = 0x00800000 -L $(gcclibdir)/m32 -T nios.lds + PLATFORM_CPPFLAGS += -m32 -DCONFIG_NIOS -D__NIOS__ -ffixed-g7 -gstabs diff --git a/lib_nios2/config.mk b/lib_nios2/config.mk index 59931c25b5f..34ee6977d93 100644 --- a/lib_nios2/config.mk +++ b/lib_nios2/config.mk @@ -24,5 +24,7 @@ CROSS_COMPILE ?= nios2-elf- +STANDALONE_LOAD_ADDR = 0x02000000 -L $(gcclibdir) -T nios2.lds + PLATFORM_CPPFLAGS += -DCONFIG_NIOS2 -D__NIOS2__ PLATFORM_CPPFLAGS += -ffixed-r15 -G0 diff --git a/lib_ppc/config.mk b/lib_ppc/config.mk index d91ef7f0b50..010d874da68 100644 --- a/lib_ppc/config.mk +++ b/lib_ppc/config.mk @@ -23,6 +23,8 @@ CROSS_COMPILE ?= ppc_8xx- +STANDALONE_LOAD_ADDR = 0x40000 + PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__ PLATFORM_LDFLAGS += -n diff --git a/lib_sh/config.mk b/lib_sh/config.mk index 67d7e9e6cc0..fa5369fd084 100644 --- a/lib_sh/config.mk +++ b/lib_sh/config.mk @@ -23,6 +23,11 @@ CROSS_COMPILE ?= sh4-linux- +STANDALONE_LOAD_ADDR = 0x8C000000 +ifeq ($(CPU),sh2) +STANDALONE_LOAD_ADDR += -EB +endif + PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__ PLATFORM_LDFLAGS += -e $(TEXT_BASE) --defsym reloc_dst=$(TEXT_BASE) diff --git a/lib_sparc/config.mk b/lib_sparc/config.mk index 07b528c3d5d..4de6515ef49 100644 --- a/lib_sparc/config.mk +++ b/lib_sparc/config.mk @@ -23,4 +23,6 @@ CROSS_COMPILE ?= sparc-elf- +STANDALONE_LOAD_ADDR = 0x00000000 -L $(gcclibdir) -T sparc.lds + PLATFORM_CPPFLAGS += -DCONFIG_SPARC -D__sparc__ From 9f23ca42b3ba19b24e66fade572f2b86d929b6e8 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 4 Sep 2009 23:20:29 +0200 Subject: [PATCH 041/208] ARM: Update mach-types Signed-off-by: Wolfgang Denk --- include/asm-arm/mach-types.h | 2068 +++++++++++++++++++++++++++++++++- 1 file changed, 2056 insertions(+), 12 deletions(-) diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index 5293d679eb0..6c1f5ac4e6c 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -1,6 +1,9 @@ /* - * This was automagically generated from arch/arm/tools/mach-types! + * This was automagically generated from mach-types! * Do NOT edit + * + * Last update: Fri Sep 4 22:16:22 2009 + * */ #ifndef __ASM_ARM_MACH_TYPE_H @@ -1451,7 +1454,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_H6044 1458 #define MACH_TYPE_APP 1459 #define MACH_TYPE_TCT_HAMMER 1460 -#define MACH_TYPE_HERMES 1461 +#define MACH_TYPE_HERALD 1461 #define MACH_TYPE_ARTEMIS 1462 #define MACH_TYPE_HTCTITAN 1463 #define MACH_TYPE_QRANIUM 1464 @@ -1765,7 +1768,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_MI424WR 1778 #define MACH_TYPE_AXS_ULTRAX 1779 #define MACH_TYPE_AT572D940DEB 1780 -#define MACH_TYPE_DAVINCI_DA8XX_EVM 1781 +#define MACH_TYPE_DAVINCI_DA830_EVM 1781 #define MACH_TYPE_EP9302 1782 #define MACH_TYPE_AT572D940HFEB 1783 #define MACH_TYPE_CYBOOK3 1784 @@ -2241,6 +2244,163 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_OMAP3_WL_FF 2258 #define MACH_TYPE_SIMCOM 2259 #define MACH_TYPE_MCWEBIO 2260 +#define MACH_TYPE_OMAP3_PHRAZER 2261 +#define MACH_TYPE_DARWIN 2262 +#define MACH_TYPE_ORATISCOMU 2263 +#define MACH_TYPE_RTSBC20 2264 +#define MACH_TYPE_I780 2265 +#define MACH_TYPE_GEMINI324 2266 +#define MACH_TYPE_ORATISLAN 2267 +#define MACH_TYPE_ORATISALOG 2268 +#define MACH_TYPE_ORATISMADI 2269 +#define MACH_TYPE_ORATISOT16 2270 +#define MACH_TYPE_ORATISDESK 2271 +#define MACH_TYPE_V2P_CA9 2272 +#define MACH_TYPE_SINTEXO 2273 +#define MACH_TYPE_CM3389 2274 +#define MACH_TYPE_OMAP3_CIO 2275 +#define MACH_TYPE_SGH_I900 2276 +#define MACH_TYPE_BST100 2277 +#define MACH_TYPE_PASSION 2278 +#define MACH_TYPE_INDESIGN_AT91SAM 2279 +#define MACH_TYPE_C4_BADGER 2280 +#define MACH_TYPE_C4_VIPER 2281 +#define MACH_TYPE_D2NET 2282 +#define MACH_TYPE_BIGDISK 2283 +#define MACH_TYPE_NOTALVISION 2284 +#define MACH_TYPE_OMAP3_KBOC 2285 +#define MACH_TYPE_CYCLONE 2286 +#define MACH_TYPE_NINJA 2287 +#define MACH_TYPE_AT91SAM9G20EK_2MMC 2288 +#define MACH_TYPE_BCMRING 2289 +#define MACH_TYPE_RESOL_DL2 2290 +#define MACH_TYPE_IFOSW 2291 +#define MACH_TYPE_HTCRHODIUM 2292 +#define MACH_TYPE_HTCTOPAZ 2293 +#define MACH_TYPE_MATRIX504 2294 +#define MACH_TYPE_MRFSA 2295 +#define MACH_TYPE_SC_P270 2296 +#define MACH_TYPE_ATLAS5_EVB 2297 +#define MACH_TYPE_PELCO_LOBOX 2298 +#define MACH_TYPE_DILAX_PCU200 2299 +#define MACH_TYPE_LEONARDO 2300 +#define MACH_TYPE_ZORAN_APPROACH7 2301 +#define MACH_TYPE_DP6XX 2302 +#define MACH_TYPE_BCM2153_VESPER 2303 +#define MACH_TYPE_MAHIMAHI 2304 +#define MACH_TYPE_CLICKC 2305 +#define MACH_TYPE_ZB_GATEWAY 2306 +#define MACH_TYPE_TAZCARD 2307 +#define MACH_TYPE_TAZDEV 2308 +#define MACH_TYPE_ANNAX_CB_ARM 2309 +#define MACH_TYPE_ANNAX_DM3 2310 +#define MACH_TYPE_CEREBRIC 2311 +#define MACH_TYPE_ORCA 2312 +#define MACH_TYPE_PC9260 2313 +#define MACH_TYPE_EMS285A 2314 +#define MACH_TYPE_GEC2410 2315 +#define MACH_TYPE_GEC2440 2316 +#define MACH_TYPE_ARCH_MW903 2317 +#define MACH_TYPE_MW2440 2318 +#define MACH_TYPE_ECAC2378 2319 +#define MACH_TYPE_TAZKIOSK 2320 +#define MACH_TYPE_WHITERABBIT_MCH 2321 +#define MACH_TYPE_SBOX9263 2322 +#define MACH_TYPE_OREO 2323 +#define MACH_TYPE_SMDK6442 2324 +#define MACH_TYPE_OPENRD_BASE 2325 +#define MACH_TYPE_INCREDIBLE 2326 +#define MACH_TYPE_INCREDIBLEC 2327 +#define MACH_TYPE_HEROCT 2328 +#define MACH_TYPE_MMNET1000 2329 +#define MACH_TYPE_DEVKIT8000 2330 +#define MACH_TYPE_DEVKIT9000 2331 +#define MACH_TYPE_MX31TXTR 2332 +#define MACH_TYPE_U380 2333 +#define MACH_TYPE_HUALU_BOARD 2334 +#define MACH_TYPE_NPCMX50 2335 +#define MACH_TYPE_MX51_LANGE51 2336 +#define MACH_TYPE_MX51_LANGE52 2337 +#define MACH_TYPE_RIOM 2338 +#define MACH_TYPE_COMCAS 2339 +#define MACH_TYPE_WSI_MX27 2340 +#define MACH_TYPE_CM_T35 2341 +#define MACH_TYPE_NET2BIG 2342 +#define MACH_TYPE_MOTOROLA_A1600 2343 +#define MACH_TYPE_IGEP0020 2344 +#define MACH_TYPE_IGEP0010 2345 +#define MACH_TYPE_MV6281GTWGE2 2346 +#define MACH_TYPE_SCAT100 2347 +#define MACH_TYPE_SANMINA 2348 +#define MACH_TYPE_MOMENTO 2349 +#define MACH_TYPE_NUC9XX 2350 +#define MACH_TYPE_NUC910EVB 2351 +#define MACH_TYPE_NUC920EVB 2352 +#define MACH_TYPE_NUC950EVB 2353 +#define MACH_TYPE_NUC945EVB 2354 +#define MACH_TYPE_NUC960EVB 2355 +#define MACH_TYPE_NUC932EVB 2356 +#define MACH_TYPE_NUC900 2357 +#define MACH_TYPE_SD1SOC 2358 +#define MACH_TYPE_LN2440BC 2359 +#define MACH_TYPE_RSBC 2360 +#define MACH_TYPE_OPENRD_CLIENT 2361 +#define MACH_TYPE_HPIPAQ11X 2362 +#define MACH_TYPE_WAYLAND 2363 +#define MACH_TYPE_ACNBSX102 2364 +#define MACH_TYPE_HWAT91 2365 +#define MACH_TYPE_AT91SAM9263CS 2366 +#define MACH_TYPE_CSB732 2367 +#define MACH_TYPE_U8500 2368 +#define MACH_TYPE_HUQIU 2369 +#define MACH_TYPE_MX51_KUNLUN 2370 +#define MACH_TYPE_PMT1G 2371 +#define MACH_TYPE_HTCELF 2372 +#define MACH_TYPE_ARMADILLO420 2373 +#define MACH_TYPE_ARMADILLO440 2374 +#define MACH_TYPE_U_CHIP_DUAL_ARM 2375 +#define MACH_TYPE_CSR_BDB3 2376 +#define MACH_TYPE_DOLBY_CAT1018 2377 +#define MACH_TYPE_HY9307 2378 +#define MACH_TYPE_A_ES 2379 +#define MACH_TYPE_DAVINCI_IRIF 2380 +#define MACH_TYPE_AGAMA9263 2381 +#define MACH_TYPE_MARVELL_JASPER 2382 +#define MACH_TYPE_FLINT 2383 +#define MACH_TYPE_TAVOREVB3 2384 +#define MACH_TYPE_SCH_M490 2386 +#define MACH_TYPE_RBL01 2387 +#define MACH_TYPE_OMNIFI 2388 +#define MACH_TYPE_OTAVALO 2389 +#define MACH_TYPE_SIENNA 2390 +#define MACH_TYPE_HTC_EXCALIBUR_S620 2391 +#define MACH_TYPE_HTC_OPAL 2392 +#define MACH_TYPE_TOUCHBOOK 2393 +#define MACH_TYPE_LATTE 2394 +#define MACH_TYPE_XA200 2395 +#define MACH_TYPE_NIMROD 2396 +#define MACH_TYPE_CC9P9215_3G 2397 +#define MACH_TYPE_CC9P9215_3GJS 2398 +#define MACH_TYPE_TK71 2399 +#define MACH_TYPE_COMHAM3525 2400 +#define MACH_TYPE_MX31EREBUS 2401 +#define MACH_TYPE_MCARDMX27 2402 +#define MACH_TYPE_PARADISE 2403 +#define MACH_TYPE_TIDE 2404 +#define MACH_TYPE_WZL2440 2405 +#define MACH_TYPE_SDRDEMO 2406 +#define MACH_TYPE_ETHERCAN2 2407 +#define MACH_TYPE_ECMIMG20 2408 +#define MACH_TYPE_OMAP_DRAGON 2409 +#define MACH_TYPE_HALO 2410 +#define MACH_TYPE_HUANGSHAN 2411 +#define MACH_TYPE_VL_MA2SC 2412 +#define MACH_TYPE_RAUMFELD_RC 2413 +#define MACH_TYPE_RAUMFELD_CONNECTOR 2414 +#define MACH_TYPE_RAUMFELD_SPEAKER 2415 +#define MACH_TYPE_MULTIBUS_MASTER 2416 +#define MACH_TYPE_MULTIBUS_PBK 2417 +#define MACH_TYPE_TNETV107X 2418 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -19510,14 +19670,14 @@ extern unsigned int __machine_arch_type; # define machine_is_tct_hammer() (0) #endif -#ifdef CONFIG_MACH_HERMES +#ifdef CONFIG_MACH_HERALD # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_HERMES +# define machine_arch_type MACH_TYPE_HERALD # endif -# define machine_is_herald() (machine_arch_type == MACH_TYPE_HERMES) +# define machine_is_herald() (machine_arch_type == MACH_TYPE_HERALD) #else # define machine_is_herald() (0) #endif @@ -23278,16 +23438,16 @@ extern unsigned int __machine_arch_type; # define machine_is_at572d940deb() (0) #endif -#ifdef CONFIG_MACH_DAVINCI_DA8XX_EVM +#ifdef CONFIG_MACH_DAVINCI_DA830_EVM # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_DAVINCI_DA8XX_EVM +# define machine_arch_type MACH_TYPE_DAVINCI_DA830_EVM # endif -# define machine_is_davinci_da8xx_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DA8XX_EVM) +# define machine_is_davinci_da830_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM) #else -# define machine_is_davinci_da8xx_evm() (0) +# define machine_is_davinci_da830_evm() (0) #endif #ifdef CONFIG_MACH_EP9302 @@ -25601,9 +25761,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_CPUIMX27 # endif -# define machine_is_cpuimx27() (machine_arch_type == MACH_TYPE_CPUIMX27) +# define machine_is_eukrea_cpuimx27() (machine_arch_type == MACH_TYPE_CPUIMX27) #else -# define machine_is_cpuimx27() (0) +# define machine_is_eukrea_cpuimx27() (0) #endif #ifdef CONFIG_MACH_CHEFLUX @@ -28990,6 +29150,1890 @@ extern unsigned int __machine_arch_type; # define machine_is_mcwebio() (0) #endif +#ifdef CONFIG_MACH_OMAP3_PHRAZER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_PHRAZER +# endif +# define machine_is_omap3_phrazer() (machine_arch_type == MACH_TYPE_OMAP3_PHRAZER) +#else +# define machine_is_omap3_phrazer() (0) +#endif + +#ifdef CONFIG_MACH_DARWIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DARWIN +# endif +# define machine_is_darwin() (machine_arch_type == MACH_TYPE_DARWIN) +#else +# define machine_is_darwin() (0) +#endif + +#ifdef CONFIG_MACH_ORATISCOMU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISCOMU +# endif +# define machine_is_oratiscomu() (machine_arch_type == MACH_TYPE_ORATISCOMU) +#else +# define machine_is_oratiscomu() (0) +#endif + +#ifdef CONFIG_MACH_RTSBC20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RTSBC20 +# endif +# define machine_is_rtsbc20() (machine_arch_type == MACH_TYPE_RTSBC20) +#else +# define machine_is_rtsbc20() (0) +#endif + +#ifdef CONFIG_MACH_I780 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_I780 +# endif +# define machine_is_sgh_i780() (machine_arch_type == MACH_TYPE_I780) +#else +# define machine_is_sgh_i780() (0) +#endif + +#ifdef CONFIG_MACH_GEMINI324 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GEMINI324 +# endif +# define machine_is_gemini324() (machine_arch_type == MACH_TYPE_GEMINI324) +#else +# define machine_is_gemini324() (0) +#endif + +#ifdef CONFIG_MACH_ORATISLAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISLAN +# endif +# define machine_is_oratislan() (machine_arch_type == MACH_TYPE_ORATISLAN) +#else +# define machine_is_oratislan() (0) +#endif + +#ifdef CONFIG_MACH_ORATISALOG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISALOG +# endif +# define machine_is_oratisalog() (machine_arch_type == MACH_TYPE_ORATISALOG) +#else +# define machine_is_oratisalog() (0) +#endif + +#ifdef CONFIG_MACH_ORATISMADI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISMADI +# endif +# define machine_is_oratismadi() (machine_arch_type == MACH_TYPE_ORATISMADI) +#else +# define machine_is_oratismadi() (0) +#endif + +#ifdef CONFIG_MACH_ORATISOT16 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISOT16 +# endif +# define machine_is_oratisot16() (machine_arch_type == MACH_TYPE_ORATISOT16) +#else +# define machine_is_oratisot16() (0) +#endif + +#ifdef CONFIG_MACH_ORATISDESK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISDESK +# endif +# define machine_is_oratisdesk() (machine_arch_type == MACH_TYPE_ORATISDESK) +#else +# define machine_is_oratisdesk() (0) +#endif + +#ifdef CONFIG_MACH_V2P_CA9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_V2P_CA9 +# endif +# define machine_is_v2_ca9() (machine_arch_type == MACH_TYPE_V2P_CA9) +#else +# define machine_is_v2_ca9() (0) +#endif + +#ifdef CONFIG_MACH_SINTEXO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SINTEXO +# endif +# define machine_is_sintexo() (machine_arch_type == MACH_TYPE_SINTEXO) +#else +# define machine_is_sintexo() (0) +#endif + +#ifdef CONFIG_MACH_CM3389 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM3389 +# endif +# define machine_is_cm3389() (machine_arch_type == MACH_TYPE_CM3389) +#else +# define machine_is_cm3389() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_CIO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_CIO +# endif +# define machine_is_omap3_cio() (machine_arch_type == MACH_TYPE_OMAP3_CIO) +#else +# define machine_is_omap3_cio() (0) +#endif + +#ifdef CONFIG_MACH_SGH_I900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SGH_I900 +# endif +# define machine_is_sgh_i900() (machine_arch_type == MACH_TYPE_SGH_I900) +#else +# define machine_is_sgh_i900() (0) +#endif + +#ifdef CONFIG_MACH_BST100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BST100 +# endif +# define machine_is_bst100() (machine_arch_type == MACH_TYPE_BST100) +#else +# define machine_is_bst100() (0) +#endif + +#ifdef CONFIG_MACH_PASSION +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PASSION +# endif +# define machine_is_passion() (machine_arch_type == MACH_TYPE_PASSION) +#else +# define machine_is_passion() (0) +#endif + +#ifdef CONFIG_MACH_INDESIGN_AT91SAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INDESIGN_AT91SAM +# endif +# define machine_is_indesign_at91sam() (machine_arch_type == MACH_TYPE_INDESIGN_AT91SAM) +#else +# define machine_is_indesign_at91sam() (0) +#endif + +#ifdef CONFIG_MACH_C4_BADGER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_C4_BADGER +# endif +# define machine_is_c4_badger() (machine_arch_type == MACH_TYPE_C4_BADGER) +#else +# define machine_is_c4_badger() (0) +#endif + +#ifdef CONFIG_MACH_C4_VIPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_C4_VIPER +# endif +# define machine_is_c4_viper() (machine_arch_type == MACH_TYPE_C4_VIPER) +#else +# define machine_is_c4_viper() (0) +#endif + +#ifdef CONFIG_MACH_D2NET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_D2NET +# endif +# define machine_is_d2net() (machine_arch_type == MACH_TYPE_D2NET) +#else +# define machine_is_d2net() (0) +#endif + +#ifdef CONFIG_MACH_BIGDISK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BIGDISK +# endif +# define machine_is_bigdisk() (machine_arch_type == MACH_TYPE_BIGDISK) +#else +# define machine_is_bigdisk() (0) +#endif + +#ifdef CONFIG_MACH_NOTALVISION +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NOTALVISION +# endif +# define machine_is_notalvision() (machine_arch_type == MACH_TYPE_NOTALVISION) +#else +# define machine_is_notalvision() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_KBOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_KBOC +# endif +# define machine_is_omap3_kboc() (machine_arch_type == MACH_TYPE_OMAP3_KBOC) +#else +# define machine_is_omap3_kboc() (0) +#endif + +#ifdef CONFIG_MACH_CYCLONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CYCLONE +# endif +# define machine_is_cyclone() (machine_arch_type == MACH_TYPE_CYCLONE) +#else +# define machine_is_cyclone() (0) +#endif + +#ifdef CONFIG_MACH_NINJA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NINJA +# endif +# define machine_is_ninja() (machine_arch_type == MACH_TYPE_NINJA) +#else +# define machine_is_ninja() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9G20EK_2MMC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9G20EK_2MMC +# endif +# define machine_is_at91sam9g20ek_2mmc() (machine_arch_type == MACH_TYPE_AT91SAM9G20EK_2MMC) +#else +# define machine_is_at91sam9g20ek_2mmc() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING +# endif +# define machine_is_bcmring() (machine_arch_type == MACH_TYPE_BCMRING) +#else +# define machine_is_bcmring() (0) +#endif + +#ifdef CONFIG_MACH_RESOL_DL2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RESOL_DL2 +# endif +# define machine_is_resol_dl2() (machine_arch_type == MACH_TYPE_RESOL_DL2) +#else +# define machine_is_resol_dl2() (0) +#endif + +#ifdef CONFIG_MACH_IFOSW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IFOSW +# endif +# define machine_is_ifosw() (machine_arch_type == MACH_TYPE_IFOSW) +#else +# define machine_is_ifosw() (0) +#endif + +#ifdef CONFIG_MACH_HTCRHODIUM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCRHODIUM +# endif +# define machine_is_htcrhodium() (machine_arch_type == MACH_TYPE_HTCRHODIUM) +#else +# define machine_is_htcrhodium() (0) +#endif + +#ifdef CONFIG_MACH_HTCTOPAZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCTOPAZ +# endif +# define machine_is_htctopaz() (machine_arch_type == MACH_TYPE_HTCTOPAZ) +#else +# define machine_is_htctopaz() (0) +#endif + +#ifdef CONFIG_MACH_MATRIX504 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MATRIX504 +# endif +# define machine_is_matrix504() (machine_arch_type == MACH_TYPE_MATRIX504) +#else +# define machine_is_matrix504() (0) +#endif + +#ifdef CONFIG_MACH_MRFSA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MRFSA +# endif +# define machine_is_mrfsa() (machine_arch_type == MACH_TYPE_MRFSA) +#else +# define machine_is_mrfsa() (0) +#endif + +#ifdef CONFIG_MACH_SC_P270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SC_P270 +# endif +# define machine_is_sc_p270() (machine_arch_type == MACH_TYPE_SC_P270) +#else +# define machine_is_sc_p270() (0) +#endif + +#ifdef CONFIG_MACH_ATLAS5_EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATLAS5_EVB +# endif +# define machine_is_atlas5_evb() (machine_arch_type == MACH_TYPE_ATLAS5_EVB) +#else +# define machine_is_atlas5_evb() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_LOBOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_LOBOX +# endif +# define machine_is_pelco_lobox() (machine_arch_type == MACH_TYPE_PELCO_LOBOX) +#else +# define machine_is_pelco_lobox() (0) +#endif + +#ifdef CONFIG_MACH_DILAX_PCU200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DILAX_PCU200 +# endif +# define machine_is_dilax_pcu200() (machine_arch_type == MACH_TYPE_DILAX_PCU200) +#else +# define machine_is_dilax_pcu200() (0) +#endif + +#ifdef CONFIG_MACH_LEONARDO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEONARDO +# endif +# define machine_is_leonardo() (machine_arch_type == MACH_TYPE_LEONARDO) +#else +# define machine_is_leonardo() (0) +#endif + +#ifdef CONFIG_MACH_ZORAN_APPROACH7 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZORAN_APPROACH7 +# endif +# define machine_is_zoran_approach7() (machine_arch_type == MACH_TYPE_ZORAN_APPROACH7) +#else +# define machine_is_zoran_approach7() (0) +#endif + +#ifdef CONFIG_MACH_DP6XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DP6XX +# endif +# define machine_is_dp6xx() (machine_arch_type == MACH_TYPE_DP6XX) +#else +# define machine_is_dp6xx() (0) +#endif + +#ifdef CONFIG_MACH_BCM2153_VESPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCM2153_VESPER +# endif +# define machine_is_bcm2153_vesper() (machine_arch_type == MACH_TYPE_BCM2153_VESPER) +#else +# define machine_is_bcm2153_vesper() (0) +#endif + +#ifdef CONFIG_MACH_MAHIMAHI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAHIMAHI +# endif +# define machine_is_mahimahi() (machine_arch_type == MACH_TYPE_MAHIMAHI) +#else +# define machine_is_mahimahi() (0) +#endif + +#ifdef CONFIG_MACH_CLICKC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CLICKC +# endif +# define machine_is_clickc() (machine_arch_type == MACH_TYPE_CLICKC) +#else +# define machine_is_clickc() (0) +#endif + +#ifdef CONFIG_MACH_ZB_GATEWAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZB_GATEWAY +# endif +# define machine_is_zb_gateway() (machine_arch_type == MACH_TYPE_ZB_GATEWAY) +#else +# define machine_is_zb_gateway() (0) +#endif + +#ifdef CONFIG_MACH_TAZCARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAZCARD +# endif +# define machine_is_tazcard() (machine_arch_type == MACH_TYPE_TAZCARD) +#else +# define machine_is_tazcard() (0) +#endif + +#ifdef CONFIG_MACH_TAZDEV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAZDEV +# endif +# define machine_is_tazdev() (machine_arch_type == MACH_TYPE_TAZDEV) +#else +# define machine_is_tazdev() (0) +#endif + +#ifdef CONFIG_MACH_ANNAX_CB_ARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANNAX_CB_ARM +# endif +# define machine_is_annax_cb_arm() (machine_arch_type == MACH_TYPE_ANNAX_CB_ARM) +#else +# define machine_is_annax_cb_arm() (0) +#endif + +#ifdef CONFIG_MACH_ANNAX_DM3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANNAX_DM3 +# endif +# define machine_is_annax_dm3() (machine_arch_type == MACH_TYPE_ANNAX_DM3) +#else +# define machine_is_annax_dm3() (0) +#endif + +#ifdef CONFIG_MACH_CEREBRIC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CEREBRIC +# endif +# define machine_is_cerebric() (machine_arch_type == MACH_TYPE_CEREBRIC) +#else +# define machine_is_cerebric() (0) +#endif + +#ifdef CONFIG_MACH_ORCA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORCA +# endif +# define machine_is_orca() (machine_arch_type == MACH_TYPE_ORCA) +#else +# define machine_is_orca() (0) +#endif + +#ifdef CONFIG_MACH_PC9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PC9260 +# endif +# define machine_is_pc9260() (machine_arch_type == MACH_TYPE_PC9260) +#else +# define machine_is_pc9260() (0) +#endif + +#ifdef CONFIG_MACH_EMS285A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMS285A +# endif +# define machine_is_ems285a() (machine_arch_type == MACH_TYPE_EMS285A) +#else +# define machine_is_ems285a() (0) +#endif + +#ifdef CONFIG_MACH_GEC2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GEC2410 +# endif +# define machine_is_gec2410() (machine_arch_type == MACH_TYPE_GEC2410) +#else +# define machine_is_gec2410() (0) +#endif + +#ifdef CONFIG_MACH_GEC2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GEC2440 +# endif +# define machine_is_gec2440() (machine_arch_type == MACH_TYPE_GEC2440) +#else +# define machine_is_gec2440() (0) +#endif + +#ifdef CONFIG_MACH_ARCH_MW903 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARCH_MW903 +# endif +# define machine_is_mw903() (machine_arch_type == MACH_TYPE_ARCH_MW903) +#else +# define machine_is_mw903() (0) +#endif + +#ifdef CONFIG_MACH_MW2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MW2440 +# endif +# define machine_is_mw2440() (machine_arch_type == MACH_TYPE_MW2440) +#else +# define machine_is_mw2440() (0) +#endif + +#ifdef CONFIG_MACH_ECAC2378 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECAC2378 +# endif +# define machine_is_ecac2378() (machine_arch_type == MACH_TYPE_ECAC2378) +#else +# define machine_is_ecac2378() (0) +#endif + +#ifdef CONFIG_MACH_TAZKIOSK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAZKIOSK +# endif +# define machine_is_tazkiosk() (machine_arch_type == MACH_TYPE_TAZKIOSK) +#else +# define machine_is_tazkiosk() (0) +#endif + +#ifdef CONFIG_MACH_WHITERABBIT_MCH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WHITERABBIT_MCH +# endif +# define machine_is_whiterabbit_mch() (machine_arch_type == MACH_TYPE_WHITERABBIT_MCH) +#else +# define machine_is_whiterabbit_mch() (0) +#endif + +#ifdef CONFIG_MACH_SBOX9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBOX9263 +# endif +# define machine_is_sbox9263() (machine_arch_type == MACH_TYPE_SBOX9263) +#else +# define machine_is_sbox9263() (0) +#endif + +#ifdef CONFIG_MACH_OREO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OREO +# endif +# define machine_is_oreo() (machine_arch_type == MACH_TYPE_OREO) +#else +# define machine_is_oreo() (0) +#endif + +#ifdef CONFIG_MACH_SMDK6442 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK6442 +# endif +# define machine_is_smdk6442() (machine_arch_type == MACH_TYPE_SMDK6442) +#else +# define machine_is_smdk6442() (0) +#endif + +#ifdef CONFIG_MACH_OPENRD_BASE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPENRD_BASE +# endif +# define machine_is_openrd_base() (machine_arch_type == MACH_TYPE_OPENRD_BASE) +#else +# define machine_is_openrd_base() (0) +#endif + +#ifdef CONFIG_MACH_INCREDIBLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INCREDIBLE +# endif +# define machine_is_incredible() (machine_arch_type == MACH_TYPE_INCREDIBLE) +#else +# define machine_is_incredible() (0) +#endif + +#ifdef CONFIG_MACH_INCREDIBLEC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INCREDIBLEC +# endif +# define machine_is_incrediblec() (machine_arch_type == MACH_TYPE_INCREDIBLEC) +#else +# define machine_is_incrediblec() (0) +#endif + +#ifdef CONFIG_MACH_HEROCT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HEROCT +# endif +# define machine_is_heroct() (machine_arch_type == MACH_TYPE_HEROCT) +#else +# define machine_is_heroct() (0) +#endif + +#ifdef CONFIG_MACH_MMNET1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MMNET1000 +# endif +# define machine_is_mmnet1000() (machine_arch_type == MACH_TYPE_MMNET1000) +#else +# define machine_is_mmnet1000() (0) +#endif + +#ifdef CONFIG_MACH_DEVKIT8000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEVKIT8000 +# endif +# define machine_is_devkit8000() (machine_arch_type == MACH_TYPE_DEVKIT8000) +#else +# define machine_is_devkit8000() (0) +#endif + +#ifdef CONFIG_MACH_DEVKIT9000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEVKIT9000 +# endif +# define machine_is_devkit9000() (machine_arch_type == MACH_TYPE_DEVKIT9000) +#else +# define machine_is_devkit9000() (0) +#endif + +#ifdef CONFIG_MACH_MX31TXTR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX31TXTR +# endif +# define machine_is_mx31txtr() (machine_arch_type == MACH_TYPE_MX31TXTR) +#else +# define machine_is_mx31txtr() (0) +#endif + +#ifdef CONFIG_MACH_U380 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U380 +# endif +# define machine_is_u380() (machine_arch_type == MACH_TYPE_U380) +#else +# define machine_is_u380() (0) +#endif + +#ifdef CONFIG_MACH_HUALU_BOARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HUALU_BOARD +# endif +# define machine_is_oamp3_hualu() (machine_arch_type == MACH_TYPE_HUALU_BOARD) +#else +# define machine_is_oamp3_hualu() (0) +#endif + +#ifdef CONFIG_MACH_NPCMX50 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NPCMX50 +# endif +# define machine_is_npcmx50() (machine_arch_type == MACH_TYPE_NPCMX50) +#else +# define machine_is_npcmx50() (0) +#endif + +#ifdef CONFIG_MACH_MX51_LANGE51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_LANGE51 +# endif +# define machine_is_mx51_lange51() (machine_arch_type == MACH_TYPE_MX51_LANGE51) +#else +# define machine_is_mx51_lange51() (0) +#endif + +#ifdef CONFIG_MACH_MX51_LANGE52 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_LANGE52 +# endif +# define machine_is_mx51_lange52() (machine_arch_type == MACH_TYPE_MX51_LANGE52) +#else +# define machine_is_mx51_lange52() (0) +#endif + +#ifdef CONFIG_MACH_RIOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIOM +# endif +# define machine_is_riom() (machine_arch_type == MACH_TYPE_RIOM) +#else +# define machine_is_riom() (0) +#endif + +#ifdef CONFIG_MACH_COMCAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COMCAS +# endif +# define machine_is_comcas() (machine_arch_type == MACH_TYPE_COMCAS) +#else +# define machine_is_comcas() (0) +#endif + +#ifdef CONFIG_MACH_WSI_MX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WSI_MX27 +# endif +# define machine_is_wsi_mx27() (machine_arch_type == MACH_TYPE_WSI_MX27) +#else +# define machine_is_wsi_mx27() (0) +#endif + +#ifdef CONFIG_MACH_CM_T35 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM_T35 +# endif +# define machine_is_cm_t35() (machine_arch_type == MACH_TYPE_CM_T35) +#else +# define machine_is_cm_t35() (0) +#endif + +#ifdef CONFIG_MACH_NET2BIG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NET2BIG +# endif +# define machine_is_net2big() (machine_arch_type == MACH_TYPE_NET2BIG) +#else +# define machine_is_net2big() (0) +#endif + +#ifdef CONFIG_MACH_MOTOROLA_A1600 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOTOROLA_A1600 +# endif +# define machine_is_motorola_a1600() (machine_arch_type == MACH_TYPE_MOTOROLA_A1600) +#else +# define machine_is_motorola_a1600() (0) +#endif + +#ifdef CONFIG_MACH_IGEP0020 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IGEP0020 +# endif +# define machine_is_igep0020() (machine_arch_type == MACH_TYPE_IGEP0020) +#else +# define machine_is_igep0020() (0) +#endif + +#ifdef CONFIG_MACH_IGEP0010 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IGEP0010 +# endif +# define machine_is_igep0010() (machine_arch_type == MACH_TYPE_IGEP0010) +#else +# define machine_is_igep0010() (0) +#endif + +#ifdef CONFIG_MACH_MV6281GTWGE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MV6281GTWGE2 +# endif +# define machine_is_mv6281gtwge2() (machine_arch_type == MACH_TYPE_MV6281GTWGE2) +#else +# define machine_is_mv6281gtwge2() (0) +#endif + +#ifdef CONFIG_MACH_SCAT100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCAT100 +# endif +# define machine_is_scat100() (machine_arch_type == MACH_TYPE_SCAT100) +#else +# define machine_is_scat100() (0) +#endif + +#ifdef CONFIG_MACH_SANMINA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SANMINA +# endif +# define machine_is_sanmina() (machine_arch_type == MACH_TYPE_SANMINA) +#else +# define machine_is_sanmina() (0) +#endif + +#ifdef CONFIG_MACH_MOMENTO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOMENTO +# endif +# define machine_is_momento() (machine_arch_type == MACH_TYPE_MOMENTO) +#else +# define machine_is_momento() (0) +#endif + +#ifdef CONFIG_MACH_NUC9XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC9XX +# endif +# define machine_is_nuc9xx() (machine_arch_type == MACH_TYPE_NUC9XX) +#else +# define machine_is_nuc9xx() (0) +#endif + +#ifdef CONFIG_MACH_NUC910EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC910EVB +# endif +# define machine_is_nuc910evb() (machine_arch_type == MACH_TYPE_NUC910EVB) +#else +# define machine_is_nuc910evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC920EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC920EVB +# endif +# define machine_is_nuc920evb() (machine_arch_type == MACH_TYPE_NUC920EVB) +#else +# define machine_is_nuc920evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC950EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC950EVB +# endif +# define machine_is_nuc950evb() (machine_arch_type == MACH_TYPE_NUC950EVB) +#else +# define machine_is_nuc950evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC945EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC945EVB +# endif +# define machine_is_nuc945evb() (machine_arch_type == MACH_TYPE_NUC945EVB) +#else +# define machine_is_nuc945evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC960EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC960EVB +# endif +# define machine_is_nuc960evb() (machine_arch_type == MACH_TYPE_NUC960EVB) +#else +# define machine_is_nuc960evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC932EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC932EVB +# endif +# define machine_is_nuc932evb() (machine_arch_type == MACH_TYPE_NUC932EVB) +#else +# define machine_is_nuc932evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC900 +# endif +# define machine_is_nuc900() (machine_arch_type == MACH_TYPE_NUC900) +#else +# define machine_is_nuc900() (0) +#endif + +#ifdef CONFIG_MACH_SD1SOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SD1SOC +# endif +# define machine_is_sd1soc() (machine_arch_type == MACH_TYPE_SD1SOC) +#else +# define machine_is_sd1soc() (0) +#endif + +#ifdef CONFIG_MACH_LN2440BC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LN2440BC +# endif +# define machine_is_ln2440bc() (machine_arch_type == MACH_TYPE_LN2440BC) +#else +# define machine_is_ln2440bc() (0) +#endif + +#ifdef CONFIG_MACH_RSBC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RSBC +# endif +# define machine_is_rsbc() (machine_arch_type == MACH_TYPE_RSBC) +#else +# define machine_is_rsbc() (0) +#endif + +#ifdef CONFIG_MACH_OPENRD_CLIENT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPENRD_CLIENT +# endif +# define machine_is_openrd_client() (machine_arch_type == MACH_TYPE_OPENRD_CLIENT) +#else +# define machine_is_openrd_client() (0) +#endif + +#ifdef CONFIG_MACH_HPIPAQ11X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HPIPAQ11X +# endif +# define machine_is_hpipaq11x() (machine_arch_type == MACH_TYPE_HPIPAQ11X) +#else +# define machine_is_hpipaq11x() (0) +#endif + +#ifdef CONFIG_MACH_WAYLAND +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WAYLAND +# endif +# define machine_is_wayland() (machine_arch_type == MACH_TYPE_WAYLAND) +#else +# define machine_is_wayland() (0) +#endif + +#ifdef CONFIG_MACH_ACNBSX102 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACNBSX102 +# endif +# define machine_is_acnbsx102() (machine_arch_type == MACH_TYPE_ACNBSX102) +#else +# define machine_is_acnbsx102() (0) +#endif + +#ifdef CONFIG_MACH_HWAT91 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HWAT91 +# endif +# define machine_is_hwat91() (machine_arch_type == MACH_TYPE_HWAT91) +#else +# define machine_is_hwat91() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9263CS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9263CS +# endif +# define machine_is_at91sam9263cs() (machine_arch_type == MACH_TYPE_AT91SAM9263CS) +#else +# define machine_is_at91sam9263cs() (0) +#endif + +#ifdef CONFIG_MACH_CSB732 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB732 +# endif +# define machine_is_csb732() (machine_arch_type == MACH_TYPE_CSB732) +#else +# define machine_is_csb732() (0) +#endif + +#ifdef CONFIG_MACH_U8500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U8500 +# endif +# define machine_is_u8500() (machine_arch_type == MACH_TYPE_U8500) +#else +# define machine_is_u8500() (0) +#endif + +#ifdef CONFIG_MACH_HUQIU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HUQIU +# endif +# define machine_is_huqiu() (machine_arch_type == MACH_TYPE_HUQIU) +#else +# define machine_is_huqiu() (0) +#endif + +#ifdef CONFIG_MACH_MX51_KUNLUN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_KUNLUN +# endif +# define machine_is_mx51_kunlun() (machine_arch_type == MACH_TYPE_MX51_KUNLUN) +#else +# define machine_is_mx51_kunlun() (0) +#endif + +#ifdef CONFIG_MACH_PMT1G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PMT1G +# endif +# define machine_is_pmt1g() (machine_arch_type == MACH_TYPE_PMT1G) +#else +# define machine_is_pmt1g() (0) +#endif + +#ifdef CONFIG_MACH_HTCELF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCELF +# endif +# define machine_is_htcelf() (machine_arch_type == MACH_TYPE_HTCELF) +#else +# define machine_is_htcelf() (0) +#endif + +#ifdef CONFIG_MACH_ARMADILLO420 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMADILLO420 +# endif +# define machine_is_armadillo420() (machine_arch_type == MACH_TYPE_ARMADILLO420) +#else +# define machine_is_armadillo420() (0) +#endif + +#ifdef CONFIG_MACH_ARMADILLO440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMADILLO440 +# endif +# define machine_is_armadillo440() (machine_arch_type == MACH_TYPE_ARMADILLO440) +#else +# define machine_is_armadillo440() (0) +#endif + +#ifdef CONFIG_MACH_U_CHIP_DUAL_ARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U_CHIP_DUAL_ARM +# endif +# define machine_is_u_chip_dual_arm() (machine_arch_type == MACH_TYPE_U_CHIP_DUAL_ARM) +#else +# define machine_is_u_chip_dual_arm() (0) +#endif + +#ifdef CONFIG_MACH_CSR_BDB3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSR_BDB3 +# endif +# define machine_is_csr_bdb3() (machine_arch_type == MACH_TYPE_CSR_BDB3) +#else +# define machine_is_csr_bdb3() (0) +#endif + +#ifdef CONFIG_MACH_DOLBY_CAT1018 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DOLBY_CAT1018 +# endif +# define machine_is_dolby_cat1018() (machine_arch_type == MACH_TYPE_DOLBY_CAT1018) +#else +# define machine_is_dolby_cat1018() (0) +#endif + +#ifdef CONFIG_MACH_HY9307 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HY9307 +# endif +# define machine_is_hy9307() (machine_arch_type == MACH_TYPE_HY9307) +#else +# define machine_is_hy9307() (0) +#endif + +#ifdef CONFIG_MACH_A_ES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A_ES +# endif +# define machine_is_aspire_easystore() (machine_arch_type == MACH_TYPE_A_ES) +#else +# define machine_is_aspire_easystore() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_IRIF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_IRIF +# endif +# define machine_is_davinci_irif() (machine_arch_type == MACH_TYPE_DAVINCI_IRIF) +#else +# define machine_is_davinci_irif() (0) +#endif + +#ifdef CONFIG_MACH_AGAMA9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AGAMA9263 +# endif +# define machine_is_agama9263() (machine_arch_type == MACH_TYPE_AGAMA9263) +#else +# define machine_is_agama9263() (0) +#endif + +#ifdef CONFIG_MACH_MARVELL_JASPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MARVELL_JASPER +# endif +# define machine_is_marvell_jasper() (machine_arch_type == MACH_TYPE_MARVELL_JASPER) +#else +# define machine_is_marvell_jasper() (0) +#endif + +#ifdef CONFIG_MACH_FLINT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FLINT +# endif +# define machine_is_flint() (machine_arch_type == MACH_TYPE_FLINT) +#else +# define machine_is_flint() (0) +#endif + +#ifdef CONFIG_MACH_TAVOREVB3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAVOREVB3 +# endif +# define machine_is_tavorevb3() (machine_arch_type == MACH_TYPE_TAVOREVB3) +#else +# define machine_is_tavorevb3() (0) +#endif + +#ifdef CONFIG_MACH_SCH_M490 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCH_M490 +# endif +# define machine_is_sch_m490() (machine_arch_type == MACH_TYPE_SCH_M490) +#else +# define machine_is_sch_m490() (0) +#endif + +#ifdef CONFIG_MACH_RBL01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RBL01 +# endif +# define machine_is_rbl01() (machine_arch_type == MACH_TYPE_RBL01) +#else +# define machine_is_rbl01() (0) +#endif + +#ifdef CONFIG_MACH_OMNIFI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMNIFI +# endif +# define machine_is_omnifi() (machine_arch_type == MACH_TYPE_OMNIFI) +#else +# define machine_is_omnifi() (0) +#endif + +#ifdef CONFIG_MACH_OTAVALO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OTAVALO +# endif +# define machine_is_otavalo() (machine_arch_type == MACH_TYPE_OTAVALO) +#else +# define machine_is_otavalo() (0) +#endif + +#ifdef CONFIG_MACH_SIENNA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIENNA +# endif +# define machine_is_sienna() (machine_arch_type == MACH_TYPE_SIENNA) +#else +# define machine_is_sienna() (0) +#endif + +#ifdef CONFIG_MACH_HTC_EXCALIBUR_S620 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTC_EXCALIBUR_S620 +# endif +# define machine_is_htc_excalibur_s620() (machine_arch_type == MACH_TYPE_HTC_EXCALIBUR_S620) +#else +# define machine_is_htc_excalibur_s620() (0) +#endif + +#ifdef CONFIG_MACH_HTC_OPAL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTC_OPAL +# endif +# define machine_is_htc_opal() (machine_arch_type == MACH_TYPE_HTC_OPAL) +#else +# define machine_is_htc_opal() (0) +#endif + +#ifdef CONFIG_MACH_TOUCHBOOK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOUCHBOOK +# endif +# define machine_is_touchbook() (machine_arch_type == MACH_TYPE_TOUCHBOOK) +#else +# define machine_is_touchbook() (0) +#endif + +#ifdef CONFIG_MACH_LATTE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LATTE +# endif +# define machine_is_latte() (machine_arch_type == MACH_TYPE_LATTE) +#else +# define machine_is_latte() (0) +#endif + +#ifdef CONFIG_MACH_XA200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XA200 +# endif +# define machine_is_xa200() (machine_arch_type == MACH_TYPE_XA200) +#else +# define machine_is_xa200() (0) +#endif + +#ifdef CONFIG_MACH_NIMROD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NIMROD +# endif +# define machine_is_nimrod() (machine_arch_type == MACH_TYPE_NIMROD) +#else +# define machine_is_nimrod() (0) +#endif + +#ifdef CONFIG_MACH_CC9P9215_3G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9P9215_3G +# endif +# define machine_is_cc9p9215_3g() (machine_arch_type == MACH_TYPE_CC9P9215_3G) +#else +# define machine_is_cc9p9215_3g() (0) +#endif + +#ifdef CONFIG_MACH_CC9P9215_3GJS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9P9215_3GJS +# endif +# define machine_is_cc9p9215_3gjs() (machine_arch_type == MACH_TYPE_CC9P9215_3GJS) +#else +# define machine_is_cc9p9215_3gjs() (0) +#endif + +#ifdef CONFIG_MACH_TK71 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TK71 +# endif +# define machine_is_tk71() (machine_arch_type == MACH_TYPE_TK71) +#else +# define machine_is_tk71() (0) +#endif + +#ifdef CONFIG_MACH_COMHAM3525 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COMHAM3525 +# endif +# define machine_is_comham3525() (machine_arch_type == MACH_TYPE_COMHAM3525) +#else +# define machine_is_comham3525() (0) +#endif + +#ifdef CONFIG_MACH_MX31EREBUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX31EREBUS +# endif +# define machine_is_mx31erebus() (machine_arch_type == MACH_TYPE_MX31EREBUS) +#else +# define machine_is_mx31erebus() (0) +#endif + +#ifdef CONFIG_MACH_MCARDMX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MCARDMX27 +# endif +# define machine_is_mcardmx27() (machine_arch_type == MACH_TYPE_MCARDMX27) +#else +# define machine_is_mcardmx27() (0) +#endif + +#ifdef CONFIG_MACH_PARADISE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PARADISE +# endif +# define machine_is_paradise() (machine_arch_type == MACH_TYPE_PARADISE) +#else +# define machine_is_paradise() (0) +#endif + +#ifdef CONFIG_MACH_TIDE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TIDE +# endif +# define machine_is_tide() (machine_arch_type == MACH_TYPE_TIDE) +#else +# define machine_is_tide() (0) +#endif + +#ifdef CONFIG_MACH_WZL2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WZL2440 +# endif +# define machine_is_wzl2440() (machine_arch_type == MACH_TYPE_WZL2440) +#else +# define machine_is_wzl2440() (0) +#endif + +#ifdef CONFIG_MACH_SDRDEMO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SDRDEMO +# endif +# define machine_is_sdrdemo() (machine_arch_type == MACH_TYPE_SDRDEMO) +#else +# define machine_is_sdrdemo() (0) +#endif + +#ifdef CONFIG_MACH_ETHERCAN2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ETHERCAN2 +# endif +# define machine_is_ethercan2() (machine_arch_type == MACH_TYPE_ETHERCAN2) +#else +# define machine_is_ethercan2() (0) +#endif + +#ifdef CONFIG_MACH_ECMIMG20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECMIMG20 +# endif +# define machine_is_ecmimg20() (machine_arch_type == MACH_TYPE_ECMIMG20) +#else +# define machine_is_ecmimg20() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_DRAGON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_DRAGON +# endif +# define machine_is_omap_dragon() (machine_arch_type == MACH_TYPE_OMAP_DRAGON) +#else +# define machine_is_omap_dragon() (0) +#endif + +#ifdef CONFIG_MACH_HALO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HALO +# endif +# define machine_is_halo() (machine_arch_type == MACH_TYPE_HALO) +#else +# define machine_is_halo() (0) +#endif + +#ifdef CONFIG_MACH_HUANGSHAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HUANGSHAN +# endif +# define machine_is_huangshan() (machine_arch_type == MACH_TYPE_HUANGSHAN) +#else +# define machine_is_huangshan() (0) +#endif + +#ifdef CONFIG_MACH_VL_MA2SC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VL_MA2SC +# endif +# define machine_is_vl_ma2sc() (machine_arch_type == MACH_TYPE_VL_MA2SC) +#else +# define machine_is_vl_ma2sc() (0) +#endif + +#ifdef CONFIG_MACH_RAUMFELD_RC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RAUMFELD_RC +# endif +# define machine_is_raumfeld_rc() (machine_arch_type == MACH_TYPE_RAUMFELD_RC) +#else +# define machine_is_raumfeld_rc() (0) +#endif + +#ifdef CONFIG_MACH_RAUMFELD_CONNECTOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RAUMFELD_CONNECTOR +# endif +# define machine_is_raumfeld_connector() (machine_arch_type == MACH_TYPE_RAUMFELD_CONNECTOR) +#else +# define machine_is_raumfeld_connector() (0) +#endif + +#ifdef CONFIG_MACH_RAUMFELD_SPEAKER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RAUMFELD_SPEAKER +# endif +# define machine_is_raumfeld_speaker() (machine_arch_type == MACH_TYPE_RAUMFELD_SPEAKER) +#else +# define machine_is_raumfeld_speaker() (0) +#endif + +#ifdef CONFIG_MACH_MULTIBUS_MASTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MULTIBUS_MASTER +# endif +# define machine_is_multibus_master() (machine_arch_type == MACH_TYPE_MULTIBUS_MASTER) +#else +# define machine_is_multibus_master() (0) +#endif + +#ifdef CONFIG_MACH_MULTIBUS_PBK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MULTIBUS_PBK +# endif +# define machine_is_multibus_pbk() (machine_arch_type == MACH_TYPE_MULTIBUS_PBK) +#else +# define machine_is_multibus_pbk() (0) +#endif + +#ifdef CONFIG_MACH_TNETV107X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TNETV107X +# endif +# define machine_is_tnetv107x() (machine_arch_type == MACH_TYPE_TNETV107X) +#else +# define machine_is_tnetv107x() (0) +#endif + /* * These have not yet been registered */ From 5da71efa18e8b4eac9afd8bfa13e3c7e7ddde1d0 Mon Sep 17 00:00:00 2001 From: Eric Millbrandt Date: Thu, 3 Sep 2009 08:09:44 -0500 Subject: [PATCH 042/208] Reset i2c slave devices during init on mpc5xxx cpus Reset any i2c devices that may have been interrupted during a system reset. Normally this would be accomplished by clocking the line until SCL and SDA are released and then sending a start condtiion (From an Atmel datasheet). There is no direct access to the i2c pins so instead create start commands through the i2c interface. Send a start command then delay for the SDA Hold time, repeat this by disabling/enabling the bus a total of 9 times. Signed-off-by: Eric Millbrandt --- README | 7 ++++++ cpu/mpc5xxx/i2c.c | 49 ++++++++++++++++++++++++++++++++++++ include/configs/galaxy5200.h | 1 + 3 files changed, 57 insertions(+) diff --git a/README b/README index c90f6ee2d9d..ff4ed8b95c0 100644 --- a/README +++ b/README @@ -1366,6 +1366,13 @@ The following options need to be configured: therefore be cleared to 0 (See, eg, MPC823e User's Manual p.16-473). So, set CONFIG_SYS_I2C_SLAVE to 0. + CONFIG_SYS_I2C_INIT_MPC5XXX + + When a board is reset during an i2c bus transfer + chips might think that the current transfer is still + in progress. Reset the slave devices by sending start + commands until the slave device responds. + That's all that's required for CONFIG_HARD_I2C. If you use the software i2c interface (CONFIG_SOFT_I2C) diff --git a/cpu/mpc5xxx/i2c.c b/cpu/mpc5xxx/i2c.c index 23419324ba5..4f7f7163287 100644 --- a/cpu/mpc5xxx/i2c.c +++ b/cpu/mpc5xxx/i2c.c @@ -207,6 +207,52 @@ static int receive_bytes(uchar chip, char *buf, int len) return 0; } +#if defined(CONFIG_SYS_I2C_INIT_MPC5XXX) + +#define FDR510(x) (u8) (((x & 0x20) >> 3) | (x & 0x3)) +#define FDR432(x) (u8) ((x & 0x1C) >> 2) +/* + * Reset any i2c devices that may have been interrupted during a system reset. + * Normally this would be accomplished by clocking the line until SCL and SDA + * are released and then sending a start condtiion (From an Atmel datasheet). + * There is no direct access to the i2c pins so instead create start commands + * through the i2c interface. Send a start command then delay for the SDA Hold + * time, repeat this by disabling/enabling the bus a total of 9 times. + */ +static void send_reset(void) +{ + struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; + int i; + u32 delay; + u8 fdr; + int SDA_Tap[] = { 3, 3, 4, 4, 1, 1, 2, 2}; + struct mpc5xxx_i2c_tap scltap[] = { + {4, 1}, + {4, 2}, + {6, 4}, + {6, 8}, + {14, 16}, + {30, 32}, + {62, 64}, + {126, 128} + }; + + fdr = (u8)mpc_reg_in(®s->mfdr); + + delay = scltap[FDR432(fdr)].scl2tap + ((SDA_Tap[FDR510(fdr)] - 1) * \ + scltap[FDR432(fdr)].tap2tap) + 3; + + for (i = 0; i < 9; i++) { + mpc_reg_out(®s->mcr, I2C_EN|I2C_STA|I2C_TX, I2C_INIT_MASK); + udelay(delay); + mpc_reg_out(®s->mcr, 0, I2C_INIT_MASK); + udelay(delay); + } + + mpc_reg_out(®s->mcr, I2C_EN, I2C_INIT_MASK); +} +#endif /* CONFIG_SYS_I2c_INIT_MPC5XXX */ + /**************** I2C API ****************/ void i2c_init(int speed, int saddr) @@ -225,6 +271,9 @@ void i2c_init(int speed, int saddr) mpc_reg_out(®s->mcr, I2C_EN, I2C_INIT_MASK); mpc_reg_out(®s->msr, 0, I2C_IF); +#if defined(CONFIG_SYS_I2C_INIT_MPC5XXX) + send_reset(); +#endif return; } diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h index a5b5a03a9a2..f4b520d39f2 100644 --- a/include/configs/galaxy5200.h +++ b/include/configs/galaxy5200.h @@ -110,6 +110,7 @@ #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ #define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_INIT_MPC5XXX /* Reset devices on i2c bus */ /* * EEPROM CAT24WC32 configuration From 92477a631bbda2dc0dd2194e03f9bd3ddb8b9c21 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Fri, 4 Sep 2009 16:28:35 -0500 Subject: [PATCH 043/208] fsl_i2c: increase I2C timeout values and make them configurable The value of I2C_TIMEOUT in fsl_i2c.c has several problems. First, it is defined as CONFIG_HZ/4, but it is used as a count of microseconds, so it makes no sense to derive it from a clock rate. Second, the current value (250) is too low for some boards, so it needs to be increased. Third, the timeout necessary for multiple-master arbitration is larger than the timeout for basic read/write operations, so we shouldn't have a single constant for both timeouts. Finally, it would be nice if we could override these values on a per-board basis. Signed-off-by: Timur Tabi Acked-by: Wolfgang Denk Tested-by: Peter Tyser Acked-by: Peter Tyser --- drivers/i2c/fsl_i2c.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index ce0f301e131..47bbf792c40 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -1,5 +1,5 @@ /* - * Copyright 2006 Freescale Semiconductor, Inc. + * Copyright 2006,2009 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -26,7 +26,21 @@ #include #include /* HW definitions */ -#define I2C_TIMEOUT (CONFIG_SYS_HZ / 4) +/* The maximum number of microseconds we will wait until another master has + * released the bus. If not defined in the board header file, then use a + * generic value. + */ +#ifndef CONFIG_I2C_MBB_TIMEOUT +#define CONFIG_I2C_MBB_TIMEOUT 100000 +#endif + +/* The maximum number of microseconds we will wait for a read or write + * operation to complete. If not defined in the board header file, then use a + * generic value. + */ +#ifndef CONFIG_I2C_TIMEOUT +#define CONFIG_I2C_TIMEOUT 10000 +#endif #define I2C_READ_BIT 1 #define I2C_WRITE_BIT 0 @@ -213,9 +227,10 @@ static __inline__ int i2c_wait4bus(void) { unsigned long long timeval = get_ticks(); + const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT); while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) { - if ((get_ticks() - timeval) > usec2ticks(I2C_TIMEOUT)) + if ((get_ticks() - timeval) > timeout) return -1; } @@ -227,6 +242,7 @@ i2c_wait(int write) { u32 csr; unsigned long long timeval = get_ticks(); + const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT); do { csr = readb(&i2c_dev[i2c_bus_num]->sr); @@ -251,7 +267,7 @@ i2c_wait(int write) } return 0; - } while ((get_ticks() - timeval) < usec2ticks(I2C_TIMEOUT)); + } while ((get_ticks() - timeval) < timeout); debug("i2c_wait: timed out\n"); return -1; From 6b9ea08c5010eab5ad1056bc9bf033afb672d9cc Mon Sep 17 00:00:00 2001 From: Dipen Dudhat Date: Tue, 1 Sep 2009 17:27:00 +0530 Subject: [PATCH 044/208] ppc/85xx: Use CONFIG_FSL_ESDHC to enable sdhc clk Enable eSDHC Clock based on generic CONFIG_FSL_ESDHC define instead of a platform define. This will enable all the 85xx platforms to use sdhc_clk based on CONFIG_FSL_ESDHC. Signed-off-by: Gao Guanhua Signed-off-by: Dipen Dudhat Signed-off-by: Kumar Gala --- cpu/mpc85xx/speed.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 3ef49b456fb..2fdcefb219c 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -153,7 +153,7 @@ int get_clocks (void) #endif gd->i2c2_clk = gd->i2c1_clk; -#if defined(CONFIG_MPC8536) +#if defined(CONFIG_FSL_ESDHC) gd->sdhc_clk = gd->bus_clk / 2; #endif From 9c671e7062720074f894ee329eaa6995b0823727 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Wed, 2 Sep 2009 02:17:24 +0400 Subject: [PATCH 045/208] fsl: sys_eeprom: Fix 'may be used uninitialized' warning The warning is bogus, so silence it by initializing the 'ret' variable. Signed-off-by: Anton Vorontsov Acked-by: Timur Tabi Signed-off-by: Kumar Gala --- board/freescale/common/sys_eeprom.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index c0fff686b1c..661015e0006 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -204,7 +204,8 @@ static void update_crc(void) */ static int prog_eeprom(void) { - int ret, i; + int ret = 0; /* shut up gcc */ + int i; void *p; #ifdef CONFIG_SYS_EEPROM_BUS_NUM unsigned int bus; From 13d46ab2572c0283d34f93bebc9a41295ef84ca5 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 1 Sep 2009 21:07:08 -0500 Subject: [PATCH 046/208] ppc/8xxx: relocate cpu pointer in global data Now that we have a pointer to the cpu struct we need to relocate it once we get into ram. Signed-off-by: Kumar Gala --- lib_ppc/board.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/lib_ppc/board.c b/lib_ppc/board.c index d9a12a12413..e8509ee0e8d 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -655,6 +655,10 @@ void board_init_r (gd_t *id, ulong dest_addr) TOTAL_MALLOC_LEN; #endif +#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) + gd->cpu += gd->reloc_off; +#endif + #ifdef CONFIG_SERIAL_MULTI serial_initialize(); #endif From 2abbd31da6d900473ed678ca50789ee58bc9bb00 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 1 Sep 2009 22:01:54 -0500 Subject: [PATCH 047/208] ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist The ddr_pd_cntl isn't defined in any reference manual and thus we wil remove especially since we set it to 0, which would most likely be its POR value. Signed-off-by: Kumar Gala --- board/freescale/p1_p2_rdb/ddr.c | 5 ----- cpu/mpc85xx/ddr-gen3.c | 1 - cpu/mpc8xxx/ddr/ctrl_regs.c | 23 ----------------------- include/asm-ppc/fsl_ddr_sdram.h | 1 - include/asm-ppc/immap_85xx.h | 2 +- 5 files changed, 1 insertion(+), 31 deletions(-) diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 9518392cddb..d1e659b46b0 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -43,7 +43,6 @@ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x00000000 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x00000000 -#define CONFIG_SYS_DDR_PD_CONTROL 0x00000000 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 #define CONFIG_SYS_DDR_RCW_1 0x00000000 #define CONFIG_SYS_DDR_RCW_2 0x00000000 @@ -110,7 +109,6 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = { .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, - .ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL, .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 @@ -138,7 +136,6 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = { .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, - .ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL, .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 @@ -166,7 +163,6 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = { .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, - .ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL, .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 @@ -194,7 +190,6 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, - .ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL, .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c index 8ac3d5fbebf..0691ca455af 100644 --- a/cpu/mpc85xx/ddr-gen3.c +++ b/cpu/mpc85xx/ddr-gen3.c @@ -74,7 +74,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); - out_be32(&ddr->ddr_pd_cntl, regs->ddr_pd_cntl); out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index 1689d680bdf..5e63c5df3ad 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1066,28 +1066,6 @@ static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it) ddr->ddr_sr_cntr = (sr_it & 0xF) << 16; } -/* DDR Pre-Drive Conditioning Control (DDR_PD_CNTL) */ -static void set_ddr_pd_cntl(fsl_ddr_cfg_regs_t *ddr) -{ - /* Termination value during pre-drive conditioning */ - unsigned int tvpd = 0; - unsigned int pd_en = 0; /* Pre-Drive Conditioning Enable */ - unsigned int pdar = 0; /* Pre-Drive After Read */ - unsigned int pdaw = 0; /* Pre-Drive After Write */ - unsigned int pd_on = 0; /* Pre-Drive Conditioning On */ - unsigned int pd_off = 0; /* Pre-Drive Conditioning Off */ - - ddr->ddr_pd_cntl = (0 - | ((pd_en & 0x1) << 31) - | ((tvpd & 0x7) << 28) - | ((pdar & 0x7F) << 20) - | ((pdaw & 0x7F) << 12) - | ((pd_on & 0x1F) << 6) - | ((pd_off & 0x1F) << 0) - ); -} - - /* DDR SDRAM Register Control Word 1 (DDR_SDRAM_RCW_1) */ static void set_ddr_sdram_rcw_1(fsl_ddr_cfg_regs_t *ddr) { @@ -1355,7 +1333,6 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_ddr_zq_cntl(ddr, zq_en); set_ddr_wrlvl_cntl(ddr, wrlvl_en); - set_ddr_pd_cntl(ddr); set_ddr_sr_cntr(ddr, sr_it); set_ddr_sdram_rcw_1(ddr); diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h index c2e5aeebcbf..69b857b41cd 100644 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ b/include/asm-ppc/fsl_ddr_sdram.h @@ -110,7 +110,6 @@ typedef struct fsl_ddr_cfg_regs_s { unsigned int timing_cfg_5; unsigned int ddr_zq_cntl; unsigned int ddr_wrlvl_cntl; - unsigned int ddr_pd_cntl; unsigned int ddr_sr_cntr; unsigned int ddr_sdram_rcw_1; unsigned int ddr_sdram_rcw_2; diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 375d80444f5..e7d412dba23 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -132,7 +132,7 @@ typedef struct ccsr_ddr { char reg8_1a[8]; uint ddr_zq_cntl; /* 0x2170 - DDR ZQ calibration control*/ uint ddr_wrlvl_cntl; /* 0x2174 - DDR write leveling control*/ - uint ddr_pd_cntl; /* 0x2178 - DDR pre-drive conditioning control*/ + char reg8_1aa[4]; uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */ uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */ uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */ From da1cd955dfec35b0e15381ad1ee248fa194eed82 Mon Sep 17 00:00:00 2001 From: Dipen Dudhat Date: Wed, 2 Sep 2009 11:25:08 +0530 Subject: [PATCH 048/208] ppc/85xx: Fix up eSDHC controller clock frequency in the device tree Signed-off-by: Dipen Dudhat Signed-off-by: Kumar Gala --- cpu/mpc85xx/fdt.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index a692529689d..8366379ab60 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -27,6 +27,9 @@ #include #include #include +#ifdef CONFIG_FSL_ESDHC +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -326,4 +329,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) #endif ft_fixup_cache(blob); + +#if defined(CONFIG_FSL_ESDHC) + fdt_fixup_esdhc(blob, bd); +#endif } From 26f4cdba6b51deab4ec99d60be381244068ef950 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 14 Aug 2009 13:37:54 -0500 Subject: [PATCH 049/208] 85xx: Add support for setting IVORs to fixed offset defaults In future Book-E implementations IVORs will most likely go away and be replaced with fixed offsets. The IVPR will continue to exist to allow for relocation of the interrupt vectors. This code adds support to setup the IVORs as their fixed offset values per the ISA 2.06 spec when we transition from u-boot to another OS either via 'bootm' or a cpu release. Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu_init.c | 7 ++++ cpu/mpc85xx/fixed_ivor.S | 79 +++++++++++++++++++++++++++++++++++++ cpu/mpc85xx/release.S | 3 ++ cpu/mpc85xx/start.S | 6 +++ include/asm-ppc/processor.h | 12 ++++++ 5 files changed, 107 insertions(+) create mode 100644 cpu/mpc85xx/fixed_ivor.S diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index c4d1a9dd9c7..a54cf5d1570 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -375,3 +375,10 @@ int cpu_init_r(void) #endif return 0; } + +extern void setup_ivors(void); + +void arch_preboot_os(void) +{ + setup_ivors(); +} diff --git a/cpu/mpc85xx/fixed_ivor.S b/cpu/mpc85xx/fixed_ivor.S new file mode 100644 index 00000000000..dc725c94813 --- /dev/null +++ b/cpu/mpc85xx/fixed_ivor.S @@ -0,0 +1,79 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * Kumar Gala + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* This file is intended to be included by other asm code since + * we will want to execute this on both the primary core when + * it does a bootm and the secondary core's that get released + * out of the spin table */ + +#define SET_IVOR(vector_number, vector_offset) \ + li r3,vector_offset@l; \ + mtspr SPRN_IVOR##vector_number,r3; + +#define SET_GIVOR(vector_number, vector_offset) \ + li r3,vector_offset@l; \ + mtspr SPRN_GIVOR##vector_number,r3; + + SET_IVOR(0, 0x020) /* Critical Input */ + SET_IVOR(1, 0x000) /* Machine Check */ + SET_IVOR(2, 0x060) /* Data Storage */ + SET_IVOR(3, 0x080) /* Instruction Storage */ + SET_IVOR(4, 0x0a0) /* External Input */ + SET_IVOR(5, 0x0c0) /* Alignment */ + SET_IVOR(6, 0x0e0) /* Program */ + SET_IVOR(7, 0x100) /* FP Unavailable */ + SET_IVOR(8, 0x120) /* System Call */ + SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */ + SET_IVOR(10, 0x160) /* Decrementer */ + SET_IVOR(11, 0x180) /* Fixed Interval Timer */ + SET_IVOR(12, 0x1a0) /* Watchdog Timer */ + SET_IVOR(13, 0x1c0) /* Data TLB Error */ + SET_IVOR(14, 0x1e0) /* Instruction TLB Error */ + SET_IVOR(15, 0x040) /* Debug */ + +/* e500v1 & e500v2 only */ +#ifndef CONFIG_E500MC + SET_IVOR(32, 0x200) /* SPE Unavailable */ + SET_IVOR(33, 0x220) /* Embedded FP Data */ + SET_IVOR(34, 0x240) /* Embedded FP Round */ +#endif + + SET_IVOR(35, 0x260) /* Performance monitor */ + +/* e500mc only */ +#ifdef CONFIG_E500MC + SET_IVOR(36, 0x280) /* Processor doorbell */ + SET_IVOR(37, 0x2a0) /* Processor doorbell critical */ + SET_IVOR(38, 0x2c0) /* Guest Processor doorbell */ + SET_IVOR(39, 0x2e0) /* Guest Processor critical & machine check */ + SET_IVOR(40, 0x300) /* Hypervisor system call */ + SET_IVOR(41, 0x320) /* Hypervisor Priviledge */ + + SET_GIVOR(2, 0x060) /* Guest Data Storage */ + SET_GIVOR(3, 0x080) /* Guest Instruction Storage */ + SET_GIVOR(4, 0x0a0) /* Guest External Input */ + SET_GIVOR(8, 0x120) /* Guest System Call */ + SET_GIVOR(13, 0x1c0) /* Guest Data TLB Error */ + SET_GIVOR(14, 0x1e0) /* Guest Instruction TLB Error */ +#endif diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 2d4f219a3b7..074b056b749 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -168,6 +168,9 @@ __secondary_start_page: bne 2b isync + /* setup IVORs to match fixed offsets */ +#include "fixed_ivor.S" + /* get the upper bits of the addr */ lwz r11,ENTRY_ADDR_UPPER(r10) diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 4f7236fc35c..e21a4eb8767 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -1122,3 +1122,9 @@ flush_dcache: isync blr + +.globl setup_ivors +setup_ivors: + +#include "fixed_ivor.S" + blr diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index dcaf8c030a3..78ef4187f23 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -468,6 +468,16 @@ #define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */ #define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */ #define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */ +#define SPRN_IVOR38 0x1b0 /* Interrupt Vector Offset Register 38 */ +#define SPRN_IVOR39 0x1b1 /* Interrupt Vector Offset Register 39 */ +#define SPRN_IVOR40 0x1b2 /* Interrupt Vector Offset Register 40 */ +#define SPRN_IVOR41 0x1b3 /* Interrupt Vector Offset Register 41 */ +#define SPRN_GIVOR2 0x1b8 /* Guest Interrupt Vector Offset Register 2 */ +#define SPRN_GIVOR3 0x1b9 /* Guest Interrupt Vector Offset Register 3 */ +#define SPRN_GIVOR4 0x1ba /* Guest Interrupt Vector Offset Register 4 */ +#define SPRN_GIVOR8 0x1bb /* Guest Interrupt Vector Offset Register 8 */ +#define SPRN_GIVOR13 0x1bc /* Guest Interrupt Vector Offset Register 13 */ +#define SPRN_GIVOR14 0x1bd /* Guest Interrupt Vector Offset Register 14 */ /* e500 definitions */ #define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */ @@ -513,6 +523,8 @@ #define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ #define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ #define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ +#define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */ +#define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */ #define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ #define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */ From c2287af1552bd630956568d3957c370f86801b7d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 3 Sep 2009 08:20:24 -0500 Subject: [PATCH 050/208] ppc/85xx: Add a simple function to search the TLB Allow us to search the TLB array based on an address. This is useful if we want to change an entry but dont know where it happens to be located. For example, the boot page mapping we use on MP or the flash TLB that we change the WIMGE settings for after we've relocated. Signed-off-by: Kumar Gala --- cpu/mpc85xx/tlb.c | 27 +++++++++++++++++++++++++++ include/asm-ppc/mmu.h | 7 +++++-- 2 files changed, 32 insertions(+), 2 deletions(-) diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index f3d3080c44e..0497a29ba83 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -106,6 +106,33 @@ void init_tlbs(void) return ; } +static void tlbsx (const volatile unsigned *addr) +{ + __asm__ __volatile__ ("tlbsx 0,%0" : : "r" (addr), "m" (*addr)); +} + +/* return -1 if we didn't find anything */ +int find_tlb_idx(void *addr, u8 tlbsel) +{ + u32 _mas0, _mas1; + + /* zero out Search PID, AS */ + mtspr(MAS6, 0); + + tlbsx(addr); + + _mas0 = mfspr(MAS0); + _mas1 = mfspr(MAS1); + + /* we found something, and its in the TLB we expect */ + if ((MAS1_VALID & _mas1) && + (MAS0_TLBSEL(tlbsel) == (_mas0 & MAS0_TLBSEL_MSK))) { + return ((_mas0 & MAS0_ESEL_MSK) >> 16); + } + + return -1; +} + #ifdef CONFIG_ADDR_MAP void init_addr_map(void) { diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index fa92b90c337..eda2959b7d0 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -387,8 +387,10 @@ extern void print_bats(void); * FSL Book-E support */ -#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000) -#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000) +#define MAS0_TLBSEL_MSK 0x30000000 +#define MAS0_TLBSEL(x) ((x << 28) & MAS0_TLBSEL_MSK) +#define MAS0_ESEL_MSK 0x0FFF0000 +#define MAS0_ESEL(x) ((x << 16) & MAS0_ESEL_MSK) #define MAS0_NV(x) ((x) & 0x00000FFF) #define MAS1_VALID 0x80000000 @@ -474,6 +476,7 @@ extern void set_tlb(u8 tlb, u32 epn, u64 rpn, extern void disable_tlb(u8 esel); extern void invalidate_tlb(u8 tlb); extern void init_tlbs(void); +extern int find_tlb_idx(void *addr, u8 tlbsel); extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); From c7259086816405fe0eb77f4dc22e76980a040cef Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 3 Sep 2009 08:41:31 -0500 Subject: [PATCH 051/208] ppc/85xx: Fix bug in setup_mp code Its possible that we try and copy the boot page code out of flash into a DDR location that doesn't have a TLB cover it. For example, if we have 3G of DDR we typically only map the first 2G. In the cases of 4G+ this wasn't an issue since the reset page TLB mapping covered the last page of memory which we wanted to copy to. We now change the physical address of the reset page TLB to map to the true physical location of the boot page code, copy and than set the TLB back to its 1:1 mapping of the reset page. Signed-off-by: Kumar Gala --- cpu/mpc85xx/mp.c | 32 +++++++++++++++++++++++++++++--- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index 2df55c71d49..fa65bed083b 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "mp.h" DECLARE_GLOBAL_DATA_PTR; @@ -209,8 +210,33 @@ void setup_mp(void) ulong fixup = (ulong)&__secondary_start_page; u32 bootpg = determine_mp_bootpg(); - memcpy((void *)bootpg, (void *)fixup, 4096); - flush_cache(bootpg, 4096); + /* look for the tlb covering the reset page, there better be one */ + int i = find_tlb_idx((void *)0xfffff000, 1); - pq3_mp_up(bootpg); + /* we found a match */ + if (i != -1) { + /* map reset page to bootpg so we can copy code there */ + disable_tlb(i); + + set_tlb(1, 0xfffff000, bootpg, /* tlb, epn, rpn */ + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, /* perms, wimge */ + 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ + + memcpy((void *)0xfffff000, (void *)fixup, 4096); + flush_cache(0xfffff000, 4096); + + disable_tlb(i); + + /* setup reset page back to 1:1, we'll use HW boot translation + * to map this where we want + */ + set_tlb(1, 0xfffff000, 0xfffff000, /* tlb, epn, rpn */ + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */ + 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ + + pq3_mp_up(bootpg); + } else { + puts("WARNING: No reset page TLB. " + "Skipping secondary core setup\n"); + } } From 74c5dfd81f94a2a1f0d6990d17c491d718e8b9ea Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Fri, 4 Sep 2009 17:05:24 -0500 Subject: [PATCH 052/208] fsl: add register read-back to set_law() After programming a new LAW, we should read-back the LAWAR register so that we sync the writes. Otherwise, code that attempts to use the new LAW-mapped memory might fail right away. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala --- drivers/misc/fsl_law.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index 147fe0a21c8..7bdd355c745 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -58,7 +58,8 @@ void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) out_be32(lawbar, addr >> 12); out_be32(lawar, LAWAR_EN | ((u32)id << 20) | (u32)sz); - return ; + /* Read back so that we sync the writes */ + in_be32(lawar); } int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) From 5052a771cf1722c37c732f3c340775b55fbe3a22 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 2 Sep 2009 09:00:50 -0500 Subject: [PATCH 053/208] ppc/85xx: Cleanup makefile and related optional files Cleaned up cpu/mpc85xx/Makefile to use CONFIG_* for those obvious cases we have like PCI, CPM2, QE. Also reworked it to use one line per file for everything and sorted in alphabetical order. Signed-off-by: Kumar Gala --- cpu/mpc85xx/Makefile | 23 +++++++++++++++++------ cpu/mpc85xx/commproc.c | 3 --- cpu/mpc85xx/ether_fcc.c | 4 ---- cpu/mpc85xx/pci.c | 4 ++-- cpu/mpc85xx/serial_scc.c | 3 --- 5 files changed, 19 insertions(+), 18 deletions(-) diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 1bd8f3057ae..a177f427efe 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -29,10 +29,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o resetvec.o -SOBJS-$(CONFIG_MP) += release.o +SOBJS-$(CONFIG_MP) += release.o SOBJS = $(SOBJS-y) -COBJS-$(CONFIG_MP) += mp.o -COBJS-$(CONFIG_OF_LIBFDT) += fdt.o + +COBJS-$(CONFIG_CPM2) += commproc.o # supports ddr1 COBJS-$(CONFIG_MPC8540) += ddr-gen1.o @@ -54,10 +54,21 @@ COBJS-$(CONFIG_P1020) += ddr-gen3.o COBJS-$(CONFIG_P2010) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o +COBJS-$(CONFIG_CPM2) += ether_fcc.o +COBJS-$(CONFIG_OF_LIBFDT) += fdt.o +COBJS-$(CONFIG_MP) += mp.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o -COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \ - pci.o serial_scc.o commproc.o ether_fcc.o qe_io.o \ - $(COBJS-y) +COBJS-$(CONFIG_PCI) += pci.o +COBJS-$(CONFIG_QE) += qe_io.o +COBJS-$(CONFIG_CPM2) += serial_scc.o + +COBJS = $(COBJS-y) +COBJS += cpu.o +COBJS += cpu_init.o +COBJS += interrupts.o +COBJS += speed.o +COBJS += tlb.o +COBJS += traps.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc85xx/commproc.c b/cpu/mpc85xx/commproc.c index fff8dff5032..594aace4b12 100644 --- a/cpu/mpc85xx/commproc.c +++ b/cpu/mpc85xx/commproc.c @@ -26,7 +26,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_CPM2) /* * because we have stack and init data in dual port ram * we must reduce the size @@ -204,5 +203,3 @@ ulong post_word_load (void) } #endif /* CONFIG_POST */ - -#endif /* CONFIG_CPM2 */ diff --git a/cpu/mpc85xx/ether_fcc.c b/cpu/mpc85xx/ether_fcc.c index 32ad46956ed..5f1414d7581 100644 --- a/cpu/mpc85xx/ether_fcc.c +++ b/cpu/mpc85xx/ether_fcc.c @@ -52,8 +52,6 @@ #include #endif -#if defined(CONFIG_CPM2) - #if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET) && \ defined(CONFIG_NET_MULTI) @@ -469,5 +467,3 @@ int fec_initialize(bd_t *bis) } #endif - -#endif /* CONFIG_CPM2 */ diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index fedf1a54df6..75d2716ef40 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -29,7 +29,7 @@ #include #include -#if defined(CONFIG_PCI) && !defined(CONFIG_FSL_PCI_INIT) +#if !defined(CONFIG_FSL_PCI_INIT) #ifndef CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE @@ -227,4 +227,4 @@ pci_mpc85xx_init(struct pci_controller *board_hose) hose->last_busno = pci_hose_scan(hose); #endif } -#endif /* CONFIG_PCI */ +#endif /* !CONFIG_FSL_PCI_INIT */ diff --git a/cpu/mpc85xx/serial_scc.c b/cpu/mpc85xx/serial_scc.c index 05fb80875d8..2dab2124fcc 100644 --- a/cpu/mpc85xx/serial_scc.c +++ b/cpu/mpc85xx/serial_scc.c @@ -37,7 +37,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_CPM2) #if defined(CONFIG_CONS_ON_SCC) #if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */ @@ -267,5 +266,3 @@ serial_tstc() } #endif /* CONFIG_CONS_ON_SCC */ - -#endif /* CONFIG_CPM2 */ From 3e7b6c1f2db5ec31f9e7dbc3e0cbca602167a46a Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 2 Sep 2009 09:03:08 -0500 Subject: [PATCH 054/208] ppc/8xxx: Refactor code to determine if PCI is enabled & agent/host Refactor the code into a simple bitmask lookup table that determines if a given PCI controller is enabled and if its in host/root-complex or agent/end-point mode. Each processor in the PQ3/MPC86xx family specified different encodings for the cfg_host_agt[] and cfg_IO_ports[] boot strapping signals. Signed-off-by: Kumar Gala --- board/atum8548/atum8548.c | 6 +- board/freescale/mpc8536ds/mpc8536ds.c | 15 +- board/freescale/mpc8544ds/mpc8544ds.c | 14 +- board/freescale/mpc8548cds/mpc8548cds.c | 6 +- board/freescale/mpc8568mds/mpc8568mds.c | 4 +- board/freescale/mpc8569mds/mpc8569mds.c | 4 +- board/freescale/mpc8572ds/mpc8572ds.c | 17 +- board/freescale/mpc8610hpcd/mpc8610hpcd.c | 12 +- board/freescale/mpc8641hpcn/mpc8641hpcn.c | 5 +- board/freescale/p1_p2_rdb/pci.c | 10 +- board/freescale/p2020ds/p2020ds.c | 14 +- board/sbc8548/sbc8548.c | 6 +- board/tqc/tqm85xx/tqm85xx.c | 8 +- cpu/mpc8xxx/Makefile | 1 + cpu/mpc8xxx/pci_cfg.c | 225 ++++++++++++++++++++++ include/asm-ppc/fsl_pci.h | 5 + 16 files changed, 284 insertions(+), 68 deletions(-) create mode 100644 cpu/mpc8xxx/pci_cfg.c diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c index 85c0adc70cf..a220ad4d7af 100644 --- a/board/atum8548/atum8548.c +++ b/board/atum8548/atum8548.c @@ -202,8 +202,8 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent == 5); - int pcie_configured = io_sel & 6; + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -262,7 +262,7 @@ pci_init_board(void) struct pci_controller *hose = &pci1_hose; struct pci_region *r = hose->regions; - uint pci_agent = (host_agent == 6); + uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */ uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 032d7323b59..da729166b14 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -216,8 +216,8 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; struct pci_controller *hose = &pcie3_hose; - int pcie_ep = (host_agent == 1); - int pcie_configured = (io_sel == 7); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -265,9 +265,8 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent == 5); - int pcie_configured = (io_sel == 2 || io_sel == 3 - || io_sel == 5 || io_sel == 7); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -323,8 +322,8 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; struct pci_controller *hose = &pcie2_hose; - int pcie_ep = (host_agent == 3); - int pcie_configured = (io_sel == 5 || io_sel == 7); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -381,7 +380,7 @@ pci_init_board(void) struct pci_controller *hose = &pci1_hose; struct pci_region *r = hose->regions; - uint pci_agent = (host_agent == 6); + uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI, host_agent); uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ uint pci_32 = 1; uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 5a47d0a008e..244a197049c 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -125,8 +125,8 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; struct pci_controller *hose = &pcie3_hose; - int pcie_ep = (host_agent == 1); - int pcie_configured = io_sel >= 6; + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -188,8 +188,8 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent == 5); - int pcie_configured = io_sel >= 2; + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -246,8 +246,8 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; struct pci_controller *hose = &pcie2_hose; - int pcie_ep = (host_agent == 3); - int pcie_configured = io_sel >= 4; + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -306,7 +306,7 @@ pci_init_board(void) struct pci_controller *hose = &pci1_hose; struct pci_region *r = hose->regions; - uint pci_agent = (host_agent == 6); + uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI, host_agent); uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ uint pci_32 = 1; uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 9df5f822e15..80de6f8762b 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -283,7 +283,7 @@ pci_init_board(void) uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ - uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); + uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ @@ -361,10 +361,10 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); struct pci_region *r = hose->regions; - int pcie_configured = io_sel >= 1; + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE connected to slot as %s (base address %x)", diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index fe505b05c15..e2dc69ea933 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -422,10 +422,10 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); struct pci_region *r = hose->regions; - int pcie_configured = io_sel >= 1; + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE connected to slot as %s (base address %x)", diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 63c21dd2a38..cc8873117ef 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -331,9 +331,9 @@ pci_init_board(void) pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; hose = &pcie1_hose; - pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); r = hose->regions; - pcie_configured = io_sel >= 1; + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE connected to slot as %s (base address %x)", diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 7da70fe9938..c69934ca62d 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -186,9 +186,8 @@ void pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; struct pci_controller *hose = &pcie3_hose; - int pcie_ep = (host_agent == 0) || (host_agent == 3) || - (host_agent == 5) || (host_agent == 6); - int pcie_configured = (io_sel == 0x7); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); struct pci_region *r = hose->regions; u32 temp32; @@ -252,9 +251,8 @@ void pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; struct pci_controller *hose = &pcie2_hose; - int pcie_ep = (host_agent == 2) || (host_agent == 4) || - (host_agent == 6) || (host_agent == 0); - int pcie_configured = (io_sel == 0x3) || (io_sel == 0x7); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ @@ -301,11 +299,8 @@ void pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent <= 1) || (host_agent == 4) || - (host_agent == 5); - int pcie_configured = (io_sel == 0x2) || (io_sel == 0x3) || - (io_sel == 0x7) || (io_sel == 0xb) || - (io_sel == 0xc) || (io_sel == 0xf); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 45000d92b22..98111eb60bd 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -248,9 +248,8 @@ void pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_configured = (io_sel == 1) || (io_sel == 4); - int pcie_ep = (host_agent == 0) || (host_agent == 2) || - (host_agent == 5); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) { @@ -298,9 +297,8 @@ void pci_init_board(void) struct pci_controller *hose = &pcie2_hose; struct pci_region *r = hose->regions; - int pcie_configured = (io_sel == 0) || (io_sel == 4); - int pcie_ep = (host_agent == 0) || (host_agent == 1) || - (host_agent == 4); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) { printf(" PCI-Express 2 connected to slot as %s" \ @@ -345,7 +343,7 @@ void pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; - int pci_agent = (host_agent >= 4) && (host_agent <= 6); + int pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); struct pci_region *r = hose->regions; if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) { diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index fab4fae058c..1a08afa69ec 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -155,15 +155,14 @@ void pci_init_board(void) uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) >> MPC8641_PORDEVSR_IO_SEL_SHIFT; + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); #ifdef DEBUG uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA) >> MPC8641_PORBMSR_HA_SHIFT; uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); #endif - if ((io_sel == 2 || io_sel == 3 || io_sel == 5 - || io_sel == 6 || io_sel == 7 || io_sel == 0xF) - && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { + if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); if (pci->pme_msg_det) { diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c index 174a8a7d78f..a3617d57037 100644 --- a/board/freescale/p1_p2_rdb/pci.c +++ b/board/freescale/p1_p2_rdb/pci.c @@ -59,9 +59,8 @@ void pci_init_board(void) #ifdef CONFIG_PCIE2 SET_STD_PCIE_INFO(pci_info[num], 2); - pcie_ep = (host_agent == 2) || (host_agent == 4) || - (host_agent == 6) || (host_agent == 0); - pcie_configured = (io_sel == 0xE); + pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ puts ("\n PCIE2 connected to Slot 1 as "); @@ -80,9 +79,8 @@ void pci_init_board(void) #ifdef CONFIG_PCIE1 SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = (host_agent <= 1) || (host_agent == 4) || - (host_agent == 5); - pcie_configured = (io_sel == 0xE); + pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ puts ("\n PCIE1 connected to Slot 2 as "); diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index 3fe72cd32c3..7ad9be88c32 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -219,9 +219,8 @@ void pci_init_board(void) #ifdef CONFIG_PCIE2 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; hose = &pcie2_hose; - pcie_ep = (host_agent == 2) || (host_agent == 4) || - (host_agent == 6) || (host_agent == 0); - pcie_configured = (io_sel == 0x2) || (io_sel == 0xe); + pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { @@ -287,9 +286,8 @@ void pci_init_board(void) #ifdef CONFIG_PCIE3 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; hose = &pcie3_hose; - pcie_ep = (host_agent == 0) || (host_agent == 3) || - (host_agent == 5) || (host_agent == 6); - pcie_configured = (io_sel == 0x2) || (io_sel == 0x4); + pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { @@ -336,8 +334,8 @@ void pci_init_board(void) #ifdef CONFIG_PCIE1 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; hose = &pcie1_hose; - pcie_ep = (host_agent <= 1) || (host_agent == 4) || (host_agent == 5); - pcie_configured = (io_sel & 6) || (io_sel == 0xE) || (io_sel == 0xF); + pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) { diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 1ae4cda8b0e..e5b21b555e9 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -363,7 +363,7 @@ pci_init_board(void) uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ - uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); + uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ @@ -441,10 +441,10 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); struct pci_region *r = hose->regions; - int pcie_configured = io_sel >= 1; + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE connected to slot as %s (base address %x)", diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 277edcd14e8..3931ec5036f 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -561,8 +561,7 @@ static inline void init_pci1(void) /* PORPLLSR[16] */ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; - uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || - (host_agent == 6); + uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */ @@ -630,11 +629,10 @@ static inline void init_pcie1(void) uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || - (host_agent == 3); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); struct pci_region *r = hose->regions; - int pcie_configured = io_sel >= 1; + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("PCIe: %s, base address %x", diff --git a/cpu/mpc8xxx/Makefile b/cpu/mpc8xxx/Makefile index 430a75f6f8c..5cb6814403d 100644 --- a/cpu/mpc8xxx/Makefile +++ b/cpu/mpc8xxx/Makefile @@ -11,6 +11,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib8xxx.a COBJS-y += cpu.o +COBJS-$(CONFIG_PCI) += pci_cfg.o SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/cpu/mpc8xxx/pci_cfg.c b/cpu/mpc8xxx/pci_cfg.c new file mode 100644 index 00000000000..9c7d92c4d93 --- /dev/null +++ b/cpu/mpc8xxx/pci_cfg.c @@ -0,0 +1,225 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +struct pci_info { + u16 agent; + u16 cfg; +}; + +/* The agent field is a bit mask in which each bit represents the value of + * cfg_host_agt[] signal and the bit is set of the given interface would be + * in agent/end-point mode for the given interface. + * + * The same idea is true of the cfg field. The bit will be set if the + * interface would be enabled based on the value of cfg_IO_ports[] signal + * + * On MPC86xx/PQ3 based systems: + * we extract cfg_host_agt from GUTS register PORBMSR + * we extract cfg_IO_ports from GUTS register PORDEVSR + * + * cfg_IO_ports only exist on systems w/PCIe (we set cfg 0 for systems + * without PCIe) + */ + +#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8560) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .agent = (1 << 0) | (1 << 2), + .cfg = 0, + }, +}; +#elif defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .agent = (1 << 0), + .cfg = 0, + }, +}; +#elif defined(CONFIG_MPC8536) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .agent = (1 << 6), + .cfg = 0, + }, + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 5), + .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_2] = { + .agent = (1 << 3), + .cfg = (1 << 5) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_3] = { + .agent = (1 << 1), + .cfg = (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8544) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .agent = (1 << 6), + .cfg = 0, + }, + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 5), + .cfg = (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) | + (1 << 6) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_2] = { + .agent = (1 << 3), + .cfg = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_3] = { + .agent = (1 << 1), + .cfg = (1 << 6) | (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8548) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI_1] = { + .agent = (1 << 4) | (1 << 6), + .cfg = 0, + }, + [LAW_TRGT_IF_PCI_2] = { + .agent = (1 << 4) | (1 << 6), + .cfg = 0, + }, + /* PCI_2 is always host and we dont use iosel to determine enable/disable */ + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 2), + .cfg = (1 << 3) | (1 << 4) | (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8568) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .agent = (1 << 0) | (1 << 4) | (1 << 6), + .cfg = 0, + }, + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 2) | (1 << 4), + .cfg = (1 << 3) | (1 << 4) | (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8569) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 6), + .cfg = (1 << 0) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | + (1 << 8) | (1 << 0xc) | (1 << 0xf), + }, +}; +#elif defined(CONFIG_MPC8572) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5), + .cfg = (1 << 2) | (1 << 3) | (1 << 7) | + (1 << 0xb) | (1 << 0xc) | (1 << 0xf), + }, + [LAW_TRGT_IF_PCIE_2] = { + .agent = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6), + .cfg = (1 << 3) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_3] = { + .agent = (1 << 0) | (1 << 3) | (1 << 5) | (1 << 6), + .cfg = (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8610) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI_1] = { + .agent = (1 << 4) | (1 << 5) | (1 << 6), + .cfg = 0, + }, + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 2) | (1 << 5), + .cfg = (1 << 1) | (1 << 4), + }, + [LAW_TRGT_IF_PCIE_2] = { + .agent = (1 << 0) | (1 << 1) | (1 << 4), + .cfg = (1 << 0) | (1 << 4), + }, +}; +#elif defined(CONFIG_MPC8641) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .agent = 0, /* we dont use agent on 8641 */ + .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) | + (1 << 7) | (1 << 0xe) | (1 << 0xf), + }, +}; +#elif defined(CONFIG_P1011) || defined(CONFIG_P1020) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 1), + .cfg = (1 << 0) | (1 << 6) | (1 << 0xe) | (1 << 0xf), + }, + [LAW_TRGT_IF_PCIE_2] = { + .agent = (1 << 0) | (1 << 2), + .cfg = (1 << 0xe), + }, +}; +#elif defined(CONFIG_P2010) || defined(CONFIG_P2020) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5), + .cfg = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6) | + (1 << 0xd) | (1 << 0xe) | (1 << 0xf), + }, + [LAW_TRGT_IF_PCIE_2] = { + .agent = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6), + .cfg = (1 << 2) | (1 << 0xe), + }, + [LAW_TRGT_IF_PCIE_3] = { + .agent = (1 << 0) | (1 << 3) | (1 << 5) | (1 << 6), + .cfg = (1 << 2) | (1 << 4), + }, +}; +#else +#error Need to define pci_config_info for processor +#endif + +int is_fsl_pci_agent(enum law_trgt_if trgt, u32 host_agent) +{ + return ((1 << host_agent) & pci_config_info[trgt].agent); +} + +int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel) +{ + return ((1 << io_sel) & pci_config_info[trgt].cfg); +} diff --git a/include/asm-ppc/fsl_pci.h b/include/asm-ppc/fsl_pci.h index f625d19ee42..b9972dabe37 100644 --- a/include/asm-ppc/fsl_pci.h +++ b/include/asm-ppc/fsl_pci.h @@ -20,6 +20,11 @@ #ifndef __FSL_PCI_H_ #define __FSL_PCI_H_ +#include + +int is_fsl_pci_agent(enum law_trgt_if trgt, u32 host_agent); +int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel); + void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data); void fsl_pci_config_unlock(struct pci_controller *hose); void ft_fsl_pci_setup(void *blob, const char *pci_alias, From 58442dc01e47cc8ce42af4f29486a34cad60b9d2 Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Wed, 2 Sep 2009 13:35:21 +0530 Subject: [PATCH 055/208] ppc/85xx,86xx: Handling Unknown SOC version Incase the system is detected with Unknown SVR, let the system boot with a default value and a proper message. Now with dynamic detection of SOC properties from SVR, this is necessary to prevent a crash. Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu.c | 10 +++------- cpu/mpc86xx/cpu.c | 5 +---- cpu/mpc8xxx/cpu.c | 5 +++-- include/asm-ppc/processor.h | 2 ++ 4 files changed, 9 insertions(+), 13 deletions(-) diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 6be98dc350c..63bdb6fde1d 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -69,13 +69,9 @@ int checkcpu (void) cpu = gd->cpu; - if (cpu->name) { - puts(cpu->name); - if (IS_E_PROCESSOR(svr)) - puts("E"); - } else { - puts("Unknown"); - } + puts(cpu->name); + if (IS_E_PROCESSOR(svr)) + puts("E"); printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 04409cec68f..e97ab6d8a5b 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -65,10 +65,7 @@ checkcpu(void) cpu = gd->cpu; - if (cpu->name) - puts(cpu->name); - else - puts("Unknown"); + puts(cpu->name); printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); puts("Core: "); diff --git a/cpu/mpc8xxx/cpu.c b/cpu/mpc8xxx/cpu.c index 339f6d97c2b..c73ac3cc6d2 100644 --- a/cpu/mpc8xxx/cpu.c +++ b/cpu/mpc8xxx/cpu.c @@ -79,6 +79,8 @@ struct cpu_type cpu_type_list [] = { #endif }; +struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 1); + struct cpu_type *identify_cpu(u32 ver) { int i; @@ -86,8 +88,7 @@ struct cpu_type *identify_cpu(u32 ver) if (cpu_type_list[i].soc_ver == ver) return &cpu_type_list[i]; } - - return NULL; + return &cpu_type_unknown; } int cpu_numcores() { diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 78ef4187f23..0a4c66c9d9e 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -1034,6 +1034,8 @@ #define SVR_8641 0x809000 #define SVR_8641D 0x809001 +#define SVR_Unknown 0xFFFFFF + #define _GLOBAL(n)\ .globl n;\ n: From f8027f6b4789e3340f10620d8fb6113b95b88d9c Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Wed, 2 Sep 2009 19:40:36 +0530 Subject: [PATCH 056/208] ppc/85xx/86xx: Device tree fixup for number of cores Fixing the number of cores in the device tree based on the actual number of cores on the system. With this same device tree image can be used for dual core and single core members of otherwise exactly same SOC. For example: * P2020RDB and P2010RDB * P1020RDB and P1011RDB * MPC8641D and MPC8641 Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- cpu/mpc85xx/fdt.c | 2 ++ cpu/mpc86xx/fdt.c | 3 +++ cpu/mpc8xxx/Makefile | 1 + cpu/mpc8xxx/fdt.c | 55 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 61 insertions(+) create mode 100644 cpu/mpc8xxx/fdt.c diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 8366379ab60..723f473dabf 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -34,6 +34,7 @@ DECLARE_GLOBAL_DATA_PTR; extern void ft_qe_setup(void *blob); +extern void ft_fixup_num_cores(void *blob); #ifdef CONFIG_MP #include "mp.h" @@ -327,6 +328,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_MP ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); #endif + ft_fixup_num_cores(blob); ft_fixup_cache(blob); diff --git a/cpu/mpc86xx/fdt.c b/cpu/mpc86xx/fdt.c index a36ee30c3f0..51f3f4c2203 100644 --- a/cpu/mpc86xx/fdt.c +++ b/cpu/mpc86xx/fdt.c @@ -13,6 +13,8 @@ DECLARE_GLOBAL_DATA_PTR; +extern void ft_fixup_num_cores(void *blob); + void ft_cpu_setup(void *blob, bd_t *bd) { #ifdef CONFIG_MP @@ -54,4 +56,5 @@ void ft_cpu_setup(void *blob, bd_t *bd) if (off < 0) printf("%s: %s\n", __FUNCTION__, fdt_strerror(off)); #endif + ft_fixup_num_cores(blob); } diff --git a/cpu/mpc8xxx/Makefile b/cpu/mpc8xxx/Makefile index 5cb6814403d..481f9e541dc 100644 --- a/cpu/mpc8xxx/Makefile +++ b/cpu/mpc8xxx/Makefile @@ -11,6 +11,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib8xxx.a COBJS-y += cpu.o +COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-$(CONFIG_PCI) += pci_cfg.o SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) diff --git a/cpu/mpc8xxx/fdt.c b/cpu/mpc8xxx/fdt.c new file mode 100644 index 00000000000..3a9b5841b69 --- /dev/null +++ b/cpu/mpc8xxx/fdt.c @@ -0,0 +1,55 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This file is derived from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c. + * Basically this file contains cpu specific common code for 85xx/86xx + * processors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +void ft_fixup_num_cores(void *blob) { + int off, num_cores, del_cores; + + del_cores = 0; + num_cores = cpu_numcores(); + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + while (off != -FDT_ERR_NOTFOUND) { + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); + + /* if we find a cpu node outside of what we expect delete it + * and reset the offset back to the start since we can't + * trust the offsets anymore + */ + if (*reg > num_cores-1) { + fdt_del_node(blob, off); + del_cores++; + off = -1; + } + off = fdt_node_offset_by_prop_value(blob, off, + "device_type", "cpu", 4); + } + debug ("%x core system found\n", num_cores); + debug ("deleted %d extra core entry entries from device tree\n", + del_cores); +} From 21170c80a83f1e60ce7f6f83005e06a5c2d15a8e Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Thu, 3 Sep 2009 19:42:40 +0530 Subject: [PATCH 057/208] ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu(). While in probecpu() UART is still not initialized. Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu.c | 4 ++++ cpu/mpc86xx/cpu.c | 6 ++++++ cpu/mpc8xxx/cpu.c | 6 ------ 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 63bdb6fde1d..8b3810f5b00 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -61,6 +61,10 @@ int checkcpu (void) minor = SVR_MIN(svr); if (cpu_numcores() > 1) { +#ifndef CONFIG_MP + puts("Unicore software on multiprocessor system!!\n" + "To enable mutlticore build define CONFIG_MP\n"); +#endif volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); printf("CPU%d: ", pic->whoami); } else { diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index e97ab6d8a5b..f7e012db573 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -61,6 +61,12 @@ checkcpu(void) major = SVR_MAJ(svr); minor = SVR_MIN(svr); + if (cpu_numcores() > 1) { +#ifndef CONFIG_MP + puts("Unicore software on multiprocessor system!!\n" + "To enable mutlticore build define CONFIG_MP\n"); +#endif + } puts("CPU: "); cpu = gd->cpu; diff --git a/cpu/mpc8xxx/cpu.c b/cpu/mpc8xxx/cpu.c index c73ac3cc6d2..00791e11bd5 100644 --- a/cpu/mpc8xxx/cpu.c +++ b/cpu/mpc8xxx/cpu.c @@ -107,12 +107,6 @@ int probecpu (void) gd->cpu = identify_cpu(ver); -#ifndef CONFIG_MP - if (cpu_numcores() > 1) { - puts("Unicore software on multiprocessor system!!\n" - "To enable mutlticore build define CONFIG_MP\n"); - } -#endif return 0; } From c348322ac7f76318295cf25ffab2cc2a4900a234 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 8 Sep 2009 13:46:46 -0500 Subject: [PATCH 058/208] ppc/85xx: Clean up do_reset There is no reason to do a run time check for e500 v1 based cores to determine if we have the GUTs RSTCR facility. Only the first generation of PQ3 parts (MPC8540/41/55/60) do not have it. So checking to see if we are e500 v2 would miss future parts (like e500mc). Just change this to be ifdef'd based on CONFIG_MPC85{40,41,55,60}. Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu.c | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 8b3810f5b00..bdd9ee4c833 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -153,27 +153,15 @@ int checkcpu (void) int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { - uint pvr; - uint ver; +/* Everything after the first generation of PQ3 parts has RSTCR */ +#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) unsigned long val, msr; - pvr = get_pvr(); - ver = PVR_VER(pvr); - - if (ver & 1){ - /* e500 v2 core has reset control register */ - volatile unsigned int * rstcr; - rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0); - *rstcr = 0x2; /* HRESET_REQ */ - udelay(100); - } - /* - * Fallthrough if the code above failed * Initiate hard reset in debug control register DBCR0 - * Make sure MSR[DE] = 1 + * Make sure MSR[DE] = 1. This only resets the core. */ - msr = mfmsr (); msr |= MSR_DE; mtmsr (msr); @@ -181,6 +169,11 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) val = mfspr(DBCR0); val |= 0x70000000; mtspr(DBCR0,val); +#else + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */ + udelay(100); +#endif return 1; } From 6c97a20d0b2f56cb4f3745d94b1f96986e8cced5 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 9 Sep 2009 11:40:41 -0500 Subject: [PATCH 059/208] ppc/85xx: Introduce RESET_VECTOR_ADDRESS to handle non-standard link address Some board ports place TEXT_BASE at a location that would cause the RESET_VECTOR_ADDRESS not to be at 0xfffffffc when we link. By default we assume RESET_VECTOR_ADDRESS will be 0xfffffffc if the board doesn't explicitly set it. Signed-off-by: Kumar Gala Acked-by: Wolfgang Denk --- board/freescale/mpc8536ds/config.mk | 2 ++ board/freescale/mpc8572ds/config.mk | 2 ++ board/freescale/p1_p2_rdb/config.mk | 2 ++ board/freescale/p2020ds/config.mk | 2 ++ config.mk | 4 ++++ cpu/mpc85xx/u-boot.lds | 10 +++++++--- 6 files changed, 19 insertions(+), 3 deletions(-) diff --git a/board/freescale/mpc8536ds/config.mk b/board/freescale/mpc8536ds/config.mk index f03087620a3..c1d0525678e 100644 --- a/board/freescale/mpc8536ds/config.mk +++ b/board/freescale/mpc8536ds/config.mk @@ -26,3 +26,5 @@ ifndef TEXT_BASE TEXT_BASE = 0xeff80000 endif + +RESET_VECTOR_ADDRESS = 0xeffffffc diff --git a/board/freescale/mpc8572ds/config.mk b/board/freescale/mpc8572ds/config.mk index 08b61f09ab2..67394c9b718 100644 --- a/board/freescale/mpc8572ds/config.mk +++ b/board/freescale/mpc8572ds/config.mk @@ -26,3 +26,5 @@ ifndef TEXT_BASE TEXT_BASE = 0xeff80000 endif + +RESET_VECTOR_ADDRESS = 0xeffffffc diff --git a/board/freescale/p1_p2_rdb/config.mk b/board/freescale/p1_p2_rdb/config.mk index abd64bbbec0..a56b5366b75 100644 --- a/board/freescale/p1_p2_rdb/config.mk +++ b/board/freescale/p1_p2_rdb/config.mk @@ -27,3 +27,5 @@ ifndef TEXT_BASE TEXT_BASE = 0xeff80000 endif + +RESET_VECTOR_ADDRESS = 0xeffffffc diff --git a/board/freescale/p2020ds/config.mk b/board/freescale/p2020ds/config.mk index 439fa8fca69..4fcd69c5d67 100644 --- a/board/freescale/p2020ds/config.mk +++ b/board/freescale/p2020ds/config.mk @@ -26,3 +26,5 @@ ifndef TEXT_BASE TEXT_BASE = 0xeff80000 endif + +RESET_VECTOR_ADDRESS = 0xeffffffc diff --git a/config.mk b/config.mk index 885215799e6..8cfd60c86ca 100644 --- a/config.mk +++ b/config.mk @@ -128,6 +128,10 @@ ifneq ($(TEXT_BASE),) CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) endif +ifneq ($(RESET_VECTOR_ADDRESS),) +CPPFLAGS += -DRESET_VECTOR_ADDRESS=$(RESET_VECTOR_ADDRESS) +endif + ifneq ($(OBJTREE),$(SRCTREE)) CPPFLAGS += -I$(OBJTREE)/include2 -I$(OBJTREE)/include endif diff --git a/cpu/mpc85xx/u-boot.lds b/cpu/mpc85xx/u-boot.lds index d6e22a7210e..ec4787157cc 100644 --- a/cpu/mpc85xx/u-boot.lds +++ b/cpu/mpc85xx/u-boot.lds @@ -20,6 +20,10 @@ * MA 02111-1307 USA */ +#ifndef RESET_VECTOR_ADDRESS +#define RESET_VECTOR_ADDRESS 0xfffffffc +#endif + OUTPUT_ARCH(powerpc) /* Do we need any of these for elf? __DYNAMIC = 0; */ @@ -116,17 +120,17 @@ SECTIONS . = ALIGN(256); __init_end = .; - .bootpg ADDR(.text) + 0x7f000 : + .bootpg RESET_VECTOR_ADDRESS - 0xffc : { cpu/mpc85xx/start.o (.bootpg) } :text = 0xffff - .resetvec ADDR(.text) + 0x7fffc : + .resetvec RESET_VECTOR_ADDRESS : { *(.resetvec) } :text = 0xffff - . = ADDR(.text) + 0x80000; + . = RESET_VECTOR_ADDRESS + 0x4; __bss_start = .; .bss (NOLOAD) : From c8355b9d9f778bd12ee19c8f34d88e13758a4efd Mon Sep 17 00:00:00 2001 From: Detlev Zundel Date: Wed, 2 Sep 2009 17:24:57 +0200 Subject: [PATCH 060/208] amcc-common.h: Use filenames from environment variables for update procedure. Using a separate "u-boot" environment variable allows to easily specify different filenames for the update procedure. This is also in line with many other board configurations defining an "update" script. Signed-off-by: Detlev Zundel Acked-by: Wolfgang Denk Signed-off-by: Stefan Roese --- include/configs/amcc-common.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index a2b7ee8cfec..51128a3b566 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2008 + * (C) Copyright 2008, 2009 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * Common configuration options for all AMCC boards @@ -271,7 +271,8 @@ "bootm ${kernel_addr_r}\0" #define CONFIG_AMCC_DEF_ENV_NOR_UPD \ - "load=tftp 200000 " xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ + "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \ "era " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \ "cp.b ${fileaddr} " xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize};" \ @@ -279,7 +280,8 @@ "upd=run load update\0" \ #define CONFIG_AMCC_DEF_ENV_NAND_UPD \ - "nload=tftp 200000 " xstr(CONFIG_HOSTNAME) "/u-boot-nand.bin\0" \ + "u-boot-nand=" xstr(CONFIG_HOSTNAME) "/u-boot-nand.bin\0" \ + "nload=tftp 200000 ${u-boot-nand}\0" \ "nupdate=nand erase 0 100000;nand write 200000 0 100000;" \ "setenv filesize;saveenv\0" \ "nupd=run nload nupdate\0" From cfab2ae322a99ad55364d054054f138f51130c2a Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Fri, 4 Sep 2009 10:37:04 +0200 Subject: [PATCH 061/208] ppc4xx: Fix PMC405DE support This patch fixes PMC405DE support. Patch 85d6bf0b fixed out-of-tree building for this board but the loadpci object did not get linked after that. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- board/esd/pmc405de/Makefile | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/board/esd/pmc405de/Makefile b/board/esd/pmc405de/Makefile index 327e51e6071..f435495767a 100644 --- a/board/esd/pmc405de/Makefile +++ b/board/esd/pmc405de/Makefile @@ -22,12 +22,15 @@ # include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif LIB = $(obj)lib$(BOARD).a COBJS-y = $(BOARD).o COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o -COBJS += ../common/cmd_loadpci.o +COBJS-y += ../common/cmd_loadpci.o COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) From 99bcf14d553f399148a7660b98f7acbd8cc72d80 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Mon, 7 Sep 2009 17:00:40 +0200 Subject: [PATCH 062/208] ppc4xx: Allow overwriting pci target registers for all 4xx boards This patch adds the CONFIG_PCI_4xx_PTM_OVERWRITE option and replaces the ugly 'if defined(BOARD1) || ... || defined(BOARDn)' construct in 4xx pci code. When CONFIG_PCI_4xx_PTM_OVERWRITE is defined the default ptm register setup can be overwritten through environment variables ptm1la, ptm1ms, ptm2la and ptm2ms to do application specific pci target BAR configuration. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c index 5d7d59c0ea0..184cef5d114 100644 --- a/cpu/ppc4xx/4xx_pci.c +++ b/cpu/ppc4xx/4xx_pci.c @@ -138,7 +138,7 @@ void pci_405gp_init(struct pci_controller *hose) unsigned short temp_short; unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI}; -#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405) +#if defined(CONFIG_PCI_4xx_PTM_OVERWRITE) char *ptmla_str, *ptmms_str; #endif unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA}; @@ -160,7 +160,7 @@ void pci_405gp_init(struct pci_controller *hose) #endif #endif -#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405) +#if defined(CONFIG_PCI_4xx_PTM_OVERWRITE) ptmla_str = getenv("ptm1la"); ptmms_str = getenv("ptm1ms"); if(NULL != ptmla_str && NULL != ptmms_str ) { From 82379b5564819e62624a3c58fbc43f1afedf4f5f Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Mon, 7 Sep 2009 17:00:41 +0200 Subject: [PATCH 063/208] ppc4xx: Add CONFIG_PCI_4xx_PTM_OVERWRITE to some esd 4xx boards Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- include/configs/CPCI405.h | 2 ++ include/configs/CPCI4052.h | 2 ++ include/configs/CPCI405AB.h | 2 ++ include/configs/CPCI405DT.h | 2 ++ include/configs/PMC405.h | 2 ++ include/configs/PMC405DE.h | 2 ++ 6 files changed, 12 insertions(+) diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index f032a8d7ab2..fca6de0c6bc 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -171,6 +171,8 @@ #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ + /*----------------------------------------------------------------------- * IDE/ATA stuff *----------------------------------------------------------------------- diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index daa3c197d55..fd045660897 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -192,6 +192,8 @@ #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ + /*----------------------------------------------------------------------- * IDE/ATA stuff *----------------------------------------------------------------------- diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 41795a77264..d718ed40a3d 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -189,6 +189,8 @@ #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ + /*----------------------------------------------------------------------- * IDE/ATA stuff *----------------------------------------------------------------------- diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 233320878c0..09df47082b6 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -193,6 +193,8 @@ #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ + /*----------------------------------------------------------------------- * IDE/ATA stuff *----------------------------------------------------------------------- diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index a9e71346e0f..87ea7b6d47e 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -181,6 +181,8 @@ #define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */ #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ +#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ + /* * Start addresses for the final memory configuration * (Set up by the startup code) diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h index 5232745a0a8..7198632c36b 100644 --- a/include/configs/PMC405DE.h +++ b/include/configs/PMC405DE.h @@ -164,6 +164,8 @@ #define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable=1 */ #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ + /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is From 0b34dbbd0b6969c98c44313b291836d9056ec40a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 7 Sep 2009 10:52:24 +0200 Subject: [PATCH 064/208] ppc4xx: Fix compilation warning in 4xx miiphy.c This patch fixes the following compilation warning: miiphy.c: In function 'emac4xx_miiphy_read': miiphy.c:353: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Stefan Roese --- cpu/ppc4xx/miiphy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index 6a92bf83648..fa3bfc8d9f5 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -350,7 +350,7 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg, return -1; sta_reg = in_be32((void *)EMAC_STACR + emac_reg); - *value = *(u16 *)(&sta_reg); + *value = sta_reg >> 16; return 0; } From d640ac58dbf61c769864b3fe76314306b7336cf1 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 7 Sep 2009 23:52:31 +0200 Subject: [PATCH 065/208] Remove "atmel_df_pow2" binary with "make clean" Commit 65f6f07b added support for the atmel_df_pow2 standalone program but missed to add a rule to remove it to the "clean" make target. Signed-off-by: Wolfgang Denk --- Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/Makefile b/Makefile index 0449a5bb703..54610c637a7 100644 --- a/Makefile +++ b/Makefile @@ -3717,6 +3717,7 @@ grsim_leon2_config : unconfig clean: @rm -f $(obj)examples/standalone/82559_eeprom \ + $(obj)examples/standalone/atmel_df_pow2 \ $(obj)examples/standalone/eepro100_eeprom \ $(obj)examples/standalone/hello_world \ $(obj)examples/standalone/interrupt \ From 511c02f611cb5afa1b8ca5980caaaabaa0de377f Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Tue, 8 Sep 2009 15:07:12 +0800 Subject: [PATCH 066/208] mkconfig: pass the board name to board config file Then we can handle different config targets in the board file, which simplifies the top level Makefile for boards that have multiple config targets. Signed-off-by: Mingkai Hu --- mkconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/mkconfig b/mkconfig index b0bbbd1e7f4..9efd2fa7db0 100755 --- a/mkconfig +++ b/mkconfig @@ -82,6 +82,7 @@ else > config.h # Create new config file fi echo "/* Automatically generated - do not edit */" >>config.h +echo "#define CONFIG_MK_${BOARD_NAME} 1" >>config.h echo "#include " >>config.h echo "#include " >>config.h From f7644c0bf3502529031657a869fa213cda5a2424 Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Mon, 10 Aug 2009 18:49:37 +0530 Subject: [PATCH 067/208] tools: mkimage : bugfix returns correct value for list command List command always return "EXIT_SUCCESS" even in case of failure by any means. This patch return 0 if list command is sucessful, returns negative value reported by check_header functions Signed-off-by: Prafulla Wadaskar Signed-off-by: Wolfgang Denk --- tools/mkimage.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/tools/mkimage.c b/tools/mkimage.c index 7fd9fd1aeb8..dc2d4c5386f 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -27,7 +27,7 @@ extern unsigned long crc32 (unsigned long crc, const char *buf, unsigned int len); static void copy_file (int, const char *, int); static void usage (void); -static void image_verify_header (char *, int); +static int image_verify_header (char *, int); static void fit_handle_file (void); char *datafile; @@ -59,6 +59,7 @@ main (int argc, char **argv) struct stat sbuf; unsigned char *ptr; char *name = ""; + int retval; cmdname = *argv; @@ -218,24 +219,24 @@ NXTARG: ; exit (EXIT_FAILURE); } - if (fdt_check_header (ptr)) { - /* old-style image */ - image_verify_header ((char *)ptr, sbuf.st_size); - image_print_contents ((image_header_t *)ptr); - } else { + if (!(retval = fdt_check_header (ptr))) { /* FIT image */ fit_print_contents (ptr); + } else if (!(retval = image_verify_header ((char *)ptr, + sbuf.st_size))) { + /* old-style image */ + image_print_contents ((image_header_t *)ptr); } (void) munmap((void *)ptr, sbuf.st_size); (void) close (ifd); - exit (EXIT_SUCCESS); + exit (retval); } else if (fflag) { /* Flattened Image Tree (FIT) format handling */ debug ("FIT format handling\n"); fit_handle_file (); - exit (EXIT_SUCCESS); + exit (retval); } /* @@ -479,7 +480,7 @@ usage () exit (EXIT_FAILURE); } -static void +static int image_verify_header (char *ptr, int image_size) { int len; @@ -499,7 +500,7 @@ image_verify_header (char *ptr, int image_size) fprintf (stderr, "%s: Bad Magic Number: \"%s\" is no valid image\n", cmdname, imagefile); - exit (EXIT_FAILURE); + return -FDT_ERR_BADMAGIC; } data = (char *)hdr; @@ -512,7 +513,7 @@ image_verify_header (char *ptr, int image_size) fprintf (stderr, "%s: ERROR: \"%s\" has bad header checksum!\n", cmdname, imagefile); - exit (EXIT_FAILURE); + return -FDT_ERR_BADSTATE; } data = ptr + sizeof(image_header_t); @@ -522,8 +523,9 @@ image_verify_header (char *ptr, int image_size) fprintf (stderr, "%s: ERROR: \"%s\" has corrupted data!\n", cmdname, imagefile); - exit (EXIT_FAILURE); + return -FDT_ERR_BADSTRUCTURE; } + return 0; } /** From 14821d7dea8d7209f2457c3179fa6551c088ba71 Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Mon, 10 Aug 2009 20:44:06 +0530 Subject: [PATCH 068/208] tools: mkimage: Makefile sorted The tools/Makefile is sorted for all entries, Signed-off-by: Prafulla Wadaskar --- tools/Makefile | 64 +++++++++++++++++++++++++------------------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/tools/Makefile b/tools/Makefile index b5a1e39b022..6f36f23dcc3 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -66,8 +66,8 @@ endif include $(TOPDIR)/config.mk # Generated executable files -BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX) -BIN_FILES-y += mkimage$(SFX) +BIN_FILES-$(CONFIG_LCD_LOGO) += bmp_logo$(SFX) +BIN_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo$(SFX) BIN_FILES-$(CONFIG_ENV_IS_EMBEDDED) += envcrc$(SFX) BIN_FILES-$(CONFIG_ENV_IS_IN_DATAFLASH) += envcrc$(SFX) BIN_FILES-$(CONFIG_ENV_IS_IN_EEPROM) += envcrc$(SFX) @@ -76,31 +76,31 @@ BIN_FILES-$(CONFIG_ENV_IS_IN_ONENAND) += envcrc$(SFX) BIN_FILES-$(CONFIG_ENV_IS_IN_NAND) += envcrc$(SFX) BIN_FILES-$(CONFIG_ENV_IS_IN_NVRAM) += envcrc$(SFX) BIN_FILES-$(CONFIG_ENV_IS_IN_SPI_FLASH) += envcrc$(SFX) -BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX) BIN_FILES-$(CONFIG_CMD_NET) += gen_eth_addr$(SFX) -BIN_FILES-$(CONFIG_LCD_LOGO) += bmp_logo$(SFX) -BIN_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo$(SFX) +BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX) BIN_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes$(SFX) +BIN_FILES-y += mkimage$(SFX) BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX) +BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX) # Source files which exist outside the tools directory EXT_OBJ_FILES-y += common/env_embedded.o +EXT_OBJ_FILES-y += common/image.o EXT_OBJ_FILES-y += lib_generic/crc32.o EXT_OBJ_FILES-y += lib_generic/md5.o EXT_OBJ_FILES-y += lib_generic/sha1.o -EXT_OBJ_FILES-y += common/image.o # Source files located in the tools directory -OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o -OBJ_FILES-y += mkimage.o -OBJ_FILES-$(CONFIG_ENV_IS_EMBEDDED) += envcrc.o -OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o -OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o OBJ_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo.o +OBJ_FILES-$(CONFIG_ENV_IS_EMBEDDED) += envcrc.o +OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o +OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o OBJ_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes.o +OBJ_FILES-y += mkimage.o OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o OBJ_FILES-y += os_support.o +OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o # Don't build by default #ifeq ($(ARCH),ppc) @@ -160,26 +160,7 @@ MAKEDEPEND = makedepend all: $(obj).depend $(BINS) $(LOGO-y) subdirs -$(obj)envcrc$(SFX): $(obj)envcrc.o $(obj)crc32.o $(obj)env_embedded.o $(obj)sha1.o - $(CC) $(CFLAGS) -o $@ $^ - -$(obj)ubsha1$(SFX): $(obj)ubsha1.o $(obj)sha1.o $(obj)os_support.o - $(CC) $(CFLAGS) -o $@ $^ - -$(obj)img2srec$(SFX): $(obj)img2srec.o - $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ - $(STRIP) $@ - -$(obj)mkimage$(SFX): $(obj)mkimage.o $(obj)crc32.o $(obj)image.o $(obj)md5.o \ - $(obj)sha1.o $(LIBFDT_OBJS) $(obj)os_support.o - $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ - $(STRIP) $@ - -$(obj)ncb$(SFX): $(obj)ncb.o - $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ - $(STRIP) $@ - -$(obj)gen_eth_addr$(SFX): $(obj)gen_eth_addr.o +$(obj)bin2header$(SFX): $(obj)bin2header.o $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ $(STRIP) $@ @@ -187,18 +168,37 @@ $(obj)bmp_logo$(SFX): $(obj)bmp_logo.o $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ $(STRIP) $@ +$(obj)envcrc$(SFX): $(obj)crc32.o $(obj)env_embedded.o $(obj)envcrc.o $(obj)sha1.o + $(CC) $(CFLAGS) -o $@ $^ + +$(obj)gen_eth_addr$(SFX): $(obj)gen_eth_addr.o + $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ + $(STRIP) $@ + +$(obj)img2srec$(SFX): $(obj)img2srec.o + $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ + $(STRIP) $@ + $(obj)inca-swap-bytes$(SFX): $(obj)inca-swap-bytes.o $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ $(STRIP) $@ +$(obj)mkimage$(SFX): $(obj)crc32.o $(obj)mkimage.o $(obj)image.o $(obj)md5.o $(obj)mkimage.o \ + $(obj)os_support.o $(obj)sha1.o $(LIBFDT_OBJS) + $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ + $(STRIP) $@ + $(obj)mpc86x_clk$(SFX): $(obj)mpc86x_clk.o $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ $(STRIP) $@ -$(obj)bin2header$(SFX): $(obj)bin2header.o +$(obj)ncb$(SFX): $(obj)ncb.o $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ $(STRIP) $@ +$(obj)ubsha1$(SFX): $(obj)os_support.o $(obj)sha1.o $(obj)ubsha1.o + $(CC) $(CFLAGS) -o $@ $^ + # Some files complain if compiled with -pedantic, use FIT_CFLAGS $(obj)image.o: $(SRCTREE)/common/image.c $(CC) -g $(FIT_CFLAGS) -c -o $@ $< From 449609f5b11cce6beba7338bc4ce0f3345376a0b Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Sun, 16 Aug 2009 05:28:19 +0530 Subject: [PATCH 069/208] tools: mkimage: Fixed build warnings uninitialized retval variable warning fixed crc32 APIs moved to crc.h (newly added) and build warnings fixed Signed-off-by: Prafulla Wadaskar Signed-off-by: Wolfgang Denk --- include/common.h | 4 +--- include/u-boot/crc.h | 33 +++++++++++++++++++++++++++++++++ tools/mkimage.c | 16 +++++++++------- 3 files changed, 43 insertions(+), 10 deletions(-) create mode 100644 include/u-boot/crc.h diff --git a/include/common.h b/include/common.h index 35f12c0b034..f7c93bf5a6d 100644 --- a/include/common.h +++ b/include/common.h @@ -624,9 +624,7 @@ int vsprintf(char *buf, const char *fmt, va_list args); char * strmhz(char *buf, long hz); /* lib_generic/crc32.c */ -uint32_t crc32 (uint32_t, const unsigned char *, uint); -uint32_t crc32_wd (uint32_t, const unsigned char *, uint, uint); -uint32_t crc32_no_comp (uint32_t, const unsigned char *, uint); +#include /* common/console.c */ int console_init_f(void); /* Before relocation; uses the serial stuff */ diff --git a/include/u-boot/crc.h b/include/u-boot/crc.h new file mode 100644 index 00000000000..61bce679145 --- /dev/null +++ b/include/u-boot/crc.h @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _UBOOT_CRC_H +#define _UBOOT_CRC_H + +/* lib_generic/crc32.c */ +uint32_t crc32 (uint32_t, const unsigned char *, uint); +uint32_t crc32_wd (uint32_t, const unsigned char *, uint, uint); +uint32_t crc32_no_comp (uint32_t, const unsigned char *, uint); + +#endif /* _UBOOT_CRC_H */ diff --git a/tools/mkimage.c b/tools/mkimage.c index dc2d4c5386f..b0c02ebcf34 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -23,8 +23,8 @@ #include "mkimage.h" #include +#include -extern unsigned long crc32 (unsigned long crc, const char *buf, unsigned int len); static void copy_file (int, const char *, int); static void usage (void); static int image_verify_header (char *, int); @@ -59,7 +59,7 @@ main (int argc, char **argv) struct stat sbuf; unsigned char *ptr; char *name = ""; - int retval; + int retval = 0; cmdname = *argv; @@ -333,7 +333,8 @@ NXTARG: ; hdr = (image_header_t *)ptr; checksum = crc32 (0, - (const char *)(ptr + image_get_header_size ()), + (const unsigned char *)(ptr + + image_get_header_size ()), sbuf.st_size - image_get_header_size () ); @@ -351,7 +352,8 @@ NXTARG: ; image_set_name (hdr, name); - checksum = crc32 (0, (const char *)hdr, image_get_header_size ()); + checksum = crc32 (0, (const unsigned char *)hdr, + image_get_header_size ()); image_set_hcrc (hdr, checksum); @@ -484,7 +486,7 @@ static int image_verify_header (char *ptr, int image_size) { int len; - char *data; + const unsigned char *data; uint32_t checksum; image_header_t header; image_header_t *hdr = &header; @@ -503,7 +505,7 @@ image_verify_header (char *ptr, int image_size) return -FDT_ERR_BADMAGIC; } - data = (char *)hdr; + data = (const unsigned char *)hdr; len = sizeof(image_header_t); checksum = be32_to_cpu(hdr->ih_hcrc); @@ -516,7 +518,7 @@ image_verify_header (char *ptr, int image_size) return -FDT_ERR_BADSTATE; } - data = ptr + sizeof(image_header_t); + data = (const unsigned char *)ptr + sizeof(image_header_t); len = image_size - sizeof(image_header_t) ; if (crc32 (0, data, len) != be32_to_cpu(hdr->ih_dcrc)) { From 89a4d6b12fd6394898b8a454cbabeaf1cd59bae5 Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Wed, 19 Aug 2009 17:36:46 +0530 Subject: [PATCH 070/208] tools: mkimage: split code into core, default and FIT image specific This is a first step towards reorganizing the mkimage code to make it easier to add support for additional images types. Current mkimage code is specific to generating uImage and FIT image files, but the same framework can be used to generate other image types like Kirkwood boot images (kwbimage-TBD). For this, the mkimage code gets reworked: Here is the brief plan for the same:- a) Split mkimage code into core and image specific support b) Implement callback functions for image specific code c) Move image type specific code to respective C files Currently there are two types of file generation/list supported (i.e uImage, FIT), the code is abstracted from mkimage.c/.h and put in default_image.c and fit_image.c; all code in these file is static except init function call d) mkimage_register API is added to add new image type support All above is addressed in this patch e) Add kwbimage type support to this new framework (TBD) This will be implemented in a following commit. Signed-off-by: Prafulla Wadaskar Edit commit message, fix coding style and typos. Signed-off-by: Wolfgang Denk --- tools/Makefile | 17 +- tools/default_image.c | 149 ++++++++++++ tools/fit_image.c | 212 +++++++++++++++++ tools/mkimage.c | 543 ++++++++++++++++++++---------------------- tools/mkimage.h | 101 +++++++- 5 files changed, 732 insertions(+), 290 deletions(-) create mode 100644 tools/default_image.c create mode 100644 tools/fit_image.c diff --git a/tools/Makefile b/tools/Makefile index 6f36f23dcc3..858b0e8f0a0 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -183,8 +183,15 @@ $(obj)inca-swap-bytes$(SFX): $(obj)inca-swap-bytes.o $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ $(STRIP) $@ -$(obj)mkimage$(SFX): $(obj)crc32.o $(obj)mkimage.o $(obj)image.o $(obj)md5.o $(obj)mkimage.o \ - $(obj)os_support.o $(obj)sha1.o $(LIBFDT_OBJS) +$(obj)mkimage$(SFX): $(obj)crc32.o \ + $(obj)default_image.o \ + $(obj)fit_image.o \ + $(obj)image.o \ + $(obj)md5.o \ + $(obj)mkimage.o \ + $(obj)os_support.o \ + $(obj)sha1.o \ + $(LIBFDT_OBJS) $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ $(STRIP) $@ @@ -200,6 +207,12 @@ $(obj)ubsha1$(SFX): $(obj)os_support.o $(obj)sha1.o $(obj)ubsha1.o $(CC) $(CFLAGS) -o $@ $^ # Some files complain if compiled with -pedantic, use FIT_CFLAGS +$(obj)default_image.o: $(SRCTREE)/tools/default_image.c + $(CC) -g $(FIT_CFLAGS) -c -o $@ $< + +$(obj)fit_image.o: $(SRCTREE)/tools/fit_image.c + $(CC) -g $(FIT_CFLAGS) -c -o $@ $< + $(obj)image.o: $(SRCTREE)/common/image.c $(CC) -g $(FIT_CFLAGS) -c -o $@ $< diff --git a/tools/default_image.c b/tools/default_image.c new file mode 100644 index 00000000000..f5bad4757db --- /dev/null +++ b/tools/default_image.c @@ -0,0 +1,149 @@ +/* + * (C) Copyright 2008 Semihalf + * + * (C) Copyright 2000-2004 + * DENX Software Engineering + * Wolfgang Denk, wd@denx.de + * + * Updated-by: Prafulla Wadaskar + * default_image specific code abstracted from mkimage.c + * some functions added to address abstraction + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "mkimage.h" +#include +#include + +static image_header_t header; + +static int image_check_image_types (uint8_t type) +{ + if ((type > IH_TYPE_INVALID) && (type < IH_TYPE_FLATDT)) + return EXIT_SUCCESS; + else + return EXIT_FAILURE; +} + +static int image_check_params (struct mkimage_params *params) +{ + return ((params->dflag && (params->fflag || params->lflag)) || + (params->fflag && (params->dflag || params->lflag)) || + (params->lflag && (params->dflag || params->fflag))); +} + +static int image_verify_header (unsigned char *ptr, int image_size, + struct mkimage_params *params) +{ + uint32_t len; + const unsigned char *data; + uint32_t checksum; + image_header_t header; + image_header_t *hdr = &header; + + /* + * create copy of header so that we can blank out the + * checksum field for checking - this can't be done + * on the PROT_READ mapped data. + */ + memcpy (hdr, ptr, sizeof(image_header_t)); + + if (be32_to_cpu(hdr->ih_magic) != IH_MAGIC) { + fprintf (stderr, + "%s: Bad Magic Number: \"%s\" is no valid image\n", + params->cmdname, params->imagefile); + return -FDT_ERR_BADMAGIC; + } + + data = (const unsigned char *)hdr; + len = sizeof(image_header_t); + + checksum = be32_to_cpu(hdr->ih_hcrc); + hdr->ih_hcrc = cpu_to_be32(0); /* clear for re-calculation */ + + if (crc32 (0, data, len) != checksum) { + fprintf (stderr, + "%s: ERROR: \"%s\" has bad header checksum!\n", + params->cmdname, params->imagefile); + return -FDT_ERR_BADSTATE; + } + + data = (const unsigned char *)ptr + sizeof(image_header_t); + len = image_size - sizeof(image_header_t) ; + + checksum = be32_to_cpu(hdr->ih_dcrc); + if (crc32 (0, data, len) != checksum) { + fprintf (stderr, + "%s: ERROR: \"%s\" has corrupted data!\n", + params->cmdname, params->imagefile); + return -FDT_ERR_BADSTRUCTURE; + } + return 0; +} + +static void image_set_header (void *ptr, struct stat *sbuf, int ifd, + struct mkimage_params *params) +{ + uint32_t checksum; + + image_header_t * hdr = (image_header_t *)ptr; + + checksum = crc32 (0, + (const unsigned char *)(ptr + + sizeof(image_header_t)), + sbuf->st_size - sizeof(image_header_t)); + + /* Build new header */ + image_set_magic (hdr, IH_MAGIC); + image_set_time (hdr, sbuf->st_mtime); + image_set_size (hdr, sbuf->st_size - sizeof(image_header_t)); + image_set_load (hdr, params->addr); + image_set_ep (hdr, params->ep); + image_set_dcrc (hdr, checksum); + image_set_os (hdr, params->os); + image_set_arch (hdr, params->arch); + image_set_type (hdr, params->type); + image_set_comp (hdr, params->comp); + + image_set_name (hdr, params->imagename); + + checksum = crc32 (0, (const unsigned char *)hdr, + sizeof(image_header_t)); + + image_set_hcrc (hdr, checksum); +} + +/* + * Default image type parameters definition + */ +static struct image_type_params defimage_params = { + .name = "Default Image support", + .header_size = sizeof(image_header_t), + .hdr = (void*)&header, + .check_image_type = image_check_image_types, + .verify_header = image_verify_header, + .print_header = image_print_contents, + .set_header = image_set_header, + .check_params = image_check_params, +}; + +void init_default_image_type (void) +{ + mkimage_register (&defimage_params); +} diff --git a/tools/fit_image.c b/tools/fit_image.c new file mode 100644 index 00000000000..d1e612fece3 --- /dev/null +++ b/tools/fit_image.c @@ -0,0 +1,212 @@ +/* + * (C) Copyright 2008 Semihalf + * + * (C) Copyright 2000-2004 + * DENX Software Engineering + * Wolfgang Denk, wd@denx.de + * + * Updated-by: Prafulla Wadaskar + * FIT image specific code abstracted from mkimage.c + * some functions added to address abstraction + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "mkimage.h" +#include +#include + +static image_header_t header; + +static int fit_verify_header (unsigned char *ptr, int image_size, + struct mkimage_params *params) +{ + return fdt_check_header ((void *)ptr); +} + +static int fit_check_image_types (uint8_t type) +{ + if (type == IH_TYPE_FLATDT) + return EXIT_SUCCESS; + else + return EXIT_FAILURE; +} + +/** + * fit_handle_file - main FIT file processing function + * + * fit_handle_file() runs dtc to convert .its to .itb, includes + * binary data, updates timestamp property and calculates hashes. + * + * datafile - .its file + * imagefile - .itb file + * + * returns: + * only on success, otherwise calls exit (EXIT_FAILURE); + */ +static int fit_handle_file (struct mkimage_params *params) +{ + char tmpfile[MKIMAGE_MAX_TMPFILE_LEN]; + char cmd[MKIMAGE_MAX_DTC_CMDLINE_LEN]; + int tfd; + struct stat sbuf; + unsigned char *ptr; + + /* Flattened Image Tree (FIT) format handling */ + debug ("FIT format handling\n"); + + /* call dtc to include binary properties into the tmp file */ + if (strlen (params->imagefile) + + strlen (MKIMAGE_TMPFILE_SUFFIX) + 1 > sizeof (tmpfile)) { + fprintf (stderr, "%s: Image file name (%s) too long, " + "can't create tmpfile", + params->imagefile, params->cmdname); + return (EXIT_FAILURE); + } + sprintf (tmpfile, "%s%s", params->imagefile, MKIMAGE_TMPFILE_SUFFIX); + + /* dtc -I dts -O -p 200 datafile > tmpfile */ + sprintf (cmd, "%s %s %s > %s", + MKIMAGE_DTC, params->dtc, params->datafile, tmpfile); + debug ("Trying to execute \"%s\"\n", cmd); + if (system (cmd) == -1) { + fprintf (stderr, "%s: system(%s) failed: %s\n", + params->cmdname, cmd, strerror(errno)); + unlink (tmpfile); + return (EXIT_FAILURE); + } + + /* load FIT blob into memory */ + tfd = open (tmpfile, O_RDWR|O_BINARY); + + if (tfd < 0) { + fprintf (stderr, "%s: Can't open %s: %s\n", + params->cmdname, tmpfile, strerror(errno)); + unlink (tmpfile); + return (EXIT_FAILURE); + } + + if (fstat (tfd, &sbuf) < 0) { + fprintf (stderr, "%s: Can't stat %s: %s\n", + params->cmdname, tmpfile, strerror(errno)); + unlink (tmpfile); + return (EXIT_FAILURE); + } + + ptr = mmap (0, sbuf.st_size, PROT_READ|PROT_WRITE, MAP_SHARED, + tfd, 0); + if (ptr == MAP_FAILED) { + fprintf (stderr, "%s: Can't read %s: %s\n", + params->cmdname, tmpfile, strerror(errno)); + unlink (tmpfile); + return (EXIT_FAILURE); + } + + /* check if ptr has a valid blob */ + if (fdt_check_header (ptr)) { + fprintf (stderr, "%s: Invalid FIT blob\n", params->cmdname); + unlink (tmpfile); + return (EXIT_FAILURE); + } + + /* set hashes for images in the blob */ + if (fit_set_hashes (ptr)) { + fprintf (stderr, "%s Can't add hashes to FIT blob", + params->cmdname); + unlink (tmpfile); + return (EXIT_FAILURE); + } + + /* add a timestamp at offset 0 i.e., root */ + if (fit_set_timestamp (ptr, 0, sbuf.st_mtime)) { + fprintf (stderr, "%s: Can't add image timestamp\n", + params->cmdname); + unlink (tmpfile); + return (EXIT_FAILURE); + } + debug ("Added timestamp successfully\n"); + + munmap ((void *)ptr, sbuf.st_size); + close (tfd); + + if (rename (tmpfile, params->imagefile) == -1) { + fprintf (stderr, "%s: Can't rename %s to %s: %s\n", + params->cmdname, tmpfile, params->imagefile, + strerror (errno)); + unlink (tmpfile); + unlink (params->imagefile); + return (EXIT_FAILURE); + } + return (EXIT_SUCCESS); +} + +static void fit_set_header (void *ptr, struct stat *sbuf, int ifd, + struct mkimage_params *params) +{ + uint32_t checksum; + + image_header_t * hdr = (image_header_t *)ptr; + + checksum = crc32 (0, + (const unsigned char *)(ptr + + sizeof(image_header_t)), + sbuf->st_size - sizeof(image_header_t)); + + /* Build new header */ + image_set_magic (hdr, IH_MAGIC); + image_set_time (hdr, sbuf->st_mtime); + image_set_size (hdr, sbuf->st_size - sizeof(image_header_t)); + image_set_load (hdr, params->addr); + image_set_ep (hdr, params->ep); + image_set_dcrc (hdr, checksum); + image_set_os (hdr, params->os); + image_set_arch (hdr, params->arch); + image_set_type (hdr, params->type); + image_set_comp (hdr, params->comp); + + image_set_name (hdr, params->imagename); + + checksum = crc32 (0, (const unsigned char *)hdr, + sizeof(image_header_t)); + + image_set_hcrc (hdr, checksum); +} + +static int fit_check_params (struct mkimage_params *params) +{ + return ((params->dflag && (params->fflag || params->lflag)) || + (params->fflag && (params->dflag || params->lflag)) || + (params->lflag && (params->dflag || params->fflag))); +} + +static struct image_type_params fitimage_params = { + .name = "FIT Image support", + .header_size = sizeof(image_header_t), + .hdr = (void*)&header, + .verify_header = fit_verify_header, + .print_header = fit_print_contents, + .check_image_type = fit_check_image_types, + .fflag_handle = fit_handle_file, + .set_header = fit_set_header, + .check_params = fit_check_params, +}; + +void init_fit_image_type (void) +{ + mkimage_register (&fitimage_params); +} diff --git a/tools/mkimage.c b/tools/mkimage.c index b0c02ebcf34..c43b2077269 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -1,7 +1,7 @@ /* * (C) Copyright 2008 Semihalf * - * (C) Copyright 2000-2004 + * (C) Copyright 2000-2009 * DENX Software Engineering * Wolfgang Denk, wd@denx.de * @@ -23,126 +23,223 @@ #include "mkimage.h" #include -#include -static void copy_file (int, const char *, int); -static void usage (void); -static int image_verify_header (char *, int); -static void fit_handle_file (void); +static void copy_file(int, const char *, int); +static void usage(void); -char *datafile; -char *imagefile; -char *cmdname; +/* image_type_params link list to maintain registered image type supports */ +struct image_type_params *mkimage_tparams = NULL; -int dflag = 0; -int eflag = 0; -int fflag = 0; -int lflag = 0; -int vflag = 0; -int xflag = 0; -int opt_os = IH_OS_LINUX; -int opt_arch = IH_ARCH_PPC; -int opt_type = IH_TYPE_KERNEL; -int opt_comp = IH_COMP_GZIP; -char *opt_dtc = MKIMAGE_DEFAULT_DTC_OPTIONS; +/* parameters initialized by core will be used by the image type code */ +struct mkimage_params params = { + .os = IH_OS_LINUX, + .arch = IH_ARCH_PPC, + .type = IH_TYPE_KERNEL, + .comp = IH_COMP_GZIP, + .dtc = MKIMAGE_DEFAULT_DTC_OPTIONS, +}; -image_header_t header; -image_header_t *hdr = &header; +/* + * mkimage_register - + * + * It is used to register respective image generation/list support to the + * mkimage core + * + * the input struct image_type_params is checked and appended to the link + * list, if the input structure is already registered, error + */ +void mkimage_register (struct image_type_params *tparams) +{ + struct image_type_params **tp; + + if (!tparams) { + fprintf (stderr, "%s: %s: Null input\n", + params.cmdname, __FUNCTION__); + exit (EXIT_FAILURE); + } + + /* scan the linked list, check for registry and point the last one */ + for (tp = &mkimage_tparams; *tp != NULL; tp = &(*tp)->next) { + if (!strcmp((*tp)->name, tparams->name)) { + fprintf (stderr, "%s: %s already registered\n", + params.cmdname, tparams->name); + return; + } + } + + /* add input struct entry at the end of link list */ + *tp = tparams; + /* mark input entry as last entry in the link list */ + tparams->next = NULL; + + debug ("Registered %s\n", tparams->name); +} + +/* + * mkimage_get_type - + * + * It scans all registers image type supports + * checks the input type_id for each supported image type + * + * if successful, + * returns respective image_type_params pointer if success + * if input type_id is not supported by any of image_type_support + * returns NULL + */ +struct image_type_params *mkimage_get_type(int type) +{ + struct image_type_params *curr; + + for (curr = mkimage_tparams; curr != NULL; curr = curr->next) { + if (curr->check_image_type) { + if (!curr->check_image_type (type)) + return curr; + } + } + return NULL; +} + +/* + * mkimage_verify_print_header - + * + * It scans mkimage_tparams link list, + * verifies image_header for each supported image type + * if verification is successful, prints respective header + * + * returns negative if input image format does not match with any of + * supported image types + */ +int mkimage_verify_print_header (void *ptr, struct stat *sbuf) +{ + int retval = -1; + struct image_type_params *curr; + + for (curr = mkimage_tparams; curr != NULL; curr = curr->next ) { + if (curr->verify_header) { + retval = curr->verify_header ( + (unsigned char *)ptr, sbuf->st_size, + ¶ms); + + if (retval == 0) { + /* + * Print the image information + * if verify is successful + */ + if (curr->print_header) + curr->print_header (ptr); + else { + fprintf (stderr, + "%s: print_header undefined for %s\n", + params.cmdname, curr->name); + } + break; + } + } + } + return retval; +} int main (int argc, char **argv) { int ifd = -1; - uint32_t checksum; - uint32_t addr; - uint32_t ep; struct stat sbuf; unsigned char *ptr; - char *name = ""; int retval = 0; + struct image_type_params *tparams = NULL; - cmdname = *argv; + /* Init FIT image generation/list support */ + init_fit_image_type (); + /* Init Default image generation/list support */ + init_default_image_type (); - addr = ep = 0; + params.cmdname = *argv; + params.addr = params.ep = 0; while (--argc > 0 && **++argv == '-') { while (*++*argv) { switch (**argv) { case 'l': - lflag = 1; + params.lflag = 1; break; case 'A': if ((--argc <= 0) || - (opt_arch = genimg_get_arch_id (*++argv)) < 0) + (params.arch = + genimg_get_arch_id (*++argv)) < 0) usage (); goto NXTARG; case 'C': if ((--argc <= 0) || - (opt_comp = genimg_get_comp_id (*++argv)) < 0) + (params.comp = + genimg_get_comp_id (*++argv)) < 0) usage (); goto NXTARG; case 'D': if (--argc <= 0) usage (); - opt_dtc = *++argv; + params.dtc = *++argv; goto NXTARG; case 'O': if ((--argc <= 0) || - (opt_os = genimg_get_os_id (*++argv)) < 0) + (params.os = + genimg_get_os_id (*++argv)) < 0) usage (); goto NXTARG; case 'T': if ((--argc <= 0) || - (opt_type = genimg_get_type_id (*++argv)) < 0) + (params.type = + genimg_get_type_id (*++argv)) < 0) usage (); goto NXTARG; case 'a': if (--argc <= 0) usage (); - addr = strtoul (*++argv, (char **)&ptr, 16); + params.addr = strtoul (*++argv, + (char **)&ptr, 16); if (*ptr) { fprintf (stderr, "%s: invalid load address %s\n", - cmdname, *argv); + params.cmdname, *argv); exit (EXIT_FAILURE); } goto NXTARG; case 'd': if (--argc <= 0) usage (); - datafile = *++argv; - dflag = 1; + params.datafile = *++argv; + params.dflag = 1; goto NXTARG; case 'e': if (--argc <= 0) usage (); - ep = strtoul (*++argv, (char **)&ptr, 16); + params.ep = strtoul (*++argv, + (char **)&ptr, 16); if (*ptr) { fprintf (stderr, "%s: invalid entry point %s\n", - cmdname, *argv); + params.cmdname, *argv); exit (EXIT_FAILURE); } - eflag = 1; + params.eflag = 1; goto NXTARG; case 'f': if (--argc <= 0) usage (); - datafile = *++argv; - fflag = 1; + params.datafile = *++argv; + params.fflag = 1; goto NXTARG; case 'n': if (--argc <= 0) usage (); - name = *++argv; + params.imagename = *++argv; goto NXTARG; case 'v': - vflag++; + params.vflag++; break; case 'x': - xflag++; + params.xflag++; break; default: usage (); @@ -151,91 +248,112 @@ main (int argc, char **argv) NXTARG: ; } - if ((argc != 1) || - (dflag && (fflag || lflag)) || - (fflag && (dflag || lflag)) || - (lflag && (dflag || fflag))) - usage(); + if (argc != 1) + usage (); - if (!eflag) { - ep = addr; + /* set tparams as per input type_id */ + tparams = mkimage_get_type(params.type); + if (tparams == NULL) { + fprintf (stderr, "%s: unsupported type %s\n", + params.cmdname, genimg_get_type_name(params.type)); + exit (EXIT_FAILURE); + } + + /* + * check the passed arguments parameters meets the requirements + * as per image type to be generated/listed + */ + if (tparams->check_params) + if (tparams->check_params (¶ms)) + usage (); + + if (!params.eflag) { + params.ep = params.addr; /* If XIP, entry point must be after the U-Boot header */ - if (xflag) - ep += image_get_header_size (); + if (params.xflag) + params.ep += tparams->header_size; } /* * If XIP, ensure the entry point is equal to the load address plus * the size of the U-Boot header. */ - if (xflag) { - if (ep != addr + image_get_header_size ()) { + if (params.xflag) { + if (params.ep != params.addr + tparams->header_size) { fprintf (stderr, "%s: For XIP, the entry point must be the load addr + %lu\n", - cmdname, - (unsigned long)image_get_header_size ()); + params.cmdname, + (unsigned long)tparams->header_size); exit (EXIT_FAILURE); } } - imagefile = *argv; + params.imagefile = *argv; - if (!fflag){ - if (lflag) { - ifd = open (imagefile, O_RDONLY|O_BINARY); + if (!params.fflag){ + if (params.lflag) { + ifd = open (params.imagefile, O_RDONLY|O_BINARY); } else { - ifd = open (imagefile, + ifd = open (params.imagefile, O_RDWR|O_CREAT|O_TRUNC|O_BINARY, 0666); } if (ifd < 0) { fprintf (stderr, "%s: Can't open %s: %s\n", - cmdname, imagefile, strerror(errno)); + params.cmdname, params.imagefile, + strerror(errno)); exit (EXIT_FAILURE); } } - if (lflag) { + if (params.lflag) { /* * list header information of existing image */ if (fstat(ifd, &sbuf) < 0) { fprintf (stderr, "%s: Can't stat %s: %s\n", - cmdname, imagefile, strerror(errno)); + params.cmdname, params.imagefile, + strerror(errno)); exit (EXIT_FAILURE); } - if ((unsigned)sbuf.st_size < image_get_header_size ()) { + if ((unsigned)sbuf.st_size < tparams->header_size) { fprintf (stderr, - "%s: Bad size: \"%s\" is no valid image\n", - cmdname, imagefile); + "%s: Bad size: \"%s\" is not valid image\n", + params.cmdname, params.imagefile); exit (EXIT_FAILURE); } ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, ifd, 0); if (ptr == MAP_FAILED) { fprintf (stderr, "%s: Can't read %s: %s\n", - cmdname, imagefile, strerror(errno)); + params.cmdname, params.imagefile, + strerror(errno)); exit (EXIT_FAILURE); } - if (!(retval = fdt_check_header (ptr))) { - /* FIT image */ - fit_print_contents (ptr); - } else if (!(retval = image_verify_header ((char *)ptr, - sbuf.st_size))) { - /* old-style image */ - image_print_contents ((image_header_t *)ptr); - } + /* + * scan through mkimage registry for all supported image types + * and verify the input image file header for match + * Print the image information for matched image type + * Returns the error code if not matched + */ + retval = mkimage_verify_print_header (ptr, &sbuf); (void) munmap((void *)ptr, sbuf.st_size); (void) close (ifd); exit (retval); - } else if (fflag) { - /* Flattened Image Tree (FIT) format handling */ - debug ("FIT format handling\n"); - fit_handle_file (); + } else if (params.fflag) { + if (tparams->fflag_handle) + /* + * in some cases, some additional processing needs + * to be done if fflag is defined + * + * For ex. fit_handle_file for Fit file support + */ + retval = tparams->fflag_handle(¶ms); + exit (retval); } @@ -244,16 +362,17 @@ NXTARG: ; * * write dummy header, to be fixed later */ - memset (hdr, 0, image_get_header_size ()); + memset (tparams->hdr, 0, tparams->header_size); - if (write(ifd, hdr, image_get_header_size ()) != image_get_header_size ()) { + if (write(ifd, tparams->hdr, tparams->header_size) + != tparams->header_size) { fprintf (stderr, "%s: Write error on %s: %s\n", - cmdname, imagefile, strerror(errno)); + params.cmdname, params.imagefile, strerror(errno)); exit (EXIT_FAILURE); } - if (opt_type == IH_TYPE_MULTI || opt_type == IH_TYPE_SCRIPT) { - char *file = datafile; + if (params.type == IH_TYPE_MULTI || params.type == IH_TYPE_SCRIPT) { + char *file = params.datafile; uint32_t size; for (;;) { @@ -266,7 +385,7 @@ NXTARG: ; if (stat (file, &sbuf) < 0) { fprintf (stderr, "%s: Can't stat %s: %s\n", - cmdname, file, strerror(errno)); + params.cmdname, file, strerror(errno)); exit (EXIT_FAILURE); } size = cpu_to_uimage (sbuf.st_size); @@ -276,7 +395,8 @@ NXTARG: ; if (write(ifd, (char *)&size, sizeof(size)) != sizeof(size)) { fprintf (stderr, "%s: Write error on %s: %s\n", - cmdname, imagefile, strerror(errno)); + params.cmdname, params.imagefile, + strerror(errno)); exit (EXIT_FAILURE); } @@ -292,7 +412,7 @@ NXTARG: ; } } - file = datafile; + file = params.datafile; for (;;) { char *sep = strchr(file, ':'); @@ -307,11 +427,14 @@ NXTARG: ; } } } else { - copy_file (ifd, datafile, 0); + copy_file (ifd, params.datafile, 0); } /* We're a bit of paranoid */ -#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) && !defined(__APPLE__) +#if defined(_POSIX_SYNCHRONIZED_IO) && \ + !defined(__sun__) && \ + !defined(__FreeBSD__) && \ + !defined(__APPLE__) (void) fdatasync (ifd); #else (void) fsync (ifd); @@ -319,50 +442,42 @@ NXTARG: ; if (fstat(ifd, &sbuf) < 0) { fprintf (stderr, "%s: Can't stat %s: %s\n", - cmdname, imagefile, strerror(errno)); + params.cmdname, params.imagefile, strerror(errno)); exit (EXIT_FAILURE); } ptr = mmap(0, sbuf.st_size, PROT_READ|PROT_WRITE, MAP_SHARED, ifd, 0); if (ptr == MAP_FAILED) { fprintf (stderr, "%s: Can't map %s: %s\n", - cmdname, imagefile, strerror(errno)); + params.cmdname, params.imagefile, strerror(errno)); exit (EXIT_FAILURE); } - hdr = (image_header_t *)ptr; + /* Setup the image header as per input image type*/ + if (tparams->set_header) + tparams->set_header (ptr, &sbuf, ifd, ¶ms); + else { + fprintf (stderr, "%s: Can't set header for %s: %s\n", + params.cmdname, tparams->name, strerror(errno)); + exit (EXIT_FAILURE); + } - checksum = crc32 (0, - (const unsigned char *)(ptr + - image_get_header_size ()), - sbuf.st_size - image_get_header_size () - ); - - /* Build new header */ - image_set_magic (hdr, IH_MAGIC); - image_set_time (hdr, sbuf.st_mtime); - image_set_size (hdr, sbuf.st_size - image_get_header_size ()); - image_set_load (hdr, addr); - image_set_ep (hdr, ep); - image_set_dcrc (hdr, checksum); - image_set_os (hdr, opt_os); - image_set_arch (hdr, opt_arch); - image_set_type (hdr, opt_type); - image_set_comp (hdr, opt_comp); - - image_set_name (hdr, name); - - checksum = crc32 (0, (const unsigned char *)hdr, - image_get_header_size ()); - - image_set_hcrc (hdr, checksum); - - image_print_contents (hdr); + /* Print the image information by processing image header */ + if (tparams->print_header) + tparams->print_header (ptr); + else { + fprintf (stderr, "%s: Can't print header for %s: %s\n", + params.cmdname, tparams->name, strerror(errno)); + exit (EXIT_FAILURE); + } (void) munmap((void *)ptr, sbuf.st_size); /* We're a bit of paranoid */ -#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) && !defined(__APPLE__) +#if defined(_POSIX_SYNCHRONIZED_IO) && \ + !defined(__sun__) && \ + !defined(__FreeBSD__) && \ + !defined(__APPLE__) (void) fdatasync (ifd); #else (void) fsync (ifd); @@ -370,7 +485,7 @@ NXTARG: ; if (close(ifd)) { fprintf (stderr, "%s: Write error on %s: %s\n", - cmdname, imagefile, strerror(errno)); + params.cmdname, params.imagefile, strerror(errno)); exit (EXIT_FAILURE); } @@ -387,31 +502,32 @@ copy_file (int ifd, const char *datafile, int pad) int zero = 0; int offset = 0; int size; + struct image_type_params *tparams = mkimage_get_type (params.type); - if (vflag) { + if (params.vflag) { fprintf (stderr, "Adding Image %s\n", datafile); } if ((dfd = open(datafile, O_RDONLY|O_BINARY)) < 0) { fprintf (stderr, "%s: Can't open %s: %s\n", - cmdname, datafile, strerror(errno)); + params.cmdname, datafile, strerror(errno)); exit (EXIT_FAILURE); } if (fstat(dfd, &sbuf) < 0) { fprintf (stderr, "%s: Can't stat %s: %s\n", - cmdname, datafile, strerror(errno)); + params.cmdname, datafile, strerror(errno)); exit (EXIT_FAILURE); } ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, dfd, 0); if (ptr == MAP_FAILED) { fprintf (stderr, "%s: Can't read %s: %s\n", - cmdname, datafile, strerror(errno)); + params.cmdname, datafile, strerror(errno)); exit (EXIT_FAILURE); } - if (xflag) { + if (params.xflag) { unsigned char *p = NULL; /* * XIP: do not append the image_header_t at the @@ -419,29 +535,29 @@ copy_file (int ifd, const char *datafile, int pad) * reserved for it. */ - if ((unsigned)sbuf.st_size < image_get_header_size ()) { + if ((unsigned)sbuf.st_size < tparams->header_size) { fprintf (stderr, "%s: Bad size: \"%s\" is too small for XIP\n", - cmdname, datafile); + params.cmdname, datafile); exit (EXIT_FAILURE); } - for (p = ptr; p < ptr + image_get_header_size (); p++) { + for (p = ptr; p < ptr + tparams->header_size; p++) { if ( *p != 0xff ) { fprintf (stderr, "%s: Bad file: \"%s\" has invalid buffer for XIP\n", - cmdname, datafile); + params.cmdname, datafile); exit (EXIT_FAILURE); } } - offset = image_get_header_size (); + offset = tparams->header_size; } size = sbuf.st_size - offset; if (write(ifd, ptr + offset, size) != size) { fprintf (stderr, "%s: Write error on %s: %s\n", - cmdname, imagefile, strerror(errno)); + params.cmdname, params.imagefile, strerror(errno)); exit (EXIT_FAILURE); } @@ -449,7 +565,8 @@ copy_file (int ifd, const char *datafile, int pad) if (write(ifd, (char *)&zero, 4-tail) != 4-tail) { fprintf (stderr, "%s: Write error on %s: %s\n", - cmdname, imagefile, strerror(errno)); + params.cmdname, params.imagefile, + strerror(errno)); exit (EXIT_FAILURE); } } @@ -463,7 +580,7 @@ usage () { fprintf (stderr, "Usage: %s -l image\n" " -l ==> list image header information\n", - cmdname); + params.cmdname); fprintf (stderr, " %s [-x] -A arch -O os -T type -C comp " "-a addr -e ep -n name -d data_file[:data_file...] image\n" " -A ==> set architecture to 'arch'\n" @@ -475,157 +592,9 @@ usage () " -n ==> set image name to 'name'\n" " -d ==> use image data from 'datafile'\n" " -x ==> set XIP (execute in place)\n", - cmdname); + params.cmdname); fprintf (stderr, " %s [-D dtc_options] -f fit-image.its fit-image\n", - cmdname); + params.cmdname); exit (EXIT_FAILURE); } - -static int -image_verify_header (char *ptr, int image_size) -{ - int len; - const unsigned char *data; - uint32_t checksum; - image_header_t header; - image_header_t *hdr = &header; - - /* - * create copy of header so that we can blank out the - * checksum field for checking - this can't be done - * on the PROT_READ mapped data. - */ - memcpy (hdr, ptr, sizeof(image_header_t)); - - if (be32_to_cpu(hdr->ih_magic) != IH_MAGIC) { - fprintf (stderr, - "%s: Bad Magic Number: \"%s\" is no valid image\n", - cmdname, imagefile); - return -FDT_ERR_BADMAGIC; - } - - data = (const unsigned char *)hdr; - len = sizeof(image_header_t); - - checksum = be32_to_cpu(hdr->ih_hcrc); - hdr->ih_hcrc = cpu_to_be32(0); /* clear for re-calculation */ - - if (crc32 (0, data, len) != checksum) { - fprintf (stderr, - "%s: ERROR: \"%s\" has bad header checksum!\n", - cmdname, imagefile); - return -FDT_ERR_BADSTATE; - } - - data = (const unsigned char *)ptr + sizeof(image_header_t); - len = image_size - sizeof(image_header_t) ; - - if (crc32 (0, data, len) != be32_to_cpu(hdr->ih_dcrc)) { - fprintf (stderr, - "%s: ERROR: \"%s\" has corrupted data!\n", - cmdname, imagefile); - return -FDT_ERR_BADSTRUCTURE; - } - return 0; -} - -/** - * fit_handle_file - main FIT file processing function - * - * fit_handle_file() runs dtc to convert .its to .itb, includes - * binary data, updates timestamp property and calculates hashes. - * - * datafile - .its file - * imagefile - .itb file - * - * returns: - * only on success, otherwise calls exit (EXIT_FAILURE); - */ -static void fit_handle_file (void) -{ - char tmpfile[MKIMAGE_MAX_TMPFILE_LEN]; - char cmd[MKIMAGE_MAX_DTC_CMDLINE_LEN]; - int tfd; - struct stat sbuf; - unsigned char *ptr; - - /* call dtc to include binary properties into the tmp file */ - if (strlen (imagefile) + strlen (MKIMAGE_TMPFILE_SUFFIX) + 1 > - sizeof (tmpfile)) { - fprintf (stderr, "%s: Image file name (%s) too long, " - "can't create tmpfile", - imagefile, cmdname); - exit (EXIT_FAILURE); - } - sprintf (tmpfile, "%s%s", imagefile, MKIMAGE_TMPFILE_SUFFIX); - - /* dtc -I dts -O -p 200 datafile > tmpfile */ - sprintf (cmd, "%s %s %s > %s", - MKIMAGE_DTC, opt_dtc, datafile, tmpfile); - debug ("Trying to execute \"%s\"\n", cmd); - if (system (cmd) == -1) { - fprintf (stderr, "%s: system(%s) failed: %s\n", - cmdname, cmd, strerror(errno)); - unlink (tmpfile); - exit (EXIT_FAILURE); - } - - /* load FIT blob into memory */ - tfd = open (tmpfile, O_RDWR|O_BINARY); - - if (tfd < 0) { - fprintf (stderr, "%s: Can't open %s: %s\n", - cmdname, tmpfile, strerror(errno)); - unlink (tmpfile); - exit (EXIT_FAILURE); - } - - if (fstat (tfd, &sbuf) < 0) { - fprintf (stderr, "%s: Can't stat %s: %s\n", - cmdname, tmpfile, strerror(errno)); - unlink (tmpfile); - exit (EXIT_FAILURE); - } - - ptr = mmap (0, sbuf.st_size, PROT_READ|PROT_WRITE, MAP_SHARED, tfd, 0); - if (ptr == MAP_FAILED) { - fprintf (stderr, "%s: Can't read %s: %s\n", - cmdname, tmpfile, strerror(errno)); - unlink (tmpfile); - exit (EXIT_FAILURE); - } - - /* check if ptr has a valid blob */ - if (fdt_check_header (ptr)) { - fprintf (stderr, "%s: Invalid FIT blob\n", cmdname); - unlink (tmpfile); - exit (EXIT_FAILURE); - } - - /* set hashes for images in the blob */ - if (fit_set_hashes (ptr)) { - fprintf (stderr, "%s Can't add hashes to FIT blob", cmdname); - unlink (tmpfile); - exit (EXIT_FAILURE); - } - - /* add a timestamp at offset 0 i.e., root */ - if (fit_set_timestamp (ptr, 0, sbuf.st_mtime)) { - fprintf (stderr, "%s: Can't add image timestamp\n", cmdname); - unlink (tmpfile); - exit (EXIT_FAILURE); - } - debug ("Added timestamp successfully\n"); - - munmap ((void *)ptr, sbuf.st_size); - close (tfd); - - if (rename (tmpfile, imagefile) == -1) { - fprintf (stderr, "%s: Can't rename %s to %s: %s\n", - cmdname, tmpfile, imagefile, strerror (errno)); - unlink (tmpfile); - unlink (imagefile); - exit (EXIT_FAILURE); - } -} diff --git a/tools/mkimage.h b/tools/mkimage.h index c077dc955ff..120970fc68f 100644 --- a/tools/mkimage.h +++ b/tools/mkimage.h @@ -19,6 +19,9 @@ * MA 02111-1307 USA */ +#ifndef _MKIIMAGE_H_ +#define _MKIIMAGE_H_ + #include "os_support.h" #include #include @@ -31,7 +34,7 @@ #include #include "fdt_host.h" -#define MKIMAGE_DEBUG +#undef MKIMAGE_DEBUG #ifdef MKIMAGE_DEBUG #define debug(fmt,args...) printf (fmt ,##args) @@ -44,3 +47,99 @@ #define MKIMAGE_DEFAULT_DTC_OPTIONS "-I dts -O dtb -p 500" #define MKIMAGE_MAX_DTC_CMDLINE_LEN 512 #define MKIMAGE_DTC "dtc" /* assume dtc is in $PATH */ + +/* + * This structure defines all such variables those are initialized by + * mkimage main core and need to be referred by image type specific + * functions + */ +struct mkimage_params { + int dflag; + int eflag; + int fflag; + int lflag; + int vflag; + int xflag; + int os; + int arch; + int type; + int comp; + char *dtc; + unsigned int addr; + unsigned int ep; + char *imagename; + char *datafile; + char *imagefile; + char *cmdname; +}; + +/* + * image type specific variables and callback functions + */ +struct image_type_params { + /* name is an identification tag string for added support */ + char *name; + /* + * header size is local to the specific image type to be supported, + * mkimage core treats this as number of bytes + */ + uint32_t header_size; + /* Image type header pointer */ + void *hdr; + /* + * There are several arguments that are passed on the command line + * and are registered as flags in mkimage_params structure. + * This callback function can be used to check the passed arguments + * are in-lined with the image type to be supported + * + * Returns 1 if parameter check is successful + */ + int (*check_params) (struct mkimage_params *); + /* + * This function is used by list command (i.e. mkimage -l ) + * image type verification code must be put here + * + * Returns 0 if image header verification is successful + * otherwise, returns respective negative error codes + */ + int (*verify_header) (unsigned char *, int, struct mkimage_params *); + /* Prints image information abstracting from image header */ + void (*print_header) (void *); + /* + * The header or image contents need to be set as per image type to + * be generated using this callback function. + * further output file post processing (for ex. checksum calculation, + * padding bytes etc..) can also be done in this callback function. + */ + void (*set_header) (void *, struct stat *, int, + struct mkimage_params *); + /* + * Some image generation support for ex (default image type) supports + * more than one type_ids, this callback function is used to check + * whether input (-T ) is supported by registered image + * generation/list low level code + */ + int (*check_image_type) (uint8_t); + /* This callback function will be executed if fflag is defined */ + int (*fflag_handle) (struct mkimage_params *); + /* pointer to the next registered entry in linked list */ + struct image_type_params *next; +}; + +/* + * Exported functions + */ +void mkimage_register (struct image_type_params *tparams); + +/* + * There is a c file associated with supported image type low level code + * for ex. default_image.c, fit_image.c + * init is the only function referred by mkimage core. + * to avoid a single lined header file, you can define them here + * + * Supported image types init functions + */ +void init_default_image_type (void); +void init_fit_image_type (void); + +#endif /* _MKIIMAGE_H_ */ From 3a2003f61ee79ac53d20c24cc896c2637a2dfc24 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 19 Aug 2009 11:42:56 +0200 Subject: [PATCH 071/208] tools/mkimage: fix compiler warnings, use "const" This fixes some compiler warnings: tools/default_image.c:141: warning: initialization from incompatible pointer type tools/fit_image.c:202: warning: initialization from incompatible pointer type and changes to code to use "const" attributes in a few places where it's appropriate. Signed-off-by: Wolfgang Denk --- common/image.c | 39 ++++++++++++++++++++------------------- include/image.h | 34 +++++++++++++++++----------------- tools/mkimage.h | 2 +- 3 files changed, 38 insertions(+), 37 deletions(-) diff --git a/common/image.c b/common/image.c index e22c974f358..f3dd647c05e 100644 --- a/common/image.c +++ b/common/image.c @@ -65,7 +65,7 @@ extern int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); DECLARE_GLOBAL_DATA_PTR; -static image_header_t* image_get_ramdisk (ulong rd_addr, uint8_t arch, +static const image_header_t* image_get_ramdisk (ulong rd_addr, uint8_t arch, int verify); #else #include "mkimage.h" @@ -166,7 +166,7 @@ static void genimg_print_time (time_t timestamp); /*****************************************************************************/ /* Legacy format routines */ /*****************************************************************************/ -int image_check_hcrc (image_header_t *hdr) +int image_check_hcrc (const image_header_t *hdr) { ulong hcrc; ulong len = image_get_header_size (); @@ -181,7 +181,7 @@ int image_check_hcrc (image_header_t *hdr) return (hcrc == image_get_hcrc (hdr)); } -int image_check_dcrc (image_header_t *hdr) +int image_check_dcrc (const image_header_t *hdr) { ulong data = image_get_data (hdr); ulong len = image_get_data_size (hdr); @@ -203,7 +203,7 @@ int image_check_dcrc (image_header_t *hdr) * returns: * number of components */ -ulong image_multi_count (image_header_t *hdr) +ulong image_multi_count (const image_header_t *hdr) { ulong i, count = 0; uint32_t *size; @@ -236,7 +236,7 @@ ulong image_multi_count (image_header_t *hdr) * data address and size of the component, if idx is valid * 0 in data and len, if idx is out of range */ -void image_multi_getimg (image_header_t *hdr, ulong idx, +void image_multi_getimg (const image_header_t *hdr, ulong idx, ulong *data, ulong *len) { int i; @@ -272,7 +272,7 @@ void image_multi_getimg (image_header_t *hdr, ulong idx, } } -static void image_print_type (image_header_t *hdr) +static void image_print_type (const image_header_t *hdr) { const char *os, *arch, *type, *comp; @@ -286,7 +286,7 @@ static void image_print_type (image_header_t *hdr) /** * image_print_contents - prints out the contents of the legacy format image - * @hdr: pointer to the legacy format image header + * @ptr: pointer to the legacy format image header * @p: pointer to prefix string * * image_print_contents() formats a multi line legacy image contents description. @@ -296,8 +296,9 @@ static void image_print_type (image_header_t *hdr) * returns: * no returned results */ -void image_print_contents (image_header_t *hdr) +void image_print_contents (const void *ptr) { + const image_header_t *hdr = (const image_header_t *)ptr; const char *p; #ifdef USE_HOSTCC @@ -363,10 +364,10 @@ void image_print_contents (image_header_t *hdr) * pointer to a ramdisk image header, if image was found and valid * otherwise, return NULL */ -static image_header_t* image_get_ramdisk (ulong rd_addr, uint8_t arch, +static const image_header_t *image_get_ramdisk (ulong rd_addr, uint8_t arch, int verify) { - image_header_t *rd_hdr = (image_header_t *)rd_addr; + const image_header_t *rd_hdr = (const image_header_t *)rd_addr; if (!image_check_magic (rd_hdr)) { puts ("Bad Magic Number\n"); @@ -628,13 +629,13 @@ int genimg_get_comp_id (const char *name) */ int genimg_get_format (void *img_addr) { - ulong format = IMAGE_FORMAT_INVALID; - image_header_t *hdr; + ulong format = IMAGE_FORMAT_INVALID; + const image_header_t *hdr; #if defined(CONFIG_FIT) || defined(CONFIG_OF_LIBFDT) - char *fit_hdr; + char *fit_hdr; #endif - hdr = (image_header_t *)img_addr; + hdr = (const image_header_t *)img_addr; if (image_check_magic(hdr)) format = IMAGE_FORMAT_LEGACY; #if defined(CONFIG_FIT) || defined(CONFIG_OF_LIBFDT) @@ -685,7 +686,7 @@ ulong genimg_get_image (ulong img_addr) /* get data size */ switch (genimg_get_format ((void *)ram_addr)) { case IMAGE_FORMAT_LEGACY: - d_size = image_get_data_size ((image_header_t *)ram_addr); + d_size = image_get_data_size ((const image_header_t *)ram_addr); debug (" Legacy format image found at 0x%08lx, size 0x%08lx\n", ram_addr, d_size); break; @@ -762,7 +763,7 @@ int boot_get_ramdisk (int argc, char *argv[], bootm_headers_t *images, { ulong rd_addr, rd_load; ulong rd_data, rd_len; - image_header_t *rd_hdr; + const image_header_t *rd_hdr; #if defined(CONFIG_FIT) void *fit_hdr; const char *fit_uname_config = NULL; @@ -1085,9 +1086,9 @@ static void fdt_error (const char *msg) puts (" - must RESET the board to recover.\n"); } -static image_header_t *image_get_fdt (ulong fdt_addr) +static const image_header_t *image_get_fdt (ulong fdt_addr) { - image_header_t *fdt_hdr = (image_header_t *)fdt_addr; + const image_header_t *fdt_hdr = (const image_header_t *)fdt_addr; image_print_contents (fdt_hdr); @@ -1283,8 +1284,8 @@ error: int boot_get_fdt (int flag, int argc, char *argv[], bootm_headers_t *images, char **of_flat_tree, ulong *of_size) { + const image_header_t *fdt_hdr; ulong fdt_addr; - image_header_t *fdt_hdr; char *fdt_blob = NULL; ulong image_start, image_end; ulong load_start, load_end; diff --git a/include/image.h b/include/image.h index beb3a16cd1f..a62669fc63c 100644 --- a/include/image.h +++ b/include/image.h @@ -333,7 +333,7 @@ static inline uint32_t image_get_header_size (void) } #define image_get_hdr_l(f) \ - static inline uint32_t image_get_##f(image_header_t *hdr) \ + static inline uint32_t image_get_##f(const image_header_t *hdr) \ { \ return uimage_to_cpu (hdr->ih_##f); \ } @@ -346,7 +346,7 @@ image_get_hdr_l (ep); /* image_get_ep */ image_get_hdr_l (dcrc); /* image_get_dcrc */ #define image_get_hdr_b(f) \ - static inline uint8_t image_get_##f(image_header_t *hdr) \ + static inline uint8_t image_get_##f(const image_header_t *hdr) \ { \ return hdr->ih_##f; \ } @@ -355,12 +355,12 @@ image_get_hdr_b (arch); /* image_get_arch */ image_get_hdr_b (type); /* image_get_type */ image_get_hdr_b (comp); /* image_get_comp */ -static inline char *image_get_name (image_header_t *hdr) +static inline char *image_get_name (const image_header_t *hdr) { return (char *)hdr->ih_name; } -static inline uint32_t image_get_data_size (image_header_t *hdr) +static inline uint32_t image_get_data_size (const image_header_t *hdr) { return image_get_size (hdr); } @@ -376,16 +376,16 @@ static inline uint32_t image_get_data_size (image_header_t *hdr) * returns: * image payload data start address */ -static inline ulong image_get_data (image_header_t *hdr) +static inline ulong image_get_data (const image_header_t *hdr) { return ((ulong)hdr + image_get_header_size ()); } -static inline uint32_t image_get_image_size (image_header_t *hdr) +static inline uint32_t image_get_image_size (const image_header_t *hdr) { return (image_get_size (hdr) + image_get_header_size ()); } -static inline ulong image_get_image_end (image_header_t *hdr) +static inline ulong image_get_image_end (const image_header_t *hdr) { return ((ulong)hdr + image_get_image_size (hdr)); } @@ -418,8 +418,8 @@ static inline void image_set_name (image_header_t *hdr, const char *name) strncpy (image_get_name (hdr), name, IH_NMLEN); } -int image_check_hcrc (image_header_t *hdr); -int image_check_dcrc (image_header_t *hdr); +int image_check_hcrc (const image_header_t *hdr); +int image_check_dcrc (const image_header_t *hdr); #ifndef USE_HOSTCC int getenv_yesno (char *var); ulong getenv_bootm_low(void); @@ -427,31 +427,31 @@ phys_size_t getenv_bootm_size(void); void memmove_wd (void *to, void *from, size_t len, ulong chunksz); #endif -static inline int image_check_magic (image_header_t *hdr) +static inline int image_check_magic (const image_header_t *hdr) { return (image_get_magic (hdr) == IH_MAGIC); } -static inline int image_check_type (image_header_t *hdr, uint8_t type) +static inline int image_check_type (const image_header_t *hdr, uint8_t type) { return (image_get_type (hdr) == type); } -static inline int image_check_arch (image_header_t *hdr, uint8_t arch) +static inline int image_check_arch (const image_header_t *hdr, uint8_t arch) { return (image_get_arch (hdr) == arch); } -static inline int image_check_os (image_header_t *hdr, uint8_t os) +static inline int image_check_os (const image_header_t *hdr, uint8_t os) { return (image_get_os (hdr) == os); } -ulong image_multi_count (image_header_t *hdr); -void image_multi_getimg (image_header_t *hdr, ulong idx, +ulong image_multi_count (const image_header_t *hdr); +void image_multi_getimg (const image_header_t *hdr, ulong idx, ulong *data, ulong *len); -void image_print_contents (image_header_t *hdr); +void image_print_contents (const void *hdr); #ifndef USE_HOSTCC -static inline int image_check_target_arch (image_header_t *hdr) +static inline int image_check_target_arch (const image_header_t *hdr) { #if defined(__ARM__) if (!image_check_arch (hdr, IH_ARCH_ARM)) diff --git a/tools/mkimage.h b/tools/mkimage.h index 120970fc68f..96f2ef8f13f 100644 --- a/tools/mkimage.h +++ b/tools/mkimage.h @@ -104,7 +104,7 @@ struct image_type_params { */ int (*verify_header) (unsigned char *, int, struct mkimage_params *); /* Prints image information abstracting from image header */ - void (*print_header) (void *); + void (*print_header) (const void *); /* * The header or image contents need to be set as per image type to * be generated using this callback function. From 37b801888cf73b18f78c1109140ff44e3e37914f Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Mon, 7 Sep 2009 14:59:06 +0530 Subject: [PATCH 072/208] mkimage: Include missing files in build dependency calculations Include default_image.o and fit_image.o into the build dependency calculations. This makes sure they get rebuilt if any of the headers they include are modified Signed-off-by: Prafulla Wadaskar Acked-by: Ron Lee Edited commit message. Signed-off-by: Wolfgang Denk --- tools/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/Makefile b/tools/Makefile index 858b0e8f0a0..d5c23fd7ee9 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -93,7 +93,9 @@ EXT_OBJ_FILES-y += lib_generic/sha1.o # Source files located in the tools directory OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o OBJ_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo.o +OBJ_FILES-y += default_image.o OBJ_FILES-$(CONFIG_ENV_IS_EMBEDDED) += envcrc.o +OBJ_FILES-y += fit_image.o OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o OBJ_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes.o From f666dea8ab215c76c3c2a077ad299f90dd1ace7c Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Mon, 7 Sep 2009 14:59:07 +0530 Subject: [PATCH 073/208] mkimage: Make genimg_print_size() global Currently it is used by image.c only, but the the function can be used to support additional mkimage types like for example kwbimage, so make this function globally visible. Signed-off-by: Prafulla Wadaskar Edited commit message. Signed-off-by: Wolfgang Denk --- common/image.c | 3 +-- include/image.h | 1 + 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/common/image.c b/common/image.c index f3dd647c05e..ca8205ce43d 100644 --- a/common/image.c +++ b/common/image.c @@ -158,7 +158,6 @@ static table_entry_t uimage_comp[] = { uint32_t crc32 (uint32_t, const unsigned char *, uint); uint32_t crc32_wd (uint32_t, const unsigned char *, uint, uint); -static void genimg_print_size (uint32_t size); #if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC) static void genimg_print_time (time_t timestamp); #endif @@ -473,7 +472,7 @@ void memmove_wd (void *to, void *from, size_t len, ulong chunksz) } #endif /* !USE_HOSTCC */ -static void genimg_print_size (uint32_t size) +void genimg_print_size (uint32_t size) { #ifndef USE_HOSTCC printf ("%d Bytes = ", size); diff --git a/include/image.h b/include/image.h index a62669fc63c..4a7bf7820a8 100644 --- a/include/image.h +++ b/include/image.h @@ -292,6 +292,7 @@ int genimg_get_os_id (const char *name); int genimg_get_arch_id (const char *name); int genimg_get_type_id (const char *name); int genimg_get_comp_id (const char *name); +void genimg_print_size (uint32_t size); #ifndef USE_HOSTCC /* Image format types, returned by _get_format() routine */ From b029dddc9ae958b1ccf875649f52c6db396a742d Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Mon, 7 Sep 2009 14:59:08 +0530 Subject: [PATCH 074/208] mkimage: Make table_entry code global - make get_table_entry_id() global - make get_table_entry_name() global - move struct table_entry to image.h Currently this code is used by image.c only. This patch makes this API global so it can be used by other parts of code, too. Signed-off-by: Prafulla Wadaskar Acked-by: Ron Lee Edit comments and commit message. Signed-off-by: Wolfgang Denk --- common/image.c | 10 ++-------- include/image.h | 24 ++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 8 deletions(-) diff --git a/common/image.c b/common/image.c index ca8205ce43d..e8ecfa5c032 100644 --- a/common/image.c +++ b/common/image.c @@ -74,12 +74,6 @@ static const image_header_t* image_get_ramdisk (ulong rd_addr, uint8_t arch, #include #endif /* !USE_HOSTCC*/ -typedef struct table_entry { - int id; /* as defined in image.h */ - char *sname; /* short (input) name */ - char *lname; /* long (output) name */ -} table_entry_t; - static table_entry_t uimage_arch[] = { { IH_ARCH_INVALID, NULL, "Invalid ARCH", }, { IH_ARCH_ALPHA, "alpha", "Alpha", }, @@ -514,7 +508,7 @@ static void genimg_print_time (time_t timestamp) * long entry name if translation succeeds * msg otherwise */ -static char *get_table_entry_name (table_entry_t *table, char *msg, int id) +char *get_table_entry_name (table_entry_t *table, char *msg, int id) { for (; table->id >= 0; ++table) { if (table->id == id) @@ -561,7 +555,7 @@ const char *genimg_get_comp_name (uint8_t comp) * entry id if translation succeeds * -1 otherwise */ -static int get_table_entry_id (table_entry_t *table, +int get_table_entry_id (table_entry_t *table, const char *table_name, const char *name) { table_entry_t *t; diff --git a/include/image.h b/include/image.h index 4a7bf7820a8..d4cbf8c7093 100644 --- a/include/image.h +++ b/include/image.h @@ -284,6 +284,30 @@ typedef struct bootm_headers { #define uimage_to_cpu(x) be32_to_cpu(x) #define cpu_to_uimage(x) cpu_to_be32(x) +/* + * Translation table for entries of a specific type; used by + * get_table_entry_id() and get_table_entry_name(). + */ +typedef struct table_entry { + int id; + char *sname; /* short (input) name to find table entry */ + char *lname; /* long (output) name to print for messages */ +} table_entry_t; + +/* + * get_table_entry_id() scans the translation table trying to find an + * entry that matches the given short name. If a matching entry is + * found, it's id is returned to the caller. + */ +int get_table_entry_id (table_entry_t *table, + const char *table_name, const char *name); +/* + * get_table_entry_name() scans the translation table trying to find + * an entry that matches the given id. If a matching entry is found, + * its long name is returned to the caller. + */ +char *get_table_entry_name (table_entry_t *table, char *msg, int id); + const char *genimg_get_os_name (uint8_t os); const char *genimg_get_arch_name (uint8_t arch); const char *genimg_get_type_name (uint8_t type); From 7809fbb9aafd60e3a6e5dfe456ae30b93ac61338 Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Mon, 7 Sep 2009 14:59:09 +0530 Subject: [PATCH 075/208] Kirkwood: Sheevaplug: Add kwimage configuration file Signed-off-by: Prafulla Wadaskar --- board/Marvell/sheevaplug/config.mk | 3 + board/Marvell/sheevaplug/kwbimage.cfg | 162 ++++++++++++++++++++++++++ 2 files changed, 165 insertions(+) create mode 100644 board/Marvell/sheevaplug/kwbimage.cfg diff --git a/board/Marvell/sheevaplug/config.mk b/board/Marvell/sheevaplug/config.mk index a4ea7691095..2bd9f79fcf3 100644 --- a/board/Marvell/sheevaplug/config.mk +++ b/board/Marvell/sheevaplug/config.mk @@ -23,3 +23,6 @@ # TEXT_BASE = 0x00600000 + +# Kirkwood Boot Image configuration file +KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg diff --git a/board/Marvell/sheevaplug/kwbimage.cfg b/board/Marvell/sheevaplug/kwbimage.cfg new file mode 100644 index 00000000000..6c47d6267b9 --- /dev/null +++ b/board/Marvell/sheevaplug/kwbimage.cfg @@ -0,0 +1,162 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x37543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x00000099 # DDR Address Control +# bit1-0: 01, Cs0width=x16 +# bit3-2: 10, Cs0size=512Mb +# bit5-4: 01, Cs1width=x16 +# bit7-6: 10, Cs1size=512Mb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000C52 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000040 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb +DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 + +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000E803 # CPU ODT Control +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 From aa0c7a86cd236b8193218a09e1365c8991bb5ddc Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Mon, 7 Sep 2009 15:05:02 +0530 Subject: [PATCH 076/208] mkimage: Add Kirkwood Boot Image support (kwbimage) This patch adds support for "kwbimage" (Kirkwood Boot Image) image types to the mkimage code. For details refer to docs/README.kwbimage This patch is tested with Sheevaplug board Signed-off-by: Prafulla Wadaskar Acked-by: Ron Lee Signed-off-by: Prafulla Wadaskar --- Makefile | 5 + common/image.c | 1 + doc/README.kwbimage | 93 ++++++++++ include/image.h | 1 + tools/Makefile | 5 + tools/kwbimage.c | 405 ++++++++++++++++++++++++++++++++++++++++++++ tools/kwbimage.h | 106 ++++++++++++ tools/mkimage.c | 2 + tools/mkimage.h | 1 + 9 files changed, 619 insertions(+) create mode 100644 doc/README.kwbimage create mode 100644 tools/kwbimage.c create mode 100644 tools/kwbimage.h diff --git a/Makefile b/Makefile index 54610c637a7..9764cea894f 100644 --- a/Makefile +++ b/Makefile @@ -324,6 +324,10 @@ $(obj)u-boot.img: $(obj)u-boot.bin sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \ -d $< $@ +$(obj)u-boot.kwb: $(obj)u-boot.bin + $(obj)tools/mkimage -n $(KWD_CONFIG) -T kwbimage \ + -a $(TEXT_BASE) -e $(TEXT_BASE) -d $< $@ + $(obj)u-boot.sha1: $(obj)u-boot.bin $(obj)tools/ubsha1 $(obj)u-boot.bin @@ -3759,6 +3763,7 @@ clobber: clean @rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS \ $(obj)cscope.* $(obj)*.*~ @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL) + @rm -f $(obj)u-boot.kwb @rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes} @rm -f $(obj)cpu/mpc824x/bedbug_603e.c @rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm diff --git a/common/image.c b/common/image.c index e8ecfa5c032..d0f169d660c 100644 --- a/common/image.c +++ b/common/image.c @@ -139,6 +139,7 @@ static table_entry_t uimage_type[] = { { IH_TYPE_SCRIPT, "script", "Script", }, { IH_TYPE_STANDALONE, "standalone", "Standalone Program", }, { IH_TYPE_FLATDT, "flat_dt", "Flat Device Tree", }, + { IH_TYPE_KWBIMAGE, "kwbimage", "Kirkwood Boot Image",}, { -1, "", "", }, }; diff --git a/doc/README.kwbimage b/doc/README.kwbimage new file mode 100644 index 00000000000..2a5b3b3be5d --- /dev/null +++ b/doc/README.kwbimage @@ -0,0 +1,93 @@ +--------------------------------------------- +Kirkwood Boot Image generation using mkimage +--------------------------------------------- + +This document describes the U-Boot feature as it +is implemented for the Kirkwood family of SoCs. + +The Kirkwood SoC's can boot directly from NAND FLASH, +SPI FLASH, SATA etc. using its internal bootRom support. + +for more details refer section 24.2 of Kirkwood functional specifications. +ref: www.marvell.com/products/embedded.../kirkwood/index.jsp + +Command syntax: +-------------- +./tools/mkimage -l + to list the kwb image file details + +./tools/mkimage -n \ + -T kwbimage -a -e \ + -d + +for ex. +./tools/mkimage -n ./board/Marvell/openrd_base/kwbimage.cfg \ + -T kwbimage -a 0x00600000 -e 0x00600000 \ + -d u-boot.bin u-boot.kwb + +kwimage support available with mkimage utility will generate kirkwood boot +image that can be flashed on the board NAND/SPI flash + +Board specific configuration file specifications: +------------------------------------------------ +1. This file must present in the $(BOARDDIR) and the name should be + kwbimage.cfg (since this is used in Makefile) +2. This file can have empty lines and lines starting with "#" as first + character to put comments +3. This file can have configuration command lines as mentioned below, + any other information in this file is treated as invalid. + +Configuration command line syntax: +--------------------------------- +1. Each command line is must have two strings, first one command or address + and second one data string +2. Following are the valid command strings and associated data strings:- + Command string data string + -------------- ----------- + BOOT_FROM nand/spi/sata + NAND_ECC_MODE default/rs/hamming/disabled + NAND_PAGE_SIZE any uint16_t hex value + SATA_PIO_MODE any uint32_t hex value + DDR_INIT_DELAY any uint32_t hex value + DATA regaddr and regdara hex value + you can have maximum 55 such register programming commands + +3. All commands are optional to program + +Typical example of kwimage.cfg file: +----------------------------------- + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b +# DRAM Configuration +DATA 0xFFD01400 0x43000c30 +DATA 0xFFD01404 0x37543000 +DATA 0xFFD01408 0x22125451 +DATA 0xFFD0140C 0x00000a33 +DATA 0xFFD01410 0x000000cc +DATA 0xFFD01414 0x00000000 +DATA 0xFFD01418 0x00000000 +DATA 0xFFD0141C 0x00000C52 +DATA 0xFFD01420 0x00000040 +DATA 0xFFD01424 0x0000F17F +DATA 0xFFD01428 0x00085520 +DATA 0xFFD0147C 0x00008552 +DATA 0xFFD01504 0x0FFFFFF1 +DATA 0xFFD01508 0x10000000 +DATA 0xFFD0150C 0x0FFFFFF5 +DATA 0xFFD01514 0x00000000 +DATA 0xFFD0151C 0x00000000 +DATA 0xFFD01494 0x00030000 +DATA 0xFFD01498 0x00000000 +DATA 0xFFD0149C 0x0000E803 +DATA 0xFFD01480 0x00000001 +# End of Header extension +DATA 0x0 0x0 + +------------------------------------------------ +Author: Prafulla Wadaskar diff --git a/include/image.h b/include/image.h index d4cbf8c7093..5a424e6a942 100644 --- a/include/image.h +++ b/include/image.h @@ -155,6 +155,7 @@ #define IH_TYPE_SCRIPT 6 /* Script file */ #define IH_TYPE_FILESYSTEM 7 /* Filesystem Image (any type) */ #define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */ +#define IH_TYPE_KWBIMAGE 9 /* Kirkwood Boot Image */ /* * Compression Types diff --git a/tools/Makefile b/tools/Makefile index d5c23fd7ee9..b04e3f30441 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -99,6 +99,7 @@ OBJ_FILES-y += fit_image.o OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o OBJ_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes.o +OBJ_FILES-y += kwbimage.o OBJ_FILES-y += mkimage.o OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o OBJ_FILES-y += os_support.o @@ -189,6 +190,7 @@ $(obj)mkimage$(SFX): $(obj)crc32.o \ $(obj)default_image.o \ $(obj)fit_image.o \ $(obj)image.o \ + $(obj)kwbimage.o \ $(obj)md5.o \ $(obj)mkimage.o \ $(obj)os_support.o \ @@ -218,6 +220,9 @@ $(obj)fit_image.o: $(SRCTREE)/tools/fit_image.c $(obj)image.o: $(SRCTREE)/common/image.c $(CC) -g $(FIT_CFLAGS) -c -o $@ $< +$(obj)kwbimage.o: $(SRCTREE)/tools/kwbimage.c + $(CC) -g $(FIT_CFLAGS) -c -o $@ $< + $(obj)mkimage.o: $(SRCTREE)/tools/mkimage.c $(CC) -g $(FIT_CFLAGS) -c -o $@ $< diff --git a/tools/kwbimage.c b/tools/kwbimage.c new file mode 100644 index 00000000000..28dc2d605df --- /dev/null +++ b/tools/kwbimage.c @@ -0,0 +1,405 @@ +/* + * (C) Copyright 2008 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Required to obtain the getline prototype from stdio.h */ +#define _GNU_SOURCE + +#include "mkimage.h" +#include +#include "kwbimage.h" + +/* + * Supported commands for configuration file + */ +static table_entry_t kwbimage_cmds[] = { + {CMD_BOOT_FROM, "BOOT_FROM", "boot comand", }, + {CMD_NAND_ECC_MODE, "NAND_ECC_MODE", "NAND mode", }, + {CMD_NAND_PAGE_SIZE, "NAND_PAGE_SIZE", "NAND size", }, + {CMD_SATA_PIO_MODE, "SATA_PIO_MODE", "SATA mode", }, + {CMD_DDR_INIT_DELAY, "DDR_INIT_DELAY", "DDR init dly", }, + {CMD_DATA, "DATA", "Reg Write Data", }, + {CMD_INVALID, "", "", }, +}; + +/* + * Supported Boot options for configuration file + */ +static table_entry_t kwbimage_bootops[] = { + {IBR_HDR_SPI_ID, "spi", "SPI Flash", }, + {IBR_HDR_NAND_ID, "nand", "NAND Flash", }, + {IBR_HDR_SATA_ID, "sata", "Sata port", }, + {IBR_HDR_PEX_ID, "pex", "PCIe port", }, + {IBR_HDR_UART_ID, "uart", "Serial port", }, + {-1, "", "Invalid", }, +}; + +/* + * Supported NAND ecc options configuration file + */ +static table_entry_t kwbimage_eccmodes[] = { + {IBR_HDR_ECC_DEFAULT, "default", "Default mode", }, + {IBR_HDR_ECC_FORCED_HAMMING, "hamming", "Hamming mode", }, + {IBR_HDR_ECC_FORCED_RS, "rs", "RS mode", }, + {IBR_HDR_ECC_DISABLED, "disabled", "ECC Disabled", }, + {-1, "", "", }, +}; + +static struct kwb_header kwbimage_header; +static int datacmd_cnt = 0; +static char * fname = "Unknown"; +static int lineno = -1; + +/* + * Report Error if xflag is set in addition to default + */ +static int kwbimage_check_params (struct mkimage_params *params) +{ + if (!strlen (params->imagename)) { + printf ("Error:%s - Configuration file not specified, " + "it is needed for kwbimage generation\n", + params->cmdname); + return CFG_INVALID; + } + return ((params->dflag && (params->fflag || params->lflag)) || + (params->fflag && (params->dflag || params->lflag)) || + (params->lflag && (params->dflag || params->fflag)) || + (params->xflag) || !(strlen (params->imagename))); +} + +static uint32_t check_get_hexval (char *token) +{ + uint32_t hexval; + + if (!sscanf (token, "%x", &hexval)) { + printf ("Error:%s[%d] - Invalid hex data(%s)\n", fname, + lineno, token); + exit (EXIT_FAILURE); + } + return hexval; +} + +/* + * Generates 8 bit checksum + */ +static uint8_t kwbimage_checksum8 (void *start, uint32_t len, uint8_t csum) +{ + register uint8_t sum = csum; + volatile uint8_t *p = (volatile uint8_t *)start; + + /* check len and return zero checksum if invalid */ + if (!len) + return 0; + + do { + sum += *p; + p++; + } while (--len); + return (sum); +} + +/* + * Generates 32 bit checksum + */ +static uint32_t kwbimage_checksum32 (uint32_t *start, uint32_t len, uint32_t csum) +{ + register uint32_t sum = csum; + volatile uint32_t *p = start; + + /* check len and return zero checksum if invalid */ + if (!len) + return 0; + + if (len % sizeof(uint32_t)) { + printf ("Error:%s[%d] - lenght is not in multiple of %d\n", + __FUNCTION__, len, sizeof(uint32_t)); + return 0; + } + + do { + sum += *p; + p++; + len -= sizeof(uint32_t); + } while (len > 0); + return (sum); +} + +static void kwbimage_check_cfgdata (char *token, enum kwbimage_cmd cmdsw, + struct kwb_header *kwbhdr) +{ + bhr_t *mhdr = &kwbhdr->kwb_hdr; + extbhr_t *exthdr = &kwbhdr->kwb_exthdr; + int i; + + switch (cmdsw) { + case CMD_BOOT_FROM: + i = get_table_entry_id (kwbimage_bootops, + "Kwbimage boot option", token); + + if (i < 0) + goto INVL_DATA; + + mhdr->blockid = i; + printf ("Preparing kirkwood boot image to boot " + "from %s\n", token); + break; + case CMD_NAND_ECC_MODE: + i = get_table_entry_id (kwbimage_eccmodes, + "NAND ecc mode", token); + + if (i < 0) + goto INVL_DATA; + + mhdr->nandeccmode = i; + printf ("Nand ECC mode = %s\n", token); + break; + case CMD_NAND_PAGE_SIZE: + mhdr->nandpagesize = + (uint16_t) check_get_hexval (token); + printf ("Nand page size = 0x%x\n", mhdr->nandpagesize); + break; + case CMD_SATA_PIO_MODE: + mhdr->satapiomode = + (uint8_t) check_get_hexval (token); + printf ("Sata PIO mode = 0x%x\n", + mhdr->satapiomode); + break; + case CMD_DDR_INIT_DELAY: + mhdr->ddrinitdelay = + (uint16_t) check_get_hexval (token); + printf ("DDR init delay = %d msec\n", mhdr->ddrinitdelay); + break; + case CMD_DATA: + exthdr->rcfg[datacmd_cnt].raddr = + check_get_hexval (token); + + break; + case CMD_INVALID: + goto INVL_DATA; + default: + goto INVL_DATA; + } + return; + +INVL_DATA: + printf ("Error:%s[%d] - Invalid data\n", fname, lineno); + exit (EXIT_FAILURE); +} + +/* + * this function sets the kwbimage header by- + * 1. Abstracting input command line arguments data + * 2. parses the kwbimage configuration file and update extebded header data + * 3. calculates header, extended header and image checksums + */ +static void kwdimage_set_ext_header (struct kwb_header *kwbhdr, char* name) { + bhr_t *mhdr = &kwbhdr->kwb_hdr; + extbhr_t *exthdr = &kwbhdr->kwb_exthdr; + FILE *fd = NULL; + int j; + char *line = NULL; + char * token, *saveptr1, *saveptr2; + size_t len = 0; + enum kwbimage_cmd cmd; + + fname = name; + /* set dram register offset */ + exthdr->dramregsoffs = (intptr_t)&exthdr->rcfg - (intptr_t)mhdr; + + if ((fd = fopen (name, "r")) == 0) { + printf ("Error:%s - Can't open\n", fname); + exit (EXIT_FAILURE); + } + + /* Simple kwimage.cfg file parser */ + lineno=0; + while ((getline (&line, &len, fd)) > 0) { + lineno++; + token = strtok_r (line, "\r\n", &saveptr1); + /* drop all lines with zero tokens (= empty lines) */ + if (token == NULL) + continue; + + for (j = 0, cmd = CMD_INVALID, line = token; ; line = NULL) { + token = strtok_r (line, " \t", &saveptr2); + if (token == NULL) + break; + /* Drop all text starting with '#' as comments */ + if (token[0] == '#') + break; + + /* Process rest as valid config command line */ + switch (j) { + case CFG_COMMAND: + cmd = get_table_entry_id (kwbimage_cmds, + "Kwbimage command", token); + + if (cmd == CMD_INVALID) + goto INVL_CMD; + break; + + case CFG_DATA0: + kwbimage_check_cfgdata (token, cmd, kwbhdr); + break; + + case CFG_DATA1: + if (cmd != CMD_DATA) + goto INVL_CMD; + + exthdr->rcfg[datacmd_cnt].rdata = + check_get_hexval (token); + + if (datacmd_cnt > KWBIMAGE_MAX_CONFIG ) { + printf ("Error:%s[%d] - Found more " + "than max(%zd) allowed " + "data configurations\n", + fname, lineno, + KWBIMAGE_MAX_CONFIG); + exit (EXIT_FAILURE); + } else + datacmd_cnt++; + break; + + default: + goto INVL_CMD; + } + j++; + } + } + if (line) + free (line); + + fclose (fd); + return; + +/* + * Invalid Command error reporring + * + * command CMD_DATA needs three strings on a line + * whereas other commands need only two. + * + * if more than two/three (as per command type) are observed, + * then error will be reported + */ +INVL_CMD: + printf ("Error:%s[%d] - Invalid command\n", fname, lineno); + exit (EXIT_FAILURE); +} + +static void kwbimage_set_header (void *ptr, struct stat *sbuf, int ifd, + struct mkimage_params *params) +{ + struct kwb_header *hdr = (struct kwb_header *)ptr; + bhr_t *mhdr = &hdr->kwb_hdr; + extbhr_t *exthdr = &hdr->kwb_exthdr; + uint32_t checksum; + int size; + + /* Build and add image checksum header */ + checksum = kwbimage_checksum32 ((uint32_t *)ptr, sbuf->st_size, 0); + + size = write (ifd, &checksum, sizeof(uint32_t)); + if (size != sizeof(uint32_t)) { + printf ("Error:%s - Checksum write %d bytes %s\n", + params->cmdname, size, params->imagefile); + exit (EXIT_FAILURE); + } + + sbuf->st_size += sizeof(uint32_t); + + mhdr->blocksize = sbuf->st_size - sizeof(struct kwb_header); + mhdr->srcaddr = sizeof(struct kwb_header); + mhdr->destaddr= params->addr; + mhdr->execaddr =params->ep; + mhdr->ext = 0x1; /* header extension appended */ + + kwdimage_set_ext_header (hdr, params->imagename); + /* calculate checksums */ + mhdr->checkSum = kwbimage_checksum8 ((void *)mhdr, sizeof(bhr_t), 0); + exthdr->checkSum = kwbimage_checksum8 ((void *)exthdr, + sizeof(extbhr_t), 0); +} + +static int kwbimage_verify_header (unsigned char *ptr, int image_size, + struct mkimage_params *params) +{ + struct kwb_header *hdr = (struct kwb_header *)ptr; + bhr_t *mhdr = &hdr->kwb_hdr; + extbhr_t *exthdr = &hdr->kwb_exthdr; + uint8_t calc_hdrcsum; + uint8_t calc_exthdrcsum; + + calc_hdrcsum = kwbimage_checksum8 ((void *)mhdr, + sizeof(bhr_t) - sizeof(uint8_t), 0); + if (calc_hdrcsum != mhdr->checkSum) + return -FDT_ERR_BADSTRUCTURE; /* mhdr csum not matched */ + + calc_exthdrcsum = kwbimage_checksum8 ((void *)exthdr, + sizeof(extbhr_t) - sizeof(uint8_t), 0); + if (calc_hdrcsum != mhdr->checkSum) + return -FDT_ERR_BADSTRUCTURE; /* exthdr csum not matched */ + + return 0; +} + +static void kwbimage_print_header (const void *ptr) +{ + struct kwb_header *hdr = (struct kwb_header *) ptr; + bhr_t *mhdr = &hdr->kwb_hdr; + char *name = get_table_entry_name (kwbimage_bootops, + "Kwbimage boot option", + (int) mhdr->blockid); + + printf ("Image Type: Kirkwood Boot from %s Image\n", name); + printf ("Data Size: "); + genimg_print_size (mhdr->blocksize - sizeof(uint32_t)); + printf ("Load Address: %08x\n", mhdr->destaddr); + printf ("Entry Point: %08x\n", mhdr->execaddr); +} + +static int kwbimage_check_image_types (uint8_t type) +{ + if (type == IH_TYPE_KWBIMAGE) + return EXIT_SUCCESS; + else + return EXIT_FAILURE; +} + +/* + * kwbimage type parameters definition + */ +static struct image_type_params kwbimage_params = { + .name = "Kirkwood Boot Image support", + .header_size = sizeof(struct kwb_header), + .hdr = (void*)&kwbimage_header, + .check_image_type = kwbimage_check_image_types, + .verify_header = kwbimage_verify_header, + .print_header = kwbimage_print_header, + .set_header = kwbimage_set_header, + .check_params = kwbimage_check_params, +}; + +void init_kwb_image_type (void) +{ + mkimage_register (&kwbimage_params); +} diff --git a/tools/kwbimage.h b/tools/kwbimage.h new file mode 100644 index 00000000000..3d3d5e9130c --- /dev/null +++ b/tools/kwbimage.h @@ -0,0 +1,106 @@ +/* + * (C) Copyright 2008 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _KWBIMAGE_H_ +#define _KWBIMAGE_H_ + +#include + +#define KWBIMAGE_MAX_CONFIG ((0x1dc - 0x20)/sizeof(struct reg_config)) +#define MAX_TEMPBUF_LEN 32 + +/* NAND ECC Mode */ +#define IBR_HDR_ECC_DEFAULT 0x00 +#define IBR_HDR_ECC_FORCED_HAMMING 0x01 +#define IBR_HDR_ECC_FORCED_RS 0x02 +#define IBR_HDR_ECC_DISABLED 0x03 + +/* Boot Type - block ID */ +#define IBR_HDR_I2C_ID 0x4D +#define IBR_HDR_SPI_ID 0x5A +#define IBR_HDR_NAND_ID 0x8B +#define IBR_HDR_SATA_ID 0x78 +#define IBR_HDR_PEX_ID 0x9C +#define IBR_HDR_UART_ID 0x69 +#define IBR_DEF_ATTRIB 0x00 + +enum kwbimage_cmd { + CMD_INVALID, + CMD_BOOT_FROM, + CMD_NAND_ECC_MODE, + CMD_NAND_PAGE_SIZE, + CMD_SATA_PIO_MODE, + CMD_DDR_INIT_DELAY, + CMD_DATA +}; + +enum kwbimage_cmd_types { + CFG_INVALID = -1, + CFG_COMMAND, + CFG_DATA0, + CFG_DATA1 +}; + +/* typedefs */ +typedef struct bhr_t { + uint8_t blockid; /*0 */ + uint8_t nandeccmode; /*1 */ + uint16_t nandpagesize; /*2-3 */ + uint32_t blocksize; /*4-7 */ + uint32_t rsvd1; /*8-11 */ + uint32_t srcaddr; /*12-15 */ + uint32_t destaddr; /*16-19 */ + uint32_t execaddr; /*20-23 */ + uint8_t satapiomode; /*24 */ + uint8_t rsvd3; /*25 */ + uint16_t ddrinitdelay; /*26-27 */ + uint16_t rsvd2; /*28-29 */ + uint8_t ext; /*30 */ + uint8_t checkSum; /*31 */ +} bhr_t, *pbhr_t; + +struct reg_config { + uint32_t raddr; + uint32_t rdata; +}; + +typedef struct extbhr_t { + uint32_t dramregsoffs; + uint8_t rsrvd1[0x20 - sizeof(uint32_t)]; + struct reg_config rcfg[KWBIMAGE_MAX_CONFIG]; + uint8_t rsrvd2[7]; + uint8_t checkSum; +} extbhr_t, *pextbhr_t; + +struct kwb_header { + bhr_t kwb_hdr; + extbhr_t kwb_exthdr; +}; + +/* + * functions + */ +void init_kwb_image_type (void); + +#endif /* _KWBIMAGE_H_ */ diff --git a/tools/mkimage.c b/tools/mkimage.c index c43b2077269..ab6ea32ad05 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -148,6 +148,8 @@ main (int argc, char **argv) int retval = 0; struct image_type_params *tparams = NULL; + /* Init Kirkwood Boot image generation/list support */ + init_kwb_image_type (); /* Init FIT image generation/list support */ init_fit_image_type (); /* Init Default image generation/list support */ diff --git a/tools/mkimage.h b/tools/mkimage.h index 96f2ef8f13f..ec6733625dc 100644 --- a/tools/mkimage.h +++ b/tools/mkimage.h @@ -139,6 +139,7 @@ void mkimage_register (struct image_type_params *tparams); * * Supported image types init functions */ +void init_kwb_image_type (void); void init_default_image_type (void); void init_fit_image_type (void); From 45f89f340b4d8aa099fd022260dcb13cf3321b61 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 9 Sep 2009 21:22:08 +0200 Subject: [PATCH 077/208] ep8248: add support for device tree and secondary Ethernet interface. Signed-off-by: Marcel Ziswiler --- board/ep8248/ep8248.c | 12 ++++++++-- include/configs/ep8248.h | 49 ++++++++++++++++------------------------ 2 files changed, 29 insertions(+), 32 deletions(-) diff --git a/board/ep8248/ep8248.c b/board/ep8248/ep8248.c index bc20ba739c2..57d39aa7e55 100644 --- a/board/ep8248/ep8248.c +++ b/board/ep8248/ep8248.c @@ -35,8 +35,8 @@ * according to the five values podr/pdir/ppar/psor/pdat for that entry */ -#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1) -#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2) +#define CONFIG_SYS_FCC1 (CONFIG_ETHER_ON_FCC1 == 1) +#define CONFIG_SYS_FCC2 (CONFIG_ETHER_ON_FCC2 == 1) const iop_conf_t iop_conf_tab[4][32] = { @@ -261,3 +261,11 @@ int checkboard(void) return 0; } + +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup( blob, bd); +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ + diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h index f7b3fdea88d..cb4185a67bb 100644 --- a/include/configs/ep8248.h +++ b/include/configs/ep8248.h @@ -50,50 +50,41 @@ #define CONFIG_SYS_BCSR 0xFA000000 -/* - * Select ethernet configuration - * - * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, - * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for - * SCC, 1-3 for FCC) - * - * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CONFIG_CMD_NET - * must be unset. - */ +/* Pass open firmware flat device tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc/cpm/serial 11a80" + +/* Select ethernet configuration */ #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ #undef CONFIG_ETHER_NONE /* No external Ethernet */ -#ifdef CONFIG_ETHER_ON_FCC - -#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */ - -#if (CONFIG_ETHER_INDEX == 1) +#define CONFIG_NET_MULTI +#define CONFIG_SYS_CPMFCR_RAMTYPE 0 +#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) +#define CONFIG_HAS_ETH0 +#define CONFIG_ETHER_ON_FCC1 1 /* - Rx clock is CLK10 * - Tx clock is CLK11 * - BDs/buffers on 60x bus * - Full duplex */ -#define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) -#define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11) -#define CONFIG_SYS_CPMFCR_RAMTYPE 0 -#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#elif (CONFIG_ETHER_INDEX == 2) +#define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) +#define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11) +#define CONFIG_HAS_ETH1 +#define CONFIG_ETHER_ON_FCC2 1 /* - Rx clock is CLK13 * - Tx clock is CLK14 * - BDs/buffers on 60x bus * - Full duplex */ -#define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) -#define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) -#define CONFIG_SYS_CPMFCR_RAMTYPE 0 -#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_INDEX */ +#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) +#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) #define CONFIG_MII /* MII PHY management */ #define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ @@ -113,8 +104,6 @@ #define MIIDELAY udelay(1) -#endif /* CONFIG_ETHER_ON_FCC */ - #ifndef CONFIG_8260_CLKIN #define CONFIG_8260_CLKIN 66000000 /* in Hz */ #endif From c7c1dbbf7159b38f3302b845dd97d28a543ff91b Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 9 Sep 2009 21:09:00 +0200 Subject: [PATCH 078/208] r7780mp: fix typo in Ethernet chip model number comment. Signed-off-by: Marcel Ziswiler --- include/configs/r7780mp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h index 7738a17b01f..71c570eee90 100644 --- a/include/configs/r7780mp.h +++ b/include/configs/r7780mp.h @@ -154,7 +154,7 @@ #define CONFIG_NET_MULTI #define CONFIG_RTL8169 */ -/* AX88696L Support(NE2000 base chip) */ +/* AX88796L Support(NE2000 base chip) */ #define CONFIG_DRIVER_NE2000 #define CONFIG_DRIVER_AX88796L #define CONFIG_DRIVER_NE2000_BASE 0xA4100000 From e7963772eb78a6aa1fa65063d64eab3a8626daac Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 9 Sep 2009 21:11:18 +0200 Subject: [PATCH 079/208] muas3001: remove BRG clock node fixup to use common mpc8260 code. Signed-off-by: Marcel Ziswiler Acked-by: Heiko Schocher --- board/muas3001/muas3001.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/board/muas3001/muas3001.c b/board/muas3001/muas3001.c index 8f83dd9af8e..bf4ccb6e190 100644 --- a/board/muas3001/muas3001.c +++ b/board/muas3001/muas3001.c @@ -310,7 +310,6 @@ void ft_blob_update (void *blob, bd_t *bd) int ret, nodeoffset = 0; ulong memory_data[2] = {0}; ulong flash_data[4] = {0}; - ulong freq = 0; ulong speed = 0; memory_data[0] = cpu_to_be32 (bd->bi_memstart); @@ -359,21 +358,6 @@ void ft_blob_update (void *blob, bd_t *bd) "err:%s\n", fdt_strerror (nodeoffset)); } - /* brg clock */ - nodeoffset = fdt_path_offset (blob, "/soc/cpm/brg"); - if (nodeoffset >= 0) { - freq = cpu_to_be32 (bd->bi_brgfreq); - ret = fdt_setprop (blob, nodeoffset, "clock-frequency", &freq, - sizeof (unsigned long)); - if (ret < 0) - printf ("ft_blob_update): cannot set /soc/cpm/brg/clock-frequency " - "property err:%s\n", fdt_strerror (ret)); - } else { - /* memory node is required in dts */ - printf ("ft_blob_update(): cannot find /soc/cpm/brg/clock-frequency node " - "err:%s\n", fdt_strerror (nodeoffset)); - } - /* baudrate */ nodeoffset = fdt_path_offset (blob, "/soc/cpm/serial"); if (nodeoffset >= 0) { From 51003b89816848cbe86a8fe48f970ba8b14005f5 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 11 Sep 2009 08:58:11 +0200 Subject: [PATCH 080/208] kwbimage.c: Fix compile warning when building on 64 bit systems Fix this warning when building on 64 bit systems: tools/kwbimage.c: In function 'kwbimage_checksum32': tools/kwbimage.c:135: warning: format '%d' expects type 'int', but argument 4 has type 'long unsigned int' Signed-off-by: Wolfgang Denk Cc: Prafulla Wadaskar --- tools/kwbimage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/kwbimage.c b/tools/kwbimage.c index 28dc2d605df..ee067cbd81d 100644 --- a/tools/kwbimage.c +++ b/tools/kwbimage.c @@ -131,7 +131,7 @@ static uint32_t kwbimage_checksum32 (uint32_t *start, uint32_t len, uint32_t csu return 0; if (len % sizeof(uint32_t)) { - printf ("Error:%s[%d] - lenght is not in multiple of %d\n", + printf ("Error:%s[%d] - lenght is not in multiple of %ld\n", __FUNCTION__, len, sizeof(uint32_t)); return 0; } From d8d8724be06df43772162dc344ae20dfa814dc72 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 11 Sep 2009 09:05:32 +0200 Subject: [PATCH 081/208] net/bootp.c: fix compile warning Fix warning: bootp.c:695: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Wolfgang Denk Cc: Ben Warren --- net/bootp.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/net/bootp.c b/net/bootp.c index 0799ae2b0fc..309385278f3 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -683,6 +683,9 @@ static void DhcpOptionsProcess (uchar * popt, Bootp_t *bp) { uchar *end = popt + BOOTP_HDR_SIZE; int oplen, size; +#if defined(CONFIG_CMD_SNTP) && defined(CONFIG_BOOTP_TIMEOFFSET) + int *to_ptr; +#endif while (popt < end && *popt != 0xff) { oplen = *(popt + 1); @@ -692,7 +695,8 @@ static void DhcpOptionsProcess (uchar * popt, Bootp_t *bp) break; #if defined(CONFIG_CMD_SNTP) && defined(CONFIG_BOOTP_TIMEOFFSET) case 2: /* Time offset */ - NetCopyLong ((ulong *)&NetTimeOffset, (ulong *) (popt + 2)); + to_ptr = &NetTimeOffset; + NetCopyLong ((ulong *)to_ptr, (ulong *)(popt + 2)); NetTimeOffset = ntohl (NetTimeOffset); break; #endif From d1c3b27525b664e8c4db6bb173eed51bfc8220de Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 9 Sep 2009 16:25:29 +0200 Subject: [PATCH 082/208] ppc4xx: Big cleanup of PPC4xx defines This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese --- board/amcc/acadia/acadia.c | 12 +- board/amcc/acadia/memory.c | 18 +- board/amcc/acadia/pll.c | 52 +-- board/amcc/bamboo/bamboo.c | 104 ++--- board/amcc/bamboo/flash.c | 2 +- board/amcc/bubinga/bubinga.c | 4 +- board/amcc/bubinga/flash.c | 20 +- board/amcc/canyonlands/canyonlands.c | 4 +- board/amcc/ebony/ebony.c | 32 +- board/amcc/katmai/katmai.c | 6 +- board/amcc/luan/luan.c | 18 +- board/amcc/ocotea/ocotea.c | 48 +-- board/amcc/redwood/redwood.c | 18 +- board/amcc/sequoia/sequoia.c | 60 +-- board/amcc/taihu/taihu.c | 6 +- board/amcc/taishan/showinfo.c | 70 ++-- board/amcc/taishan/taishan.c | 44 +-- board/amcc/walnut/flash.c | 20 +- board/amcc/yosemite/yosemite.c | 58 +-- board/amcc/yucca/flash.c | 2 +- board/amcc/yucca/yucca.c | 20 +- board/cray/L1/L1.c | 38 +- board/cray/L1/init.S | 24 +- board/csb272/csb272.c | 18 +- board/csb272/init.S | 50 +-- board/csb472/csb472.c | 18 +- board/csb472/init.S | 54 +-- board/dave/PPChameleonEVB/PPChameleonEVB.c | 6 +- board/dave/PPChameleonEVB/flash.c | 8 +- board/eric/eric.c | 2 +- board/eric/flash.c | 20 +- board/eric/init.S | 126 +++--- board/esd/apc405/apc405.c | 26 +- board/esd/ar405/flash.c | 8 +- board/esd/ash405/ash405.c | 2 +- board/esd/ash405/flash.c | 8 +- board/esd/canbt/canbt.c | 8 +- board/esd/canbt/flash.c | 10 +- board/esd/cms700/cms700.c | 2 +- board/esd/cms700/flash.c | 8 +- board/esd/cpci2dp/cpci2dp.c | 12 +- board/esd/cpci2dp/flash.c | 10 +- board/esd/cpci405/cpci405.c | 22 +- board/esd/cpci405/flash.c | 20 +- board/esd/cpciiser4/flash.c | 10 +- board/esd/dp405/dp405.c | 2 +- board/esd/dp405/flash.c | 8 +- board/esd/du405/du405.c | 8 +- board/esd/du405/flash.c | 20 +- board/esd/du440/du440.c | 56 +-- board/esd/hh405/flash.c | 8 +- board/esd/hh405/hh405.c | 2 +- board/esd/hub405/flash.c | 8 +- board/esd/hub405/hub405.c | 2 +- board/esd/ocrtc/flash.c | 20 +- board/esd/ocrtc/ocrtc.c | 2 +- board/esd/pci405/flash.c | 8 +- board/esd/pci405/pci405.c | 28 +- board/esd/plu405/flash.c | 8 +- board/esd/plu405/plu405.c | 2 +- board/esd/pmc405/pmc405.c | 6 +- board/esd/pmc405de/pmc405de.c | 2 +- board/esd/pmc440/pmc440.c | 66 ++-- board/esd/voh405/flash.c | 8 +- board/esd/voh405/voh405.c | 2 +- board/esd/vom405/flash.c | 8 +- board/esd/vom405/vom405.c | 2 +- board/esd/wuh405/flash.c | 8 +- board/esd/wuh405/wuh405.c | 2 +- board/exbitgen/exbitgen.c | 16 +- board/exbitgen/init.S | 104 ++--- board/g2000/g2000.c | 14 +- board/gdsys/compactcenter/compactcenter.c | 2 +- board/gdsys/dlvision/dlvision.c | 2 +- board/gdsys/gdppc440etx/gdppc440etx.c | 52 +-- board/gdsys/neo/neo.c | 2 +- board/jse/init.S | 14 +- board/jse/jse.c | 8 +- board/jse/sdram.c | 80 ++-- board/korat/korat.c | 64 +-- board/lwmon5/lwmon5.c | 52 +-- board/mpl/common/flash.c | 58 +-- board/mpl/mip405/init.S | 74 ++-- board/mpl/mip405/mip405.c | 132 +++---- board/mpl/pip405/init.S | 74 ++-- board/mpl/pip405/pip405.c | 82 ++-- board/netstal/hcu4/hcu4.c | 2 +- board/netstal/hcu5/hcu5.c | 30 +- board/netstal/hcu5/sdram.c | 4 +- board/netstal/mcu25/mcu25.c | 6 +- board/pcs440ep/pcs440ep.c | 58 +-- board/prodrive/alpr/alpr.c | 6 +- board/prodrive/p3p440/p3p440.c | 22 +- board/sandburst/common/sb_common.c | 2 +- board/sandburst/karef/karef.c | 36 +- board/sandburst/metrobox/metrobox.c | 36 +- board/sbc405/sbc405.c | 2 +- board/sc3/init.S | 130 +++---- board/sc3/sc3.c | 96 ++--- board/snmc/qs850/flash.c | 16 +- board/snmc/qs860t/flash.c | 16 +- board/tb0229/flash.c | 20 +- board/w7o/init.S | 66 ++-- board/w7o/w7o.c | 16 +- board/xes/xpedite1000/xpedite1000.c | 26 +- board/zeus/zeus.c | 6 +- common/cmd_reginfo.c | 146 +++---- cpu/ppc4xx/40x_spd_sdram.c | 2 +- cpu/ppc4xx/44x_spd_ddr.c | 20 +- cpu/ppc4xx/4xx_pci.c | 10 +- cpu/ppc4xx/4xx_uart.c | 28 +- cpu/ppc4xx/cpu.c | 38 +- cpu/ppc4xx/cpu_init.c | 68 ++-- cpu/ppc4xx/fdt.c | 4 +- cpu/ppc4xx/sdram.c | 4 +- cpu/ppc4xx/speed.c | 52 +-- cpu/ppc4xx/start.S | 112 +++--- cpu/ppc4xx/usbdev.c | 4 +- drivers/mtd/nand/ndfc.c | 4 +- drivers/net/4xx_enet.c | 136 +++---- include/configs/W7OLMC.h | 4 +- include/configs/W7OLMG.h | 4 +- include/ppc405.h | 395 ++++++------------- include/ppc440.h | 432 +++++++-------------- include/ppc4xx.h | 104 +++-- nand_spl/board/amcc/bamboo/sdram.c | 4 +- post/cpu/ppc4xx/ether.c | 50 +-- post/cpu/ppc4xx/uart.c | 22 +- 128 files changed, 2086 insertions(+), 2397 deletions(-) diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c index 8d79be2cedc..0db619952eb 100644 --- a/board/amcc/acadia/acadia.c +++ b/board/amcc/acadia/acadia.c @@ -57,7 +57,7 @@ int board_early_init_f(void) #if !defined(CONFIG_NAND_U_BOOT) /* don't reinit PLL when booting via I2C bootstrap option */ - mfsdr(SDR_PINSTP, reg); + mfsdr(SDR0_PINSTP, reg); if (reg != 0xf0000000) board_pll_init_f(); #endif @@ -65,18 +65,18 @@ int board_early_init_f(void) acadia_gpio_init(); /* Configure 405EZ for NAND usage */ - mtsdr(sdrnand0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN); - mfsdr(sdrultra0, reg); + mtsdr(SDR0_NAND0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN); + mfsdr(SDR0_ULTRA0, reg); reg &= ~SDR_ULTRA0_CSN_MASK; reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) | SDR_ULTRA0_NDGPIOBP | SDR_ULTRA0_EBCRDYEN | SDR_ULTRA0_NFSRSTEN; - mtsdr(sdrultra0, reg); + mtsdr(SDR0_ULTRA0, reg); /* USB Host core needs this bit set */ - mfsdr(sdrultra1, reg); - mtsdr(sdrultra1, reg | SDR_ULTRA1_LEDNENABLE); + mfsdr(SDR0_ULTRA1, reg); + mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE); mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr(uicer, 0x00000000); /* disable all ints */ diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index 3e5c80ea429..8c2addcb945 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -65,7 +65,7 @@ phys_size_t initdram(int board_type) u32 reg; /* don't reinit PLL when booting via I2C bootstrap option */ - mfsdr(SDR_PINSTP, reg); + mfsdr(SDR0_PINSTP, reg); if (reg != 0xf0000000) board_pll_init_f(); #endif @@ -81,25 +81,25 @@ phys_size_t initdram(int board_type) gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG); /* 2. EBC in Async mode */ - mtebc(pb1ap, 0x078F1EC0); - mtebc(pb2ap, 0x078F1EC0); - mtebc(pb1cr, 0x000BC000); - mtebc(pb2cr, 0x020BC000); + mtebc(PB1AP, 0x078F1EC0); + mtebc(PB2AP, 0x078F1EC0); + mtebc(PB1CR, 0x000BC000); + mtebc(PB2CR, 0x020BC000); /* 3. Set CRAM in Sync mode */ cram_bcr_write(0x7012); /* CRAM burst setting */ /* 4. EBC in Sync mode */ - mtebc(pb1ap, 0x9C0201C0); - mtebc(pb2ap, 0x9C0201C0); + mtebc(PB1AP, 0x9C0201C0); + mtebc(PB2AP, 0x9C0201C0); /* Set GPIO pins back to alternate function */ gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); /* Config EBC to use RDY */ - mfsdr(sdrultra0, val); - mtsdr(sdrultra0, val | SDR_ULTRA0_EBCRDYEN); + mfsdr(SDR0_ULTRA0, val); + mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN); /* Wait a short while, since for NAND booting this is too fast */ for (i=0; i<200000; i++) diff --git a/board/amcc/acadia/pll.c b/board/amcc/acadia/pll.c index 9dcce35c89b..b63813c7be4 100644 --- a/board/amcc/acadia/pll.c +++ b/board/amcc/acadia/pll.c @@ -51,11 +51,11 @@ void board_pll_init_f(void) */ /* Initialize PLL */ - mtcpr(cprpllc, 0x0000033c); - mtcpr(cprplld, 0x0c010200); - mtcpr(cprprimad, 0x04060c0c); - mtcpr(cprperd0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */ - mtcpr(cprclkupd, 0x40000000); + mtcpr(CPR0_PLLC, 0x0000033c); + mtcpr(CPR0_PLLD, 0x0c010200); + mtcpr(CPC0_PRIMAD, 0x04060c0c); + mtcpr(CPC0_PERD0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */ + mtcpr(CPR0_CLKUP, 0x40000000); } #elif defined(PLLMR0_266_160_80) @@ -83,13 +83,13 @@ void board_pll_init_f(void) */ /* Initialize PLL */ - mtcpr(cprpllc, 0x20000238); - mtcpr(cprplld, 0x03010400); - mtcpr(cprprimad, 0x03050a0a); - mtcpr(cprperc0, 0x00000000); - mtcpr(cprperd0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */ - mtcpr(cprperd1, 0x07323200); - mtcpr(cprclkupd, 0x40000000); + mtcpr(CPR0_PLLC, 0x20000238); + mtcpr(CPR0_PLLD, 0x03010400); + mtcpr(CPC0_PRIMAD, 0x03050a0a); + mtcpr(CPC0_PERC0, 0x00000000); + mtcpr(CPC0_PERD0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */ + mtcpr(CPC0_PERD1, 0x07323200); + mtcpr(CPR0_CLKUP, 0x40000000); } #elif defined(PLLMR0_333_166_83) @@ -117,12 +117,12 @@ void board_pll_init_f(void) */ /* Initialize PLL */ - mtcpr(cprpllc, 0x0000033C); - mtcpr(cprplld, 0x0a010000); - mtcpr(cprprimad, 0x02040808); - mtcpr(cprperd0, 0x02080505); /* SPI clk div. eq. OPB clk div. */ - mtcpr(cprperd1, 0xA6A60300); - mtcpr(cprclkupd, 0x40000000); + mtcpr(CPR0_PLLC, 0x0000033C); + mtcpr(CPR0_PLLD, 0x0a010000); + mtcpr(CPC0_PRIMAD, 0x02040808); + mtcpr(CPC0_PERD0, 0x02080505); /* SPI clk div. eq. OPB clk div. */ + mtcpr(CPC0_PERD1, 0xA6A60300); + mtcpr(CPR0_CLKUP, 0x40000000); } #elif defined(PLLMR0_100_100_12) @@ -143,12 +143,12 @@ void board_pll_init_f(void) */ /* Initialize PLL */ - mtcpr(cprpllc, 0x000003BC); - mtcpr(cprplld, 0x06060600); - mtcpr(cprprimad, 0x02020004); - mtcpr(cprperd0, 0x04002828); /* SPI clk div. eq. OPB clk div. */ - mtcpr(cprperd1, 0xC8C81600); - mtcpr(cprclkupd, 0x40000000); + mtcpr(CPR0_PLLC, 0x000003BC); + mtcpr(CPR0_PLLD, 0x06060600); + mtcpr(CPC0_PRIMAD, 0x02020004); + mtcpr(CPC0_PERD0, 0x04002828); /* SPI clk div. eq. OPB clk div. */ + mtcpr(CPC0_PERD1, 0xC8C81600); + mtcpr(CPR0_CLKUP, 0x40000000); } #endif /* CPU__405EZ */ @@ -167,12 +167,12 @@ unsigned long get_tbclk(void) /* * Read PLL Mode registers */ - mfcpr(cprplld, cpr_plld); + mfcpr(CPR0_PLLD, cpr_plld); /* * Read CPR_PRIMAD register */ - mfcpr(cprprimad, cpr_primad); + mfcpr(CPC0_PRIMAD, cpr_primad); /* * Determine CPU clock frequency diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index febc61a0869..2ffd720d5c4 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -487,35 +487,35 @@ int pci_pre_init(struct pci_controller *hose) | Set priority for all PLB3 devices to 0. | Set PLB3 arbiter to fair mode. +-------------------------------------------------------------------------*/ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /*-------------------------------------------------------------------------+ | Set priority for all PLB4 devices to 0. +-------------------------------------------------------------------------*/ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4_ACR, addr); /*-------------------------------------------------------------------------+ | Set Nebula PLB4 arbiter to fair mode. +-------------------------------------------------------------------------*/ /* Segment0 */ - addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; - addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; - addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; - addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; - mtdcr(plb0_acr, addr); + addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; + addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; + addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; + addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; + mtdcr(PLB0_ACR, addr); /* Segment1 */ - addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; - addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; - addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; - addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; - mtdcr(plb1_acr, addr); + addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; + addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; + addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; + addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; + mtdcr(PLB1_ACR, addr); return 1; } @@ -695,8 +695,8 @@ void ext_bus_cntlr_init(void) | +-------------------------------------------------------------------------*/ /* NVRAM - FPGA */ - mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA); - mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5); + mtebc(PB5AP, EBC0_BNAP_NVRAM_FPGA); + mtebc(PB5CR, EBC0_BNCR_NVRAM_FPGA_CS5); /*-------------------------------------------------------------------------+ | @@ -749,7 +749,7 @@ void ext_bus_cntlr_init(void) case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN: /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */ /* Read Serial Device Strap Register1 in PPC440EP */ - mfsdr(sdr_sdstp1, sdr0_sdstp1); + mfsdr(SDR0_SDSTP1, sdr0_sdstp1); boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK; ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK; @@ -822,7 +822,7 @@ void ext_bus_cntlr_init(void) /* Default Strap Settings 5-7 */ /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */ /* Read Serial Device Strap Register1 in PPC440EP */ - mfsdr(sdr_sdstp1, sdr0_sdstp1); + mfsdr(SDR0_SDSTP1, sdr0_sdstp1); boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK; ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK; @@ -1013,8 +1013,8 @@ void ext_bus_cntlr_init(void) /*-------------------------------------------------------------------------+ | Initialize EBC CONFIG +-------------------------------------------------------------------------*/ - mtdcr(ebccfga, xbcfg); - mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN | + mtdcr(EBC0_CFGADDR, EBC0_CFG); + mtdcr(EBC0_CFGDATA, EBC0_CFG_EBTC_DRIVEN | EBC0_CFG_PTD_ENABLED | EBC0_CFG_RTC_2048PERCLK | EBC0_CFG_EMPL_LOW | @@ -1029,20 +1029,20 @@ void ext_bus_cntlr_init(void) | Initialize EBC Bank 0-4 +-------------------------------------------------------------------------*/ /* EBC Bank0 */ - mtebc(pb0ap, ebc0_cs0_bnap_value); - mtebc(pb0cr, ebc0_cs0_bncr_value); + mtebc(PB0AP, ebc0_cs0_bnap_value); + mtebc(PB0CR, ebc0_cs0_bncr_value); /* EBC Bank1 */ - mtebc(pb1ap, ebc0_cs1_bnap_value); - mtebc(pb1cr, ebc0_cs1_bncr_value); + mtebc(PB1AP, ebc0_cs1_bnap_value); + mtebc(PB1CR, ebc0_cs1_bncr_value); /* EBC Bank2 */ - mtebc(pb2ap, ebc0_cs2_bnap_value); - mtebc(pb2cr, ebc0_cs2_bncr_value); + mtebc(PB2AP, ebc0_cs2_bnap_value); + mtebc(PB2CR, ebc0_cs2_bncr_value); /* EBC Bank3 */ - mtebc(pb3ap, ebc0_cs3_bnap_value); - mtebc(pb3cr, ebc0_cs3_bncr_value); + mtebc(PB3AP, ebc0_cs3_bnap_value); + mtebc(PB3CR, ebc0_cs3_bncr_value); /* EBC Bank4 */ - mtebc(pb4ap, ebc0_cs4_bnap_value); - mtebc(pb4cr, ebc0_cs4_bncr_value); + mtebc(PB4AP, ebc0_cs4_bnap_value); + mtebc(PB4CR, ebc0_cs4_bncr_value); return; } @@ -1939,10 +1939,10 @@ void configure_ppc440ep_pins(void) sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL; sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE; - mfsdr(sdr_usb0, sdr0_usb0); + mfsdr(SDR0_USB0, sdr0_usb0); sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK; sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL; - mtsdr(sdr_usb0, sdr0_usb0); + mtsdr(SDR0_USB0, sdr0_usb0); usb2_device_selection_in_fpga(); } @@ -1950,19 +1950,19 @@ void configure_ppc440ep_pins(void) /* USB1.1 Device Selection */ if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED) { - mfsdr(sdr_usb0, sdr0_usb0); + mfsdr(SDR0_USB0, sdr0_usb0); sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK; sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL; - mtsdr(sdr_usb0, sdr0_usb0); + mtsdr(SDR0_USB0, sdr0_usb0); } /* USB1.1 Host Selection */ if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED) { - mfsdr(sdr_usb0, sdr0_usb0); + mfsdr(SDR0_USB0, sdr0_usb0); sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK; sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE; - mtsdr(sdr_usb0, sdr0_usb0); + mtsdr(SDR0_USB0, sdr0_usb0); } /* NAND Flash Selection */ @@ -1971,14 +1971,14 @@ void configure_ppc440ep_pins(void) update_ndfc_ios(gpio_tab); #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) - mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL | + mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL | SDR0_CUST0_NDFC_ENABLE | SDR0_CUST0_NDFC_BW_8_BIT | SDR0_CUST0_NDFC_ARE_MASK | SDR0_CUST0_CHIPSELGAT_EN1 | SDR0_CUST0_CHIPSELGAT_EN2); #else - mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL | + mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL | SDR0_CUST0_NDFC_ENABLE | SDR0_CUST0_NDFC_BW_8_BIT | SDR0_CUST0_NDFC_ARE_MASK | @@ -1991,16 +1991,16 @@ void configure_ppc440ep_pins(void) else { /* Set Mux on EMAC */ - mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL); + mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_EMAC_SEL); } /* MII Selection */ if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED) { update_zii_ios(gpio_tab); - mfsdr(sdr_mfr, sdr0_mfr); + mfsdr(SDR0_MFR, sdr0_mfr); sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII; - mtsdr(sdr_mfr, sdr0_mfr); + mtsdr(SDR0_MFR, sdr0_mfr); set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII); } @@ -2009,9 +2009,9 @@ void configure_ppc440ep_pins(void) if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED) { update_zii_ios(gpio_tab); - mfsdr(sdr_mfr, sdr0_mfr); + mfsdr(SDR0_MFR, sdr0_mfr); sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; - mtsdr(sdr_mfr, sdr0_mfr); + mtsdr(SDR0_MFR, sdr0_mfr); set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII); } @@ -2020,9 +2020,9 @@ void configure_ppc440ep_pins(void) if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED) { update_zii_ios(gpio_tab); - mfsdr(sdr_mfr, sdr0_mfr); + mfsdr(SDR0_MFR, sdr0_mfr); sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII; - mtsdr(sdr_mfr, sdr0_mfr); + mtsdr(SDR0_MFR, sdr0_mfr); set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII); } @@ -2071,13 +2071,13 @@ void configure_ppc440ep_pins(void) /* Packet Reject Function Enable */ if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED) { - mfsdr(sdr_mfr, sdr0_mfr); + mfsdr(SDR0_MFR, sdr0_mfr); sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;; - mtsdr(sdr_mfr, sdr0_mfr); + mtsdr(SDR0_MFR, sdr0_mfr); } /* Perform effective access to hardware */ - mtsdr(sdr_pfc1, sdr0_pfc1); + mtsdr(SDR0_PFC1, sdr0_pfc1); set_chip_gpio_configuration(GPIO0, gpio_tab); set_chip_gpio_configuration(GPIO1, gpio_tab); diff --git a/board/amcc/bamboo/flash.c b/board/amcc/bamboo/flash.c index 001348ac5c9..7bf877de895 100644 --- a/board/amcc/bamboo/flash.c +++ b/board/amcc/bamboo/flash.c @@ -94,7 +94,7 @@ unsigned long flash_init(void) * Boot Settings in IIC EEprom address 0xA8 or 0xA4 * Read Serial Device Strap Register1 in PPC440EP */ - mfsdr(sdr_sdstp1, val); + mfsdr(SDR0_SDSTP1, val); boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK; ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK; diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c index 74a2a1c2144..d0aebec2cd4 100644 --- a/board/amcc/bubinga/bubinga.c +++ b/board/amcc/bubinga/bubinga.c @@ -41,9 +41,9 @@ int board_early_init_f(void) * and enable the internal PCI arbiter if selected */ if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB) - mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); + mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); else - mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN); + mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN); return 0; } diff --git a/board/amcc/bubinga/flash.c b/board/amcc/bubinga/flash.c index a10babbf739..baf89d5483f 100644 --- a/board/amcc/bubinga/flash.c +++ b/board/amcc/bubinga/flash.c @@ -106,25 +106,25 @@ unsigned long flash_init(void) /* Re-do sizing to get full correct info */ if (size_b1) { - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b1 = -size_b1; pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1 / 1024 / 1024) - 1) << 17); - mtdcr(ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr(EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ } if (size_b0) { - mtdcr(ebccfga, pb1cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb1cr); + mtdcr(EBC0_CFGADDR, PB1CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB1CR); base_b0 = base_b1 - size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0 / 1024 / 1024) - 1) << 17); - mtdcr(ebccfgd, pbcr); - /* printf("pb0cr = %x\n", pbcr); */ + mtdcr(EBC0_CFGDATA, pbcr); + /* printf("PB0CR = %x\n", pbcr); */ } size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]); diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 710a0af8252..3a03f307310 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -475,9 +475,9 @@ int board_early_init_r (void) /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */ #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtebc(pb3cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); + mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); #else - mtebc(pb0cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); + mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); #endif /* Remove TLB entry of boot EBC mapping */ diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c index ad09e62077c..2439b03a9f7 100644 --- a/board/amcc/ebony/ebony.c +++ b/board/amcc/ebony/ebony.c @@ -41,30 +41,30 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup the external bus controller/chip selects *-------------------------------------------------------------------*/ - mtdcr(ebccfga, xbcfg); - reg = mfdcr(ebccfgd); - mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ + mtdcr(EBC0_CFGADDR, EBC0_CFG); + reg = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */ - mtebc(pb1ap, 0x02815480); /* NVRAM/RTC */ - mtebc(pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */ - mtebc(pb7ap, 0x01015280); /* FPGA registers */ - mtebc(pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */ + mtebc(PB1AP, 0x02815480); /* NVRAM/RTC */ + mtebc(PB1CR, 0x48018000); /* BA=0x480 1MB R/W 8-bit */ + mtebc(PB7AP, 0x01015280); /* FPGA registers */ + mtebc(PB7CR, 0x48318000); /* BA=0x483 1MB R/W 8-bit */ /* read FPGA_REG0 and set the bus controller */ status = *fpga_base; if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) { - mtebc(pb0ap, 0x9b015480); /* FLASH/SRAM */ - mtebc(pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */ - mtebc(pb2ap, 0x9b015480); /* 4MB FLASH */ - mtebc(pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */ + mtebc(PB0AP, 0x9b015480); /* FLASH/SRAM */ + mtebc(PB0CR, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */ + mtebc(PB2AP, 0x9b015480); /* 4MB FLASH */ + mtebc(PB2CR, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */ } else { - mtebc(pb0ap, 0x9b015480); /* 4MB FLASH */ - mtebc(pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */ + mtebc(PB0AP, 0x9b015480); /* 4MB FLASH */ + mtebc(PB0CR, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */ /* set CS2 if FLASH_ONBD_N == 0 */ if (!(status & FLASH_ONBD_N)) { - mtebc(pb2ap, 0x9b015480); /* FLASH/SRAM */ - mtebc(pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */ + mtebc(PB2AP, 0x9b015480); /* FLASH/SRAM */ + mtebc(PB2CR, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */ } } @@ -186,7 +186,7 @@ int pci_pre_init(struct pci_controller *hose) * The ebony board is always configured as the host & requires the * PCI arbiter to be enabled. *--------------------------------------------------------------------------*/ - strap = mfdcr(cpc0_strp1); + strap = mfdcr(CPC0_STRP1); if ((strap & 0x00100000) == 0) { printf("PCI: CPC0_STRP1[PAE] not set.\n"); return 0; diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index e078ba4f9cf..1a45056daa0 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -220,9 +220,9 @@ int board_early_init_f (void) mtdcr (uic0sr, 0x00000000); /* clear all interrupts*/ mtdcr (uic0sr, 0xffffffff); /* clear all interrupts*/ - mfsdr(sdr_mfr, mfr); + mfsdr(SDR0_MFR, mfr); mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ - mtsdr(sdr_mfr, mfr); + mtsdr(SDR0_MFR, mfr); mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0); @@ -280,7 +280,7 @@ int pci_pre_init(struct pci_controller * hose ) * The katmai board is always configured as the host & requires the * PCI arbiter to be enabled. *-------------------------------------------------------------------*/ - mfsdr(sdr_sdstp1, strap); + mfsdr(SDR0_SDSTP1, strap); if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) { printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); return 0; diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 7d02d904e09..71ad89fa6c3 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -42,12 +42,12 @@ int board_early_init_f(void) { u32 mfr; - mtebc( pb0ap, 0x03800000 ); /* set chip selects */ - mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */ - mtebc( pb1ap, 0x03800000 ); - mtebc( pb1cr, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */ - mtebc( pb2ap, 0x03800000 ); - mtebc( pb2cr, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */ + mtebc( PB0AP, 0x03800000 ); /* set chip selects */ + mtebc( PB0CR, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */ + mtebc( PB1AP, 0x03800000 ); + mtebc( PB1CR, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */ + mtebc( PB2AP, 0x03800000 ); + mtebc( PB2CR, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */ mtdcr( uic1sr, 0xffffffff ); /* Clear all interrupts */ mtdcr( uic1er, 0x00000000 ); /* disable all interrupts */ @@ -67,9 +67,9 @@ int board_early_init_f(void) mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */ mtdcr( uic0sr, 0xffffffff ); - mfsdr(sdr_mfr, mfr); + mfsdr(SDR0_MFR, mfr); mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ - mtsdr(sdr_mfr, mfr); + mtsdr(SDR0_MFR, mfr); return 0; } @@ -147,7 +147,7 @@ int pci_pre_init( struct pci_controller *hose ) * The luan board is always configured as the host & requires the * PCI arbiter to be enabled. *--------------------------------------------------------------------------*/ - mfsdr(sdr_sdstp1, strap); + mfsdr(SDR0_SDSTP1, strap); if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) { printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index fe4540849da..5e32e8a7844 100644 --- a/board/amcc/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -54,7 +54,7 @@ int board_early_init_f (void) /*-------------------------------------------------------------------------+ | Initialize EBC CONFIG +-------------------------------------------------------------------------*/ - mtebc(xbcfg, EBC_CFG_LE_UNLOCK | + mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | @@ -63,14 +63,14 @@ int board_early_init_f (void) /*-------------------------------------------------------------------------+ | FPGA. Initialize bank 7 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| + mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| EBC_BXAP_BCE_DISABLE| EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| EBC_BXAP_BEM_WRITEONLY| EBC_BXAP_PEN_DISABLED); - mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)| + mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)| EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /* read FPGA base register FPGA_REG0 */ @@ -95,53 +95,53 @@ int board_early_init_f (void) /*-------------------------------------------------------------------------+ | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)| + mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)| EBC_BXAP_BCE_DISABLE| EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| EBC_BXAP_BEM_WRITEONLY| EBC_BXAP_PEN_DISABLED); - mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)| + mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(cs0_base)| cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------------+ | 8KB NVRAM/RTC. Initialize bank 1 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)| + mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)| EBC_BXAP_BCE_DISABLE| EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| EBC_BXAP_BEM_WRITEONLY| EBC_BXAP_PEN_DISABLED); - mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000)| + mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000)| EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------------+ | 4 MB FLASH. Initialize bank 2 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)| + mtebc(PB2AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)| EBC_BXAP_BCE_DISABLE| EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| EBC_BXAP_BEM_WRITEONLY| EBC_BXAP_PEN_DISABLED); - mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)| + mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(cs2_base)| cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------------+ | FPGA. Initialize bank 7 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| + mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| EBC_BXAP_BCE_DISABLE| EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| EBC_BXAP_BEM_WRITEONLY| EBC_BXAP_PEN_DISABLED); - mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)| + mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)| EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------- @@ -189,9 +189,9 @@ int board_early_init_f (void) mtdcr (uic0pr, 0xfc000000); /* */ mtdcr (uic0tr, 0x00000000); /* */ mtdcr (uic0vr, 0x00000001); /* */ - mfsdr (sdr_mfr, mfr); + mfsdr (SDR0_MFR, mfr); mfr &= ~SDR0_MFR_ECS_MASK; -/* mtsdr(sdr_mfr, mfr); */ +/* mtsdr(SDR0_MFR, mfr); */ fpga_init(); return 0; @@ -297,7 +297,7 @@ int pci_pre_init(struct pci_controller * hose ) * The ocotea board is always configured as the host & requires the * PCI arbiter to be enabled. *--------------------------------------------------------------------------*/ - mfsdr(sdr_sdstp1, strap); + mfsdr(SDR0_SDSTP1, strap); if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); return 0; @@ -379,8 +379,8 @@ void fpga_init(void) unsigned long sdr0_cust0; unsigned long pvr; - mfsdr (sdr_pfc0, sdr0_pfc0); - mfsdr (sdr_pfc1, sdr0_pfc1); + mfsdr (SDR0_PFC0, sdr0_pfc0); + mfsdr (SDR0_PFC1, sdr0_pfc1); group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1); pvr = get_pvr (); @@ -390,8 +390,8 @@ void fpga_init(void) sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS; out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | FPGA_REG2_EXT_INTFACE_ENABLE); - mtsdr (sdr_pfc0, sdr0_pfc0); - mtsdr (sdr_pfc1, sdr0_pfc1); + mtsdr (SDR0_PFC0, sdr0_pfc0); + mtsdr (SDR0_PFC1, sdr0_pfc1); } else { sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE; switch (group) @@ -403,8 +403,8 @@ void fpga_init(void) out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | FPGA_REG2_EXT_INTFACE_ENABLE); sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS; - mtsdr (sdr_pfc0, sdr0_pfc0); - mtsdr (sdr_pfc1, sdr0_pfc1); + mtsdr (SDR0_PFC0, sdr0_pfc0); + mtsdr (SDR0_PFC1, sdr0_pfc1); break; case 3: case 4: @@ -412,8 +412,8 @@ void fpga_init(void) case 6: /* CPU trace B - Over EBMI */ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE; - mtsdr (sdr_pfc0, sdr0_pfc0); - mtsdr (sdr_pfc1, sdr0_pfc1); + mtsdr (SDR0_PFC0, sdr0_pfc0); + mtsdr (SDR0_PFC1, sdr0_pfc1); out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | FPGA_REG2_EXT_INTFACE_DISABLE); break; @@ -421,8 +421,8 @@ void fpga_init(void) } /* Initialize the ethernet specific functions in the fpga */ - mfsdr(sdr_pfc1, sdr0_pfc1); - mfsdr(sdr_cust0, sdr0_cust0); + mfsdr(SDR0_PFC1, sdr0_pfc1); + mfsdr(SDR0_CUST0, sdr0_cust0); if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) && ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) || (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI))) diff --git a/board/amcc/redwood/redwood.c b/board/amcc/redwood/redwood.c index 37a0c310fed..49078ebee2f 100644 --- a/board/amcc/redwood/redwood.c +++ b/board/amcc/redwood/redwood.c @@ -220,7 +220,7 @@ static void early_init_EBC(void) * default value : * 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 */ - mtebc(xbcfg, EBC_CFG_LE_UNLOCK | + mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_16PERCLK | EBC_CFG_ATC_PREVIOUS | @@ -237,8 +237,8 @@ static void early_init_EBC(void) * since some board registers values may be needed to determine the * boot type */ - mtebc(pb1ap, EBC_BXAP_FPGA); - mtebc(pb1cr, EBC_BXCR_FPGA_CS3); + mtebc(PB1AP, EBC_BXAP_FPGA); + mtebc(PB1CR, EBC_BXCR_FPGA_CS3); } @@ -399,12 +399,12 @@ static void early_reinit_EBC(int computed_boot_device) break; } - mtebc(pb0ap, ebc0_cs0_bxap_value); - mtebc(pb0cr, ebc0_cs0_bxcr_value); - mtebc(pb1ap, ebc0_cs1_bxap_value); - mtebc(pb1cr, ebc0_cs1_bxcr_value); - mtebc(pb2ap, ebc0_cs2_bxap_value); - mtebc(pb2cr, ebc0_cs2_bxcr_value); + mtebc(PB0AP, ebc0_cs0_bxap_value); + mtebc(PB0CR, ebc0_cs0_bxcr_value); + mtebc(PB1AP, ebc0_cs1_bxap_value); + mtebc(PB1CR, ebc0_cs1_bxcr_value); + mtebc(PB2AP, ebc0_cs2_bxap_value); + mtebc(PB2CR, ebc0_cs2_bxcr_value); } static void early_init_UIC(void) diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 246ad948439..5913455ba15 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -46,8 +46,8 @@ int board_early_init_f(void) u32 sdr0_pfc1, sdr0_pfc2; u32 reg; - mtdcr(ebccfga, xbcfg); - mtdcr(ebccfgd, 0xb8400000); + mtdcr(EBC0_CFGADDR, EBC0_CFG); + mtdcr(EBC0_CFGDATA, 0xb8400000); /* * Setup the interrupt controller polarities, triggers, etc. @@ -107,8 +107,8 @@ int board_early_init_f(void) mtsdr(SDR0_PFC1, sdr0_pfc1); /* PCI arbiter enabled */ - mfsdr(sdr_pci0, reg); - mtsdr(sdr_pci0, 0x80000000 | reg); + mfsdr(SDR0_PCI0, reg); + mtsdr(SDR0_PCI0, 0x80000000 | reg); /* setup NAND FLASH */ mfsdr(SDR0_CUST0, sdr0_cust0); @@ -144,19 +144,19 @@ int misc_init_r(void) gd->bd->bi_flashoffset = 0; #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtdcr(ebccfga, pb3cr); + mtdcr(EBC0_CFGADDR, PB3CR); #else - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); #endif - pbcr = mfdcr(ebccfgd); + pbcr = mfdcr(EBC0_CFGDATA); size_val = ffs(gd->bd->bi_flashsize) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtdcr(ebccfga, pb3cr); + mtdcr(EBC0_CFGADDR, PB3CR); #else - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); #endif - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* * Re-check to get correct base address @@ -309,8 +309,8 @@ int misc_init_r(void) * This fix will make the MAL burst disabling patch for the Linux * EMAC driver obsolete. */ - reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; - mtdcr(plb4_acr, reg); + reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP; + mtdcr(PLB4_ACR, reg); return 0; } @@ -370,35 +370,35 @@ int pci_pre_init(struct pci_controller *hose) * Set priority for all PLB3 devices to 0. * Set PLB3 arbiter to fair mode. */ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /* * Set priority for all PLB4 devices to 0. */ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4_ACR, addr); /* * Set Nebula PLB4 arbiter to fair mode. */ /* Segment0 */ - addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; - addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; - addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; - addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; - mtdcr(plb0_acr, addr); + addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; + addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; + addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; + addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; + mtdcr(PLB0_ACR, addr); /* Segment1 */ - addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; - addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; - addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; - addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; - mtdcr(plb1_acr, addr); + addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; + addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; + addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; + addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; + mtdcr(PLB1_ACR, addr); #ifdef CONFIG_PCI_PNP hose->fixup_irq = sequoia_pci_fixup_irq; diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c index d8806ac32dd..4e5796ee828 100644 --- a/board/amcc/taihu/taihu.c +++ b/board/amcc/taihu/taihu.c @@ -48,14 +48,14 @@ int board_early_init_f(void) mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtebc(pb3ap, CONFIG_SYS_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */ - mtebc(pb3cr, CONFIG_SYS_EBC_PB3CR); + mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */ + mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR); /* * Configure CPC0_PCI to enable PerWE as output * and enable the internal PCI arbiter */ - mtdcr(cpc0_pci, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); + mtdcr(CPC0_PCI, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); return 0; } diff --git a/board/amcc/taishan/showinfo.c b/board/amcc/taishan/showinfo.c index 2a78a22e65e..e4e441b319d 100644 --- a/board/amcc/taishan/showinfo.c +++ b/board/amcc/taishan/showinfo.c @@ -33,60 +33,60 @@ void show_reset_reg(void) /* read clock regsiter */ printf("===== Display reset and initialize register Start =========\n"); - mfcpr(clk_pllc,reg); + mfcpr(CPR0_PLLC,reg); printf("cpr_pllc = %#010lx\n",reg); - mfcpr(clk_plld,reg); + mfcpr(CPR0_PLLD,reg); printf("cpr_plld = %#010lx\n",reg); - mfcpr(clk_primad,reg); + mfcpr(CPR0_PRIMAD,reg); printf("cpr_primad = %#010lx\n",reg); - mfcpr(clk_primbd,reg); + mfcpr(CPR0_PRIMBD,reg); printf("cpr_primbd = %#010lx\n",reg); - mfcpr(clk_opbd,reg); + mfcpr(CPR0_OPBD,reg); printf("cpr_opbd = %#010lx\n",reg); - mfcpr(clk_perd,reg); + mfcpr(CPR0_PERD,reg); printf("cpr_perd = %#010lx\n",reg); - mfcpr(clk_mald,reg); + mfcpr(CPR0_MALD,reg); printf("cpr_mald = %#010lx\n",reg); /* read sdr register */ - mfsdr(sdr_ebc,reg); - printf("sdr_ebc = %#010lx\n",reg); + mfsdr(SDR0_EBC,reg); + printf("SDR0_EBC = %#010lx\n",reg); - mfsdr(sdr_cp440,reg); - printf("sdr_cp440 = %#010lx\n",reg); + mfsdr(SDR0_CP440,reg); + printf("SDR0_CP440 = %#010lx\n",reg); - mfsdr(sdr_xcr,reg); - printf("sdr_xcr = %#010lx\n",reg); + mfsdr(SDR0_XCR,reg); + printf("SDR0_XCR = %#010lx\n",reg); - mfsdr(sdr_xpllc,reg); - printf("sdr_xpllc = %#010lx\n",reg); + mfsdr(SDR0_XPLLC,reg); + printf("SDR0_XPLLC = %#010lx\n",reg); - mfsdr(sdr_xplld,reg); - printf("sdr_xplld = %#010lx\n",reg); + mfsdr(SDR0_XPLLD,reg); + printf("SDR0_XPLLD = %#010lx\n",reg); - mfsdr(sdr_pfc0,reg); - printf("sdr_pfc0 = %#010lx\n",reg); + mfsdr(SDR0_PFC0,reg); + printf("SDR0_PFC0 = %#010lx\n",reg); - mfsdr(sdr_pfc1,reg); - printf("sdr_pfc1 = %#010lx\n",reg); + mfsdr(SDR0_PFC1,reg); + printf("SDR0_PFC1 = %#010lx\n",reg); - mfsdr(sdr_cust0,reg); - printf("sdr_cust0 = %#010lx\n",reg); + mfsdr(SDR0_CUST0,reg); + printf("SDR0_CUST0 = %#010lx\n",reg); - mfsdr(sdr_cust1,reg); - printf("sdr_cust1 = %#010lx\n",reg); + mfsdr(SDR0_CUST1,reg); + printf("SDR0_CUST1 = %#010lx\n",reg); - mfsdr(sdr_uart0,reg); - printf("sdr_uart0 = %#010lx\n",reg); + mfsdr(SDR0_UART0,reg); + printf("SDR0_UART0 = %#010lx\n",reg); - mfsdr(sdr_uart1,reg); - printf("sdr_uart1 = %#010lx\n",reg); + mfsdr(SDR0_UART1,reg); + printf("SDR0_UART1 = %#010lx\n",reg); printf("===== Display reset and initialize register End =========\n"); } @@ -96,14 +96,14 @@ void show_xbridge_info(void) unsigned long reg; printf("PCI-X chip control registers\n"); - mfsdr(sdr_xcr, reg); - printf("sdr_xcr = %#010lx\n", reg); + mfsdr(SDR0_XCR, reg); + printf("SDR0_XCR = %#010lx\n", reg); - mfsdr(sdr_xpllc, reg); - printf("sdr_xpllc = %#010lx\n", reg); + mfsdr(SDR0_XPLLC, reg); + printf("SDR0_XPLLC = %#010lx\n", reg); - mfsdr(sdr_xplld, reg); - printf("sdr_xplld = %#010lx\n", reg); + mfsdr(SDR0_XPLLD, reg); + printf("SDR0_XPLLD = %#010lx\n", reg); printf("PCI-X Bridge Configure registers\n"); printf("PCIX0_VENDID = %#06x\n", in16r(PCIX0_VENDID)); diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c index 53ce88c6cdf..086778a6523 100644 --- a/board/amcc/taishan/taishan.c +++ b/board/amcc/taishan/taishan.c @@ -47,7 +47,7 @@ int board_early_init_f (void) /*-------------------------------------------------------------------------+ | Initialize EBC CONFIG +-------------------------------------------------------------------------*/ - mtebc(xbcfg, EBC_CFG_LE_UNLOCK | + mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_DEFAULT | @@ -56,66 +56,66 @@ int board_early_init_f (void) /*-------------------------------------------------------------------------+ | 64MB FLASH. Initialize bank 0 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) | + mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) | EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | + mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT); /*-------------------------------------------------------------------------+ | FPGA. Initialize bank 1 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) | + mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) | EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x41000000) | + mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x41000000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------------+ | LCM. Initialize bank 2 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb2ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) | + mtebc(PB2AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) | EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) | EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0x42000000) | + mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0x42000000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------------+ | TMP. Initialize bank 3 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb3ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) | + mtebc(PB3AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) | EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) | EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48000000) | + mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48000000) | EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); /*-------------------------------------------------------------------------+ | Connector 4~7. Initialize bank 3~ 7 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb4ap,0); - mtebc(pb4cr,0); - mtebc(pb5ap,0); - mtebc(pb5cr,0); - mtebc(pb6ap,0); - mtebc(pb6cr,0); - mtebc(pb7ap,0); - mtebc(pb7cr,0); + mtebc(PB4AP,0); + mtebc(PB4CR,0); + mtebc(PB5AP,0); + mtebc(PB5CR,0); + mtebc(PB6AP,0); + mtebc(PB6CR,0); + mtebc(PB7AP,0); + mtebc(PB7CR,0); /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. @@ -164,13 +164,13 @@ int board_early_init_f (void) mtdcr (uic0vr, 0x00000001); /* */ /* Enable two GPIO 10~11 and TraceA signal */ - mfsdr(sdr_pfc0,reg); + mfsdr(SDR0_PFC0,reg); reg |= 0x00300000; - mtsdr(sdr_pfc0,reg); + mtsdr(SDR0_PFC0,reg); - mfsdr(sdr_pfc1,reg); + mfsdr(SDR0_PFC1,reg); reg |= 0x00100000; - mtsdr(sdr_pfc1,reg); + mtsdr(SDR0_PFC1,reg); /* Set GPIO 10 and 11 as output */ GpioOdr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x718); @@ -230,7 +230,7 @@ int pci_pre_init(struct pci_controller * hose ) * The ocotea board is always configured as the host & requires the * PCI arbiter to be enabled. *--------------------------------------------------------------------------*/ - mfsdr(sdr_sdstp1, strap); + mfsdr(SDR0_SDSTP1, strap); if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); return 0; diff --git a/board/amcc/walnut/flash.c b/board/amcc/walnut/flash.c index d363564d550..3dc6aabe17b 100644 --- a/board/amcc/walnut/flash.c +++ b/board/amcc/walnut/flash.c @@ -102,27 +102,27 @@ unsigned long flash_init(void) /* Re-do sizing to get full correct info */ if (size_b1) { - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b1 = -size_b1; pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1 / 1024 / 1024) - 1) << 17); - mtdcr(ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr(EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ } if (size_b0) { - mtdcr(ebccfga, pb1cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb1cr); + mtdcr(EBC0_CFGADDR, PB1CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB1CR); base_b0 = base_b1 - size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0 / 1024 / 1024) - 1) << 17); - mtdcr(ebccfgd, pbcr); - /* printf("pb0cr = %x\n", pbcr); */ + mtdcr(EBC0_CFGDATA, pbcr); + /* printf("PB0CR = %x\n", pbcr); */ } size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]); diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 3982896cb32..2a654fa895b 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -40,9 +40,9 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup the external bus controller/chip selects *-------------------------------------------------------------------*/ - mtdcr(ebccfga, xbcfg); - reg = mfdcr(ebccfgd); - mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ + mtdcr(EBC0_CFGADDR, EBC0_CFG); + reg = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */ /*-------------------------------------------------------------------- * Setup the GPIO pins @@ -101,10 +101,10 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup other serial configuration *-------------------------------------------------------------------*/ - mfsdr(sdr_pci0, reg); - mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ - mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */ - mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */ + mfsdr(SDR0_PCI0, reg); + mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */ + mtsdr(SDR0_PFC0, 0x00003e00); /* Pin function */ + mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins */ /*clear tmrclk divisor */ *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00; @@ -129,8 +129,8 @@ int misc_init_r (void) int size_val = 0; /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); switch (gd->bd->bi_flashsize) { case 1 << 20: size_val = 0; @@ -158,8 +158,8 @@ int misc_init_r (void) break; } pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(ebccfga, pb0cr); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGADDR, PB0CR); + mtdcr(EBC0_CFGDATA, pbcr); /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; @@ -353,35 +353,35 @@ int pci_pre_init(struct pci_controller *hose) | Set priority for all PLB3 devices to 0. | Set PLB3 arbiter to fair mode. +-------------------------------------------------------------------------*/ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /*-------------------------------------------------------------------------+ | Set priority for all PLB4 devices to 0. +-------------------------------------------------------------------------*/ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4_ACR, addr); /*-------------------------------------------------------------------------+ | Set Nebula PLB4 arbiter to fair mode. +-------------------------------------------------------------------------*/ /* Segment0 */ - addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; - addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; - addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; - addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; - mtdcr(plb0_acr, addr); + addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; + addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; + addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; + addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; + mtdcr(PLB0_ACR, addr); /* Segment1 */ - addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; - addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; - addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; - addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; - mtdcr(plb1_acr, addr); + addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; + addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; + addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; + addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; + mtdcr(PLB1_ACR, addr); return 1; } diff --git a/board/amcc/yucca/flash.c b/board/amcc/yucca/flash.c index eda49eb1746..33b97a50407 100644 --- a/board/amcc/yucca/flash.c +++ b/board/amcc/yucca/flash.c @@ -981,7 +981,7 @@ unsigned long flash_init(void) * Boot Settings in IIC EEprom address 0xA8 or 0xA0 * Read Serial Device Strap Register1 in PPC440SPe */ - mfsdr(sdr_sdstp1, val); + mfsdr(SDR0_SDSTP1, val); boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK; ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK; diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 06c7d625a49..245004cee87 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -167,7 +167,7 @@ int board_early_init_f (void) | 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 | +-------------------------------------------------------------------*/ - mtebc(xbcfg, EBC_CFG_LE_UNLOCK | + mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_16PERCLK | EBC_CFG_ATC_PREVIOUS | @@ -188,8 +188,8 @@ int board_early_init_f (void) | boot type | +-------------------------------------------------------------------*/ - mtebc(pb1ap, EBC_BXAP_FPGA); - mtebc(pb1cr, EBC_BXCR_FPGA_CS1); + mtebc(PB1AP, EBC_BXAP_FPGA); + mtebc(PB1CR, EBC_BXCR_FPGA_CS1); /*-------------------------------------------------------------------+ | @@ -334,10 +334,10 @@ int board_early_init_f (void) break; } - mtebc(pb0ap, ebc0_cs0_bxap_value); - mtebc(pb0cr, ebc0_cs0_bxcr_value); - mtebc(pb2ap, ebc0_cs2_bxap_value); - mtebc(pb2cr, ebc0_cs2_bxcr_value); + mtebc(PB0AP, ebc0_cs0_bxap_value); + mtebc(PB0CR, ebc0_cs0_bxcr_value); + mtebc(PB2AP, ebc0_cs2_bxap_value); + mtebc(PB2CR, ebc0_cs2_bxcr_value); /*--------------------------------------------------------------------+ | Interrupt controller setup for the AMCC 440SPe Evaluation board. @@ -530,9 +530,9 @@ int board_early_init_f (void) mtdcr (uic0sr, 0x00000000); /* clear all interrupts */ mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */ - mfsdr(sdr_mfr, mfr); + mfsdr(SDR0_MFR, mfr); mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ - mtsdr(sdr_mfr, mfr); + mtsdr(SDR0_MFR, mfr); fpga_init(); @@ -608,7 +608,7 @@ int pci_pre_init(struct pci_controller * hose ) * The yucca board is always configured as the host & requires the * PCI arbiter to be enabled. *-------------------------------------------------------------------*/ - mfsdr(sdr_sdstp1, strap); + mfsdr(SDR0_SDSTP1, strap); if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) { printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); return 0; diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c index 8a06ecc6650..5d1c4170dd1 100644 --- a/board/cray/L1/L1.c +++ b/board/cray/L1/L1.c @@ -198,8 +198,8 @@ static void init_sdram (void) unsigned long tmp; /* write SDRAM bank 0 register */ - mtdcr (memcfga, mem_mb0cf); - mtdcr (memcfgd, 0x00062001); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGDATA, 0x00062001); /* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */ /* To set the appropriate timings, we need to know the SDRAM speed. */ @@ -212,26 +212,26 @@ static void init_sdram (void) /* divisor = ((mfdcr(strap)>> 28) & 0x3); */ /* write SDRAM timing for 100MHz. */ - mtdcr (memcfga, mem_sdtr1); - mtdcr (memcfgd, 0x0086400D); + mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGDATA, 0x0086400D); /* write SDRAM refresh interval register */ - mtdcr (memcfga, mem_rtr); - mtdcr (memcfgd, 0x05F00000); + mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGDATA, 0x05F00000); udelay (200); /* sdram controller.*/ - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, 0x90800000); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGDATA, 0x90800000); udelay (200); /* initially, disable ECC on all banks */ udelay (200); - mtdcr (memcfga, mem_ecccf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_ecccf); + tmp = mfdcr (SDRAM0_CFGDATA); tmp &= 0xff0fffff; - mtdcr (memcfga, mem_ecccf); - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGADDR, mem_ecccf); + mtdcr (SDRAM0_CFGDATA, tmp); return; } @@ -282,18 +282,18 @@ int testdram (void) } printf ("Enable ECC.."); - mtdcr (memcfga, mem_mcopt1); - tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000; - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000; + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGDATA, tmp); udelay (600); for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L) ; udelay (400); - mtdcr (memcfga, mem_ecccf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_ecccf); + tmp = mfdcr (SDRAM0_CFGDATA); tmp |= 0x00800000; - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGDATA, tmp); udelay (400); printf ("enabled.\n"); return (0); diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S index d700ea76cf3..e8dbb93e112 100644 --- a/board/cray/L1/init.S +++ b/board/cray/L1/init.S @@ -87,17 +87,17 @@ ext_bus_cntlr_init: /* Peripheral Bank 0 (Flash) initialization */ /*---------------------------------------------------------------------- */ /* 0x7F8FFE80 slowest boot */ - addi r4,0,pb0ap - mtdcr ebccfga,r4 + addi r4,0,PB1AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x9B01 ori r4,r4,0x5480 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb0cr - mtdcr ebccfga,r4 + addi r4,0,PB0CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */ ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 blr @@ -125,16 +125,16 @@ ext_bus_cntlr_init: /* all reserved bits=0 */ /*---------------------------------------------------------------------- */ /*---------------------------------------------------------------------- */ - addi r4,0,pb1ap - mtdcr ebccfga,r4 + addi r4,0,PB1AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0185 /* hiword */ ori r4,r4,0x4380 /* loword */ - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb1cr - mtdcr ebccfga,r4 + addi r4,0,PB1CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */ ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 blr diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c index 11596d2b7e9..cb24cd4ffeb 100644 --- a/board/csb272/csb272.c +++ b/board/csb272/csb272.c @@ -95,7 +95,7 @@ int board_early_init_f(void) mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtebc (epcr, 0xa8400000); /* EBC always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */ return 0; /* success */ } @@ -135,29 +135,29 @@ phys_size_t initdram (int board_type) tot_size = 0; - mtdcr (memcfga, mem_mb0cf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (memcfga, mem_mb1cf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (memcfga, mem_mb2cf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (memcfga, mem_mb3cf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; diff --git a/board/csb272/init.S b/board/csb272/init.S index 1cfef376a69..15b26f8bf86 100644 --- a/board/csb272/init.S +++ b/board/csb272/init.S @@ -38,17 +38,17 @@ #define WDCR_EBC(reg,val) \ addi r4,0,reg;\ - mtdcr ebccfga,r4;\ + mtdcr EBC0_CFGADDR,r4;\ addis r4,0,val@h;\ ori r4,r4,val@l;\ - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 #define WDCR_SDRAM(reg,val) \ addi r4,0,reg;\ - mtdcr memcfga,r4;\ + mtdcr SDRAM0_CFGADDR,r4;\ addis r4,0,val@h;\ ori r4,r4,val@l;\ - mtdcr memcfgd,r4 + mtdcr SDRAM0_CFGDATA,r4 /****************************************************************************** * Function: ext_bus_cntlr_init @@ -106,51 +106,51 @@ ext_bus_cntlr_init: * SETUP CPC0_CR0 *******************************************************************/ LI32(r4, 0x007000c0) - mtdcr cntrl0, r4 + mtdcr CPC0_CR0, r4 /******************************************************************** * Setup CPC0_CR1: Change PCIINT signal to PerWE *******************************************************************/ - mfdcr r4, cntrl1 + mfdcr r4, CPC0_CR1 ori r4, r4, 0x4000 - mtdcr cntrl1, r4 + mtdcr CPC0_CR1, r4 /******************************************************************** * Setup External Bus Controller (EBC). *******************************************************************/ - WDCR_EBC(epcr, 0xd84c0000) + WDCR_EBC(EBC0_CFG, 0xd84c0000) /******************************************************************** * Memory Bank 0 (Intel 28F128J3 Flash) initialization *******************************************************************/ - /*WDCR_EBC(pb0ap, 0x02869200)*/ - WDCR_EBC(pb0ap, 0x07869200) - WDCR_EBC(pb0cr, 0xfe0bc000) + /*WDCR_EBC(PB1AP, 0x02869200)*/ + WDCR_EBC(PB1AP, 0x07869200) + WDCR_EBC(PB0CR, 0xfe0bc000) /******************************************************************** * Memory Bank 1 (Holtek HT6542B PS/2) initialization *******************************************************************/ - WDCR_EBC(pb1ap, 0x1f869200) - WDCR_EBC(pb1cr, 0xf0818000) + WDCR_EBC(PB1AP, 0x1f869200) + WDCR_EBC(PB1CR, 0xf0818000) /******************************************************************** * Memory Bank 2 (Epson S1D13506) initialization *******************************************************************/ - WDCR_EBC(pb2ap, 0x05860300) - WDCR_EBC(pb2cr, 0xf045a000) + WDCR_EBC(PB2AP, 0x05860300) + WDCR_EBC(PB2CR, 0xf045a000) /******************************************************************** * Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization *******************************************************************/ - WDCR_EBC(pb3ap, 0x0387d200) - WDCR_EBC(pb3cr, 0xf021c000) + WDCR_EBC(PB3AP, 0x0387d200) + WDCR_EBC(PB3CR, 0xf021c000) /******************************************************************** * Memory Bank 4-7 (Unused) initialization *******************************************************************/ - WDCR_EBC(pb4ap, 0) - WDCR_EBC(pb4cr, 0) - WDCR_EBC(pb5ap, 0) - WDCR_EBC(pb5cr, 0) - WDCR_EBC(pb6ap, 0) - WDCR_EBC(pb6cr, 0) - WDCR_EBC(pb7ap, 0) - WDCR_EBC(pb7cr, 0) + WDCR_EBC(PB4AP, 0) + WDCR_EBC(PB4CR, 0) + WDCR_EBC(PB5AP, 0) + WDCR_EBC(PB5CR, 0) + WDCR_EBC(PB6AP, 0) + WDCR_EBC(PB6CR, 0) + WDCR_EBC(PB7AP, 0) + WDCR_EBC(PB7CR, 0) /* We are all done */ mtlr r0 /* Restore link register */ diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c index 9dc130efc17..fa0fa193e82 100644 --- a/board/csb472/csb472.c +++ b/board/csb472/csb472.c @@ -63,7 +63,7 @@ int board_early_init_f(void) mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtebc (epcr, 0xa8400000); /* EBC always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */ return 0; /* success */ } @@ -103,29 +103,29 @@ phys_size_t initdram (int board_type) tot_size = 0; - mtdcr (memcfga, mem_mb0cf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (memcfga, mem_mb1cf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (memcfga, mem_mb2cf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (memcfga, mem_mb3cf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; diff --git a/board/csb472/init.S b/board/csb472/init.S index 2cf8afc4994..105cb71bec0 100644 --- a/board/csb472/init.S +++ b/board/csb472/init.S @@ -38,17 +38,17 @@ #define WDCR_EBC(reg,val) \ addi r4,0,reg;\ - mtdcr ebccfga,r4;\ + mtdcr EBC0_CFGADDR,r4;\ addis r4,0,val@h;\ ori r4,r4,val@l;\ - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 #define WDCR_SDRAM(reg,val) \ addi r4,0,reg;\ - mtdcr memcfga,r4;\ + mtdcr SDRAM0_CFGADDR,r4;\ addis r4,0,val@h;\ ori r4,r4,val@l;\ - mtdcr memcfgd,r4 + mtdcr SDRAM0_CFGDATA,r4 /****************************************************************************** * Function: ext_bus_cntlr_init @@ -106,47 +106,47 @@ ext_bus_cntlr_init: * SETUP CPC0_CR0 *******************************************************************/ LI32(r4, 0x00c01030) - mtdcr cntrl0, r4 + mtdcr CPC0_CR0, r4 /******************************************************************** * Setup CPC0_CR1: Change PCIINT signal to PerWE *******************************************************************/ - mfdcr r4, cntrl1 + mfdcr r4, CPC0_CR1 ori r4, r4, 0x4000 - mtdcr cntrl1, r4 + mtdcr CPC0_CR1, r4 /******************************************************************** * Setup External Bus Controller (EBC). *******************************************************************/ - WDCR_EBC(epcr, 0xd84c0000) + WDCR_EBC(EBC0_CFG, 0xd84c0000) /******************************************************************** * Memory Bank 0 (Intel 28F640J3 Flash) initialization *******************************************************************/ - /*WDCR_EBC(pb0ap, 0x03055200)*/ - /*WDCR_EBC(pb0ap, 0x04055200)*/ - WDCR_EBC(pb0ap, 0x08055200) - WDCR_EBC(pb0cr, 0xff87a000) + /*WDCR_EBC(PB1AP, 0x03055200)*/ + /*WDCR_EBC(PB1AP, 0x04055200)*/ + WDCR_EBC(PB1AP, 0x08055200) + WDCR_EBC(PB0CR, 0xff87a000) /******************************************************************** * Memory Bank 3 (Xilinx XC95144 CPLD) initialization *******************************************************************/ - /*WDCR_EBC(pb3ap, 0x07869200)*/ - WDCR_EBC(pb3ap, 0x04055200) - WDCR_EBC(pb3cr, 0xf081c000) + /*WDCR_EBC(PB3AP, 0x07869200)*/ + WDCR_EBC(PB3AP, 0x04055200) + WDCR_EBC(PB3CR, 0xf081c000) /******************************************************************** * Memory Bank 1,2,4-7 (Unused) initialization *******************************************************************/ - WDCR_EBC(pb1ap, 0) - WDCR_EBC(pb1cr, 0) - WDCR_EBC(pb2ap, 0) - WDCR_EBC(pb2cr, 0) - WDCR_EBC(pb4ap, 0) - WDCR_EBC(pb4cr, 0) - WDCR_EBC(pb5ap, 0) - WDCR_EBC(pb5cr, 0) - WDCR_EBC(pb6ap, 0) - WDCR_EBC(pb6cr, 0) - WDCR_EBC(pb7ap, 0) - WDCR_EBC(pb7cr, 0) + WDCR_EBC(PB1AP, 0) + WDCR_EBC(PB1CR, 0) + WDCR_EBC(PB2AP, 0) + WDCR_EBC(PB2CR, 0) + WDCR_EBC(PB4AP, 0) + WDCR_EBC(PB4CR, 0) + WDCR_EBC(PB5AP, 0) + WDCR_EBC(PB5CR, 0) + WDCR_EBC(PB6AP, 0) + WDCR_EBC(PB6CR, 0) + WDCR_EBC(PB7AP, 0) + WDCR_EBC(PB7CR, 0) /* We are all done */ mtlr r0 /* Restore link register */ diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c index a6aa6554b95..56751e15995 100644 --- a/board/dave/PPChameleonEVB/PPChameleonEVB.c +++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c @@ -65,9 +65,9 @@ int board_early_init_f (void) * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ #if 1 /* test-only */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ #else - mtebc (epcr, 0x28400000); /* ebc in high-z */ + mtebc (EBC0_CFG, 0x28400000); /* ebc in high-z */ #endif return 0; } @@ -101,7 +101,7 @@ int misc_init_r (void) int status; int index; int i; - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { diff --git a/board/dave/PPChameleonEVB/flash.c b/board/dave/PPChameleonEVB/flash.c index e5a0d3d17e2..237c807b4ff 100644 --- a/board/dave/PPChameleonEVB/flash.c +++ b/board/dave/PPChameleonEVB/flash.c @@ -75,9 +75,9 @@ unsigned long flash_init (void) debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base = -size; switch (size) { case 1 << 20: @@ -97,7 +97,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__); /* Monitor protection ON by default */ diff --git a/board/eric/eric.c b/board/eric/eric.c index 600b9d7a7ce..bc2a907f6b9 100644 --- a/board/eric/eric.c +++ b/board/eric/eric.c @@ -70,7 +70,7 @@ int board_early_init_f (void) mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (cntrl0, 0x00002000); /* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */ + mtdcr (CPC0_CR0, 0x00002000); /* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */ out32 (PPC405GP_GPIO0_OR, 0x60000000); /*fixme is SMB_INT high or low active??; IRQ6 is GPIO23 output */ out32 (PPC405GP_GPIO0_TCR, 0x7E400000); diff --git a/board/eric/flash.c b/board/eric/flash.c index 7e57513aebf..fded41271f1 100644 --- a/board/eric/flash.c +++ b/board/eric/flash.c @@ -105,24 +105,24 @@ unsigned long flash_init (void) if (size_b1) { - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b1 = -size_b1; pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17); - mtdcr(ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr(EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ } if (size_b0) { - mtdcr(ebccfga, pb1cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb1cr); + mtdcr(EBC0_CFGADDR, PB1CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB1CR); base_b0 = base_b1 - size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); - mtdcr(ebccfgd, pbcr); - /* printf("pb0cr = %x\n", pbcr); */ + mtdcr(EBC0_CFGDATA, pbcr); + /* printf("PB0CR = %x\n", pbcr); */ } size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b0, &flash_info[0]); diff --git a/board/eric/init.S b/board/eric/init.S index 4820dd08c7f..16ab11eae25 100644 --- a/board/eric/init.S +++ b/board/eric/init.S @@ -76,129 +76,129 @@ ext_bus_cntlr_init: /* Memory Bank 0 (Flash) initialization (from openbios) */ /*----------------------------------------------------------------------- */ - addi r4,0,pb0ap - mtdcr ebccfga,r4 + addi r4,0,PB1AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS0_AP@h ori r4,r4,CS0_AP@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb0cr - mtdcr ebccfga,r4 + addi r4,0,PB0CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS0_CR@h ori r4,r4,CS0_CR@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /*----------------------------------------------------------------------- */ /* Memory Bank 1 (NVRAM/RTC) initialization */ /*----------------------------------------------------------------------- */ - addi r4,0,pb1ap - mtdcr ebccfga,r4 + addi r4,0,PB1AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS1_AP@h ori r4,r4,CS1_AP@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb1cr - mtdcr ebccfga,r4 + addi r4,0,PB1CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS1_CR@h ori r4,r4,CS1_CR@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /*----------------------------------------------------------------------- */ /* Memory Bank 2 (A/D converter) initialization */ /*----------------------------------------------------------------------- */ - addi r4,0,pb2ap - mtdcr ebccfga,r4 + addi r4,0,PB2AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS2_AP@h ori r4,r4,CS2_AP@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb2cr - mtdcr ebccfga,r4 + addi r4,0,PB2CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS2_CR@h ori r4,r4,CS2_CR@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /*----------------------------------------------------------------------- */ /* Memory Bank 3 (Ethernet PHY Reset) initialization */ /*----------------------------------------------------------------------- */ - addi r4,0,pb3ap - mtdcr ebccfga,r4 + addi r4,0,PB3AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS3_AP@h ori r4,r4,CS3_AP@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb3cr - mtdcr ebccfga,r4 + addi r4,0,PB3CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS3_CR@h ori r4,r4,CS3_CR@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /*----------------------------------------------------------------------- */ /* Memory Bank 4 (PC-MIP PRSNT1#) initialization */ /*----------------------------------------------------------------------- */ - addi r4,0,pb4ap - mtdcr ebccfga,r4 + addi r4,0,PB4AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS4_AP@h ori r4,r4,CS4_AP@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb4cr - mtdcr ebccfga,r4 + addi r4,0,PB4CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS4_CR@h ori r4,r4,CS4_CR@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /*----------------------------------------------------------------------- */ /* Memory Bank 5 (PC-MIP PRSNT2#) initialization */ /*----------------------------------------------------------------------- */ - addi r4,0,pb5ap - mtdcr ebccfga,r4 + addi r4,0,PB5AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS5_AP@h ori r4,r4,CS5_AP@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb5cr - mtdcr ebccfga,r4 + addi r4,0,PB5CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS5_CR@h ori r4,r4,CS5_CR@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /*----------------------------------------------------------------------- */ /* Memory Bank 6 (CPU LED0) initialization */ /*----------------------------------------------------------------------- */ - addi r4,0,pb6ap - mtdcr ebccfga,r4 + addi r4,0,PB6AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS6_AP@h ori r4,r4,CS6_AP@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb6cr - mtdcr ebccfga,r4 + addi r4,0,PB6CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS6_CR@h ori r4,r4,CS5_CR@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /*----------------------------------------------------------------------- */ /* Memory Bank 7 (CPU LED1) initialization */ /*----------------------------------------------------------------------- */ - addi r4,0,pb7ap - mtdcr ebccfga,r4 + addi r4,0,PB7AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS7_AP@h ori r4,r4,CS7_AP@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb7cr - mtdcr ebccfga,r4 + addi r4,0,PB7CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS7_CR@h ori r4,r4,CS7_CR@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /* addis r4,r0,FPGA_BRDC@h */ /* ori r4,r4,FPGA_BRDC@l */ @@ -229,40 +229,40 @@ sdram_init: /*------------------------------------------------------------------- */ addi r4,0,mem_mb0cf - mtdcr memcfga,r4 + mtdcr SDRAM0_CFGADDR,r4 addis r4,0,MB0CF@h ori r4,r4,MB0CF@l - mtdcr memcfgd,r4 + mtdcr SDRAM0_CFGDATA,r4 /*------------------------------------------------------------------- */ /* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) */ /*------------------------------------------------------------------- */ addi r4,0,mem_mb1cf - mtdcr memcfga,r4 + mtdcr SDRAM0_CFGADDR,r4 addis r4,0,MB1CF@h ori r4,r4,MB1CF@l - mtdcr memcfgd,r4 + mtdcr SDRAM0_CFGDATA,r4 /*------------------------------------------------------------------- */ /* Set MB2CF for bank 2. off */ /*------------------------------------------------------------------- */ addi r4,0,mem_mb2cf - mtdcr memcfga,r4 + mtdcr SDRAM0_CFGADDR,r4 addis r4,0,MB2CF@h ori r4,r4,MB2CF@l - mtdcr memcfgd,r4 + mtdcr SDRAM0_CFGDATA,r4 /*------------------------------------------------------------------- */ /* Set MB3CF for bank 3. off */ /*------------------------------------------------------------------- */ addi r4,0,mem_mb3cf - mtdcr memcfga,r4 + mtdcr SDRAM0_CFGADDR,r4 addis r4,0,MB3CF@h ori r4,r4,MB3CF@l - mtdcr memcfgd,r4 + mtdcr SDRAM0_CFGDATA,r4 /*------------------------------------------------------------------- */ /* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */ @@ -276,7 +276,7 @@ sdram_init: /* maybe 133Mhz. */ /*------------------------------------------------------------------- */ - mfdcr r5,strap /* determine FBK divider */ + mfdcr r5,CPC0_PSR /* determine FBK divider */ /* via STRAP reg to calc PLB speed. */ /* SDRAM speed is the same as the PLB */ /* speed. */ @@ -306,15 +306,15 @@ sdram_init: /* Set SDTR1 */ /*------------------------------------------------------------------- */ addi r4,0,mem_sdtr1 - mtdcr memcfga,r4 - mtdcr memcfgd,r6 + mtdcr SDRAM0_CFGADDR,r4 + mtdcr SDRAM0_CFGDATA,r6 /*------------------------------------------------------------------- */ /* Set RTR */ /*------------------------------------------------------------------- */ addi r4,0,mem_rtr - mtdcr memcfga,r4 - mtdcr memcfgd,r7 + mtdcr SDRAM0_CFGADDR,r4 + mtdcr SDRAM0_CFGDATA,r7 /*------------------------------------------------------------------- */ /* Delay to ensure 200usec have elapsed since reset. Assume worst */ @@ -333,10 +333,10 @@ sdram_init: /* read/prefetch. */ /*------------------------------------------------------------------- */ addi r4,0,mem_mcopt1 - mtdcr memcfga,r4 + mtdcr SDRAM0_CFGADDR,r4 addis r4,0,0x8080 /* set DC_EN=1 */ ori r4,r4,0x0000 - mtdcr memcfgd,r4 + mtdcr SDRAM0_CFGDATA,r4 /*------------------------------------------------------------------- */ /* Delay to ensure 10msec have elapsed since reset. This is */ diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c index 5a021552dd3..46622a29fd4 100644 --- a/board/esd/apc405/apc405.c +++ b/board/esd/apc405/apc405.c @@ -92,7 +92,7 @@ int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); int board_revision(void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; unsigned long value; /* @@ -100,8 +100,8 @@ int board_revision(void) */ /* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x03800000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03800000); out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000); out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000); @@ -113,7 +113,7 @@ int board_revision(void) /* * Restore GPIO settings */ - mtdcr(cntrl0, cntrl0Reg); + mtdcr(CPC0_CR0, CPC0_CR0Reg); switch (value) { case 0x001c0000: @@ -166,7 +166,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks */ - mtebc(epcr, 0xa8400000); /* ebc always driven */ + mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ /* * New boards have a single 32MB flash connected to CS0 @@ -174,12 +174,12 @@ int board_early_init_f (void) */ if (board_revision() >= 8) { /* disable CS1 */ - mtebc(pb1ap, 0); - mtebc(pb1cr, 0); + mtebc(PB1AP, 0); + mtebc(PB1CR, 0); /* resize CS0 to 32MB */ - mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP_HWREV8); - mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR_HWREV8); + mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP_HWREV8); + mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR_HWREV8); } return 0; @@ -209,7 +209,7 @@ int misc_init_r(void) int status; int index; int i; - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; char *str; uchar *logo_addr; ulong logo_size; @@ -219,8 +219,8 @@ int misc_init_r(void) /* * Setup GPIO pins (CS6+CS7 as GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00300000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000); dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { @@ -265,7 +265,7 @@ int misc_init_r(void) } /* restore gpio/cs settings */ - mtdcr(cntrl0, cntrl0Reg); + mtdcr(CPC0_CR0, CPC0_CR0Reg); puts("FPGA: "); diff --git a/board/esd/ar405/flash.c b/board/esd/ar405/flash.c index 274ada9fe5c..a53122b2171 100644 --- a/board/esd/ar405/flash.c +++ b/board/esd/ar405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c index 074fe08b1c1..8da08facffc 100644 --- a/board/esd/ash405/ash405.c +++ b/board/esd/ash405/ash405.c @@ -77,7 +77,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ return 0; } diff --git a/board/esd/ash405/flash.c b/board/esd/ash405/flash.c index 274ada9fe5c..a53122b2171 100644 --- a/board/esd/ash405/flash.c +++ b/board/esd/ash405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/canbt/canbt.c b/board/esd/canbt/canbt.c index 2fe6b7bf046..418d3e237ed 100644 --- a/board/esd/canbt/canbt.c +++ b/board/esd/canbt/canbt.c @@ -52,16 +52,16 @@ const unsigned char fpgadata[] = { int board_early_init_f (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; int index, len, i; int status; /* * Setup GPIO pins */ - cntrl0Reg = mfdcr (cntrl0) & 0xf0001fff; - cntrl0Reg |= 0x0070f000; - mtdcr (cntrl0, cntrl0Reg); + CPC0_CR0Reg = mfdcr (CPC0_CR0) & 0xf0001fff; + CPC0_CR0Reg |= 0x0070f000; + mtdcr (CPC0_CR0, CPC0_CR0Reg); #ifdef FPGA_DEBUG /* set up serial port with default baudrate */ diff --git a/board/esd/canbt/flash.c b/board/esd/canbt/flash.c index 56c822ec97f..224dde4ee0b 100644 --- a/board/esd/canbt/flash.c +++ b/board/esd/canbt/flash.c @@ -64,13 +64,13 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); - mtdcr(ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr(EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c index 01b12232b19..7a92401893d 100644 --- a/board/esd/cms700/cms700.c +++ b/board/esd/cms700/cms700.c @@ -56,7 +56,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ /* * Reset CPLD via GPIO12 (CS3) pin diff --git a/board/esd/cms700/flash.c b/board/esd/cms700/flash.c index 274ada9fe5c..a53122b2171 100644 --- a/board/esd/cms700/flash.c +++ b/board/esd/cms700/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c index cd57ed4598c..00c7024a852 100644 --- a/board/esd/cpci2dp/cpci2dp.c +++ b/board/esd/cpci2dp/cpci2dp.c @@ -31,13 +31,13 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; /* * Setup GPIO pins */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED | CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5)); @@ -72,7 +72,7 @@ int board_early_init_f (void) int misc_init_r (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; @@ -81,8 +81,8 @@ int misc_init_r (void) /* * Select cts (and not dsr) on uart1 */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00001000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); return (0); } diff --git a/board/esd/cpci2dp/flash.c b/board/esd/cpci2dp/flash.c index 56c822ec97f..224dde4ee0b 100644 --- a/board/esd/cpci2dp/flash.c +++ b/board/esd/cpci2dp/flash.c @@ -64,13 +64,13 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); - mtdcr(ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr(EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index a677c623f78..4c9ed2fa585 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -214,7 +214,7 @@ int ctermm2(void) int cpci405_host(void) { - if (mfdcr(strap) & PSR_PCI_ARBIT_EN) + if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN) return -1; /* yes, board is cpci405 host */ else return 0; /* no, board is cpci405 adapter */ @@ -222,14 +222,14 @@ int cpci405_host(void) int cpci405_version(void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; unsigned long value; /* * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x03000000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000); out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000); out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000); udelay(1000); /* wait some time before reading input */ @@ -238,7 +238,7 @@ int cpci405_version(void) /* * Restore GPIO settings */ - mtdcr(cntrl0, cntrl0Reg); + mtdcr(CPC0_CR0, CPC0_CR0Reg); switch (value) { case 0x00180000: @@ -261,7 +261,7 @@ int cpci405_version(void) int misc_init_r (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; @@ -283,8 +283,8 @@ int misc_init_r (void) /* * Setup GPIO pins (CS6+CS7 as GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00300000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000); dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, @@ -330,7 +330,7 @@ int misc_init_r (void) } /* restore gpio/cs settings */ - mtdcr(cntrl0, cntrl0Reg); + mtdcr(CPC0_CR0, CPC0_CR0Reg); puts("FPGA: "); @@ -400,8 +400,8 @@ int misc_init_r (void) /* * Select cts (and not dsr) on uart1 */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00001000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); return 0; } diff --git a/board/esd/cpci405/flash.c b/board/esd/cpci405/flash.c index d535924f86f..4fcf174d15b 100644 --- a/board/esd/cpci405/flash.c +++ b/board/esd/cpci405/flash.c @@ -91,13 +91,13 @@ unsigned long flash_init (void) size_b1 = 1 << 20; } base_b1 = -size_b1; - mtdcr (ebccfga, pb0cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb0cr); + mtdcr (EBC0_CFGADDR, PB0CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB0CR); pbcr = (pbcr & 0x0001ffff) | base_b1 | (calc_size(size_b1) << 17); - mtdcr (ebccfgd, pbcr); + mtdcr (EBC0_CFGDATA, pbcr); #if 0 /* test-only */ - printf("size_b1=%x base_b1=%x pb1cr = %x\n", + printf("size_b1=%x base_b1=%x PB1CR = %x\n", size_b1, base_b1, pbcr); /* test-only */ #endif } @@ -108,13 +108,13 @@ unsigned long flash_init (void) size_b0 = 1 << 20; } base_b0 = base_b1 - size_b0; - mtdcr (ebccfga, pb1cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb1cr); + mtdcr (EBC0_CFGADDR, PB1CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB1CR); pbcr = (pbcr & 0x0001ffff) | base_b0 | (calc_size(size_b0) << 17); - mtdcr (ebccfgd, pbcr); + mtdcr (EBC0_CFGDATA, pbcr); #if 0 /* test-only */ - printf("size_b0=%x base_b0=%x pb0cr = %x\n", + printf("size_b0=%x base_b0=%x PB0CR = %x\n", size_b0, base_b0, pbcr); /* test-only */ #endif } diff --git a/board/esd/cpciiser4/flash.c b/board/esd/cpciiser4/flash.c index 56c822ec97f..224dde4ee0b 100644 --- a/board/esd/cpciiser4/flash.c +++ b/board/esd/cpciiser4/flash.c @@ -64,13 +64,13 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); - mtdcr(ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr(EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/dp405/dp405.c b/board/esd/dp405/dp405.c index e52d37bc217..fc0d091bca9 100644 --- a/board/esd/dp405/dp405.c +++ b/board/esd/dp405/dp405.c @@ -54,7 +54,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ /* * Reset CPLD via GPIO13 (CS4) pin diff --git a/board/esd/dp405/flash.c b/board/esd/dp405/flash.c index 274ada9fe5c..a53122b2171 100644 --- a/board/esd/dp405/flash.c +++ b/board/esd/dp405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c index 8e9ac28b181..28a50c7b0e7 100644 --- a/board/esd/du405/du405.c +++ b/board/esd/du405/du405.c @@ -135,7 +135,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 100 us */ - mtebc (epcr, 0xb8400000); + mtebc (EBC0_CFG, 0xb8400000); return 0; } @@ -143,13 +143,13 @@ int board_early_init_f (void) int misc_init_r (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; /* * Setup UART1 handshaking: use CTS instead of DSR */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00001000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); return (0); } diff --git a/board/esd/du405/flash.c b/board/esd/du405/flash.c index 240aa09f5b4..c62c6a9b030 100644 --- a/board/esd/du405/flash.c +++ b/board/esd/du405/flash.c @@ -67,25 +67,25 @@ unsigned long flash_init (void) /* Re-do sizing to get full correct info */ if (size_b1) { - mtdcr (ebccfga, pb0cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb0cr); + mtdcr (EBC0_CFGADDR, PB0CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB0CR); base_b1 = -size_b1; pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1 / 1024 / 1024) - 1) << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr (EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ } if (size_b0) { - mtdcr (ebccfga, pb1cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb1cr); + mtdcr (EBC0_CFGADDR, PB1CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB1CR); base_b0 = base_b1 - size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0 / 1024 / 1024) - 1) << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb0cr = %x\n", pbcr); */ + mtdcr (EBC0_CFGDATA, pbcr); + /* printf("PB0CR = %x\n", pbcr); */ } size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c index 0ec519b8db6..376de983548 100644 --- a/board/esd/du440/du440.c +++ b/board/esd/du440/du440.c @@ -45,8 +45,8 @@ int board_early_init_f(void) u32 sdr0_pfc1, sdr0_pfc2; u32 reg; - mtdcr(ebccfga, xbcfg); - mtdcr(ebccfgd, 0xb8400000); + mtdcr(EBC0_CFGADDR, EBC0_CFG); + mtdcr(EBC0_CFGDATA, 0xb8400000); /* * Setup the GPIO pins @@ -145,8 +145,8 @@ int board_early_init_f(void) mtsdr(SDR0_PFC1, sdr0_pfc1); /* PCI arbiter enabled */ - mfsdr(sdr_pci0, reg); - mtsdr(sdr_pci0, 0x80000000 | reg); + mfsdr(SDR0_PCI0, reg); + mtsdr(SDR0_PCI0, 0x80000000 | reg); /* setup NAND FLASH */ mfsdr(SDR0_CUST0, sdr0_cust0); @@ -176,12 +176,12 @@ int misc_init_r(void) gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); size_val = ffs(gd->bd->bi_flashsize) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(ebccfga, pb0cr); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGADDR, PB0CR); + mtdcr(EBC0_CFGDATA, pbcr); /* * Re-check to get correct base address @@ -265,8 +265,8 @@ int misc_init_r(void) * This fix will make the MAL burst disabling patch for the Linux * EMAC driver obsolete. */ - reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; - mtdcr(plb4_acr, reg); + reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP; + mtdcr(PLB4_ACR, reg); /* * release IO-RST# @@ -380,35 +380,35 @@ int pci_pre_init(struct pci_controller *hose) * Set priority for all PLB3 devices to 0. * Set PLB3 arbiter to fair mode. */ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /* * Set priority for all PLB4 devices to 0. */ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4_ACR, addr); /* * Set Nebula PLB4 arbiter to fair mode. */ /* Segment0 */ - addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; - addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; - addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; - addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; - mtdcr(plb0_acr, addr); + addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; + addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; + addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; + addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; + mtdcr(PLB0_ACR, addr); /* Segment1 */ - addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; - addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; - addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; - addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; - mtdcr(plb1_acr, addr); + addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; + addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; + addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; + addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; + mtdcr(PLB1_ACR, addr); return 1; } diff --git a/board/esd/hh405/flash.c b/board/esd/hh405/flash.c index 274ada9fe5c..a53122b2171 100644 --- a/board/esd/hh405/flash.c +++ b/board/esd/hh405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c index 5ae4c75861e..b72b716ddf2 100644 --- a/board/esd/hh405/hh405.c +++ b/board/esd/hh405/hh405.c @@ -374,7 +374,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc(epcr, 0xa8400000); /* ebc always driven */ + mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ return 0; } diff --git a/board/esd/hub405/flash.c b/board/esd/hub405/flash.c index 274ada9fe5c..a53122b2171 100644 --- a/board/esd/hub405/flash.c +++ b/board/esd/hub405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c index 03e5ad7dd16..acb23dad1f5 100644 --- a/board/esd/hub405/hub405.c +++ b/board/esd/hub405/hub405.c @@ -97,7 +97,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ return 0; } diff --git a/board/esd/ocrtc/flash.c b/board/esd/ocrtc/flash.c index e763a895ea4..eda7c5713c3 100644 --- a/board/esd/ocrtc/flash.c +++ b/board/esd/ocrtc/flash.c @@ -68,9 +68,9 @@ unsigned long flash_init (void) /* Re-do sizing to get full correct info */ if (size_b1) { - mtdcr (ebccfga, pb0cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb0cr); + mtdcr (EBC0_CFGADDR, PB0CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB0CR); base_b1 = -size_b1; switch (size_b1) { case 1 << 20: @@ -90,14 +90,14 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b1 | (size_val << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr (EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ } if (size_b0) { - mtdcr (ebccfga, pb1cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb1cr); + mtdcr (EBC0_CFGADDR, PB1CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB1CR); base_b0 = base_b1 - size_b0; switch (size_b1) { case 1 << 20: @@ -117,8 +117,8 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb0cr = %x\n", pbcr); */ + mtdcr (EBC0_CFGDATA, pbcr); + /* printf("PB0CR = %x\n", pbcr); */ } size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); diff --git a/board/esd/ocrtc/ocrtc.c b/board/esd/ocrtc/ocrtc.c index 35bfa95f269..709bcdd9802 100644 --- a/board/esd/ocrtc/ocrtc.c +++ b/board/esd/ocrtc/ocrtc.c @@ -57,7 +57,7 @@ int board_early_init_f (void) * EBC Configuration Register: clear EBTC -> high-Z ebc signals between * transfers, set device-paced timeout to 256 cycles */ - mtebc (epcr, 0x20400000); + mtebc (EBC0_CFG, 0x20400000); return 0; } diff --git a/board/esd/pci405/flash.c b/board/esd/pci405/flash.c index 90584838008..67a7bb5d867 100644 --- a/board/esd/pci405/flash.c +++ b/board/esd/pci405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c index 56184caa8f4..04bc569ead1 100644 --- a/board/esd/pci405/pci405.c +++ b/board/esd/pci405/pci405.c @@ -67,7 +67,7 @@ const unsigned char fpgadata[] = int board_revision(void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; unsigned long value; /* @@ -77,8 +77,8 @@ int board_revision(void) /* * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x03000000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000); out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200); out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200); udelay(1000); /* wait some time before reading input */ @@ -87,7 +87,7 @@ int board_revision(void) /* * Restore GPIO settings */ - mtdcr(cntrl0, cntrl0Reg); + mtdcr(CPC0_CR0, CPC0_CR0Reg); switch (value) { case 0x00100200: @@ -133,7 +133,7 @@ unsigned long fpga_init_state(void) int board_early_init_f (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; /* * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board) @@ -166,18 +166,18 @@ int board_early_init_f (void) /* * Setup GPIO pins (IRQ4/GPIO21 as GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00008000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00008000); /* * Setup GPIO pins (CS6+CS7 as GPIO) */ - mtdcr(cntrl0, cntrl0Reg | 0x00300000); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000); /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ return 0; } @@ -282,11 +282,11 @@ int misc_init_r (void) #define PCI0_BRDGOPT1 0x4a pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20); -#define plb0_acr 0x87 +#define PLB0_ACR 0x87 /* * Enable fairness and high bus utilization */ - mtdcr(plb0_acr, 0x98000000); + mtdcr(PLB0_ACR, 0x98000000); free(dst); return (0); @@ -313,14 +313,14 @@ int checkboard (void) printf(" (Rev 1.%ld", gd->board_type); if (gd->board_type >= 2) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; unsigned long value; /* * Setup GPIO pins (Trace/GPIO1 to GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg & ~0x08000000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg & ~0x08000000); out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000); out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000); udelay(1000); /* wait some time before reading input */ diff --git a/board/esd/plu405/flash.c b/board/esd/plu405/flash.c index 274ada9fe5c..a53122b2171 100644 --- a/board/esd/plu405/flash.c +++ b/board/esd/plu405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index e41545a9369..a3c1cec6ef4 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -90,7 +90,7 @@ int board_early_init_f(void) * EBC Configuration Register: set ready timeout to * 512 ebc-clks -> ca. 15 us */ - mtebc(epcr, 0xa8400000); /* ebc always driven */ + mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ return 0; } diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c index 192a642aea0..5ff87e7a250 100644 --- a/board/esd/pmc405/pmc405.c +++ b/board/esd/pmc405/pmc405.c @@ -60,12 +60,12 @@ int board_early_init_f (void) * EBC Configuration Register: * set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); + mtebc (EBC0_CFG, 0xa8400000); /* * Setup GPIO pins */ - mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_FPGA_INIT | + mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_FPGA_INIT | CONFIG_SYS_FPGA_DONE | CONFIG_SYS_XEREADY | CONFIG_SYS_NONMONARCH | @@ -73,7 +73,7 @@ int board_early_init_f (void) if (!(in_be32((void *)GPIO0_IR) & CONFIG_SYS_REV1_2)) { /* rev 1.2 boards */ - mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_INTA_FAKE | + mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_INTA_FAKE | CONFIG_SYS_SELF_RST) << 5)); } diff --git a/board/esd/pmc405de/pmc405de.c b/board/esd/pmc405de/pmc405de.c index f68e1b5e86b..419311aec83 100644 --- a/board/esd/pmc405de/pmc405de.c +++ b/board/esd/pmc405de/pmc405de.c @@ -127,7 +127,7 @@ int board_early_init_f(void) * - set ready timeout to 512 ebc-clks -> ca. 15 us * - EBC lines are always driven */ - mtebc(epcr, 0xa8400000); + mtebc(EBC0_CFG, 0xa8400000); return 0; } diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index f22a1c28888..119cbf26273 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -64,7 +64,7 @@ struct serial_device *default_serial_console(void) * Use default console on P4 when strapping jumper * is installed (bootstrap option != 'H'). */ - mfsdr(SDR_PINSTP, val); + mfsdr(SDR0_PINSTP, val); if (((val & 0xf0000000) >> 29) != 7) return &serial1_device; @@ -100,8 +100,8 @@ int board_early_init_f(void) u32 reg; /* general EBC configuration (disable EBC timeouts) */ - mtdcr(ebccfga, xbcfg); - mtdcr(ebccfgd, 0xf8400000); + mtdcr(EBC0_CFGADDR, EBC0_CFG); + mtdcr(EBC0_CFGDATA, 0xf8400000); /* * Setup the GPIO pins @@ -134,13 +134,13 @@ int board_early_init_f(void) out_be32((void *)GPIO1_ISR3H, 0x00000000); /* patch PLB:PCI divider for 66MHz PCI */ - mfcpr(clk_spcid, reg); + mfcpr(CPR0_SPCID, reg); if (pci_is_66mhz() && (reg != 0x02000000)) { - mtcpr(clk_spcid, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */ + mtcpr(CPR0_SPCID, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */ - mfcpr(clk_icfg, reg); + mfcpr(CPR0_ICFG, reg); reg |= CPR0_ICFG_RLI_MASK; - mtcpr(clk_icfg, reg); + mtcpr(CPR0_ICFG, reg); mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */ } @@ -240,19 +240,19 @@ int misc_init_r(void) gd->bd->bi_flashoffset = 0; #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtdcr(ebccfga, pb2cr); + mtdcr(EBC0_CFGADDR, PB2CR); #else - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); #endif - pbcr = mfdcr(ebccfgd); + pbcr = mfdcr(EBC0_CFGDATA); size_val = ffs(gd->bd->bi_flashsize) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtdcr(ebccfga, pb2cr); + mtdcr(EBC0_CFGADDR, PB2CR); #else - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); #endif - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* * Re-check to get correct base address @@ -424,8 +424,8 @@ int misc_init_r(void) * This fix will make the MAL burst disabling patch for the Linux * EMAC driver obsolete. */ - reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; - mtdcr(plb4_acr, reg); + reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP; + mtdcr(PLB4_ACR, reg); #ifdef CONFIG_FPGA pmc440_init_fpga(); @@ -507,35 +507,35 @@ int pci_pre_init(struct pci_controller *hose) * Set priority for all PLB3 devices to 0. * Set PLB3 arbiter to fair mode. */ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /* * Set priority for all PLB4 devices to 0. */ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4_ACR, addr); /* * Set Nebula PLB4 arbiter to fair mode. */ /* Segment0 */ - addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; - addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; - addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; - addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; - mtdcr(plb0_acr, addr); + addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; + addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; + addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; + addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; + mtdcr(PLB0_ACR, addr); /* Segment1 */ - addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; - addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; - addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; - addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; - mtdcr(plb1_acr, addr); + addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; + addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; + addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; + addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; + mtdcr(PLB1_ACR, addr); #ifdef CONFIG_PCI_PNP hose->fixup_irq = pmc440_pci_fixup_irq; diff --git a/board/esd/voh405/flash.c b/board/esd/voh405/flash.c index 274ada9fe5c..a53122b2171 100644 --- a/board/esd/voh405/flash.c +++ b/board/esd/voh405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c index 91275507e0f..7477f56b2b1 100644 --- a/board/esd/voh405/voh405.c +++ b/board/esd/voh405/voh405.c @@ -99,7 +99,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ return 0; } diff --git a/board/esd/vom405/flash.c b/board/esd/vom405/flash.c index 274ada9fe5c..a53122b2171 100644 --- a/board/esd/vom405/flash.c +++ b/board/esd/vom405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c index a481acaea14..de9c7b974cf 100644 --- a/board/esd/vom405/vom405.c +++ b/board/esd/vom405/vom405.c @@ -56,7 +56,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ /* * Reset CPLD via GPIO12 (CS3) pin diff --git a/board/esd/wuh405/flash.c b/board/esd/wuh405/flash.c index 274ada9fe5c..a53122b2171 100644 --- a/board/esd/wuh405/flash.c +++ b/board/esd/wuh405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c index e330fff16c9..e86f1d0abc6 100644 --- a/board/esd/wuh405/wuh405.c +++ b/board/esd/wuh405/wuh405.c @@ -75,7 +75,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ return 0; } diff --git a/board/exbitgen/exbitgen.c b/board/exbitgen/exbitgen.c index dc07d3df063..0f8412776b6 100644 --- a/board/exbitgen/exbitgen.c +++ b/board/exbitgen/exbitgen.c @@ -94,29 +94,29 @@ phys_size_t initdram (int board_type) tot_size = 0; - mtdcr (memcfga, mem_mb0cf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (memcfga, mem_mb1cf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (memcfga, mem_mb2cf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (memcfga, mem_mb3cf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; diff --git a/board/exbitgen/init.S b/board/exbitgen/init.S index cb548746182..c2dae560f5f 100644 --- a/board/exbitgen/init.S +++ b/board/exbitgen/init.S @@ -109,10 +109,10 @@ #define WDCR_EBC(reg,val) addi r4,0,reg;\ - mtdcr ebccfga,r4;\ + mtdcr EBC0_CFGADDR,r4;\ addis r4,0,val@h;\ ori r4,r4,val@l;\ - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /*--------------------------------------------------------------------- * Function: ext_bus_cntlr_init @@ -164,22 +164,22 @@ ext_bus_cntlr_init: * Memory Bank 0 (Boot Flash) initialization *--------------------------------------------------------------- */ - WDCR_EBC(pb0ap, FLASH_32bit_AP) - WDCR_EBC(pb0cr, 0xffe38000) -/*pnc WDCR_EBC(pb0cr, FLASH_32bit_CR) */ + WDCR_EBC(PB1AP, FLASH_32bit_AP) + WDCR_EBC(PB0CR, 0xffe38000) +/*pnc WDCR_EBC(PB0CR, FLASH_32bit_CR) */ /*--------------------------------------------------------------- * Memory Bank 5 (CPLD) initialization *--------------------------------------------------------------- */ - WDCR_EBC(pb5ap, 0x01010040) -/*jsa recommendation: WDCR_EBC(pb5ap, 0x00010040) */ - WDCR_EBC(pb5cr, 0x10038000) + WDCR_EBC(PB5AP, 0x01010040) +/*jsa recommendation: WDCR_EBC(PB5AP, 0x00010040) */ + WDCR_EBC(PB5CR, 0x10038000) /*--------------------------------------------------------------- */ /* Memory Bank 6 (not used) initialization */ /*--------------------------------------------------------------- */ - WDCR_EBC(pb6cr, 0x00000000) + WDCR_EBC(PB6CR, 0x00000000) /* Read HW ID to determine whether old H2 board or new generic CPU board */ addis r3, 0, HW_ID_ADDR@h @@ -196,24 +196,24 @@ setup_genieboard: /*--------------------------------------------------------------- */ /* Memory Bank 1 (Application Flash) initialization for generic CPU board */ /*--------------------------------------------------------------- */ -/* WDCR_EBC(pb1ap, 0x7b015480) /###* T.B.M. */ -/* WDCR_EBC(pb1ap, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(pb1ap, 0x9b015480) /* hlb-20020207: burst 8 bit 6 cycles */ +/* WDCR_EBC(PB1AP, 0x7b015480) /###* T.B.M. */ +/* WDCR_EBC(PB1AP, 0x7F8FFE80) /###* T.B.M. */ + WDCR_EBC(PB1AP, 0x9b015480) /* hlb-20020207: burst 8 bit 6 cycles */ -/* WDCR_EBC(pb1cr, 0x20098000) /###* 16 MB */ - WDCR_EBC(pb1cr, 0x200B8000) /* 32 MB */ +/* WDCR_EBC(PB1CR, 0x20098000) /###* 16 MB */ + WDCR_EBC(PB1CR, 0x200B8000) /* 32 MB */ /*--------------------------------------------------------------- */ /* Memory Bank 4 (Onboard FPGA) initialization for generic CPU board */ /*--------------------------------------------------------------- */ - WDCR_EBC(pb4ap, 0x01010000) /* */ - WDCR_EBC(pb4cr, 0x1021c000) /* */ + WDCR_EBC(PB4AP, 0x01010000) /* */ + WDCR_EBC(PB4CR, 0x1021c000) /* */ /*--------------------------------------------------------------- */ /* Memory Bank 7 (Heathrow chip on Reference board) initialization */ /*--------------------------------------------------------------- */ - WDCR_EBC(pb7ap, 0x200ffe80) /* No Ready, many wait states (let reflections die out) */ - WDCR_EBC(pb7cr, 0X4001A000) + WDCR_EBC(PB7AP, 0x200ffe80) /* No Ready, many wait states (let reflections die out) */ + WDCR_EBC(PB7CR, 0X4001A000) bl setup_continue @@ -222,36 +222,36 @@ setup_h2evalboard: /*--------------------------------------------------------------- */ /* Memory Bank 1 (Application Flash) initialization */ /*--------------------------------------------------------------- */ - WDCR_EBC(pb1ap, 0x7b015480) /* T.B.M. */ -/*3010 WDCR_EBC(pb1ap, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(pb1cr, 0x20058000) + WDCR_EBC(PB1AP, 0x7b015480) /* T.B.M. */ +/*3010 WDCR_EBC(PB1AP, 0x7F8FFE80) /###* T.B.M. */ + WDCR_EBC(PB1CR, 0x20058000) /*--------------------------------------------------------------- */ /* Memory Bank 2 (Application Flash) initialization */ /*--------------------------------------------------------------- */ - WDCR_EBC(pb2ap, 0x7b015480) /* T.B.M. */ -/*3010 WDCR_EBC(pb2ap, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(pb2cr, 0x20458000) + WDCR_EBC(PB2AP, 0x7b015480) /* T.B.M. */ +/*3010 WDCR_EBC(PB2AP, 0x7F8FFE80) /###* T.B.M. */ + WDCR_EBC(PB2CR, 0x20458000) /*--------------------------------------------------------------- */ /* Memory Bank 3 (Application Flash) initialization */ /*--------------------------------------------------------------- */ - WDCR_EBC(pb3ap, 0x7b015480) /* T.B.M. */ -/*3010 WDCR_EBC(pb3ap, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(pb3cr, 0x20858000) + WDCR_EBC(PB3AP, 0x7b015480) /* T.B.M. */ +/*3010 WDCR_EBC(PB3AP, 0x7F8FFE80) /###* T.B.M. */ + WDCR_EBC(PB3CR, 0x20858000) /*--------------------------------------------------------------- */ /* Memory Bank 4 (Application Flash) initialization */ /*--------------------------------------------------------------- */ - WDCR_EBC(pb4ap, 0x7b015480) /* T.B.M. */ -/*3010 WDCR_EBC(pb4ap, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(pb4cr, 0x20C58000) + WDCR_EBC(PB4AP, 0x7b015480) /* T.B.M. */ +/*3010 WDCR_EBC(PB4AP, 0x7F8FFE80) /###* T.B.M. */ + WDCR_EBC(PB4CR, 0x20C58000) /*--------------------------------------------------------------- */ /* Memory Bank 7 (Heathrow chip) initialization */ /*--------------------------------------------------------------- */ - WDCR_EBC(pb7ap, 0x02000280) /* No Ready, 4 wait states */ - WDCR_EBC(pb7cr, 0X4001A000) + WDCR_EBC(PB7AP, 0x02000280) /* No Ready, 4 wait states */ + WDCR_EBC(PB7CR, 0X4001A000) setup_continue: @@ -294,7 +294,7 @@ sdram_init: /* Read PLL feedback divider and calculate clock period of local bus in */ /* granularity of 10 ps. Save clock period in r30 */ /*-------------------------------------------------------------- */ - mfdcr r4, pllmd + mfdcr r4, CPC0_PLLMR addi r9, 0, 25 srw r4, r4, r9 andi. r4, r4, 0x07 @@ -383,8 +383,8 @@ sdram_init: /* Set SDTR1 */ /*----------------------------------------------------------- */ addi r5,0,mem_sdtr1 - mtdcr memcfga,r5 - mtdcr memcfgd,r4 + mtdcr SDRAM0_CFGADDR,r5 + mtdcr SDRAM0_CFGDATA,r4 /*----------------------------------------------------------- */ /* */ @@ -414,8 +414,8 @@ sdram_init: /* Set SDRAM bank 0 register and adjust r6 for next bank */ /*------------------------------------------------------ */ addi r7,0,mem_mb0cf - mtdcr memcfga,r7 - mtdcr memcfgd,r6 + mtdcr SDRAM0_CFGADDR,r7 + mtdcr SDRAM0_CFGDATA,r6 add r6, r6, r15 /* add bank size to base address for next bank */ @@ -425,16 +425,16 @@ sdram_init: bne b1skip addi r7,0,mem_mb1cf - mtdcr memcfga,r7 - mtdcr memcfgd,r6 + mtdcr SDRAM0_CFGADDR,r7 + mtdcr SDRAM0_CFGDATA,r6 add r6, r6, r15 /* add bank size to base address for next bank */ /* Set SDRAM bank 2 register and adjust r6 for next bank */ /*------------------------------------------------------ */ b1skip: addi r7,0,mem_mb2cf - mtdcr memcfga,r7 - mtdcr memcfgd,r6 + mtdcr SDRAM0_CFGADDR,r7 + mtdcr SDRAM0_CFGDATA,r6 add r6, r6, r15 /* add bank size to base address for next bank */ @@ -444,8 +444,8 @@ b1skip: addi r7,0,mem_mb2cf bne b3skip addi r7,0,mem_mb3cf - mtdcr memcfga,r7 - mtdcr memcfgd,r6 + mtdcr SDRAM0_CFGADDR,r7 + mtdcr SDRAM0_CFGDATA,r6 b3skip: /*----------------------------------------------------------- */ @@ -457,8 +457,8 @@ b3skip: bl rtr_2 rtr_1: addis r7, 0, 0x03F8 rtr_2: addi r4,0,mem_rtr - mtdcr memcfga,r4 - mtdcr memcfgd,r7 + mtdcr SDRAM0_CFGADDR,r4 + mtdcr SDRAM0_CFGDATA,r7 /*----------------------------------------------------------- */ /* Delay to ensure 200usec have elapsed since reset. Assume worst */ @@ -477,10 +477,10 @@ rtr_2: addi r4,0,mem_rtr /* read/prefetch. */ /*----------------------------------------------------------- */ addi r4,0,mem_mcopt1 - mtdcr memcfga,r4 + mtdcr SDRAM0_CFGADDR,r4 addis r4,0,0x80C0 /* set DC_EN=1 */ ori r4,r4,0x0000 - mtdcr memcfgd,r4 + mtdcr SDRAM0_CFGDATA,r4 /*----------------------------------------------------------- */ @@ -980,9 +980,9 @@ fc07: /* For CPLD */ /* 0 + 00000 + 010 + 000 + 00 + 01 + 00 + 00 + 000 + 0 + 0 + 1 + 0 + 00000 */ -/* WDCR_EBC(pb5ap, 0x01010040) */ -/*jsa recommendation: WDCR_EBC(pb5ap, 0x00010040) */ -/* WDCR_EBC(pb5cr, 0X10018000) */ +/* WDCR_EBC(PB5AP, 0x01010040) */ +/*jsa recommendation: WDCR_EBC(PB5AP, 0x00010040) */ +/* WDCR_EBC(PB5CR, 0X10018000) */ /* Access parms */ /* 100 3 8 0 0 0 */ /* 0x100 + 001 + 11 + 00 + 0 0000 0000 0000 = 0x10038000 */ @@ -1003,9 +1003,9 @@ fc07: /* Usage: read/write */ /* Width: 32 bit */ -/* Walnut fpga pb7ap */ +/* Walnut fpga PB7AP */ /* 0 1 8 1 5 2 8 0 */ /* 0 + 00000 + 011 + 000 + 00 + 01 + 01 + 01 + 001 + 0 + 1 + 0 + 0 + 00000 */ -/* Walnut fpga pb7cr */ +/* Walnut fpga PB7CR */ /* 0xF0318000 */ /* */ diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c index f6f47197cdf..ae258e1f263 100644 --- a/board/g2000/g2000.c +++ b/board/g2000/g2000.c @@ -58,7 +58,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ #endif return 0; @@ -114,7 +114,7 @@ int checkboard (void) long int init_sdram_static_settings(void) { -#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) +#define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data) /* disable memcontroller so updates work */ mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL ); mtsdram0( mem_rtr , MEM_RTR_INIT_VAL ); @@ -154,15 +154,15 @@ int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong ap, cr; printf("\nEBC registers for PPC405GP:\n"); - mfebc(pb0ap, ap); mfebc(pb0cr, cr); + mfebc(PB0AP, ap); mfebc(PB0CR, cr); printf("0: AP=%08lx CP=%08lx\n", ap, cr); - mfebc(pb1ap, ap); mfebc(pb1cr, cr); + mfebc(PB1AP, ap); mfebc(PB1CR, cr); printf("1: AP=%08lx CP=%08lx\n", ap, cr); - mfebc(pb2ap, ap); mfebc(pb2cr, cr); + mfebc(PB2AP, ap); mfebc(PB2CR, cr); printf("2: AP=%08lx CP=%08lx\n", ap, cr); - mfebc(pb3ap, ap); mfebc(pb3cr, cr); + mfebc(PB3AP, ap); mfebc(PB3CR, cr); printf("3: AP=%08lx CP=%08lx\n", ap, cr); - mfebc(pb4ap, ap); mfebc(pb4cr, cr); + mfebc(PB4AP, ap); mfebc(PB4CR, cr); printf("4: AP=%08lx CP=%08lx\n", ap, cr); printf("\n"); diff --git a/board/gdsys/compactcenter/compactcenter.c b/board/gdsys/compactcenter/compactcenter.c index f448ef93727..8a5ea300d7a 100644 --- a/board/gdsys/compactcenter/compactcenter.c +++ b/board/gdsys/compactcenter/compactcenter.c @@ -215,7 +215,7 @@ int board_early_init_r(void) EBC_BXCR_BS_128MB : EBC_BXCR_BS_64MB; /* Remap the NOR FLASH to 0xcn00.0000 ... 0xcfff.ffff */ - mtebc(pb0cr, CONFIG_SYS_FLASH_BASE_PHYS_L + mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | bxcr_bw | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); diff --git a/board/gdsys/dlvision/dlvision.c b/board/gdsys/dlvision/dlvision.c index 4ec1cdbc3e2..5246bc8c4fb 100644 --- a/board/gdsys/dlvision/dlvision.c +++ b/board/gdsys/dlvision/dlvision.c @@ -48,7 +48,7 @@ int board_early_init_f(void) * EBC Configuration Register: set ready timeout to 512 ebc-clks * -> ca. 15 us */ - mtebc(epcr, 0xa8400000); /* ebc always driven */ + mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ /* * setup io-latches diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c index a661057438e..27c159bec62 100644 --- a/board/gdsys/gdppc440etx/gdppc440etx.c +++ b/board/gdsys/gdppc440etx/gdppc440etx.c @@ -42,8 +42,8 @@ int board_early_init_f(void) /* * Setup the external bus controller/chip selects */ - mfebc(xbcfg, reg); - mtebc(xbcfg, reg | 0x04000000); /* Set ATC */ + mfebc(EBC0_CFG, reg); + mtebc(EBC0_CFG, reg | 0x04000000); /* Set ATC */ /* * Setup the GPIO pins @@ -102,10 +102,10 @@ int board_early_init_f(void) /* * Setup other serial configuration */ - mfsdr(sdr_pci0, reg); - mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ - mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */ - mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */ + mfsdr(SDR0_PCI0, reg); + mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */ + mtsdr(SDR0_PFC0, 0x00003e00); /* Pin function */ + mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins */ return 0; } @@ -117,7 +117,7 @@ int misc_init_r(void) uint sz; /* Re-do sizing to get full correct info */ - mfebc(pb0cr, pbcr); + mfebc(PB0CR, pbcr); if (gd->bd->bi_flashsize > 0x08000000) panic("Max. flash banksize is 128 MB!\n"); @@ -127,7 +127,7 @@ int misc_init_r(void) sz <<= 1; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtebc(pb0cr, pbcr); + mtebc(PB0CR, pbcr); /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; @@ -178,35 +178,35 @@ int pci_pre_init(struct pci_controller *hose) * Set priority for all PLB3 devices to 0. * Set PLB3 arbiter to fair mode. */ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /* * Set priority for all PLB4 devices to 0. */ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4_ACR, addr); /* * Set Nebula PLB4 arbiter to fair mode. */ /* Segment0 */ - addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; - addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; - addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; - addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; - mtdcr(plb0_acr, addr); + addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; + addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; + addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; + addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; + mtdcr(PLB0_ACR, addr); /* Segment1 */ - addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; - addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; - addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; - addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; - mtdcr(plb1_acr, addr); + addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; + addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; + addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; + addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; + mtdcr(PLB1_ACR, addr); /* enable 66 MHz ext. Clock */ out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000); diff --git a/board/gdsys/neo/neo.c b/board/gdsys/neo/neo.c index 817ce17ff16..628ce3dc90b 100644 --- a/board/gdsys/neo/neo.c +++ b/board/gdsys/neo/neo.c @@ -43,7 +43,7 @@ int board_early_init_f(void) * EBC Configuration Register: set ready timeout to 512 ebc-clks * -> ca. 15 us */ - mtebc(epcr, 0xa8400000); /* ebc always driven */ + mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ return 0; } diff --git a/board/jse/init.S b/board/jse/init.S index 7b932b25f0b..92f43f4fc7d 100644 --- a/board/jse/init.S +++ b/board/jse/init.S @@ -52,8 +52,6 @@ #include #include -#define cpc0_cr0 0xB1 - .globl ext_bus_cntlr_init ext_bus_cntlr_init: mflr r4 /* save link register */ @@ -84,16 +82,16 @@ ext_bus_cntlr_init: /* Memory Bank 0 (Flash) initialization */ /*----------------------------------------------------------------- */ - addi r4,0,pb0ap - mtdcr ebccfga,r4 + addi r4,0,PB1AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x9B01 ori r4,r4,0x5480 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb0cr - mtdcr ebccfga,r4 + addi r4,0,PB0CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */ ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 blr diff --git a/board/jse/jse.c b/board/jse/jse.c index 6a6b9dd74b3..6dc9a01af8f 100644 --- a/board/jse/jse.c +++ b/board/jse/jse.c @@ -62,12 +62,12 @@ int board_early_init_f (void) /* EBC0_B1AP: BME=1, TWT=2, CSN=0, OEN=1, WBN=0, WBF=1, TH=0, RE=0, SOR=0, BEM=0, PEN=0 */ - mtdcr (ebccfga, pb1ap); - mtdcr (ebccfgd, 0x01011000); + mtdcr (EBC0_CFGADDR, PB1AP); + mtdcr (EBC0_CFGDATA, 0x01011000); /* EBC0_B1CR: BAS=x, BS=0(1MB), BU=3(R/W), BW=0(8bits) */ - mtdcr (ebccfga, pb1cr); - mtdcr (ebccfgd, CONFIG_SYS_SYSTEMACE_BASE | 0x00018000); + mtdcr (EBC0_CFGADDR, PB1CR); + mtdcr (EBC0_CFGDATA, CONFIG_SYS_SYSTEMACE_BASE | 0x00018000); /* Enable the /PerWE output as /PerWE, instead of /PCIINT. */ /* CPC0_CR1 |= PCIPW */ diff --git a/board/jse/sdram.c b/board/jse/sdram.c index a1f526de6ff..bb6f85eee51 100644 --- a/board/jse/sdram.c +++ b/board/jse/sdram.c @@ -35,60 +35,60 @@ phys_size_t initdram (int board_type) /* Configure the SDRAMS */ /* disable memory controller */ - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, 0x00000000); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGDATA, 0x00000000); udelay (500); /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */ - mtdcr (memcfga, mem_besra); - mtdcr (memcfgd, 0xffffffff); + mtdcr (SDRAM0_CFGADDR, mem_besra); + mtdcr (SDRAM0_CFGDATA, 0xffffffff); /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */ - mtdcr (memcfga, mem_besrb); - mtdcr (memcfgd, 0xffffffff); + mtdcr (SDRAM0_CFGADDR, mem_besrb); + mtdcr (SDRAM0_CFGDATA, 0xffffffff); /* Clear SDRAM0_ECCCFG (disable ECC) */ - mtdcr (memcfga, mem_ecccf); - mtdcr (memcfgd, 0x00000000); + mtdcr (SDRAM0_CFGADDR, mem_ecccf); + mtdcr (SDRAM0_CFGDATA, 0x00000000); /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */ - mtdcr (memcfga, mem_eccerr); - mtdcr (memcfgd, 0xffffffff); + mtdcr (SDRAM0_CFGADDR, mem_eccerr); + mtdcr (SDRAM0_CFGDATA, 0xffffffff); /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */ - mtdcr (memcfga, mem_sdtr1); - mtdcr (memcfgd, 0x010a4016); + mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGDATA, 0x010a4016); /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */ - mtdcr (memcfga, mem_mb0cf); - mtdcr (memcfgd, 0x00084001); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGDATA, 0x00084001); /* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */ - mtdcr (memcfga, mem_mb1cf); - mtdcr (memcfgd, 0x04084001); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGDATA, 0x04084001); /* Memory Bank 2 Config == BE=0 */ - mtdcr (memcfga, mem_mb2cf); - mtdcr (memcfgd, 0x00000000); + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGDATA, 0x00000000); /* Memory Bank 3 Config == BE=0 */ - mtdcr (memcfga, mem_mb3cf); - mtdcr (memcfgd, 0x00000000); + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGDATA, 0x00000000); /* refresh timer = 0x400 */ - mtdcr (memcfga, mem_rtr); - mtdcr (memcfgd, 0x04000000); + mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGDATA, 0x04000000); /* Power management idle timer set to the default. */ - mtdcr (memcfga, mem_pmit); - mtdcr (memcfgd, 0x07c00000); + mtdcr (SDRAM0_CFGADDR, mem_pmit); + mtdcr (SDRAM0_CFGDATA, 0x07c00000); udelay (500); /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */ - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, 0x80e00000); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGDATA, 0x80e00000); return SDRAM_LEN; } @@ -108,28 +108,28 @@ int testdram (void) #ifdef DEBUG printf ("SDRAM Controller Registers --\n"); - mtdcr (memcfga, mem_mcopt1); - val = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_CFG : 0x%08x\n", val); - mtdcr (memcfga, 0x24); - val = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, 0x24); + val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_STATUS: 0x%08x\n", val); - mtdcr (memcfga, mem_mb0cf); - val = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_B0CR : 0x%08x\n", val); - mtdcr (memcfga, mem_mb1cf); - val = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_B1CR : 0x%08x\n", val); - mtdcr (memcfga, mem_sdtr1); - val = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_TR : 0x%08x\n", val); - mtdcr (memcfga, mem_rtr); - val = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_rtr); + val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_RTR : 0x%08x\n", val); #endif @@ -137,8 +137,8 @@ int testdram (void) bit. Really, there should already have been plenty of time, given it was started long ago. But, best to check. */ for (idx = 0; idx < 1000000; idx += 1) { - mtdcr (memcfga, 0x24); - val = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, 0x24); + val = mfdcr (SDRAM0_CFGDATA); if (val & 0x80000000) break; } diff --git a/board/korat/korat.c b/board/korat/korat.c index 8328ba326db..3d4d149f6c6 100644 --- a/board/korat/korat.c +++ b/board/korat/korat.c @@ -81,8 +81,8 @@ int board_early_init_f(void) korat_buzzer(0); #endif - mtdcr(ebccfga, xbcfg); - mtdcr(ebccfgd, 0xb8400000); + mtdcr(EBC0_CFGADDR, EBC0_CFG); + mtdcr(EBC0_CFGDATA, 0xb8400000); /* * Setup the interrupt controller polarities, triggers, etc. @@ -157,8 +157,8 @@ int board_early_init_f(void) mtsdr(SDR0_PFC1, sdr0_pfc1); /* PCI arbiter enabled */ - mfsdr(sdr_pci0, reg); - mtsdr(sdr_pci0, 0x80000000 | reg); + mfsdr(SDR0_PCI0, reg); + mtsdr(SDR0_PCI0, 0x80000000 | reg); return 0; } @@ -359,12 +359,12 @@ int misc_init_r(void) gd->bd->bi_flashstart = CONFIG_SYS_FLASH1_TOP - flash1_size; gd->bd->bi_flashoffset = 0; - mtdcr(ebccfga, pb1cr); - pbcr = mfdcr(ebccfgd); + mtdcr(EBC0_CFGADDR, PB1CR); + pbcr = mfdcr(EBC0_CFGDATA); size_val = ffs(flash1_size) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(ebccfga, pb1cr); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGADDR, PB1CR); + mtdcr(EBC0_CFGDATA, pbcr); /* * Re-check to get correct base address @@ -378,12 +378,12 @@ int misc_init_r(void) gd->bd->bi_flashoffset = CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - CONFIG_SYS_FLASH1_ADDR; - mtdcr(ebccfga, pb1cr); - pbcr = mfdcr(ebccfgd); + mtdcr(EBC0_CFGADDR, PB1CR); + pbcr = mfdcr(EBC0_CFGDATA); size_val = ffs(gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(ebccfga, pb1cr); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGADDR, PB1CR); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ #if defined(CONFIG_KORAT_PERMANENT) @@ -552,8 +552,8 @@ int misc_init_r(void) * This fix will make the MAL burst disabling patch for the Linux * EMAC driver obsolete. */ - reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; - mtdcr(plb4_acr, reg); + reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP; + mtdcr(PLB4_ACR, reg); set_serial_number(); set_mac_addresses(); @@ -620,35 +620,35 @@ int pci_pre_init(struct pci_controller *hose) * Set priority for all PLB3 devices to 0. * Set PLB3 arbiter to fair mode. */ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /* * Set priority for all PLB4 devices to 0. */ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4_ACR, addr); /* * Set Nebula PLB4 arbiter to fair mode. */ /* Segment0 */ - addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; - addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; - addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; - addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; - mtdcr(plb0_acr, addr); + addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; + addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; + addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; + addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; + mtdcr(PLB0_ACR, addr); /* Segment1 */ - addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; - addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; - addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; - addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; - mtdcr(plb1_acr, addr); + addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; + addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; + addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; + addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; + mtdcr(PLB1_ACR, addr); #if defined(CONFIG_PCI_PNP) hose->fixup_irq = korat_pci_fixup_irq; diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 9b76e7663cc..a9c2a6f441a 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -38,8 +38,8 @@ int board_early_init_f(void) u32 reg; /* PLB Write pipelining disabled. Denali Core workaround */ - mtdcr(plb0_acr, 0xDE000000); - mtdcr(plb1_acr, 0xDE000000); + mtdcr(PLB0_ACR, 0xDE000000); + mtdcr(PLB1_ACR, 0xDE000000); /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. @@ -90,9 +90,9 @@ int board_early_init_f(void) /* PCI arbiter disabled */ /* PCI Host Configuration disbaled */ - mfsdr(sdr_pci0, reg); + mfsdr(SDR0_PCI0, reg); reg = 0; - mtsdr(sdr_pci0, 0x00000000 | reg); + mtsdr(SDR0_PCI0, 0x00000000 | reg); gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1); @@ -157,7 +157,7 @@ int misc_init_r(void) gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; - mfebc(pb0cr, pbcr); + mfebc(PB0CR, pbcr); switch (gd->bd->bi_flashsize) { case 1 << 20: size_val = 0; @@ -185,7 +185,7 @@ int misc_init_r(void) break; } pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtebc(pb0cr, pbcr); + mtebc(PB0CR, pbcr); /* * Re-check to get correct base address @@ -249,8 +249,8 @@ int misc_init_r(void) * This fix will make the MAL burst disabling patch for the Linux * EMAC driver obsolete. */ - reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; - mtdcr(plb4_acr, reg); + reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP; + mtdcr(PLB4_ACR, reg); /* * Init matrix keyboard @@ -296,35 +296,35 @@ int pci_pre_init(struct pci_controller *hose) | Set priority for all PLB3 devices to 0. | Set PLB3 arbiter to fair mode. +-------------------------------------------------------------------------*/ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /*-------------------------------------------------------------------------+ | Set priority for all PLB4 devices to 0. +-------------------------------------------------------------------------*/ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4_ACR, addr); /*-------------------------------------------------------------------------+ | Set Nebula PLB4 arbiter to fair mode. +-------------------------------------------------------------------------*/ /* Segment0 */ - addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; - addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; - addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; - addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; - mtdcr(plb0_acr, addr); + addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; + addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; + addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; + addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; + mtdcr(PLB0_ACR, addr); /* Segment1 */ - addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; - addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; - addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; - addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; - mtdcr(plb1_acr, addr); + addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; + addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; + addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; + addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; + mtdcr(PLB1_ACR, addr); return 1; } diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c index 355608cd3bd..682f0e76dd8 100644 --- a/board/mpl/common/flash.c +++ b/board/mpl/common/flash.c @@ -97,7 +97,7 @@ int get_boot_mode(void) { unsigned long pbcr; int res = 0; - pbcr = mfdcr (strap); + pbcr = mfdcr (CPC0_PSR); if ((pbcr & PSR_ROM_WIDTH_MASK) == 0) /* boot via MPS or MPS mapping */ res = BOOT_MPS; @@ -123,29 +123,29 @@ void setup_cs_reloc(void) /* first findout on which cs the flash is */ if(mode & BOOT_MPS) { /* map flash high on CS1 and MPS on CS0 */ - mtdcr (ebccfga, pb0ap); - mtdcr (ebccfgd, MPS_AP); - mtdcr (ebccfga, pb0cr); - mtdcr (ebccfgd, MPS_CR); + mtdcr (EBC0_CFGADDR, PB0AP); + mtdcr (EBC0_CFGDATA, MPS_AP); + mtdcr (EBC0_CFGADDR, PB0CR); + mtdcr (EBC0_CFGDATA, MPS_CR); /* we use the default values (max values) for the flash * because its real size is not yet known */ - mtdcr (ebccfga, pb1ap); - mtdcr (ebccfgd, FLASH_AP); - mtdcr (ebccfga, pb1cr); - mtdcr (ebccfgd, FLASH_CR_B); + mtdcr (EBC0_CFGADDR, PB1AP); + mtdcr (EBC0_CFGDATA, FLASH_AP); + mtdcr (EBC0_CFGADDR, PB1CR); + mtdcr (EBC0_CFGDATA, FLASH_CR_B); } else { /* map flash high on CS0 and MPS on CS1 */ - mtdcr (ebccfga, pb1ap); - mtdcr (ebccfgd, MPS_AP); - mtdcr (ebccfga, pb1cr); - mtdcr (ebccfgd, MPS_CR); + mtdcr (EBC0_CFGADDR, PB1AP); + mtdcr (EBC0_CFGDATA, MPS_AP); + mtdcr (EBC0_CFGADDR, PB1CR); + mtdcr (EBC0_CFGDATA, MPS_CR); /* we use the default values (max values) for the flash * because its real size is not yet known */ - mtdcr (ebccfga, pb0ap); - mtdcr (ebccfgd, FLASH_AP); - mtdcr (ebccfga, pb0cr); - mtdcr (ebccfgd, FLASH_CR_B); + mtdcr (EBC0_CFGADDR, PB0AP); + mtdcr (EBC0_CFGDATA, FLASH_AP); + mtdcr (EBC0_CFGADDR, PB0CR); + mtdcr (EBC0_CFGDATA, FLASH_CR_B); } } @@ -217,34 +217,34 @@ unsigned long flash_init (void) } if(mode & BOOT_MPS) { /* flash is on CS1 */ - mtdcr(ebccfga, pb1cr); - flashcr = mfdcr (ebccfgd); + mtdcr(EBC0_CFGADDR, PB1CR); + flashcr = mfdcr (EBC0_CFGDATA); /* we map the flash high in every case */ flashcr&=0x0001FFFF; /* mask out address bits */ flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */ flashcr|= (i << 17); /* size addr */ - mtdcr(ebccfga, pb1cr); - mtdcr(ebccfgd, flashcr); + mtdcr(EBC0_CFGADDR, PB1CR); + mtdcr(EBC0_CFGDATA, flashcr); } else { /* flash is on CS0 */ - mtdcr(ebccfga, pb0cr); - flashcr = mfdcr (ebccfgd); + mtdcr(EBC0_CFGADDR, PB0CR); + flashcr = mfdcr (EBC0_CFGDATA); /* we map the flash high in every case */ flashcr&=0x0001FFFF; /* mask out address bits */ flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */ flashcr|= (i << 17); /* size addr */ - mtdcr(ebccfga, pb0cr); - mtdcr(ebccfgd, flashcr); + mtdcr(EBC0_CFGADDR, PB0CR); + mtdcr(EBC0_CFGDATA, flashcr); } #if 0 /* enable this (PIP405/MIP405 only) if you want to test if the relocation has be done ok. This will disable both Chipselects */ - mtdcr (ebccfga, pb0cr); - mtdcr (ebccfgd, 0L); - mtdcr (ebccfga, pb1cr); - mtdcr (ebccfgd, 0L); + mtdcr (EBC0_CFGADDR, PB0CR); + mtdcr (EBC0_CFGDATA, 0L); + mtdcr (EBC0_CFGADDR, PB1CR); + mtdcr (EBC0_CFGDATA, 0L); printf("CS0 & CS1 switched off for test\n"); #endif /* patch version_string */ diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S index 19d92205112..f3d94c3fc1b 100644 --- a/board/mpl/mip405/init.S +++ b/board/mpl/mip405/init.S @@ -55,7 +55,7 @@ .globl ext_bus_cntlr_init ext_bus_cntlr_init: mflr r4 /* save link register */ - mfdcr r3,strap /* get strapping reg */ + mfdcr r3,CPC0_PSR /* get strapping reg */ andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */ bnelr /* jump back if PCI boot */ @@ -84,9 +84,9 @@ ext_bus_cntlr_init: /*----------------------------------------------------------------------- * decide boot up mode *----------------------------------------------------------------------- */ - addi r4,0,pb0cr - mtdcr ebccfga,r4 - mfdcr r4,ebccfgd + addi r4,0,PB0CR + mtdcr EBC0_CFGADDR,r4 + mfdcr r4,EBC0_CFGDATA andi. r0, r4, 0x2000 /* mask out irrelevant bits */ beq 0f /* jump if 8 bit bus width */ @@ -96,18 +96,18 @@ ext_bus_cntlr_init: * Memory Bank 0 (16 Bit Flash) initialization *---------------------------------------------------------------------- */ - addi r4,0,pb0ap - mtdcr ebccfga,r4 + addi r4,0,PB1AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,(FLASH_AP_B)@h ori r4,r4,(FLASH_AP_B)@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb0cr - mtdcr ebccfga,r4 + addi r4,0,PB0CR + mtdcr EBC0_CFGADDR,r4 /* BS=0x010(4MB),BU=0x3(R/W), */ addis r4,0,(FLASH_CR_B)@h ori r4,r4,(FLASH_CR_B)@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 b 1f 0: @@ -117,66 +117,66 @@ ext_bus_cntlr_init: * Memory Bank 0 Multi Purpose Socket initialization *----------------------------------------------------------------------- */ /* 0x7F8FFE80 slowest boot */ - addi r4,0,pb0ap - mtdcr ebccfga,r4 + addi r4,0,PB1AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,(MPS_AP_B)@h ori r4,r4,(MPS_AP_B)@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb0cr - mtdcr ebccfga,r4 + addi r4,0,PB0CR + mtdcr EBC0_CFGADDR,r4 /* BS=0x010(4MB),BU=0x3(R/W), */ addis r4,0,(MPS_CR_B)@h ori r4,r4,(MPS_CR_B)@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 1: /*----------------------------------------------------------------------- * Memory Bank 2-3-4-5-6 (not used) initialization *-----------------------------------------------------------------------*/ - addi r4,0,pb1cr - mtdcr ebccfga,r4 + addi r4,0,PB1CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb2cr - mtdcr ebccfga,r4 + addi r4,0,PB2CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb3cr - mtdcr ebccfga,r4 + addi r4,0,PB3CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb4cr - mtdcr ebccfga,r4 + addi r4,0,PB4CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb5cr - mtdcr ebccfga,r4 + addi r4,0,PB5CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb6cr - mtdcr ebccfga,r4 + addi r4,0,PB6CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb7cr - mtdcr ebccfga,r4 + addi r4,0,PB7CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 nop /* pass2 DCR errata #8 */ blr diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c index 1738f543885..d8279e81c98 100644 --- a/board/mpl/mip405/mip405.c +++ b/board/mpl/mip405/mip405.c @@ -256,16 +256,16 @@ int init_sdram (void) gd->baudrate = 9600; serial_init (); /* set up the pld */ - mtdcr (ebccfga, pb7ap); - mtdcr (ebccfgd, PLD_AP); - mtdcr (ebccfga, pb7cr); - mtdcr (ebccfgd, PLD_CR); + mtdcr (EBC0_CFGADDR, PB7AP); + mtdcr (EBC0_CFGDATA, PLD_AP); + mtdcr (EBC0_CFGADDR, PB7CR); + mtdcr (EBC0_CFGDATA, PLD_CR); /* THIS IS OBSOLETE */ /* set up the board rev reg*/ - mtdcr (ebccfga, pb5ap); - mtdcr (ebccfgd, BOARD_AP); - mtdcr (ebccfga, pb5cr); - mtdcr (ebccfgd, BOARD_CR); + mtdcr (EBC0_CFGADDR, PB5AP); + mtdcr (EBC0_CFGDATA, BOARD_AP); + mtdcr (EBC0_CFGADDR, PB5CR); + mtdcr (EBC0_CFGDATA, BOARD_CR); #ifdef SDRAM_DEBUG /* get all informations from PLD */ serial_puts ("\nPLD Part 0x"); @@ -289,30 +289,30 @@ int init_sdram (void) SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n"); #endif /* set-up the chipselect machine */ - mtdcr (ebccfga, pb0cr); /* get cs0 config reg */ - tmp = mfdcr (ebccfgd); + mtdcr (EBC0_CFGADDR, PB0CR); /* get cs0 config reg */ + tmp = mfdcr (EBC0_CFGDATA); if ((tmp & 0x00002000) == 0) { /* MPS Boot, set up the flash */ - mtdcr (ebccfga, pb1ap); - mtdcr (ebccfgd, FLASH_AP); - mtdcr (ebccfga, pb1cr); - mtdcr (ebccfgd, FLASH_CR); + mtdcr (EBC0_CFGADDR, PB1AP); + mtdcr (EBC0_CFGDATA, FLASH_AP); + mtdcr (EBC0_CFGADDR, PB1CR); + mtdcr (EBC0_CFGDATA, FLASH_CR); } else { /* Flash boot, set up the MPS */ - mtdcr (ebccfga, pb1ap); - mtdcr (ebccfgd, MPS_AP); - mtdcr (ebccfga, pb1cr); - mtdcr (ebccfgd, MPS_CR); + mtdcr (EBC0_CFGADDR, PB1AP); + mtdcr (EBC0_CFGDATA, MPS_AP); + mtdcr (EBC0_CFGADDR, PB1CR); + mtdcr (EBC0_CFGDATA, MPS_CR); } /* set up UART0 (CS2) and UART1 (CS3) */ - mtdcr (ebccfga, pb2ap); - mtdcr (ebccfgd, UART0_AP); - mtdcr (ebccfga, pb2cr); - mtdcr (ebccfgd, UART0_CR); - mtdcr (ebccfga, pb3ap); - mtdcr (ebccfgd, UART1_AP); - mtdcr (ebccfga, pb3cr); - mtdcr (ebccfgd, UART1_CR); + mtdcr (EBC0_CFGADDR, PB2AP); + mtdcr (EBC0_CFGDATA, UART0_AP); + mtdcr (EBC0_CFGADDR, PB2CR); + mtdcr (EBC0_CFGDATA, UART0_CR); + mtdcr (EBC0_CFGADDR, PB3AP); + mtdcr (EBC0_CFGDATA, UART1_AP); + mtdcr (EBC0_CFGADDR, PB3CR); + mtdcr (EBC0_CFGDATA, UART1_CR); bc = in8 (PLD_BOARD_CFG_REG); #ifdef SDRAM_DEBUG serial_puts ("\nstart SDRAM Setup\n"); @@ -348,8 +348,8 @@ int init_sdram (void) /* trc_clocks is sum of trp_clocks + tras_clocks */ trc_clocks = trp_clocks + tras_clocks; /* get SDRAM timing register */ - mtdcr (memcfga, mem_sdtr1); - sdram_tim = mfdcr (memcfgd) & ~0x018FC01F; + mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F; /* insert CASL value */ sdram_tim |= ((unsigned long) (cal_val)) << 23; /* insert PTA value */ @@ -369,8 +369,8 @@ int init_sdram (void) /* insert SZ value; */ tmp |= ((unsigned long) sdram_table[i].sz << 17); /* get SDRAM bank 0 register */ - mtdcr (memcfga, mem_mb0cf); - sdram_bank = mfdcr (memcfgd) & ~0xFFCEE001; + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; sdram_bank |= (baseaddr | tmp | 0x01); #ifdef SDRAM_DEBUG @@ -380,8 +380,8 @@ int init_sdram (void) #endif /* write SDRAM timing register */ - mtdcr (memcfga, mem_sdtr1); - mtdcr (memcfgd, sdram_tim); + mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGDATA, sdram_tim); #ifdef SDRAM_DEBUG serial_puts ("mb0cf: "); @@ -390,23 +390,23 @@ int init_sdram (void) #endif /* write SDRAM bank 0 register */ - mtdcr (memcfga, mem_mb0cf); - mtdcr (memcfgd, sdram_bank); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGDATA, sdram_bank); if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */ /* get SDRAM refresh interval register */ - mtdcr (memcfga, mem_rtr); - tmp = mfdcr (memcfgd) & ~0x3FF80000; + mtdcr (SDRAM0_CFGADDR, mem_rtr); + tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; tmp |= 0x07F00000; } else { /* get SDRAM refresh interval register */ - mtdcr (memcfga, mem_rtr); - tmp = mfdcr (memcfgd) & ~0x3FF80000; + mtdcr (SDRAM0_CFGADDR, mem_rtr); + tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; tmp |= 0x05F00000; } /* write SDRAM refresh interval register */ - mtdcr (memcfga, mem_rtr); - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGDATA, tmp); /* enable ECC if used */ #if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI) if (sdram_table[i].ecc) { @@ -415,19 +415,19 @@ int init_sdram (void) #ifdef SDRAM_DEBUG serial_puts ("disable ECC.. "); #endif - mtdcr (memcfga, mem_ecccf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_ecccf); + tmp = mfdcr (SDRAM0_CFGDATA); tmp &= 0xff0fffff; /* disable all banks */ - mtdcr (memcfga, mem_ecccf); + mtdcr (SDRAM0_CFGADDR, mem_ecccf); /* set up SDRAM Controller with ECC enabled */ #ifdef SDRAM_DEBUG serial_puts ("setup SDRAM Controller.. "); #endif - mtdcr (memcfgd, tmp); - mtdcr (memcfga, mem_mcopt1); - tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000; - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGDATA, tmp); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000; + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGDATA, tmp); udelay (600); #ifdef SDRAM_DEBUG serial_puts ("fill the memory..\n"); @@ -447,19 +447,19 @@ int init_sdram (void) serial_puts ("enable ECC\n"); #endif udelay (400); - mtdcr (memcfga, mem_ecccf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_ecccf); + tmp = mfdcr (SDRAM0_CFGDATA); tmp |= 0x00800000; /* enable bank 0 */ - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGDATA, tmp); udelay (400); } else #endif { /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ - mtdcr (memcfga, mem_mcopt1); - tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80C00000; - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000; + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGDATA, tmp); udelay (400); } serial_puts ("\n"); @@ -631,14 +631,14 @@ phys_size_t initdram (int board_type) ds = 0; /* since the DRAM controller is allready set up, calculate the size with the bank registers */ - mtdcr (memcfga, mem_mb0cf); - bank_reg[0] = mfdcr (memcfgd); - mtdcr (memcfga, mem_mb1cf); - bank_reg[1] = mfdcr (memcfgd); - mtdcr (memcfga, mem_mb2cf); - bank_reg[2] = mfdcr (memcfgd); - mtdcr (memcfga, mem_mb3cf); - bank_reg[3] = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + bank_reg[0] = mfdcr (SDRAM0_CFGDATA); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + bank_reg[1] = mfdcr (SDRAM0_CFGDATA); + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + bank_reg[2] = mfdcr (SDRAM0_CFGDATA); + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + bank_reg[3] = mfdcr (SDRAM0_CFGDATA); TotalSize = 0; for (i = 0; i < 4; i++) { if ((bank_reg[i] & 0x1) == 0x1) { @@ -648,8 +648,8 @@ phys_size_t initdram (int board_type) } else ds = 1; } - mtdcr (memcfga, mem_ecccf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_ecccf); + tmp = mfdcr (SDRAM0_CFGDATA); if (!tmp) printf ("No "); @@ -687,7 +687,7 @@ int misc_init_r (void) rtc_get (&tm); start=get_timer(0); /* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ - if (mfdcr(strap) & PSR_ROM_LOC) + if (mfdcr(CPC0_PSR) & PSR_ROM_LOC) mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80)); return (0); diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S index 61f37d74f2a..18e8b09dde3 100644 --- a/board/mpl/pip405/init.S +++ b/board/mpl/pip405/init.S @@ -54,7 +54,7 @@ .globl ext_bus_cntlr_init ext_bus_cntlr_init: mflr r4 /* save link register */ - mfdcr r3,strap /* get strapping reg */ + mfdcr r3,CPC0_PSR /* get strapping reg */ andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */ bnelr /* jump back if PCI boot */ @@ -83,9 +83,9 @@ /*----------------------------------------------------------------------- * decide boot up mode *----------------------------------------------------------------------- */ - addi r4,0,pb0cr - mtdcr ebccfga,r4 - mfdcr r4,ebccfgd + addi r4,0,PB0CR + mtdcr EBC0_CFGADDR,r4 + mfdcr r4,EBC0_CFGDATA andi. r0, r4, 0x2000 /* mask out irrelevant bits */ beq 0f /* jump if 8 bit bus width */ @@ -95,18 +95,18 @@ * Memory Bank 0 (16 Bit Flash) initialization *---------------------------------------------------------------------- */ - addi r4,0,pb0ap - mtdcr ebccfga,r4 + addi r4,0,PB1AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,(FLASH_AP_B)@h ori r4,r4,(FLASH_AP_B)@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb0cr - mtdcr ebccfga,r4 + addi r4,0,PB0CR + mtdcr EBC0_CFGADDR,r4 /* BS=0x010(4MB),BU=0x3(R/W), */ addis r4,0,(FLASH_CR_B)@h ori r4,r4,(FLASH_CR_B)@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 b 1f 0: @@ -115,65 +115,65 @@ * Memory Bank 0 Multi Purpose Socket initialization *----------------------------------------------------------------------- */ /* 0x7F8FFE80 slowest boot */ - addi r4,0,pb0ap - mtdcr ebccfga,r4 + addi r4,0,PB1AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,(MPS_AP_B)@h ori r4,r4,(MPS_AP_B)@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb0cr - mtdcr ebccfga,r4 + addi r4,0,PB0CR + mtdcr EBC0_CFGADDR,r4 /* BS=0x010(4MB),BU=0x3(R/W), */ addis r4,0,(MPS_CR_B)@h ori r4,r4,(MPS_CR_B)@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 1: /*----------------------------------------------------------------------- * Memory Bank 2-3-4-5-6 (not used) initialization *-----------------------------------------------------------------------*/ - addi r4,0,pb1cr - mtdcr ebccfga,r4 + addi r4,0,PB1CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb2cr - mtdcr ebccfga,r4 + addi r4,0,PB2CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb3cr - mtdcr ebccfga,r4 + addi r4,0,PB3CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb4cr - mtdcr ebccfga,r4 + addi r4,0,PB4CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb5cr - mtdcr ebccfga,r4 + addi r4,0,PB5CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb6cr - mtdcr ebccfga,r4 + addi r4,0,PB6CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb7cr - mtdcr ebccfga,r4 + addi r4,0,PB7CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 nop /* pass2 DCR errata #8 */ blr diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c index 677437d09ea..e00d1d08f5c 100644 --- a/board/mpl/pip405/pip405.c +++ b/board/mpl/pip405/pip405.c @@ -193,10 +193,10 @@ int board_early_init_f (void) unsigned char cal_index, cal_val, spd_version, spd_chksum; unsigned char buf[8]; /* set up the config port */ - mtdcr (ebccfga, pb7ap); - mtdcr (ebccfgd, CONFIG_PORT_AP); - mtdcr (ebccfga, pb7cr); - mtdcr (ebccfgd, CONFIG_PORT_CR); + mtdcr (EBC0_CFGADDR, PB7AP); + mtdcr (EBC0_CFGDATA, CONFIG_PORT_AP); + mtdcr (EBC0_CFGADDR, PB7CR); + mtdcr (EBC0_CFGDATA, CONFIG_PORT_CR); memclk = get_bus_freq (tmemclk); tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ @@ -361,8 +361,8 @@ int board_early_init_f (void) SDRAM_err ("unsupported SDRAM"); /* get SDRAM timing register */ - mtdcr (memcfga, mem_sdtr1); - tmp = mfdcr (memcfgd) & ~0x018FC01F; + mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F; /* insert CASL value */ /* tmp |= ((unsigned long)cal_val) << 23; */ tmp |= ((unsigned long) cal_val) << 23; @@ -385,8 +385,8 @@ int board_early_init_f (void) #endif /* write SDRAM timing register */ - mtdcr (memcfga, mem_sdtr1); - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGDATA, tmp); baseaddr = CONFIG_SYS_SDRAM_BASE; bank_size = (((unsigned long) density) << 22) / 2; /* insert AM value */ @@ -418,8 +418,8 @@ int board_early_init_f (void) SDRAM_err ("unsupported SDRAM"); } /* endswitch */ /* get SDRAM bank 0 register */ - mtdcr (memcfga, mem_mb0cf); - bank = mfdcr (memcfgd) & ~0xFFCEE001; + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; bank |= (baseaddr | tmp | 0x01); #ifdef SDRAM_DEBUG serial_puts ("bank0: baseaddr: "); @@ -434,12 +434,12 @@ int board_early_init_f (void) sdram_size += bank_size; /* write SDRAM bank 0 register */ - mtdcr (memcfga, mem_mb0cf); - mtdcr (memcfgd, bank); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGDATA, bank); /* get SDRAM bank 1 register */ - mtdcr (memcfga, mem_mb1cf); - bank = mfdcr (memcfgd) & ~0xFFCEE001; + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; sdram_size = 0; #ifdef SDRAM_DEBUG @@ -459,12 +459,12 @@ int board_early_init_f (void) serial_puts ("\n"); #endif /* write SDRAM bank 1 register */ - mtdcr (memcfga, mem_mb1cf); - mtdcr (memcfgd, bank); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGDATA, bank); /* get SDRAM bank 2 register */ - mtdcr (memcfga, mem_mb2cf); - bank = mfdcr (memcfgd) & ~0xFFCEE001; + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; bank |= (baseaddr | tmp | 0x01); @@ -482,12 +482,12 @@ int board_early_init_f (void) sdram_size += bank_size; /* write SDRAM bank 2 register */ - mtdcr (memcfga, mem_mb2cf); - mtdcr (memcfgd, bank); + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGDATA, bank); /* get SDRAM bank 3 register */ - mtdcr (memcfga, mem_mb3cf); - bank = mfdcr (memcfgd) & ~0xFFCEE001; + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; #ifdef SDRAM_DEBUG serial_puts ("bank3: baseaddr: "); @@ -509,13 +509,13 @@ int board_early_init_f (void) #endif /* write SDRAM bank 3 register */ - mtdcr (memcfga, mem_mb3cf); - mtdcr (memcfgd, bank); + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGDATA, bank); /* get SDRAM refresh interval register */ - mtdcr (memcfga, mem_rtr); - tmp = mfdcr (memcfgd) & ~0x3FF80000; + mtdcr (SDRAM0_CFGADDR, mem_rtr); + tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; if (tmemclk < NSto10PS (16)) tmp |= 0x05F00000; @@ -523,14 +523,14 @@ int board_early_init_f (void) tmp |= 0x03F80000; /* write SDRAM refresh interval register */ - mtdcr (memcfga, mem_rtr); - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGDATA, tmp); /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ - mtdcr (memcfga, mem_mcopt1); - tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80E00000; - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000; + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGDATA, tmp); /*-------------------------------------------------------------------------+ @@ -619,14 +619,14 @@ phys_size_t initdram (int board_type) /* since the DRAM controller is allready set up, * calculate the size with the bank registers */ - mtdcr (memcfga, mem_mb0cf); - bank_reg[0] = mfdcr (memcfgd); - mtdcr (memcfga, mem_mb1cf); - bank_reg[1] = mfdcr (memcfgd); - mtdcr (memcfga, mem_mb2cf); - bank_reg[2] = mfdcr (memcfgd); - mtdcr (memcfga, mem_mb3cf); - bank_reg[3] = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + bank_reg[0] = mfdcr (SDRAM0_CFGDATA); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + bank_reg[1] = mfdcr (SDRAM0_CFGDATA); + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + bank_reg[2] = mfdcr (SDRAM0_CFGDATA); + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + bank_reg[3] = mfdcr (SDRAM0_CFGDATA); TotalSize = 0; for (i = 0; i < 4; i++) { if ((bank_reg[i] & 0x1) == 0x1) { @@ -668,7 +668,7 @@ int misc_init_r (void) gd->bd->bi_flashoffset=0; /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ - if (mfdcr(strap) & PSR_ROM_LOC) + if (mfdcr(CPC0_PSR) & PSR_ROM_LOC) mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80)); return (0); diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c index aa8a0975cf0..40bec8edcc5 100644 --- a/board/netstal/hcu4/hcu4.c +++ b/board/netstal/hcu4/hcu4.c @@ -92,7 +92,7 @@ int checkboard (void) u16 index = boardVersReg & 0x0f; /* Cannot be done in board_early_init */ - mtdcr(cntrl0, CPC0_CR0_VALUE); + mtdcr(CPC0_CR0, CPC0_CR0_VALUE); /* Force /RTS to active. The board it not wired quite * correctly to use cts/rtc flow control, so just force the diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index 5eb33d37fac..836c0346da3 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -94,8 +94,8 @@ int board_early_init_f(void) } mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ #endif - mtdcr(ebccfga, xbcfg); - mtdcr(ebccfgd, 0xb8400000); + mtdcr(EBC0_CFGADDR, EBC0_CFG); + mtdcr(EBC0_CFGDATA, 0xb8400000); /* * Setup the GPIO pins @@ -152,8 +152,8 @@ int board_early_init_f(void) mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(uic2sr, 0xffffffff); /* clear all */ - mtsdr(sdr_pfc0, 0x00003E00); /* Pin function: */ - mtsdr(sdr_pfc1, 0x00848000); /* Pin function: UART0 has 4 pins */ + mtsdr(SDR0_PFC0, 0x00003E00); /* Pin function: */ + mtsdr(SDR0_PFC1, 0x00848000); /* Pin function: UART0 has 4 pins */ /* setup BOOT FLASH */ mtsdr(SDR0_CUST0, 0xC0082350); @@ -324,7 +324,7 @@ int board_with_pci(void) { u32 reg; - mfsdr(sdr_pci0, reg); + mfsdr(SDR0_PCI0, reg); return (reg & SDR0_XCR_PAE_MASK); } @@ -350,28 +350,28 @@ int pci_pre_init(struct pci_controller *hose) * Set priority for all PLB3 devices to 0. * Set PLB3 arbiter to fair mode. */ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */ + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /* Sequoia */ /* * Set priority for all PLB4 devices to 0. */ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); /* Sequoia */ + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4_ACR, addr); /* Sequoia */ /* * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM. * Workaround: Disable write pipelining to DDR SDRAM by setting * PLB0_ACR[WRP] = 0. */ - mtdcr(plb0_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */ + mtdcr(PLB0_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */ /* Segment1 */ - mtdcr(plb1_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */ + mtdcr(PLB1_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */ return board_with_pci(); } diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 5c2ec356397..0546cd726d1 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -89,11 +89,11 @@ static int wait_for_dlllock(void) /* -----------------------------------------------------------+ * Wait for the DCC master delay line to finish calibration * ----------------------------------------------------------*/ - mtdcr(memcfga, DDR0_17); + mtdcr(SDRAM0_CFGADDR, DDR0_17); val = DDR0_17_DLLLOCKREG_UNLOCKED; while (wait != 0xffff) { - val = mfdcr(memcfgd); + val = mfdcr(SDRAM0_CFGDATA); if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED) /* dlllockreg bit on */ diff --git a/board/netstal/mcu25/mcu25.c b/board/netstal/mcu25/mcu25.c index 67c1b0bbeac..9054282c94d 100644 --- a/board/netstal/mcu25/mcu25.c +++ b/board/netstal/mcu25/mcu25.c @@ -71,8 +71,8 @@ int board_early_init_f (void) mtdcr(uictr, 0x00000000); /* set int trigger levels */ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(cntrl1, CPC0_CR1_VALUE); - mtdcr(ecr, 0x60606000); + mtdcr(CPC0_CR1, CPC0_CR1_VALUE); + mtdcr(CPC0_ECR, 0x60606000); mtdcr(CPC0_EIRR, 0x7C000000); out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR ); out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); @@ -103,7 +103,7 @@ int checkboard (void) u16 index = boardVersReg & 0xf0; /* Cannot be done in board_early_init */ - mtdcr(cntrl0, CPC0_CR0_VALUE); + mtdcr(CPC0_CR0, CPC0_CR0_VALUE); /* Force /RTS to active. The board it not wired quite * correctly to use cts/rtc flow control, so just force the diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index 47d6391469a..f966d02f107 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -143,9 +143,9 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup the external bus controller/chip selects *-------------------------------------------------------------------*/ - mtdcr(ebccfga, xbcfg); - reg = mfdcr(ebccfgd); - mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ + mtdcr(EBC0_CFGADDR, EBC0_CFG); + reg = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */ /*-------------------------------------------------------------------- * GPIO's are alreay setup in cpu/ppc4xx/cpu_init.c @@ -174,10 +174,10 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup other serial configuration *-------------------------------------------------------------------*/ - mfsdr(sdr_pci0, reg); - mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ - mtsdr(sdr_pfc0, 0x00000000); /* Pin function: enable GPIO49-63 */ - mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */ + mfsdr(SDR0_PCI0, reg); + mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */ + mtsdr(SDR0_PFC0, 0x00000000); /* Pin function: enable GPIO49-63 */ + mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */ return 0; } @@ -444,8 +444,8 @@ int misc_init_r (void) load_ethaddr(); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); switch (gd->bd->bi_flashsize) { case 1 << 20: size_val = 0; @@ -473,8 +473,8 @@ int misc_init_r (void) break; } pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(ebccfga, pb0cr); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGADDR, PB0CR); + mtdcr(EBC0_CFGDATA, pbcr); /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; @@ -571,35 +571,35 @@ int pci_pre_init(struct pci_controller *hose) | Set priority for all PLB3 devices to 0. | Set PLB3 arbiter to fair mode. +-------------------------------------------------------------------------*/ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /*-------------------------------------------------------------------------+ | Set priority for all PLB4 devices to 0. +-------------------------------------------------------------------------*/ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4_ACR, addr); /*-------------------------------------------------------------------------+ | Set Nebula PLB4 arbiter to fair mode. +-------------------------------------------------------------------------*/ /* Segment0 */ - addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; - addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; - addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; - addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; - mtdcr(plb0_acr, addr); + addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; + addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; + addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; + addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; + mtdcr(PLB0_ACR, addr); /* Segment1 */ - addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; - addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; - addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; - addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; - mtdcr(plb1_acr, addr); + addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; + addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; + addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; + addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; + mtdcr(PLB1_ACR, addr); return 1; } diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c index dc3431961f4..be79b42bd04 100644 --- a/board/prodrive/alpr/alpr.c +++ b/board/prodrive/alpr/alpr.c @@ -39,7 +39,7 @@ int board_early_init_f (void) /*------------------------------------------------------------------------- * Initialize EBC CONFIG *-------------------------------------------------------------------------*/ - mtebc(xbcfg, EBC_CFG_LE_UNLOCK | + mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | @@ -96,7 +96,7 @@ int board_early_init_f (void) out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY)); /* Setup GPIO/IRQ multiplexing */ - mtsdr(sdr_pfc0, 0x01a33e00); + mtsdr(SDR0_PFC0, 0x01a33e00); return 0; } @@ -165,7 +165,7 @@ int pci_pre_init(struct pci_controller * hose ) * The ocotea board is always configured as the host & requires the * PCI arbiter to be enabled. *--------------------------------------------------------------------------*/ - mfsdr(sdr_sdstp1, strap); + mfsdr(SDR0_SDSTP1, strap); if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); return 0; diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c index 1a0486f5c0c..18054e45b6e 100644 --- a/board/prodrive/p3p440/p3p440.c +++ b/board/prodrive/p3p440/p3p440.c @@ -85,14 +85,14 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup the external bus controller/chip selects *-------------------------------------------------------------------*/ - mtdcr(ebccfga, xbcfg); - reg = mfdcr(ebccfgd); - mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ + mtdcr(EBC0_CFGADDR, EBC0_CFG); + reg = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */ /*-------------------------------------------------------------------- * Setup pin multiplexing (GPIO/IRQ...) *-------------------------------------------------------------------*/ - mtdcr(cpc0_gpio, 0x03F01F80); + mtdcr(CPC0_GPIO, 0x03F01F80); out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ out32(GPIO0_TCR, CONFIG_SYS_GPIO_RDY | CONFIG_SYS_EREADY_IO | CONFIG_SYS_LED_RED | CONFIG_SYS_LED_GREEN); @@ -153,12 +153,12 @@ int misc_init_r (void) * Check if only one FLASH bank is available */ if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) { - mtebc(pb1cr, 0); /* disable cs */ - mtebc(pb1ap, 0); - mtebc(pb2cr, 0); /* disable cs */ - mtebc(pb2ap, 0); - mtebc(pb3cr, 0); /* disable cs */ - mtebc(pb3ap, 0); + mtebc(PB1CR, 0); /* disable cs */ + mtebc(PB1AP, 0); + mtebc(PB2CR, 0); /* disable cs */ + mtebc(PB2AP, 0); + mtebc(PB3CR, 0); /* disable cs */ + mtebc(PB3AP, 0); } return 0; @@ -185,7 +185,7 @@ int pci_pre_init(struct pci_controller *hose) * The P3P440 board is always configured as the host & requires the * PCI arbiter to be disabled because it's an PMC module. *--------------------------------------------------------------------------*/ - strap = mfdcr(cpc0_strp1); + strap = mfdcr(CPC0_STRP1); if (strap & 0x00100000) { printf("PCI: CPC0_STRP1[PAE] set.\n"); return 0; diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c index b8160c8427d..d8b0564b3be 100644 --- a/board/sandburst/common/sb_common.c +++ b/board/sandburst/common/sb_common.c @@ -322,7 +322,7 @@ int pci_pre_init(struct pci_controller * hose ) * The metrobox is always configured as the host & requires the * PCI arbiter to be enabled. *--------------------------------------------------------------------------*/ - mfsdr(sdr_sdstp1, strap); + mfsdr(SDR0_SDSTP1, strap); if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); return 0; diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c index 92f52475652..b80c2069400 100644 --- a/board/sandburst/karef/karef.c +++ b/board/sandburst/karef/karef.c @@ -67,7 +67,7 @@ int board_early_init_f (void) ppc440_gpio_regs_t *gpio_regs; /* Enable GPIO interrupts */ - mtsdr(sdr_pfc0, 0x00103E00); + mtsdr(SDR0_PFC0, 0x00103E00); /* Setup access for LEDs, and system topology info */ gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; @@ -80,7 +80,7 @@ int board_early_init_f (void) /*--------------------------------------------------------------------+ | Initialize EBC CONFIG +-------------------------------------------------------------------*/ - mtebc(xbcfg, + mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | @@ -90,7 +90,7 @@ int board_early_init_f (void) /*--------------------------------------------------------------------+ | 1/2 MB FLASH. Initialize bank 0 with default values. +-------------------------------------------------------------------*/ - mtebc(pb0ap, + mtebc(PB0AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | @@ -98,12 +98,12 @@ int board_early_init_f (void) EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | + mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); /*--------------------------------------------------------------------+ | 8KB NVRAM/RTC. Initialize bank 1 with default values. +-------------------------------------------------------------------*/ - mtebc(pb1ap, + mtebc(PB1AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | @@ -111,13 +111,13 @@ int board_early_init_f (void) EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) | + mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); /*--------------------------------------------------------------------+ | Compact Flash, uses 2 Chip Selects (2 & 6) +-------------------------------------------------------------------*/ - mtebc(pb2ap, + mtebc(PB2AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | @@ -125,40 +125,40 @@ int board_early_init_f (void) EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) | + mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); /*--------------------------------------------------------------------+ | KaRef Scan FPGA. Initialize bank 3 with default values. +-------------------------------------------------------------------*/ - mtebc(pb5ap, + mtebc(PB5AP, EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48200000) | + mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48200000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); /*--------------------------------------------------------------------+ | MAC A & B for Kamino. OFEM FPGA decodes the addresses | Initialize bank 4 with default values. +-------------------------------------------------------------------*/ - mtebc(pb4ap, + mtebc(PB4AP, EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) | + mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) | EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); /*--------------------------------------------------------------------+ | OFEM FPGA Initialize bank 5 with default values. +-------------------------------------------------------------------*/ - mtebc(pb3ap, + mtebc(PB3AP, EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | @@ -166,14 +166,14 @@ int board_early_init_f (void) EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48400000) | + mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48400000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); /*--------------------------------------------------------------------+ | Compact Flash, uses 2 Chip Selects (2 & 6) +-------------------------------------------------------------------*/ - mtebc(pb6ap, + mtebc(PB6AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | @@ -181,20 +181,20 @@ int board_early_init_f (void) EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) | + mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); /*--------------------------------------------------------------------+ | BME-32. Initialize bank 7 with default values. +-------------------------------------------------------------------*/ - mtebc(pb7ap, + mtebc(PB7AP, EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) | + mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); /*--------------------------------------------------------------------+ diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c index 27d7f74088b..ad3f9bc28e1 100644 --- a/board/sandburst/metrobox/metrobox.c +++ b/board/sandburst/metrobox/metrobox.c @@ -57,7 +57,7 @@ int board_early_init_f (void) ppc440_gpio_regs_t *gpio_regs; /* Enable GPIO interrupts */ - mtsdr(sdr_pfc0, 0x00103E00); + mtsdr(SDR0_PFC0, 0x00103E00); /* Setup access for LEDs, and system topology info */ gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; @@ -70,7 +70,7 @@ int board_early_init_f (void) /*--------------------------------------------------------------------+ | Initialize EBC CONFIG +-------------------------------------------------------------------*/ - mtebc(xbcfg, + mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | @@ -80,7 +80,7 @@ int board_early_init_f (void) /*--------------------------------------------------------------------+ | 1/2 MB FLASH. Initialize bank 0 with default values. +-------------------------------------------------------------------*/ - mtebc(pb0ap, + mtebc(PB0AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | @@ -88,12 +88,12 @@ int board_early_init_f (void) EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | + mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); /*--------------------------------------------------------------------+ | 8KB NVRAM/RTC. Initialize bank 1 with default values. +-------------------------------------------------------------------*/ - mtebc(pb1ap, + mtebc(PB1AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | @@ -101,13 +101,13 @@ int board_early_init_f (void) EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) | + mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); /*--------------------------------------------------------------------+ | Compact Flash, uses 2 Chip Selects (2 & 6) +-------------------------------------------------------------------*/ - mtebc(pb2ap, + mtebc(PB2AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | @@ -115,20 +115,20 @@ int board_early_init_f (void) EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) | + mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); /*--------------------------------------------------------------------+ | OPTO & OFEM FPGA. Initialize bank 3 with default values. +-------------------------------------------------------------------*/ - mtebc(pb3ap, + mtebc(PB3AP, EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48200000) | + mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48200000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); /*--------------------------------------------------------------------+ @@ -136,34 +136,34 @@ int board_early_init_f (void) | MAC A & B for Kamino. OFEM FPGA decodes the addresses | Initialize bank 4 with default values. +-------------------------------------------------------------------*/ - mtebc(pb4ap, + mtebc(PB4AP, EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) | + mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); /*--------------------------------------------------------------------+ | Metrobox MAC B Initialize bank 5 with default values. | KA REF FPGA Initialize bank 5 with default values. +-------------------------------------------------------------------*/ - mtebc(pb5ap, + mtebc(PB5AP, EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48700000) | + mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48700000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); /*--------------------------------------------------------------------+ | Compact Flash, uses 2 Chip Selects (2 & 6) +-------------------------------------------------------------------*/ - mtebc(pb6ap, + mtebc(PB6AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | @@ -171,20 +171,20 @@ int board_early_init_f (void) EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) | + mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); /*--------------------------------------------------------------------+ | BME-32. Initialize bank 7 with default values. +-------------------------------------------------------------------*/ - mtebc(pb7ap, + mtebc(PB7AP, EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) | + mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); /*--------------------------------------------------------------------+ diff --git a/board/sbc405/sbc405.c b/board/sbc405/sbc405.c index 7818cd7e555..66842eaf4da 100644 --- a/board/sbc405/sbc405.c +++ b/board/sbc405/sbc405.c @@ -52,7 +52,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); + mtebc (EBC0_CFG, 0xa8400000); return 0; } diff --git a/board/sc3/init.S b/board/sc3/init.S index f97a5ea6104..6052c665534 100644 --- a/board/sc3/init.S +++ b/board/sc3/init.S @@ -58,7 +58,7 @@ ext_bus_cntlr_init: * We need the current boot up configuration to set correct * timings into internal flash and external flash */ - mfdcr r24,strap /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx + mfdcr r24,CPC0_PSR /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx 0 0 -> 8 bit external ROM 0 1 -> 16 bit internal ROM */ addi r4,0,2 @@ -113,8 +113,8 @@ ext_bus_cntlr_init: * We only have to change the timing. Mapping is ok by boot-strapping *----------------------------------------------------------------------- */ - li r4,pb0ap /* PB0AP=Peripheral Bank 0 Access Parameters */ - mtdcr ebccfga,r4 + li r4,PB1AP /* PB0AP=Peripheral Bank 0 Access Parameters */ + mtdcr EBC0_CFGADDR,r4 mr r4,r26 /* assume internal fast flash is boot flash */ cmpwi r24,0x2000 /* assumption true? ... */ @@ -122,27 +122,27 @@ ext_bus_cntlr_init: mr r4,r25 /* ...no, use the slow variant */ mr r25,r26 /* use this for the other flash */ 1: - mtdcr ebccfgd,r4 /* change timing now */ + mtdcr EBC0_CFGDATA,r4 /* change timing now */ - li r4,pb0cr /* PB0CR=Peripheral Bank 0 Control Register */ - mtdcr ebccfga,r4 - mfdcr r4,ebccfgd + li r4,PB0CR /* PB0CR=Peripheral Bank 0 Control Register */ + mtdcr EBC0_CFGADDR,r4 + mfdcr r4,EBC0_CFGDATA lis r3,0x0001 ori r3,r3,0x8000 /* allow reads and writes */ or r4,r4,r3 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /*----------------------------------------------------------------------- * Memory Bank 3 (Second-Flash) initialization * 0xF0000000...0xF01FFFFF -> 2MB *----------------------------------------------------------------------- */ - li r4,pb3ap /* Peripheral Bank 1 Access Parameter */ - mtdcr ebccfga,r4 - mtdcr ebccfgd,r2 /* change timing */ + li r4,PB3AP /* Peripheral Bank 1 Access Parameter */ + mtdcr EBC0_CFGADDR,r4 + mtdcr EBC0_CFGDATA,r2 /* change timing */ - li r4,pb3cr /* Peripheral Bank 1 Configuration Registers */ - mtdcr ebccfga,r4 + li r4,PB3CR /* Peripheral Bank 1 Configuration Registers */ + mtdcr EBC0_CFGADDR,r4 lis r4,0xF003 ori r4,r4,0x8000 @@ -151,7 +151,7 @@ ext_bus_cntlr_init: */ xori r24,r24,0x2000 /* invert current bus width */ or r4,r4,r24 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /*----------------------------------------------------------------------- * Memory Bank 1 (NAND-Flash) initialization @@ -169,28 +169,28 @@ ext_bus_cntlr_init: * ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold) *----------------------------------------------------------------------- */ - li r4,pb1ap /* Peripheral Bank 1 Access Parameter */ - mtdcr ebccfga,r4 + li r4,PB1AP /* Peripheral Bank 1 Access Parameter */ + mtdcr EBC0_CFGADDR,r4 lis r4,0x0000 ori r4,r4,0x0200 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - li r4,pb1cr /* Peripheral Bank 1 Configuration Registers */ - mtdcr ebccfga,r4 + li r4,PB1CR /* Peripheral Bank 1 Configuration Registers */ + mtdcr EBC0_CFGADDR,r4 lis r4,0x77D1 ori r4,r4,0x8000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /* USB init (without acceleration) */ #ifndef CONFIG_ISP1161_PRESENT - li r4,pb4ap /* PB4AP=Peripheral Bank 4 Access Parameters */ - mtdcr ebccfga,r4 + li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */ + mtdcr EBC0_CFGADDR,r4 lis r4,0x0180 ori r4,r4,0x5940 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 #endif /*----------------------------------------------------------------------- @@ -204,8 +204,8 @@ ext_bus_cntlr_init: A7/A24=0 -> memory cycle A7/ /A24=1 -> I/O cycle */ - li r4,pb2ap /* PB2AP=Peripheral Bank 2 Access Parameters */ - mtdcr ebccfga,r4 + li r4,PB2AP /* PB2AP=Peripheral Bank 2 Access Parameters */ + mtdcr EBC0_CFGADDR,r4 /* We emulate an ISA access @@ -226,58 +226,58 @@ ext_bus_cntlr_init: lis r4,0x0100 ori r4,r4,0x0340 #endif - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 #ifdef IDE_USES_ISA_EMULATION - li r25,pb5ap /* PB5AP=Peripheral Bank 5 Access Parameters */ - mtdcr ebccfga,r25 - mtdcr ebccfgd,r4 + li r25,PB5AP /* PB5AP=Peripheral Bank 5 Access Parameters */ + mtdcr EBC0_CFGADDR,r25 + mtdcr EBC0_CFGDATA,r4 #endif - li r25,pb6ap /* PB6AP=Peripheral Bank 6 Access Parameters */ - mtdcr ebccfga,r25 - mtdcr ebccfgd,r4 - li r25,pb7ap /* PB7AP=Peripheral Bank 7 Access Parameters */ - mtdcr ebccfga,r25 - mtdcr ebccfgd,r4 + li r25,PB6AP /* PB6AP=Peripheral Bank 6 Access Parameters */ + mtdcr EBC0_CFGADDR,r25 + mtdcr EBC0_CFGDATA,r4 + li r25,PB7AP /* PB7AP=Peripheral Bank 7 Access Parameters */ + mtdcr EBC0_CFGADDR,r25 + mtdcr EBC0_CFGDATA,r4 - li r25,pb2cr /* PB2CR=Peripheral Bank 2 Configuration Register */ - mtdcr ebccfga,r25 + li r25,PB2CR /* PB2CR=Peripheral Bank 2 Configuration Register */ + mtdcr EBC0_CFGADDR,r25 lis r4,0x780B ori r4,r4,0xA000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /* * the other areas are only 1MiB in size */ lis r4,0x7401 ori r4,r4,0xA000 - li r25,pb6cr /* PB6CR=Peripheral Bank 6 Configuration Register */ - mtdcr ebccfga,r25 + li r25,PB6CR /* PB6CR=Peripheral Bank 6 Configuration Register */ + mtdcr EBC0_CFGADDR,r25 lis r4,0x7401 ori r4,r4,0xA000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - li r25,pb7cr /* PB7CR=Peripheral Bank 7 Configuration Register */ - mtdcr ebccfga,r25 + li r25,PB7CR /* PB7CR=Peripheral Bank 7 Configuration Register */ + mtdcr EBC0_CFGADDR,r25 lis r4,0x7411 ori r4,r4,0xA000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 #ifndef CONFIG_ISP1161_PRESENT - li r25,pb4cr /* PB4CR=Peripheral Bank 4 Configuration Register */ - mtdcr ebccfga,r25 + li r25,PB4CR /* PB4CR=Peripheral Bank 4 Configuration Register */ + mtdcr EBC0_CFGADDR,r25 lis r4,0x7421 ori r4,r4,0xA000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 #endif #ifdef IDE_USES_ISA_EMULATION - li r25,pb5cr /* PB5CR=Peripheral Bank 5 Configuration Register */ - mtdcr ebccfga,r25 + li r25,PB5CR /* PB5CR=Peripheral Bank 5 Configuration Register */ + mtdcr EBC0_CFGADDR,r25 lis r4,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 #endif /*----------------------------------------------------------------------- @@ -315,19 +315,19 @@ ext_bus_cntlr_init: #ifdef CONFIG_ISP1161_PRESENT - li r4,pb4ap /* PB4AP=Peripheral Bank 4 Access Parameters */ - mtdcr ebccfga,r4 + li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */ + mtdcr EBC0_CFGADDR,r4 lis r4,0x030D ori r4,r4,0x5E80 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - li r4,pb4cr /* PB2CR=Peripheral Bank 4 Configuration Register */ - mtdcr ebccfga,r4 + li r4,PB4CR /* PB2CR=Peripheral Bank 4 Configuration Register */ + mtdcr EBC0_CFGADDR,r4 lis r4,0x77C1 ori r4,r4,0xA000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 #endif @@ -352,28 +352,28 @@ ext_bus_cntlr_init: * *----------------------------------------------------------------------- */ - li r4,pb5ap - mtdcr ebccfga,r4 + li r4,PB5AP + mtdcr EBC0_CFGADDR,r4 lis r4,0x040C ori r4,r4,0x0200 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - li r4,pb5cr /* PB2CR=Peripheral Bank 2 Configuration Register */ - mtdcr ebccfga,r4 + li r4,PB5CR /* PB2CR=Peripheral Bank 2 Configuration Register */ + mtdcr EBC0_CFGADDR,r4 lis r4,0x7A01 ori r4,r4,0xA000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 #endif /* * External Peripheral Control Register */ - li r4,epcr - mtdcr ebccfga,r4 + li r4,EBC0_CFG + mtdcr EBC0_CFGADDR,r4 lis r4,0xB84E ori r4,r4,0xF000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /* * drive POST code */ diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c index 6c82fe7e992..5ae7b1244a7 100644 --- a/board/sc3/sc3.c +++ b/board/sc3/sc3.c @@ -199,14 +199,14 @@ int board_start_ide(void) static int sc3_cameron_init (void) { /* Set up the Memory Controller for the CAMERON version */ - mtebc (pb4ap, 0x01805940); - mtebc (pb4cr, 0x7401a000); - mtebc (pb5ap, 0x01805940); - mtebc (pb5cr, 0x7401a000); - mtebc (pb6ap, 0x0); - mtebc (pb6cr, 0x0); - mtebc (pb7ap, 0x0); - mtebc (pb7cr, 0x0); + mtebc (PB4AP, 0x01805940); + mtebc (PB4CR, 0x7401a000); + mtebc (PB5AP, 0x01805940); + mtebc (PB5CR, 0x7401a000); + mtebc (PB6AP, 0x0); + mtebc (PB6CR, 0x0); + mtebc (PB7AP, 0x0); + mtebc (PB7CR, 0x0); return 0; } @@ -312,18 +312,18 @@ int board_early_init_f (void) mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ /* setup other implementation specific details */ - mtdcr (ecr, 0x60606000); + mtdcr (CPC0_ECR, 0x60606000); - mtdcr (cntrl1, 0x000042C0); + mtdcr (CPC0_CR1, 0x000042C0); if (IS_CAMERON) { - mtdcr (cntrl0, 0x01380000); + mtdcr (CPC0_CR0, 0x01380000); /* Setup the GPIOs */ writel (0x08008000, 0xEF600700); /* Output states */ writel (0x00000000, 0xEF600718); /* Open Drain control */ writel (0x68098000, 0xEF600704); /* Output control */ } else { - mtdcr (cntrl0,0x00080000); + mtdcr (CPC0_CR0,0x00080000); /* Setup the GPIOs */ writel (0x08000000, 0xEF600700); /* Output states */ writel (0x14000000, 0xEF600718); /* Open Drain control */ @@ -331,13 +331,13 @@ int board_early_init_f (void) } /* Code decompression disabled */ - mtdcr (kiar, kconf); - mtdcr (kidr, 0x2B); + mtdcr (KIAR, KCONF); + mtdcr (KIDR, 0x2B); /* CPC0_ER: enable sleep mode of (currently) unused components */ /* CPC0_FR: force unused components into sleep mode */ - mtdcr (cpmer, 0x3F800000); - mtdcr (cpmfr, 0x14000000); + mtdcr (CPMER, 0x3F800000); + mtdcr (CPMFR, 0x14000000); /* set PLB priority */ mtdcr (0x87, 0x08000000); @@ -472,19 +472,19 @@ static void printCSConfig(int reg,unsigned long ap,unsigned long cr) #ifdef SC3_DEBUGOUT -static unsigned int ap[] = {pb0ap, pb1ap, pb2ap, pb3ap, pb4ap, - pb5ap, pb6ap, pb7ap}; -static unsigned int cr[] = {pb0cr, pb1cr, pb2cr, pb3cr, pb4cr, - pb5cr, pb6cr, pb7cr}; +static unsigned int ap[] = {PB0AP, PB1AP, PB2AP, PB3AP, PB4AP, + PB5AP, PB6AP, PB7AP}; +static unsigned int cr[] = {PB0CR, PB1CR, PB2CR, PB3CR, PB4CR, + PB5CR, PB6CR, PB7CR}; static int show_reg (int nr) { unsigned long ul1, ul2; - mtdcr (ebccfga, ap[nr]); - ul1 = mfdcr (ebccfgd); - mtdcr (ebccfga, cr[nr]); - ul2 = mfdcr(ebccfgd); + mtdcr (EBC0_CFGADDR, ap[nr]); + ul1 = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, cr[nr]); + ul2 = mfdcr(EBC0_CFGDATA); printCSConfig(nr, ul1, ul2); return 0; } @@ -500,8 +500,8 @@ int checkboard (void) show_reg (i); } - mtdcr (ebccfga, epcr); - ul1 = mfdcr (ebccfgd); + mtdcr (EBC0_CFGADDR, EBC0_CFG); + ul1 = mfdcr (EBC0_CFGDATA); puts ("\nGeneral configuration:\n"); @@ -591,21 +591,21 @@ phys_size_t initdram (int board_type) puts("\nSDRAM configuration:\n"); - mtdcr (memcfga, mem_mcopt1); - ul1 = mfdcr(memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + ul1 = mfdcr(SDRAM0_CFGDATA); if (!(ul1 & 0x80000000)) { puts(" Controller disabled\n"); return 0; } for (i = 0; i < 4; i++) { - mtdcr (memcfga, mbcf[i]); - ul1 = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mbcf[i]); + ul1 = mfdcr (SDRAM0_CFGDATA); mems += printSDRAMConfig (i, ul1); } - mtdcr (memcfga, mem_sdtr1); - ul1 = mfdcr(memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + ul1 = mfdcr(SDRAM0_CFGDATA); printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1); printf (" -Precharge %lu (PTA) \n", ((ul1 & 0xC0000) >> 18) + 1); @@ -614,15 +614,15 @@ phys_size_t initdram (int board_type) printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4); printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1)); puts ("Misc:\n"); - mtdcr (memcfga, mem_rtr); - ul1 = mfdcr(memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_rtr); + ul1 = mfdcr(SDRAM0_CFGDATA); printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7); - mtdcr(memcfga,mem_pmit); - ul2=mfdcr(memcfgd); + mtdcr(SDRAM0_CFGADDR,mem_pmit); + ul2=mfdcr(SDRAM0_CFGDATA); - mtdcr(memcfga,mem_mcopt1); - ul1=mfdcr(memcfgd); + mtdcr(SDRAM0_CFGADDR,mem_mcopt1); + ul1=mfdcr(SDRAM0_CFGDATA); if (ul1 & 0x20000000) printf(" -Power Down after: %luns\n", @@ -658,8 +658,8 @@ phys_size_t initdram (int board_type) else puts(" -Memory lines only at write cycles active outputs\n"); - mtdcr (memcfga, mem_status); - ul1 = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_status); + ul1 = mfdcr (SDRAM0_CFGDATA); if (ul1 & 0x80000000) puts(" -SDRAM Controller ready\n"); else @@ -670,20 +670,20 @@ phys_size_t initdram (int board_type) return (mems * 1024 * 1024); #else - mtdcr (memcfga, mem_mb0cf); - ul1 = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + ul1 = mfdcr (SDRAM0_CFGDATA); mems = printSDRAMConfig (0, ul1); - mtdcr (memcfga, mem_mb1cf); - ul1 = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + ul1 = mfdcr (SDRAM0_CFGDATA); mems += printSDRAMConfig (1, ul1); - mtdcr (memcfga, mem_mb2cf); - ul1 = mfdcr(memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + ul1 = mfdcr(SDRAM0_CFGDATA); mems += printSDRAMConfig (2, ul1); - mtdcr (memcfga, mem_mb3cf); - ul1 = mfdcr(memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + ul1 = mfdcr(SDRAM0_CFGDATA); mems += printSDRAMConfig (3, ul1); return (mems * 1024 * 1024); diff --git a/board/snmc/qs850/flash.c b/board/snmc/qs850/flash.c index 9e276a104a3..a26a67900be 100644 --- a/board/snmc/qs850/flash.c +++ b/board/snmc/qs850/flash.c @@ -104,21 +104,21 @@ unsigned long flash_init (void) /* Re-do sizing to get full correct info */ if (size_b1) { - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b1 = -size_b1; pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); } if (size_b0) { - mtdcr(ebccfga, pb1cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb1cr); + mtdcr(EBC0_CFGADDR, PB1CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB1CR); base_b0 = base_b1 - size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); } size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b0, &flash_info[0]); diff --git a/board/snmc/qs860t/flash.c b/board/snmc/qs860t/flash.c index 2cb8dcb9d80..48c2258b3f6 100644 --- a/board/snmc/qs860t/flash.c +++ b/board/snmc/qs860t/flash.c @@ -102,21 +102,21 @@ unsigned long flash_init (void) /* Re-do sizing to get full correct info */ if (size_b1) { - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b1 = -size_b1; pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); } if (size_b0) { - mtdcr(ebccfga, pb1cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb1cr); + mtdcr(EBC0_CFGADDR, PB1CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB1CR); base_b0 = base_b1 - size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); } size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b0, &flash_info[0]); diff --git a/board/tb0229/flash.c b/board/tb0229/flash.c index 933d5ecc87e..15546421a8f 100644 --- a/board/tb0229/flash.c +++ b/board/tb0229/flash.c @@ -108,25 +108,25 @@ unsigned long flash_init (void) /* Re-do sizing to get full correct info */ if (size_b1) { - mtdcr (ebccfga, pb0cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb0cr); + mtdcr (EBC0_CFGADDR, PB0CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB0CR); base_b1 = -size_b1; pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1 / 1024 / 1024) - 1) << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr (EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ } if (size_b0) { - mtdcr (ebccfga, pb1cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb1cr); + mtdcr (EBC0_CFGADDR, PB1CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB1CR); base_b0 = base_b1 - size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0 / 1024 / 1024) - 1) << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb0cr = %x\n", pbcr); */ + mtdcr (EBC0_CFGDATA, pbcr); + /* printf("PB0CR = %x\n", pbcr); */ } size_b0 = diff --git a/board/w7o/init.S b/board/w7o/init.S index 902c6311374..090b07a1e62 100644 --- a/board/w7o/init.S +++ b/board/w7o/init.S @@ -87,48 +87,48 @@ ext_bus_cntlr_init: /******************************************************************** * Setup External Bus Controller (EBC). *******************************************************************/ - addi r3, 0, epcr - mtdcr ebccfga, r3 + addi r3, 0, EBC0_CFG + mtdcr EBC0_CFGADDR, r3 addis r4, 0, 0xb040 /* Device base timeout = 1024 cycles */ ori r4, r4, 0x0 /* Drive CS with external master */ - mtdcr ebccfgd, r4 + mtdcr EBC0_CFGDATA, r4 /******************************************************************** * Change PCIINT signal to PerWE *******************************************************************/ - mfdcr r4, cntrl1 + mfdcr r4, CPC0_CR1 ori r4, r4, 0x4000 - mtdcr cntrl1, r4 + mtdcr CPC0_CR1, r4 /******************************************************************** * Memory Bank 0 (Flash Bank 0) initialization *******************************************************************/ - addi r3, 0, pb0ap - mtdcr ebccfga, r3 + addi r3, 0, PB1AP + mtdcr EBC0_CFGADDR, r3 addis r4, 0, CONFIG_SYS_W7O_EBC_PB0AP@h ori r4, r4, CONFIG_SYS_W7O_EBC_PB0AP@l - mtdcr ebccfgd, r4 + mtdcr EBC0_CFGDATA, r4 - addi r3, 0, pb0cr - mtdcr ebccfga, r3 + addi r3, 0, PB0CR + mtdcr EBC0_CFGADDR, r3 addis r4, 0, CONFIG_SYS_W7O_EBC_PB0CR@h ori r4, r4, CONFIG_SYS_W7O_EBC_PB0CR@l - mtdcr ebccfgd, r4 + mtdcr EBC0_CFGDATA, r4 /******************************************************************** * Memory Bank 7 LEDs - NEEDED BECAUSE OF HW WATCHDOG AND LEDs. *******************************************************************/ - addi r3, 0, pb7ap - mtdcr ebccfga, r3 + addi r3, 0, PB7AP + mtdcr EBC0_CFGADDR, r3 addis r4, 0, CONFIG_SYS_W7O_EBC_PB7AP@h ori r4, r4, CONFIG_SYS_W7O_EBC_PB7AP@l - mtdcr ebccfgd, r4 + mtdcr EBC0_CFGDATA, r4 - addi r3, 0, pb7cr - mtdcr ebccfga, r3 + addi r3, 0, PB7CR + mtdcr EBC0_CFGADDR, r3 addis r4, 0, CONFIG_SYS_W7O_EBC_PB7CR@h ori r4, r4, CONFIG_SYS_W7O_EBC_PB7CR@l - mtdcr ebccfgd, r4 + mtdcr EBC0_CFGDATA, r4 /* We are all done */ mtlr r0 /* Restore link register */ @@ -183,35 +183,35 @@ sdram_init: * values to be changed. */ addi r3, 0, mem_mcopt1 - mtdcr memcfga, r3 + mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x0 ori r4, r4, 0x0 - mtdcr memcfgd, r4 + mtdcr SDRAM0_CFGDATA, r4 /* * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2 * All other banks are disabled. */ addi r3, 0, mem_mb0cf - mtdcr memcfga, r3 + mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */ ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */ - mtdcr memcfgd, r4 + mtdcr SDRAM0_CFGDATA, r4 /* Clear MB1CR,MB2CR,MB3CR to turn other banks off */ addi r4, 0, 0 /* Zero the data reg */ addi r3, r3, 4 /* Point to MB1CF reg */ - mtdcr memcfga, r3 /* Set the address */ - mtdcr memcfgd, r4 /* Zero the reg */ + mtdcr SDRAM0_CFGADDR, r3 /* Set the address */ + mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */ addi r3, r3, 4 /* Point to MB2CF reg */ - mtdcr memcfga, r3 /* Set the address */ - mtdcr memcfgd, r4 /* Zero the reg */ + mtdcr SDRAM0_CFGADDR, r3 /* Set the address */ + mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */ addi r3, r3, 4 /* Point to MB3CF reg */ - mtdcr memcfga, r3 /* Set the address */ - mtdcr memcfgd, r4 /* Zero the reg */ + mtdcr SDRAM0_CFGADDR, r3 /* Set the address */ + mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */ /******************************************************************** * Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. @@ -223,18 +223,18 @@ sdram_init: * Set up SDTR1 */ addi r3, 0, mem_sdtr1 - mtdcr memcfga, r3 + mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */ ori r4, r4, 0x400D - mtdcr memcfgd, r4 + mtdcr SDRAM0_CFGDATA, r4 /* * Set RTR */ addi r3, 0, mem_rtr - mtdcr memcfga, r3 + mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms@100Mhz */ - mtdcr memcfgd, r4 + mtdcr SDRAM0_CFGDATA, r4 /******************************************************************** * Delay to ensure 200usec have elapsed since reset. Assume worst @@ -251,10 +251,10 @@ sdram_init: * Set memory controller options reg, MCOPT1. *******************************************************************/ addi r3, 0, mem_mcopt1 - mtdcr memcfga, r3 + mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */ ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */ - mtdcr memcfgd, r4 /* EMDULR=1 */ + mtdcr SDRAM0_CFGDATA, r4 /* EMDULR=1 */ ..sdri_done: /* restore and return */ diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c index 22cdfcd7d75..6479beeb13b 100644 --- a/board/w7o/w7o.c +++ b/board/w7o/w7o.c @@ -170,17 +170,17 @@ unsigned long get_dram_size (void) int size = 0; /* Get bank Size registers */ - mtdcr (memcfga, mem_mb0cf); /* get bank 0 config reg */ - regs[0] = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); /* get bank 0 config reg */ + regs[0] = mfdcr (SDRAM0_CFGDATA); - mtdcr (memcfga, mem_mb1cf); /* get bank 1 config reg */ - regs[1] = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); /* get bank 1 config reg */ + regs[1] = mfdcr (SDRAM0_CFGDATA); - mtdcr (memcfga, mem_mb2cf); /* get bank 2 config reg */ - regs[2] = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); /* get bank 2 config reg */ + regs[2] = mfdcr (SDRAM0_CFGDATA); - mtdcr (memcfga, mem_mb3cf); /* get bank 3 config reg */ - regs[3] = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); /* get bank 3 config reg */ + regs[3] = mfdcr (SDRAM0_CFGDATA); /* compute the size, add each bank if enabled */ for (i = 0; i < 4; i++) { diff --git a/board/xes/xpedite1000/xpedite1000.c b/board/xes/xpedite1000/xpedite1000.c index 4529b7eded8..58041fcd349 100644 --- a/board/xes/xpedite1000/xpedite1000.c +++ b/board/xes/xpedite1000/xpedite1000.c @@ -42,8 +42,8 @@ int board_early_init_f(void) * 23 = #LED_STATUS1 * 24 = #LED_STATUS2 */ - mfsdr(sdr_pfc0, sdrreg); - mtsdr(sdr_pfc0, (sdrreg & ~SDR0_PFC0_TRE_ENABLE) | 0x00003e00); + mfsdr(SDR0_PFC0, sdrreg); + mtsdr(SDR0_PFC0, (sdrreg & ~SDR0_PFC0_TRE_ENABLE) | 0x00003e00); out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3)); LED0_OFF(); LED1_OFF(); @@ -51,14 +51,14 @@ int board_early_init_f(void) LED3_OFF(); /* Setup the external bus controller/chip selects */ - mtebc(pb0ap, 0x04055200); /* 16MB Strata FLASH */ - mtebc(pb0cr, 0xff098000); /* BAS=0xff0 16MB R/W 8-bit */ - mtebc(pb1ap, 0x04055200); /* 512KB Socketed AMD FLASH */ - mtebc(pb1cr, 0xfe018000); /* BAS=0xfe0 1MB R/W 8-bit */ - mtebc(pb6ap, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */ - mtebc(pb6cr, 0xf00da000); /* BAS=0xf00 64MB R/W i6-bit */ - mtebc(pb7ap, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */ - mtebc(pb7cr, 0xf40da000); /* BAS=0xf40 64MB R/W 16-bit */ + mtebc(PB0AP, 0x04055200); /* 16MB Strata FLASH */ + mtebc(PB0CR, 0xff098000); /* BAS=0xff0 16MB R/W 8-bit */ + mtebc(PB1AP, 0x04055200); /* 512KB Socketed AMD FLASH */ + mtebc(PB1CR, 0xfe018000); /* BAS=0xfe0 1MB R/W 8-bit */ + mtebc(PB6AP, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */ + mtebc(PB6CR, 0xf00da000); /* BAS=0xf00 64MB R/W i6-bit */ + mtebc(PB7AP, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */ + mtebc(PB7CR, 0xf40da000); /* BAS=0xf40 64MB R/W 16-bit */ /* * Setup the interrupt controller polarities, triggers, etc. @@ -151,15 +151,15 @@ int pci_pre_init(struct pci_controller * hose) unsigned long strap; /* See if we're supposed to setup the pci */ - mfsdr(sdr_sdstp1, strap); + mfsdr(SDR0_SDSTP1, strap); if ((strap & 0x00010000) == 0) return 0; #if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV) /* Setup System Device Register PCIX0_XCR */ - mfsdr(sdr_xcr, strap); + mfsdr(SDR0_XCR, strap); strap &= 0x0f000000; - mtsdr(sdr_xcr, strap); + mtsdr(SDR0_XCR, strap); #endif return 1; diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c index 9bc390f8379..fc9dfa02c01 100644 --- a/board/zeus/zeus.c +++ b/board/zeus/zeus.c @@ -61,7 +61,7 @@ int board_early_init_f(void) /* * Configure CPC0_PCI to enable PerWE as output */ - mtdcr(cpc0_pci, CPC0_PCI_SPE); + mtdcr(CPC0_PCI, CPC0_PCI_SPE); return 0; } @@ -107,7 +107,7 @@ int misc_init_r(void) /* Re-do sizing to get full correct info */ /* adjust flash start and offset */ - mfebc(pb0cr, pbcr); + mfebc(PB0CR, pbcr); switch (gd->bd->bi_flashsize) { case 1 << 20: size_val = 0; @@ -135,7 +135,7 @@ int misc_init_r(void) break; } pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtebc(pb0cr, pbcr); + mtebc(PB0CR, pbcr); /* * Re-check to get correct base address diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c index abb9941afbd..3ed15092ae9 100644 --- a/common/cmd_reginfo.c +++ b/common/cmd_reginfo.c @@ -108,72 +108,72 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) puts ("\nMemory (SDRAM) Configuration\n" "besra besrsa besrb besrsb bear mcopt1 rtr pmit\n"); - mtdcr(memcfga,mem_besra); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_besrsa); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_besrb); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_besrsb); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_bear); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(SDRAM0_CFGADDR,mem_besra); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_besrsa); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_besrb); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_besrsb); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_bear); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_mcopt1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_rtr); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_pmit); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); puts ("\n" "mb0cf mb1cf mb2cf mb3cf sdtr1 ecccf eccerr\n"); - mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_mb2cf); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_mb3cf); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_ecccf); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_eccerr); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(SDRAM0_CFGADDR,mem_mb0cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_mb1cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_mb2cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_mb3cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_sdtr1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_ecccf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_eccerr); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); printf ("\n\n" "DMA Channels\n" - "dmasr dmasgc dmaadr\n" + "DMASR DMASGC DMAADR\n" "%08x %08x %08x\n" "dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n" "%08x %08x %08x %08x %08x\n" "dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n" "%08x %08x %08x %08x %08x\n", - mfdcr(dmasr), mfdcr(dmasgc),mfdcr(dmaadr), - mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0), - mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1)); + mfdcr(DMASR), mfdcr(DMASGC),mfdcr(DMAADR), + mfdcr(DMACR0), mfdcr(DMACT0),mfdcr(DMADA0), mfdcr(DMASA0), mfdcr(DMASB0), + mfdcr(DMACR1), mfdcr(DMACT1),mfdcr(DMADA1), mfdcr(DMASA1), mfdcr(DMASB1)); printf ( "dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n" "dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n", - mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2), - mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) ); + mfdcr(DMACR2), mfdcr(DMACT2),mfdcr(DMADA2), mfdcr(DMASA2), mfdcr(DMASB2), + mfdcr(DMACR3), mfdcr(DMACT3),mfdcr(DMADA3), mfdcr(DMASA3), mfdcr(DMASB3) ); puts ("\n" "External Bus\n" - "pbear pbesr0 pbesr1 epcr\n"); - mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd)); + "PBEAR PBESR0 PBESR1 EBC0_CFG\n"); + mtdcr(EBC0_CFGADDR,PBEAR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PBESR0); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PBESR1); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,EBC0_CFG); printf ("%08x ", mfdcr(EBC0_CFGDATA)); puts ("\n" - "pb0cr pb0ap pb1cr pb1ap pb2cr pb2ap pb3cr pb3ap\n"); - mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd)); + "PB0CR PB0AP PB1CR PB1AP PB2CR PB2AP PB3CR PB3AP\n"); + mtdcr(EBC0_CFGADDR,PB0CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB0AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB1CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB1AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB2CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB2AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB3CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB3AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); puts ("\n" - "pb4cr pb4ap pb5cr bp5ap pb6cr pb6ap pb7cr pb7ap\n"); - mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb5cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb5ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb6cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb6ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb7cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb7ap); printf ("%08x ", mfdcr(ebccfgd)); + "PB4CR PB4AP PB5CR bp5ap PB6CR PB6AP PB7CR PB7AP\n"); + mtdcr(EBC0_CFGADDR,PB4CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB4AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB5CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB5AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB6CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB6AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB7CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB7AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); puts ("\n\n"); @@ -195,51 +195,51 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) puts ("\nMemory (SDRAM) Configuration\n" "mcopt1 rtr pmit mb0cf mb1cf sdtr1\n"); - mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(SDRAM0_CFGADDR,mem_mcopt1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_rtr); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_pmit); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_mb0cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_mb1cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_sdtr1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); printf ("\n\n" "DMA Channels\n" - "dmasr dmasgc dmaadr\n" "%08x %08x %08x\n" + "DMASR DMASGC DMAADR\n" "%08x %08x %08x\n" "dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n" "%08x %08x %08x %08x %08x\n" "dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n" "%08x %08x %08x %08x %08x\n", - mfdcr(dmasr), mfdcr(dmasgc),mfdcr(dmaadr), - mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0), - mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1)); + mfdcr(DMASR), mfdcr(DMASGC),mfdcr(DMAADR), + mfdcr(DMACR0), mfdcr(DMACT0),mfdcr(DMADA0), mfdcr(DMASA0), mfdcr(DMASB0), + mfdcr(DMACR1), mfdcr(DMACT1),mfdcr(DMADA1), mfdcr(DMASA1), mfdcr(DMASB1)); printf ( "dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n" "dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n", - mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2), - mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) ); + mfdcr(DMACR2), mfdcr(DMACT2),mfdcr(DMADA2), mfdcr(DMASA2), mfdcr(DMASB2), + mfdcr(DMACR3), mfdcr(DMACT3),mfdcr(DMADA3), mfdcr(DMASA3), mfdcr(DMASB3) ); puts ("\n" "External Bus\n" - "pbear pbesr0 pbesr1 epcr\n"); - mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd)); + "PBEAR PBESR0 PBESR1 EBC0_CFG\n"); + mtdcr(EBC0_CFGADDR,PBEAR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PBESR0); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PBESR1); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,EBC0_CFG); printf ("%08x ", mfdcr(EBC0_CFGDATA)); puts ("\n" - "pb0cr pb0ap pb1cr pb1ap pb2cr pb2ap pb3cr pb3ap\n"); - mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd)); + "PB0CR PB0AP PB1CR PB1AP PB2CR PB2AP PB3CR PB3AP\n"); + mtdcr(EBC0_CFGADDR,PB0CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB0AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB1CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB1AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB2CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB2AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB3CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB3AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); puts ("\n" - "pb4cr pb4ap\n"); - mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd)); + "PB4CR PB4AP\n"); + mtdcr(EBC0_CFGADDR,PB4CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB4AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); puts ("\n\n"); #elif defined(CONFIG_5xx) diff --git a/cpu/ppc4xx/40x_spd_sdram.c b/cpu/ppc4xx/40x_spd_sdram.c index 75bd70dc661..83fa709da2d 100644 --- a/cpu/ppc4xx/40x_spd_sdram.c +++ b/cpu/ppc4xx/40x_spd_sdram.c @@ -422,7 +422,7 @@ long int spd_sdram(int(read_spd)(uint addr)) * program all the registers. * -------------------------------------------------------------------*/ -#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) +#define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data) /* disable memcontroller so updates work */ mtsdram0( mem_mcopt1, 0 ); diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index f26fcdaa1e9..c93f23a679f 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -192,8 +192,8 @@ long int spd_sdram(void) { /* * Soft-reset SDRAM controller. */ - mtsdr(sdr_srst, SDR0_SRST_DMC); - mtsdr(sdr_srst, 0x00000000); + mtsdr(SDR0_SRST, SDR0_SRST_DMC); + mtsdr(SDR0_SRST, 0x00000000); #endif /* @@ -848,11 +848,11 @@ static int short_mem_test(void) 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}}; for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) { - mtdcr(memcfga, mem_b0cr + (bxcr_num << 2)); - if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) { + mtdcr(SDRAM0_CFGADDR, mem_b0cr + (bxcr_num << 2)); + if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) { /* Bank is enabled */ membase = (unsigned long*) - (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK); + (mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBA_MASK); /* * Run the short memory test @@ -1086,8 +1086,8 @@ static unsigned long program_bxcr(unsigned long *dimm_populated, * Set the BxCR regs. First, wipe out the bank config registers. */ for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) { - mtdcr(memcfga, mem_b0cr + (bx_cr_num << 2)); - mtdcr(memcfgd, 0x00000000); + mtdcr(SDRAM0_CFGADDR, mem_b0cr + (bx_cr_num << 2)); + mtdcr(SDRAM0_CFGDATA, 0x00000000); bank_parms[bx_cr_num].bank_size_bytes = 0; } @@ -1232,12 +1232,12 @@ static unsigned long program_bxcr(unsigned long *dimm_populated, /* Set the SDRAM0_BxCR regs thanks to sort tables */ for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) { if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) { - mtdcr(memcfga, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2)); - temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK | + mtdcr(SDRAM0_CFGADDR, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2)); + temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK | SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE); temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) | bank_parms[sorted_bank_num[bx_cr_num]].cr; - mtdcr(memcfgd, temp); + mtdcr(SDRAM0_CFGDATA, temp); bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes; debug("SDRAM0_B%dCR=0x%08lx\n", sorted_bank_num[bx_cr_num], temp); } diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c index 184cef5d114..e97f32c7b07 100644 --- a/cpu/ppc4xx/4xx_pci.c +++ b/cpu/ppc4xx/4xx_pci.c @@ -100,7 +100,7 @@ int __pci_pre_init(struct pci_controller *hose) * The arbiter is enabled in this place because of * compatibility reasons. */ - mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_ARBIT_EN); + mtdcr(CPC0_PCI, mfdcr(CPC0_PCI) | CPC0_PCI_ARBIT_EN); #endif /* CONFIG_405EP */ return 1; @@ -118,10 +118,10 @@ ushort pmc405_pci_subsys_deviceid(void); int __is_pci_host(struct pci_controller *hose) { #if defined(CONFIG_405GP) - if (mfdcr(strap) & PSR_PCI_ARBIT_EN) + if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN) return 1; #elif defined (CONFIG_405EP) - if (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN) + if (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN) return 1; #endif return 0; @@ -491,7 +491,7 @@ int pci_440_init (struct pci_controller *hose) #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) unsigned long strap; - mfsdr(sdr_sdstp1,strap); + mfsdr(SDR0_SDSTP1,strap); if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) { printf("PCI: SDR0_STRP1[PISE] not set.\n"); printf("PCI: Configuration aborted.\n"); @@ -500,7 +500,7 @@ int pci_440_init (struct pci_controller *hose) #elif defined(CONFIG_440GP) unsigned long strap; - strap = mfdcr(cpc0_strp1); + strap = mfdcr(CPC0_STRP1); if ((strap & CPC0_STRP1_PISE_MASK) == 0) { printf("PCI: CPC0_STRP1[PISE] not set.\n"); printf("PCI: Configuration aborted.\n"); diff --git a/cpu/ppc4xx/4xx_uart.c b/cpu/ppc4xx/4xx_uart.c index 0780624e4a0..8de65425c97 100644 --- a/cpu/ppc4xx/4xx_uart.c +++ b/cpu/ppc4xx/4xx_uart.c @@ -90,7 +90,7 @@ DECLARE_GLOBAL_DATA_PTR; #define CR0_EXTCLK_ENA 0x00600000 #define CR0_UDIV_POS 16 #define UDIV_SUBTRACT 1 -#define UART0_SDR cntrl0 +#define UART0_SDR CPC0_CR0 #define MFREG(a, d) d = mfdcr(a) #define MTREG(a, d) mtdcr(a, d) #else /* #if defined(CONFIG_440GP) */ @@ -99,18 +99,18 @@ DECLARE_GLOBAL_DATA_PTR; #define CR0_EXTCLK_ENA 0x00800000 #define CR0_UDIV_POS 0 #define UDIV_SUBTRACT 0 -#define UART0_SDR sdr_uart0 -#define UART1_SDR sdr_uart1 +#define UART0_SDR SDR0_UART0 +#define UART1_SDR SDR0_UART1 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define UART2_SDR sdr_uart2 +#define UART2_SDR SDR0_UART2 #endif #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define UART3_SDR sdr_uart3 +#define UART3_SDR SDR0_UART3 #endif #define MFREG(a, d) mfsdr(a, d) #define MTREG(a, d) mtsdr(a, d) @@ -130,8 +130,8 @@ DECLARE_GLOBAL_DATA_PTR; #define CR0_EXTCLK_ENA 0x00800000 #define CR0_UDIV_POS 0 #define UDIV_SUBTRACT 0 -#define UART0_SDR sdr_uart0 -#define UART1_SDR sdr_uart1 +#define UART0_SDR SDR0_UART0 +#define UART1_SDR SDR0_UART1 #else /* CONFIG_405GP || CONFIG_405CR */ #define UART0_BASE 0xef600300 #define UART1_BASE 0xef600400 @@ -282,7 +282,7 @@ static void serial_divs (int baudrate, unsigned long *pudiv, u32 reg; /* check the pll feedback source */ - mfcpr(cprpllc, cpr_pllc); + mfcpr(CPR0_PLLC, cpr_pllc); get_sys_info(&sysinfo); @@ -312,10 +312,10 @@ static void serial_divs (int baudrate, unsigned long *pudiv, } *pudiv = udiv; - mfcpr(cprperd0, reg); + mfcpr(CPC0_PERD0, reg); reg &= ~0x0000ffff; reg |= ((udiv - 0) << 8) | (udiv - 0); - mtcpr(cprperd0, reg); + mtcpr(CPC0_PERD0, reg); *pbdiv = div / udiv; } #endif /* defined(CONFIG_440) && !defined(CONFIG_SYS_EXT_SERIAL_CLK) */ @@ -412,7 +412,7 @@ int serial_init_dev (unsigned long base) clk = tmp = reg = 0; #else #ifdef CONFIG_405EP - reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK); + reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK); clk = gd->cpu_clk; tmp = CONFIG_SYS_BASE_BAUD * 16; udiv = (clk + tmp / 2) / tmp; @@ -420,9 +420,9 @@ int serial_init_dev (unsigned long base) udiv = UDIV_MAX; reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */ reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */ - mtdcr (cpc0_ucr, reg); + mtdcr (CPC0_UCR, reg); #else /* CONFIG_405EP */ - reg = mfdcr(cntrl0) & ~CR0_MASK; + reg = mfdcr(CPC0_CR0) & ~CR0_MASK; #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK clk = CONFIG_SYS_EXT_SERIAL_CLOCK; udiv = 1; @@ -439,7 +439,7 @@ int serial_init_dev (unsigned long base) #endif #endif reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ - mtdcr (cntrl0, reg); + mtdcr (CPC0_CR0, reg); #endif /* CONFIG_405EP */ tmp = gd->baudrate * udiv * 16; bdiv = (clk + tmp / 2) / tmp; diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index e9861abe762..22879046694 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -64,7 +64,7 @@ int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num"))); static int pci_async_enabled(void) { #if defined(CONFIG_405GP) - return (mfdcr(strap) & PSR_PCI_ASYNC_EN); + return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN); #endif #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ @@ -72,7 +72,7 @@ static int pci_async_enabled(void) defined(CONFIG_460EX) || defined(CONFIG_460GT) unsigned long val; - mfsdr(sdr_sdstp1, val); + mfsdr(SDR0_SDSTP1, val); return (val & SDR0_SDSTP1_PAME_MASK); #endif } @@ -84,21 +84,21 @@ static int pci_async_enabled(void) static int pci_arbiter_enabled(void) { #if defined(CONFIG_405GP) - return (mfdcr(strap) & PSR_PCI_ARBIT_EN); + return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN); #endif #if defined(CONFIG_405EP) - return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN); + return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN); #endif #if defined(CONFIG_440GP) - return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK); + return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK); #endif #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) unsigned long val; - mfsdr(sdr_xcr, val); + mfsdr(SDR0_XCR, val); return (val & 0x80000000); #endif #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ @@ -106,7 +106,7 @@ static int pci_arbiter_enabled(void) defined(CONFIG_460EX) || defined(CONFIG_460GT) unsigned long val; - mfsdr(sdr_pci0, val); + mfsdr(SDR0_PCI0, val); return (val & 0x80000000); #endif } @@ -118,11 +118,11 @@ static int pci_arbiter_enabled(void) static int i2c_bootrom_enabled(void) { #if defined(CONFIG_405EP) - return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP); + return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP); #else unsigned long val; - mfsdr(sdr_sdcs, val); + mfsdr(SDR0_SDCS0, val); return (val & SDR0_SDCS_SDD); #endif } @@ -256,7 +256,7 @@ static int bootstrap_option(void) { unsigned long val; - mfsdr(SDR_PINSTP, val); + mfsdr(SDR0_PINSTP, val); return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT); } #endif /* SDR0_PINSTP_SHIFT */ @@ -265,13 +265,13 @@ static int bootstrap_option(void) #if defined(CONFIG_440) static int do_chip_reset (unsigned long sys0, unsigned long sys1) { - /* Changes to cpc0_sys0 and cpc0_sys1 require chip + /* Changes to CPC0_SYS0 and CPC0_SYS1 require chip * reset. */ - mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */ - mtdcr (cpc0_sys0, sys0); - mtdcr (cpc0_sys1, sys1); - mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */ + mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000); /* Set SWE */ + mtdcr (CPC0_SYS0, sys0); + mtdcr (CPC0_SYS1, sys1); + mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */ mtspr (SPRN_DBCR0, 0x20000000); /* Reset the chip */ return 1; @@ -410,13 +410,13 @@ int checkcpu (void) case PVR_440GP_RB: puts("GP Rev. B"); /* See errata 1.12: CHIP_4 */ - if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) || - (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){ + if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) || + (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){ puts ( "\n\t CPC0_SYSx DCRs corrupted. " "Resetting chip ...\n"); udelay( 1000 * 1000 ); /* Give time for serial buf to clear */ - do_chip_reset ( mfdcr(cpc0_strp0), - mfdcr(cpc0_strp1) ); + do_chip_reset ( mfdcr(CPC0_STRP0), + mfdcr(CPC0_STRP1) ); } break; diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 65092fb8e47..bd06b9bc22c 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -58,17 +58,17 @@ void reconfigure_pll(u32 new_cpu_freq) target_perdv0 = 4; target_spcid0 = 4; - mfcpr(clk_primbd, reg); + mfcpr(CPR0_PRIMBD, reg); temp = (reg & PRBDV_MASK) >> 24; prbdv0 = temp ? temp : 8; if (prbdv0 != target_prbdv0) { reg &= ~PRBDV_MASK; reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24); - mtcpr(clk_primbd, reg); + mtcpr(CPR0_PRIMBD, reg); reset_needed = 1; } - mfcpr(clk_plld, reg); + mfcpr(CPR0_PLLD, reg); temp = (reg & PLLD_FWDVA_MASK) >> 16; fwdva = temp ? temp : 16; @@ -89,35 +89,35 @@ void reconfigure_pll(u32 new_cpu_freq) ((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) | ((target_fbdv == 32 ? 0 : target_fbdv) << 24) | (target_lfbdv == 64 ? 0 : target_lfbdv); - mtcpr(clk_plld, reg); + mtcpr(CPR0_PLLD, reg); reset_needed = 1; } - mfcpr(clk_perd, reg); + mfcpr(CPR0_PERD, reg); perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24; if (perdv0 != target_perdv0) { reg &= ~CPR0_PERD_PERDV0_MASK; reg |= (target_perdv0 << 24); - mtcpr(clk_perd, reg); + mtcpr(CPR0_PERD, reg); reset_needed = 1; } - mfcpr(clk_spcid, reg); + mfcpr(CPR0_SPCID, reg); temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24; spcid0 = temp ? temp : 4; if (spcid0 != target_spcid0) { reg &= ~CPR0_SPCID_SPCIDV0_MASK; reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24); - mtcpr(clk_spcid, reg); + mtcpr(CPR0_SPCID, reg); reset_needed = 1; } /* Set reload inhibit so configuration will persist across * processor resets */ - mfcpr(clk_icfg, reg); + mfcpr(CPR0_ICFG, reg); reg &= ~CPR0_ICFG_RLI_MASK; reg |= 1 << 31; - mtcpr(clk_icfg, reg); + mtcpr(CPR0_ICFG, reg); } /* Reset processor if configuration changed */ @@ -173,7 +173,7 @@ cpu_init_f (void) /* * Set EMAC noise filter bits */ - mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE); + mtdcr(CPC0_EPCTL, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE); #endif /* CONFIG_405EP */ #if defined(CONFIG_SYS_4xx_GPIO_TABLE) @@ -204,43 +204,43 @@ cpu_init_f (void) asm volatile("2: bdnz 2b" ::: "ctr", "cr0"); #endif - mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP); - mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR); + mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP); + mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR); #endif #if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1)) - mtebc(pb1ap, CONFIG_SYS_EBC_PB1AP); - mtebc(pb1cr, CONFIG_SYS_EBC_PB1CR); + mtebc(PB1AP, CONFIG_SYS_EBC_PB1AP); + mtebc(PB1CR, CONFIG_SYS_EBC_PB1CR); #endif #if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2)) - mtebc(pb2ap, CONFIG_SYS_EBC_PB2AP); - mtebc(pb2cr, CONFIG_SYS_EBC_PB2CR); + mtebc(PB2AP, CONFIG_SYS_EBC_PB2AP); + mtebc(PB2CR, CONFIG_SYS_EBC_PB2CR); #endif #if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3)) - mtebc(pb3ap, CONFIG_SYS_EBC_PB3AP); - mtebc(pb3cr, CONFIG_SYS_EBC_PB3CR); + mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); + mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR); #endif #if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4)) - mtebc(pb4ap, CONFIG_SYS_EBC_PB4AP); - mtebc(pb4cr, CONFIG_SYS_EBC_PB4CR); + mtebc(PB4AP, CONFIG_SYS_EBC_PB4AP); + mtebc(PB4CR, CONFIG_SYS_EBC_PB4CR); #endif #if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5)) - mtebc(pb5ap, CONFIG_SYS_EBC_PB5AP); - mtebc(pb5cr, CONFIG_SYS_EBC_PB5CR); + mtebc(PB5AP, CONFIG_SYS_EBC_PB5AP); + mtebc(PB5CR, CONFIG_SYS_EBC_PB5CR); #endif #if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6)) - mtebc(pb6ap, CONFIG_SYS_EBC_PB6AP); - mtebc(pb6cr, CONFIG_SYS_EBC_PB6CR); + mtebc(PB6AP, CONFIG_SYS_EBC_PB6AP); + mtebc(PB6CR, CONFIG_SYS_EBC_PB6CR); #endif #if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7)) - mtebc(pb7ap, CONFIG_SYS_EBC_PB7AP); - mtebc(pb7cr, CONFIG_SYS_EBC_PB7CR); + mtebc(PB7AP, CONFIG_SYS_EBC_PB7AP); + mtebc(PB7CR, CONFIG_SYS_EBC_PB7CR); #endif #if defined (CONFIG_SYS_EBC_CFG) @@ -276,9 +276,9 @@ cpu_init_f (void) * Compatibility mode and Ethernet Clock select are not * correct in the manual */ - mfsdr(sdr_mfr, val); + mfsdr(SDR0_MFR, val); val &= ~0x10000000; - mtsdr(sdr_mfr,val); + mtsdr(SDR0_MFR,val); #endif /* CONFIG_440GX */ #if defined(CONFIG_460EX) @@ -304,10 +304,10 @@ cpu_init_f (void) /* * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read */ - mtdcr(plb0_acr, (mfdcr(plb0_acr) & ~plb0_acr_rdp_mask) | - plb0_acr_rdp_4deep); - mtdcr(plb1_acr, (mfdcr(plb1_acr) & ~plb1_acr_rdp_mask) | - plb1_acr_rdp_4deep); + mtdcr(PLB0_ACR, (mfdcr(PLB0_ACR) & ~PLB0_ACR_RDP_MASK) | + PLB0_ACR_RDP_4DEEP); + mtdcr(PLB1_ACR, (mfdcr(PLB1_ACR) & ~PLB1_ACR_RDP_MASK) | + PLB1_ACR_RDP_4DEEP); #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */ } @@ -324,7 +324,7 @@ int cpu_init_r (void) * for compatibility to existing PPC405GP designs. */ if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) { - mtdcr(ecr, 0x60606000); + mtdcr(CPC0_ECR, 0x60606000); } #endif /* defined(CONFIG_405GP) */ diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c index ba5c120ad7f..496e0285b5b 100644 --- a/cpu/ppc4xx/fdt.c +++ b/cpu/ppc4xx/fdt.c @@ -51,8 +51,8 @@ void __ft_board_setup(void *blob, bd_t *bd) * peripheral banks into the OPB/PLB address space */ for (i = 0; i < EBC_NUM_BANKS; i++) { - mtdcr(ebccfga, EBC_BXCR(i)); - bxcr = mfdcr(ebccfgd); + mtdcr(EBC0_CFGADDR, EBC_BXCR(i)); + bxcr = mfdcr(EBC0_CFGDATA); if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) { *p++ = i; diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index 4365df9879d..5a3336e3c8a 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -375,8 +375,8 @@ phys_size_t initdram(int board_type) /* * Soft-reset SDRAM controller. */ - mtsdr(sdr_srst, SDR0_SRST_DMC); - mtsdr(sdr_srst, 0x00000000); + mtsdr(SDR0_SRST, SDR0_SRST_DMC); + mtsdr(SDR0_SRST, 0x00000000); #endif for (i=0; i> 4); sysInfo->pllFwdDivA = get_cpr0_fwdv(temp); @@ -342,7 +342,7 @@ void get_sys_info (sys_info_t *sysInfo) */ /* Decode CPR0_PLLD0 for divisors */ - mfcpr(clk_plld, reg); + mfcpr(CPR0_PLLD, reg); temp = (reg & PLLD_FWDVA_MASK) >> 16; sysInfo->pllFwdDivA = temp ? temp : 16; temp = (reg & PLLD_FWDVB_MASK) >> 8; @@ -351,28 +351,28 @@ void get_sys_info (sys_info_t *sysInfo) sysInfo->pllFbkDiv = temp ? temp : 32; lfdiv = reg & PLLD_LFBDV_MASK; - mfcpr(clk_opbd, reg); + mfcpr(CPR0_OPBD, reg); temp = (reg & OPBDDV_MASK) >> 24; sysInfo->pllOpbDiv = temp ? temp : 4; - mfcpr(clk_perd, reg); + mfcpr(CPR0_PERD, reg); temp = (reg & PERDV_MASK) >> 24; sysInfo->pllExtBusDiv = temp ? temp : 8; - mfcpr(clk_primbd, reg); + mfcpr(CPR0_PRIMBD, reg); temp = (reg & PRBDV_MASK) >> 24; prbdv0 = temp ? temp : 8; - mfcpr(clk_spcid, reg); + mfcpr(CPR0_SPCID, reg); temp = (reg & SPCID_MASK) >> 24; sysInfo->pllPciDiv = temp ? temp : 4; /* Calculate 'M' based on feedback source */ - mfsdr(sdr_sdstp0, reg); + mfsdr(SDR0_SDSTP0, reg); temp = (reg & PLLSYS0_SEL_MASK) >> 27; if (temp == 0) { /* PLL output */ /* Figure which pll to use */ - mfcpr(clk_pllc, reg); + mfcpr(CPR0_PLLC, reg); temp = (reg & PLLC_SRC_MASK) >> 29; if (!temp) /* PLLOUTA */ m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA; @@ -426,7 +426,7 @@ void get_sys_info (sys_info_t * sysInfo) unsigned long m; /* Extract configured divisors */ - strp0 = mfdcr( cpc0_strp0 ); + strp0 = mfdcr( CPC0_STRP0 ); sysInfo->pllFwdDivA = 8 - ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 15); sysInfo->pllFwdDivB = 8 - ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 12); temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 18; @@ -484,8 +484,8 @@ void get_sys_info (sys_info_t * sysInfo) #endif /* Extract configured divisors */ - mfsdr( sdr_sdstp0,strp0 ); - mfsdr( sdr_sdstp1,strp1 ); + mfsdr( SDR0_SDSTP0,strp0 ); + mfsdr( SDR0_SDSTP1,strp1 ); temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 8); sysInfo->pllFwdDivA = temp ? temp : 16 ; @@ -531,7 +531,7 @@ void get_sys_info (sys_info_t * sysInfo) /* Determine PCI Clock Period */ pci_clock_per = determine_pci_clock_per(); sysInfo->freqPCI = (ONE_BILLION/pci_clock_per) * 1000; - mfsdr(sdr_ddr0, sdr_ddrpll); + mfsdr(SDR0_DDR0, sdr_ddrpll); sysInfo->freqDDR = ((sysInfo->freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll)); #endif @@ -794,8 +794,8 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) /* * Read PLL Mode registers */ - pllmr0 = mfdcr (cpc0_pllmr0); - pllmr1 = mfdcr (cpc0_pllmr1); + pllmr0 = mfdcr (CPC0_PLLMR0); + pllmr1 = mfdcr (CPC0_PLLMR1); /* * Determine forward divider A @@ -918,8 +918,8 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) /* * Read PLL Mode registers */ - mfcpr(cprplld, cpr_plld); - mfcpr(cprpllc, cpr_pllc); + mfcpr(CPR0_PLLD, cpr_plld); + mfcpr(CPR0_PLLC, cpr_pllc); /* * Determine forward divider A @@ -943,7 +943,7 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) /* * Read CPR_PRIMAD register */ - mfcpr(cprprimad, cpr_primad); + mfcpr(CPC0_PRIMAD, cpr_primad); /* * Determine PLB_DIV. @@ -1074,7 +1074,7 @@ void get_sys_info (sys_info_t * sysInfo) }; unsigned char sel, cpudv0, plb2xDiv; - mfcpr(cpr0_plld, tmp); + mfcpr(CPR0_PLLD, tmp); /* * Determine forward divider A @@ -1094,29 +1094,29 @@ void get_sys_info (sys_info_t * sysInfo) /* * Determine PERDV0 */ - mfcpr(cpr0_perd, tmp); + mfcpr(CPR0_PERD, tmp); tmp = (tmp >> 24) & 0x03; sysInfo->pllExtBusDiv = (tmp == 0) ? 4 : tmp; /* * Determine OPBDV0 */ - mfcpr(cpr0_opbd, tmp); + mfcpr(CPR0_OPBD, tmp); tmp = (tmp >> 24) & 0x03; sysInfo->pllOpbDiv = (tmp == 0) ? 4 : tmp; /* Determine PLB2XDV0 */ - mfcpr(cpr0_plbd, tmp); + mfcpr(CPR0_PLBD, tmp); tmp = (tmp >> 16) & 0x07; plb2xDiv = (tmp == 0) ? 8 : tmp; /* Determine CPUDV0 */ - mfcpr(cpr0_cpud, tmp); + mfcpr(CPR0_CPUD, tmp); tmp = (tmp >> 24) & 0x07; cpudv0 = (tmp == 0) ? 8 : tmp; /* Determine SEL(5:7) in CPR0_PLLC */ - mfcpr(cpr0_pllc, tmp); + mfcpr(CPR0_PLLC, tmp); sel = (tmp >> 24) & 0x07; /* diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index f967d8464cf..287a912246a 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -83,64 +83,64 @@ #ifdef CONFIG_SYS_INIT_DCACHE_CS # if (CONFIG_SYS_INIT_DCACHE_CS == 0) -# define PBxAP pb0ap -# define PBxCR pb0cr +# define PBxAP PB1AP +# define PBxCR PB0CR # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR)) # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR # endif # endif # if (CONFIG_SYS_INIT_DCACHE_CS == 1) -# define PBxAP pb1ap -# define PBxCR pb1cr +# define PBxAP PB1AP +# define PBxCR PB1CR # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR)) # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR # endif # endif # if (CONFIG_SYS_INIT_DCACHE_CS == 2) -# define PBxAP pb2ap -# define PBxCR pb2cr +# define PBxAP PB2AP +# define PBxCR PB2CR # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR)) # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR # endif # endif # if (CONFIG_SYS_INIT_DCACHE_CS == 3) -# define PBxAP pb3ap -# define PBxCR pb3cr +# define PBxAP PB3AP +# define PBxCR PB3CR # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR)) # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR # endif # endif # if (CONFIG_SYS_INIT_DCACHE_CS == 4) -# define PBxAP pb4ap -# define PBxCR pb4cr +# define PBxAP PB4AP +# define PBxCR PB4CR # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR)) # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR # endif # endif # if (CONFIG_SYS_INIT_DCACHE_CS == 5) -# define PBxAP pb5ap -# define PBxCR pb5cr +# define PBxAP PB5AP +# define PBxCR PB5CR # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR)) # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR # endif # endif # if (CONFIG_SYS_INIT_DCACHE_CS == 6) -# define PBxAP pb6ap -# define PBxCR pb6cr +# define PBxAP PB6AP +# define PBxCR PB6CR # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR)) # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR # endif # endif # if (CONFIG_SYS_INIT_DCACHE_CS == 7) -# define PBxAP pb7ap -# define PBxCR pb7cr +# define PBxAP PB7AP +# define PBxCR PB7CR # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR)) # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR @@ -998,7 +998,7 @@ _start: /*----------------------------------------------------------------------- */ addis r3,r0, 0xFFFF /* Clear all existing DMA status */ ori r3,r3, 0xFFFF - mtdcr dmasr, r3 + mtdcr DMASR, r3 bl ppc405ep_init /* do ppc405ep specific init */ #endif /* CONFIG_405EP */ @@ -1015,21 +1015,21 @@ _start: lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ - mtdcr ocmplb3cr1,r3 /* Set PLB Access */ + mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */ ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ - mtdcr ocmplb3cr2,r3 /* Set PLB Access */ + mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */ isync lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ - mtdcr ocmdscr1, r3 /* Set Data Side */ - mtdcr ocmiscr1, r3 /* Set Instruction Side */ + mtdcr OCM0_DSRC1, r3 /* Set Data Side */ + mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */ ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ - mtdcr ocmdscr2, r3 /* Set Data Side */ - mtdcr ocmiscr2, r3 /* Set Instruction Side */ + mtdcr OCM0_DSRC2, r3 /* Set Data Side */ + mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */ addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */ - mtdcr ocmdsisdpc,r3 + mtdcr OCM0_DISDPC,r3 isync #else /* CONFIG_405EZ */ @@ -1039,19 +1039,19 @@ _start: /* Setup OCM */ lis r0, 0x7FFF ori r0, r0, 0xFFFF - mfdcr r3, ocmiscntl /* get instr-side IRAM config */ - mfdcr r4, ocmdscntl /* get data-side IRAM config */ + mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */ + mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */ and r3, r3, r0 /* disable data-side IRAM */ and r4, r4, r0 /* disable data-side IRAM */ - mtdcr ocmiscntl, r3 /* set instr-side IRAM config */ - mtdcr ocmdscntl, r4 /* set data-side IRAM config */ + mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */ + mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */ isync lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l - mtdcr ocmdsarc, r3 + mtdcr OCM0_DSARC, r3 addis r4, 0, 0xC000 /* OCM data area enabled */ - mtdcr ocmdscntl, r4 + mtdcr OCM0_DSCNTL, r4 isync #endif /* CONFIG_405EZ */ #endif @@ -1061,16 +1061,16 @@ _start: /*----------------------------------------------------------------------- */ #ifdef CONFIG_SYS_INIT_DCACHE_CS li r4, PBxAP - mtdcr ebccfga, r4 + mtdcr EBC0_CFGADDR, r4 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l - mtdcr ebccfgd, r4 + mtdcr EBC0_CFGDATA, r4 addi r4, 0, PBxCR - mtdcr ebccfga, r4 + mtdcr EBC0_CFGADDR, r4 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l - mtdcr ebccfgd, r4 + mtdcr EBC0_CFGDATA, r4 /* * Enable the data cache for the 128MB storage access control region @@ -1428,16 +1428,16 @@ relocate_code: /* Restore the EBC parameters */ li r3, PBxAP - mtdcr ebccfga, r3 + mtdcr EBC0_CFGADDR, r3 lis r3, PBxAP_VAL@h ori r3, r3, PBxAP_VAL@l - mtdcr ebccfgd, r3 + mtdcr EBC0_CFGDATA, r3 li r3, PBxCR - mtdcr ebccfga, r3 + mtdcr EBC0_CFGADDR, r3 lis r3, PBxCR_VAL@h ori r3, r3, PBxCR_VAL@l - mtdcr ebccfgd, r3 + mtdcr EBC0_CFGDATA, r3 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ /* Restore registers */ @@ -1860,38 +1860,38 @@ ppc405ep_init: ori r4,r4,CONFIG_SYS_GPIO0_TCR@l stw r4,0(r3) - li r3,pb1ap /* program EBC bank 1 for RTC access */ - mtdcr ebccfga,r3 + li r3,PB1AP /* program EBC bank 1 for RTC access */ + mtdcr EBC0_CFGADDR,r3 lis r3,CONFIG_SYS_EBC_PB1AP@h ori r3,r3,CONFIG_SYS_EBC_PB1AP@l - mtdcr ebccfgd,r3 - li r3,pb1cr - mtdcr ebccfga,r3 + mtdcr EBC0_CFGDATA,r3 + li r3,PB1CR + mtdcr EBC0_CFGADDR,r3 lis r3,CONFIG_SYS_EBC_PB1CR@h ori r3,r3,CONFIG_SYS_EBC_PB1CR@l - mtdcr ebccfgd,r3 + mtdcr EBC0_CFGDATA,r3 - li r3,pb1ap /* program EBC bank 1 for RTC access */ - mtdcr ebccfga,r3 + li r3,PB1AP /* program EBC bank 1 for RTC access */ + mtdcr EBC0_CFGADDR,r3 lis r3,CONFIG_SYS_EBC_PB1AP@h ori r3,r3,CONFIG_SYS_EBC_PB1AP@l - mtdcr ebccfgd,r3 - li r3,pb1cr - mtdcr ebccfga,r3 + mtdcr EBC0_CFGDATA,r3 + li r3,PB1CR + mtdcr EBC0_CFGADDR,r3 lis r3,CONFIG_SYS_EBC_PB1CR@h ori r3,r3,CONFIG_SYS_EBC_PB1CR@l - mtdcr ebccfgd,r3 + mtdcr EBC0_CFGDATA,r3 - li r3,pb4ap /* program EBC bank 4 for FPGA access */ - mtdcr ebccfga,r3 + li r3,PB4AP /* program EBC bank 4 for FPGA access */ + mtdcr EBC0_CFGADDR,r3 lis r3,CONFIG_SYS_EBC_PB4AP@h ori r3,r3,CONFIG_SYS_EBC_PB4AP@l - mtdcr ebccfgd,r3 - li r3,pb4cr - mtdcr ebccfga,r3 + mtdcr EBC0_CFGDATA,r3 + li r3,PB4CR + mtdcr EBC0_CFGADDR,r3 lis r3,CONFIG_SYS_EBC_PB4CR@h ori r3,r3,CONFIG_SYS_EBC_PB4CR@l - mtdcr ebccfgd,r3 + mtdcr EBC0_CFGDATA,r3 #endif /* diff --git a/cpu/ppc4xx/usbdev.c b/cpu/ppc4xx/usbdev.c index faf7f0878ff..5bb4f3ce632 100644 --- a/cpu/ppc4xx/usbdev.c +++ b/cpu/ppc4xx/usbdev.c @@ -206,14 +206,14 @@ void usb_dev_init() #ifdef USB_2_0_DEVICE printf("USB 2.0 Device init\n"); /*select 2.0 device */ - mtsdr(sdr_usb0, 0x0); /* 2.0 */ + mtsdr(SDR0_USB0, 0x0); /* 2.0 */ /*usb dev init */ *(unsigned char *)USB2D0_POWER_8 = 0xa1; /* 2.0 */ #else printf("USB 1.1 Device init\n"); /*select 1.1 device */ - mtsdr(sdr_usb0, 0x2); /* 1.1 */ + mtsdr(SDR0_USB0, 0x2); /* 1.1 */ /*usb dev init */ *(unsigned char *)USB2D0_POWER_8 = 0xc0; /* 1.1 */ diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c index 0891936f00d..0dd67895827 100644 --- a/drivers/mtd/nand/ndfc.c +++ b/drivers/mtd/nand/ndfc.c @@ -207,8 +207,8 @@ int board_nand_init(struct nand_chip *nand) */ mtebc(EBC0_CFG, 0xb8400000); - mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR); - mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP); + mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR); + mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP); #endif chip++; diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c index 329eef07df5..afd108415b9 100644 --- a/drivers/net/4xx_enet.c +++ b/drivers/net/4xx_enet.c @@ -319,9 +319,9 @@ static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p) defined(CONFIG_405EX) u32 val; - mfsdr(sdr_mfr, val); + mfsdr(SDR0_MFR, val); val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); - mtsdr(sdr_mfr, val); + mtsdr(SDR0_MFR, val); #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) u32 val; @@ -338,9 +338,9 @@ static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p) defined(CONFIG_405EX) u32 val; - mfsdr(sdr_mfr, val); + mfsdr(SDR0_MFR, val); val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); - mtsdr(sdr_mfr, val); + mtsdr(SDR0_MFR, val); #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) u32 val; @@ -364,14 +364,14 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) /* 1st reset MAL channel */ /* Note: writing a 0 to a channel has no effect */ #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) - mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2))); + mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> (hw_p->devnum * 2))); #else - mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum)); + mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> hw_p->devnum)); #endif - mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum)); + mtdcr (MAL0_RXCARR, (MAL_CR_MMSR >> hw_p->devnum)); /* wait for reset */ - while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) { + while (mfdcr (MAL0_RXCASR) & (MAL_CR_MMSR >> hw_p->devnum)) { udelay (1000); /* Delay 1 MS so as not to hammer the register */ val--; if (val == 0) @@ -408,7 +408,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) unsigned long zmiifer; unsigned long rmiifer; - mfsdr(sdr_pfc1, pfc1); + mfsdr(SDR0_PFC1, pfc1); pfc1 = SDR0_PFC1_EPS_DECODE(pfc1); zmiifer = 0; @@ -498,7 +498,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) unsigned long zmiifer=0x0; unsigned long pfc1; - mfsdr(sdr_pfc1, pfc1); + mfsdr(SDR0_PFC1, pfc1); pfc1 &= SDR0_PFC1_SELECT_MASK; switch (pfc1) { @@ -1240,13 +1240,13 @@ get_speed: !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \ !defined(CONFIG_460EX) && !defined(CONFIG_460GT) #if defined(CONFIG_440EP) || defined(CONFIG_440GR) - mfsdr(sdr_mfr, reg); + mfsdr(SDR0_MFR, reg); if (speed == 100) { reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M; } else { reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; } - mtsdr(sdr_mfr, reg); + mtsdr(SDR0_MFR, reg); #endif /* Set ZMII/RGMII speed according to the phy link speed */ @@ -1302,13 +1302,13 @@ get_speed: defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) - mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | + mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000); #else - mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); + mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); /* Errata 1.12: MAL_1 -- Disable MAL bursting */ if (get_pvr() == PVR_440GP_RB) { - mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB); + mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB); } #endif @@ -1398,86 +1398,86 @@ get_speed: case 1: /* setup MAL tx & rx channel pointers */ #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR) - mtdcr (maltxctp2r, hw_p->tx_phys); + mtdcr (MAL0_TXCTP2R, hw_p->tx_phys); #else - mtdcr (maltxctp1r, hw_p->tx_phys); + mtdcr (MAL0_TXCTP1R, hw_p->tx_phys); #endif #if defined(CONFIG_440) - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); #endif #if defined(CONFIG_460EX) || defined(CONFIG_460GT) - mtdcr (malrxctp8r, hw_p->rx_phys); + mtdcr (MAL0_RXCTP8R, hw_p->rx_phys); /* set RX buffer size */ - mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16); + mtdcr (MAL0_RCBS8, ENET_MAX_MTU_ALIGNED / 16); #else - mtdcr (malrxctp1r, hw_p->rx_phys); + mtdcr (MAL0_RXCTP1R, hw_p->rx_phys); /* set RX buffer size */ - mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16); + mtdcr (MAL0_RCBS1, ENET_MAX_MTU_ALIGNED / 16); #endif break; #if defined (CONFIG_440GX) case 2: /* setup MAL tx & rx channel pointers */ - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); - mtdcr (maltxctp2r, hw_p->tx_phys); - mtdcr (malrxctp2r, hw_p->rx_phys); + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); + mtdcr (MAL0_TXCTP2R, hw_p->tx_phys); + mtdcr (MAL0_RXCTP2R, hw_p->rx_phys); /* set RX buffer size */ - mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16); + mtdcr (MAL0_RCBS2, ENET_MAX_MTU_ALIGNED / 16); break; case 3: /* setup MAL tx & rx channel pointers */ - mtdcr (maltxbattr, 0x0); - mtdcr (maltxctp3r, hw_p->tx_phys); - mtdcr (malrxbattr, 0x0); - mtdcr (malrxctp3r, hw_p->rx_phys); + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_TXCTP3R, hw_p->tx_phys); + mtdcr (MAL0_RXBADDR, 0x0); + mtdcr (MAL0_RXCTP3R, hw_p->rx_phys); /* set RX buffer size */ - mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16); + mtdcr (MAL0_RCBS3, ENET_MAX_MTU_ALIGNED / 16); break; #endif /* CONFIG_440GX */ #if defined (CONFIG_460GT) case 2: /* setup MAL tx & rx channel pointers */ - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); - mtdcr (maltxctp2r, hw_p->tx_phys); - mtdcr (malrxctp16r, hw_p->rx_phys); + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); + mtdcr (MAL0_TXCTP2R, hw_p->tx_phys); + mtdcr (MAL0_RXCTP16R, hw_p->rx_phys); /* set RX buffer size */ - mtdcr (malrcbs16, ENET_MAX_MTU_ALIGNED / 16); + mtdcr (MAL0_RCBS16, ENET_MAX_MTU_ALIGNED / 16); break; case 3: /* setup MAL tx & rx channel pointers */ - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); - mtdcr (maltxctp3r, hw_p->tx_phys); - mtdcr (malrxctp24r, hw_p->rx_phys); + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); + mtdcr (MAL0_TXCTP3R, hw_p->tx_phys); + mtdcr (MAL0_RXCTP24R, hw_p->rx_phys); /* set RX buffer size */ - mtdcr (malrcbs24, ENET_MAX_MTU_ALIGNED / 16); + mtdcr (MAL0_RCBS24, ENET_MAX_MTU_ALIGNED / 16); break; #endif /* CONFIG_460GT */ case 0: default: /* setup MAL tx & rx channel pointers */ #if defined(CONFIG_440) - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); #endif - mtdcr (maltxctp0r, hw_p->tx_phys); - mtdcr (malrxctp0r, hw_p->rx_phys); + mtdcr (MAL0_TXCTP0R, hw_p->tx_phys); + mtdcr (MAL0_RXCTP0R, hw_p->rx_phys); /* set RX buffer size */ - mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16); + mtdcr (MAL0_RCBS0, ENET_MAX_MTU_ALIGNED / 16); break; } /* Enable MAL transmit and receive channels */ #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) - mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2))); + mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (hw_p->devnum*2))); #else - mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); + mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> hw_p->devnum)); #endif - mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); + mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> hw_p->devnum)); /* set transmit enable & receive enable */ out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); @@ -1493,9 +1493,9 @@ get_speed: defined(CONFIG_440SP) || defined(CONFIG_440SPE) unsigned long pfc1; - mfsdr (sdr_pfc1, pfc1); + mfsdr (SDR0_PFC1, pfc1); pfc1 |= SDR0_PFC1_EM_1000; - mtsdr (sdr_pfc1, pfc1); + mtsdr (SDR0_PFC1, pfc1); #endif mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST; } else if (speed == _100BASET) @@ -1665,7 +1665,7 @@ int enetInt (struct eth_device *dev) /* look at MAL and EMAC error interrupts */ if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) { /* we have a MAL error interrupt */ - mal_isr = mfdcr(malesr); + mal_isr = mfdcr(MAL0_ESR); mal_err(dev, mal_isr, uic_mal_err, MAL_UIC_DEF, MAL_UIC_ERR); @@ -1691,8 +1691,8 @@ int enetInt (struct eth_device *dev) /* handle MAX TX EOB interrupt from a tx */ if (uic_mal & UIC_MAL_TXEOB) { /* clear MAL interrupt status bits */ - mal_eob = mfdcr(maltxeobisr); - mtdcr(maltxeobisr, mal_eob); + mal_eob = mfdcr(MAL0_TXEOBISR); + mtdcr(MAL0_TXEOBISR, mal_eob); mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB); /* indicate that we serviced an interrupt */ @@ -1703,7 +1703,7 @@ int enetInt (struct eth_device *dev) /* handle MAL RX EOB interupt from a receive */ /* check for EOB on valid channels */ if (uic_mal & UIC_MAL_RXEOB) { - mal_eob = mfdcr(malrxeobisr); + mal_eob = mfdcr(MAL0_RXEOBISR); if (mal_eob & (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) { /* push packet to upper layer */ @@ -1731,11 +1731,11 @@ static void mal_err (struct eth_device *dev, unsigned long isr, { EMAC_4XX_HW_PST hw_p = dev->priv; - mtdcr (malesr, isr); /* clear interrupt */ + mtdcr (MAL0_ESR, isr); /* clear interrupt */ /* clear DE interrupt */ - mtdcr (maltxdeir, 0xC0000000); - mtdcr (malrxdeir, 0x80000000); + mtdcr (MAL0_TXDEIR, 0xC0000000); + mtdcr (MAL0_RXDEIR, 0x80000000); #ifdef INFO_4XX_ENET printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr); @@ -1769,10 +1769,10 @@ static void enet_rcv (struct eth_device *dev, unsigned long malisr) int i; int loop_count = 0; - rx_eob_isr = mfdcr (malrxeobisr); + rx_eob_isr = mfdcr (MAL0_RXEOBISR); if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) { /* clear EOB */ - mtdcr (malrxeobisr, rx_eob_isr); + mtdcr (MAL0_RXEOBISR, rx_eob_isr); /* EMAC RX done */ while (1) { /* do all */ @@ -1912,10 +1912,10 @@ int ppc_4xx_eth_initialize (bd_t * bis) #if defined(CONFIG_440GX) unsigned long pfc1; - mfsdr (sdr_pfc1, pfc1); + mfsdr (SDR0_PFC1, pfc1); pfc1 &= ~(0x01e00000); pfc1 |= 0x01200000; - mtsdr (sdr_pfc1, pfc1); + mtsdr (SDR0_PFC1, pfc1); #endif /* first clear all mac-addresses */ @@ -2036,10 +2036,10 @@ int ppc_4xx_eth_initialize (bd_t * bis) MAL_IER_DE | MAL_IER_NE | MAL_IER_TE | MAL_IER_OPBE | MAL_IER_PLBE; #endif - mtdcr (malesr, 0xffffffff); /* clear pending interrupts */ - mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */ - mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */ - mtdcr (malier, mal_ier); + mtdcr (MAL0_ESR, 0xffffffff); /* clear pending interrupts */ + mtdcr (MAL0_TXDEIR, 0xffffffff); /* clear pending interrupts */ + mtdcr (MAL0_RXDEIR, 0xffffffff); /* clear pending interrupts */ + mtdcr (MAL0_IER, mal_ier); /* install MAL interrupt handler */ irq_install_handler (VECNUM_MAL_SERR, diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index 553845d6d98..40e4735b681 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -207,9 +207,9 @@ #define CONFIG_SYS_EBC_PB5CR 0xFD21A000 /* bank 6 is unused */ -/* pb6ap = 0 */ +/* PB6AP = 0 */ #define CONFIG_SYS_EBC_PB6AP 0x00000000 -/* pb6cr = 0 */ +/* PB6CR = 0 */ #define CONFIG_SYS_EBC_PB6CR 0x00000000 /* bank 7 is LED register */ diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index 73d6d24b61d..a62f1b4d578 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -214,9 +214,9 @@ #define CONFIG_SYS_EBC_PB5CR 0xFD87A000 /* bank 6 is unused */ -/* pb6ap = 0 */ +/* PB6AP = 0 */ #define CONFIG_SYS_EBC_PB6AP 0x00000000 -/* pb6cr = 0 */ +/* PB6CR = 0 */ #define CONFIG_SYS_EBC_PB6CR 0x00000000 /* bank 7 is LED register */ diff --git a/include/ppc405.h b/include/ppc405.h index 55649e474fc..5e56897819a 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -42,54 +42,39 @@ * DMA ******************************************************************************/ #define DMA_DCR_BASE 0x100 -#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ -#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ -#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */ -#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */ -#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */ -#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ -#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ -#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */ -#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */ -#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */ -#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ -#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ -#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */ -#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */ -#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */ -#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */ -#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */ -#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */ -#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */ -#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */ -#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ -#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ -#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */ +#define DMACR0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ +#define DMACT0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ +#define DMADA0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */ +#define DMASA0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */ +#define DMASB0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */ +#define DMACR1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ +#define DMACT1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ +#define DMADA1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */ +#define DMASA1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */ +#define DMASB1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */ +#define DMACR2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ +#define DMACT2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ +#define DMADA2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */ +#define DMASA2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */ +#define DMASB2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */ +#define DMACR3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */ +#define DMACT3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */ +#define DMADA3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */ +#define DMASA3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */ +#define DMASB3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */ +#define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ +#define DMASGC (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ +#define DMAADR (DMA_DCR_BASE+0x24) /* DMA address decode register */ #ifndef CONFIG_405EP /****************************************************************************** * Decompression Controller ******************************************************************************/ #define DECOMP_DCR_BASE 0x14 -#define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */ -#define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */ - /* values for kiar register - indirect addressing of these regs */ - #define kitor0 0x00 /* index table origin register 0 */ - #define kitor1 0x01 /* index table origin register 1 */ - #define kitor2 0x02 /* index table origin register 2 */ - #define kitor3 0x03 /* index table origin register 3 */ - #define kaddr0 0x04 /* address decode definition regsiter 0 */ - #define kaddr1 0x05 /* address decode definition regsiter 1 */ - #define kconf 0x40 /* decompression core config register */ - #define kid 0x41 /* decompression core ID register */ - #define kver 0x42 /* decompression core version # reg */ - #define kpear 0x50 /* bus error addr reg (PLB addr) */ - #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/ - #define kesr0 0x52 /* bus error status reg 0 (R/clear) */ - #define kesr0s 0x53 /* bus error status reg 0 (set) */ - /* There are 0x400 of the following registers, from krom0 to krom3ff*/ - /* Only the first one is given here. */ - #define krom0 0x400 /* SRAM/ROM read/write */ +#define KIAR (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */ +#define KIDR (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */ +/* values for kiar register - indirect addressing of these regs */ +#define KCONF 0x40 /* decompression core config register */ #endif /****************************************************************************** @@ -100,38 +85,37 @@ #else #define POWERMAN_DCR_BASE 0xb8 #endif -#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */ -#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */ -#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */ +#define CPMSR (POWERMAN_DCR_BASE+0x0) /* Power management status */ +#define CPMER (POWERMAN_DCR_BASE+0x1) /* Power management enable */ +#define CPMFR (POWERMAN_DCR_BASE+0x2) /* Power management force */ /****************************************************************************** * Extrnal Bus Controller ******************************************************************************/ - /* values for ebccfga register - indirect addressing of these regs */ - #define pb0cr 0x00 /* periph bank 0 config reg */ - #define pb1cr 0x01 /* periph bank 1 config reg */ - #define pb2cr 0x02 /* periph bank 2 config reg */ - #define pb3cr 0x03 /* periph bank 3 config reg */ - #define pb4cr 0x04 /* periph bank 4 config reg */ + /* values for EBC0_CFGADDR register - indirect addressing of these regs */ + #define PB0CR 0x00 /* periph bank 0 config reg */ + #define PB1CR 0x01 /* periph bank 1 config reg */ + #define PB2CR 0x02 /* periph bank 2 config reg */ + #define PB3CR 0x03 /* periph bank 3 config reg */ + #define PB4CR 0x04 /* periph bank 4 config reg */ #ifndef CONFIG_405EP - #define pb5cr 0x05 /* periph bank 5 config reg */ - #define pb6cr 0x06 /* periph bank 6 config reg */ - #define pb7cr 0x07 /* periph bank 7 config reg */ + #define PB5CR 0x05 /* periph bank 5 config reg */ + #define PB6CR 0x06 /* periph bank 6 config reg */ + #define PB7CR 0x07 /* periph bank 7 config reg */ #endif - #define pb0ap 0x10 /* periph bank 0 access parameters */ - #define pb1ap 0x11 /* periph bank 1 access parameters */ - #define pb2ap 0x12 /* periph bank 2 access parameters */ - #define pb3ap 0x13 /* periph bank 3 access parameters */ - #define pb4ap 0x14 /* periph bank 4 access parameters */ + #define PB0AP 0x10 /* periph bank 0 access parameters */ + #define PB1AP 0x11 /* periph bank 1 access parameters */ + #define PB2AP 0x12 /* periph bank 2 access parameters */ + #define PB3AP 0x13 /* periph bank 3 access parameters */ + #define PB4AP 0x14 /* periph bank 4 access parameters */ #ifndef CONFIG_405EP - #define pb5ap 0x15 /* periph bank 5 access parameters */ - #define pb6ap 0x16 /* periph bank 6 access parameters */ - #define pb7ap 0x17 /* periph bank 7 access parameters */ + #define PB5AP 0x15 /* periph bank 5 access parameters */ + #define PB6AP 0x16 /* periph bank 6 access parameters */ + #define PB7AP 0x17 /* periph bank 7 access parameters */ #endif - #define pbear 0x20 /* periph bus error addr reg */ - #define pbesr0 0x21 /* periph bus error status reg 0 */ - #define pbesr1 0x22 /* periph bus error status reg 1 */ - #define epcr 0x23 /* external periph control reg */ + #define PBEAR 0x20 /* periph bus error addr reg */ + #define PBESR0 0x21 /* periph bus error status reg 0 */ + #define PBESR1 0x22 /* periph bus error status reg 1 */ #define EBC0_CFG 0x23 /* external bus configuration reg */ #ifdef CONFIG_405EP @@ -139,12 +123,12 @@ * Control ******************************************************************************/ #define CNTRL_DCR_BASE 0x0f0 -#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ -#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */ -#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ -#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ -#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */ -#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */ +#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ +#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Clock status register */ +#define CPC0_EPCTL (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ +#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ +#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART control register */ +#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI control register */ #define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ @@ -401,10 +385,10 @@ #define VCO_MIN 500 #define VCO_MAX 1000 #elif defined(CONFIG_405EZ) -#define sdrnand0 0x4000 -#define sdrultra0 0x4040 -#define sdrultra1 0x4050 -#define sdricintstat 0x4510 +#define SDR0_NAND0 0x4000 +#define SDR0_ULTRA0 0x4040 +#define SDR0_ULTRA1 0x4050 +#define SDR0_ICINTSTAT 0x4510 #define SDR_NAND0_NDEN 0x80000000 #define SDR_NAND0_NDBTEN 0x40000000 @@ -429,21 +413,19 @@ #define SDR_ICTX0_STAT 0x40000000 #define SDR_ICTX1_STAT 0x20000000 -#define SDR_PINSTP 0x40 +#define SDR0_PINSTP 0x40 /****************************************************************************** * Control ******************************************************************************/ /* CPR Registers */ -#define cprclkupd 0x020 /* CPR_CLKUPD */ -#define cprpllc 0x040 /* CPR_PLLC */ -#define cprplld 0x060 /* CPR_PLLD */ -#define cprprimad 0x080 /* CPR_PRIMAD */ -#define cprperd0 0x0e0 /* CPR_PERD0 */ -#define cprperd1 0x0e1 /* CPR_PERD1 */ -#define cprperc0 0x180 /* CPR_PERC0 */ -#define cprmisc0 0x181 /* CPR_MISC0 */ -#define cprmisc1 0x182 /* CPR_MISC1 */ +#define CPR0_CLKUP 0x020 /* CPR_CLKUPD */ +#define CPR0_PLLC 0x040 /* CPR_PLLC */ +#define CPR0_PLLD 0x060 /* CPR_PLLD */ +#define CPC0_PRIMAD 0x080 /* CPR_PRIMAD */ +#define CPC0_PERD0 0x0e0 /* CPR_PERD0 */ +#define CPC0_PERD1 0x0e1 /* CPR_PERD1 */ +#define CPC0_PERC0 0x180 /* CPR_PERC0 */ #define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */ #define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ @@ -470,21 +452,14 @@ * Control ******************************************************************************/ #define CNTRL_DCR_BASE 0x0b0 -#define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */ -#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */ -#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */ -#define reset (CNTRL_DCR_BASE+0x3) /* reset register */ -#define strap (CNTRL_DCR_BASE+0x4) /* strap register */ - -#define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* chip control register 0 */ -#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* chip control register 1 */ -#define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* chip pin strapping register */ +#define CPC0_PLLMR (CNTRL_DCR_BASE + 0x0) /* PLL mode register */ +#define CPC0_CR0 (CNTRL_DCR_BASE + 0x1) /* chip control register 0 */ +#define CPC0_CR1 (CNTRL_DCR_BASE + 0x2) /* chip control register 1 */ +#define CPC0_PSR (CNTRL_DCR_BASE + 0x4) /* chip pin strapping reg */ /* CPC0_ECR/CPC0_EIRR: PPC405GPr only */ -#define CPC0_EIRR (CNTRL_DCR_BASE+0x6) /* external interrupt routing register */ -#define CPC0_ECR (0xaa) /* edge conditioner register */ - -#define ecr (0xaa) /* edge conditioner register (405gpr) */ +#define CPC0_EIRR (CNTRL_DCR_BASE + 0x6) /* ext interrupt routing reg */ +#define CPC0_ECR 0xaa /* edge conditioner register */ /* Bit definitions */ #define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ @@ -557,140 +532,38 @@ ******************************************************************************/ #if defined(CONFIG_405EZ) #define MAL_DCR_BASE 0x380 -#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ -#define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/ -#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ -#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ -#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/ -#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ -#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ -#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ -/* 0x08-0x0F Reserved */ -#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/ -#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ -#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ -#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ -/* 0x14-0x1F Reserved */ -#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */ -#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */ -#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */ -#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */ -#define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */ -#define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */ -#define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */ -#define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */ -#define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */ -#define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */ -#define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */ -#define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */ -#define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */ -#define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */ -#define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */ -#define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */ -#define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */ -#define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */ -#define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */ -#define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */ -#define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */ -#define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */ -#define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */ -#define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */ -#define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */ -#define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */ -#define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */ -#define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */ -#define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */ -#define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */ -#define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */ -#define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */ -#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */ -#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */ -#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */ -#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */ -#define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */ -#define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */ -#define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */ -#define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */ -#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */ -#define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */ -#define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */ -#define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */ -#define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */ -#define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */ -#define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */ -#define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */ -#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */ -#define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */ -#define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */ -#define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */ -#define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */ -#define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */ -#define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */ -#define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */ -#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */ -#define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */ -#define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */ -#define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */ -#define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */ -#define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */ -#define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */ -#define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */ -#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ -#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ -#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ -#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ -#define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */ -#define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */ -#define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */ -#define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */ -#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */ -#define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */ -#define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */ -#define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */ -#define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */ -#define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */ -#define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */ -#define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */ -#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */ -#define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */ -#define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */ -#define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */ -#define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */ -#define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */ -#define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */ -#define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */ -#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ -#define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */ -#define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */ -#define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */ -#define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */ -#define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */ -#define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */ -#define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */ - -#else /* !defined(CONFIG_405EZ) */ - -#define MAL_DCR_BASE 0x180 -#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ -#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ -#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ -#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ -#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ -#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ -#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ -#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ -#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ -#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ -#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ -#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ -#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ -#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ -#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ -#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ -#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ -#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ -#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ -#endif /* defined(CONFIG_405EZ) */ +#else +#define MAL_DCR_BASE 0x180 +#endif +#define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */ +#define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Err Status (Read/Clear)*/ +#define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */ +#define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set)*/ +#define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset)*/ +#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status*/ +#define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int reg */ +#define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */ +#define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */ +#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status*/ +#define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int reg */ +#define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table ptr */ +#define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table ptr */ +#define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table ptr */ +#define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table ptr */ +#define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table ptr */ +#define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table ptr */ +#define MAL0_RXCTP2R (MAL_DCR_BASE + 0x42) /* RX 2 Channel table ptr */ +#define MAL0_RXCTP3R (MAL_DCR_BASE + 0x43) /* RX 3 Channel table ptr */ +#define MAL0_RXCTP8R (MAL_DCR_BASE + 0x48) /* RX 8 Channel table ptr */ +#define MAL0_RXCTP16R (MAL_DCR_BASE + 0x50) /* RX 16 Channel table ptr */ +#define MAL0_RXCTP24R (MAL_DCR_BASE + 0x58) /* RX 24 Channel table ptr */ +#define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ +#define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */ +#define MAL0_RCBS2 (MAL_DCR_BASE + 0x62) /* RX 2 Channel buffer size */ +#define MAL0_RCBS3 (MAL_DCR_BASE + 0x63) /* RX 3 Channel buffer size */ +#define MAL0_RCBS8 (MAL_DCR_BASE + 0x68) /* RX 8 Channel buffer size */ +#define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */ +#define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */ /*----------------------------------------------------------------------------- | IIC Register Offsets @@ -730,27 +603,19 @@ ******************************************************************************/ #if defined(CONFIG_405EZ) #define OCM_DCR_BASE 0x020 -#define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */ -#define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */ -#define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */ -#define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */ -#define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */ -#define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */ -#define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */ -#define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */ -#define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */ -#define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */ -#define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */ -#define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */ -#define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/ -#define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/ -#define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/ +#define OCM0_PLBCR1 (OCM_DCR_BASE + 0x00) /* OCM PLB3 Bank 1 Config */ +#define OCM0_PLBCR2 (OCM_DCR_BASE + 0x01) /* OCM PLB3 Bank 2 Config */ +#define OCM0_PLBBEAR (OCM_DCR_BASE + 0x02) /* OCM PLB3 Bus Error Add */ +#define OCM0_DSRC1 (OCM_DCR_BASE + 0x08) /* OCM D-side Bank 1 Config */ +#define OCM0_DSRC2 (OCM_DCR_BASE + 0x09) /* OCM D-side Bank 2 Config */ +#define OCM0_ISRC1 (OCM_DCR_BASE + 0x0A) /* OCM I-side Bank 1Config */ +#define OCM0_ISRC2 (OCM_DCR_BASE + 0x0B) /* OCM I-side Bank 2 Config */ +#define OCM0_DISDPC (OCM_DCR_BASE + 0x0C) /* OCM D-/I-side Data Par Chk*/ #else #define OCM_DCR_BASE 0x018 -#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */ -#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ -#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */ -#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */ +#define OCM0_ISCNTL (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ +#define OCM0_DSARC (OCM_DCR_BASE+0x02) /* OCM D-side address compare */ +#define OCM0_DSCNTL (OCM_DCR_BASE+0x03) /* OCM D-side control */ #endif /* CONFIG_405EZ */ /****************************************************************************** @@ -876,9 +741,9 @@ #define SDR0_SRST_AHB PPC_REG_VAL(30, 1) #define SDR0_SRST_NDFC PPC_REG_VAL(31, 1) -#define sdr_uart0 0x0120 /* UART0 Config */ -#define sdr_uart1 0x0121 /* UART1 Config */ -#define sdr_mfr 0x4300 /* SDR0_MFR reg */ +#define SDR0_UART0 0x0120 /* UART0 Config */ +#define SDR0_UART1 0x0121 /* UART1 Config */ +#define SDR0_MFR 0x4300 /* SDR0_MFR reg */ /* Defines for CPC0_EPRCSR register */ #define CPC0_EPRCSR_E0NFE 0x80000000 @@ -890,18 +755,16 @@ #define CPC0_EPRCSR_E1PCI 0x00000002 #define CPC0_EPRCSR_E0PCI 0x00000001 -#define cpr0_clkupd 0x020 -#define cpr0_pllc 0x040 -#define cpr0_plld 0x060 -#define cpr0_cpud 0x080 -#define cpr0_plbd 0x0a0 -#define cpr0_opbd 0x0c0 -#define cpr0_perd 0x0e0 -#define cpr0_ahbd 0x100 -#define cpr0_icfg 0x140 +#define CPR0_CLKUPD 0x020 +#define CPR0_PLLC 0x040 +#define CPR0_PLLD 0x060 +#define CPR0_CPUD 0x080 +#define CPR0_PLBD 0x0a0 +#define CPR0_OPBD 0x0c0 +#define CPR0_PERD 0x0e0 -#define SDR_PINSTP 0x0040 -#define sdr_sdcs 0x0060 +#define SDR0_PINSTP 0x0040 +#define SDR0_SDCS0 0x0060 #define SDR0_SDCS_SDD (0x80000000 >> 31) diff --git a/include/ppc440.h b/include/ppc440.h index 7f34fda8cfa..378a9de20a6 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -58,64 +58,55 @@ | Clocking Controller +----------------------------------------------------------------------------*/ /* values for clkcfga register - indirect addressing of these regs */ -#define clk_clkukpd 0x0020 -#define clk_pllc 0x0040 -#define clk_plld 0x0060 -#define clk_primad 0x0080 -#define clk_primbd 0x00a0 -#define clk_opbd 0x00c0 -#define clk_perd 0x00e0 -#define clk_mald 0x0100 -#define clk_spcid 0x0120 -#define clk_icfg 0x0140 +#define CPR0_PLLC 0x0040 +#define CPR0_PLLD 0x0060 +#define CPR0_PRIMAD 0x0080 +#define CPR0_PRIMBD 0x00a0 +#define CPR0_OPBD 0x00c0 +#define CPR0_PERD 0x00e0 +#define CPR0_MALD 0x0100 +#define CPR0_SPCID 0x0120 +#define CPR0_ICFG 0x0140 /* 440gx sdr register definations */ -#define sdr_sdstp0 0x0020 /* */ -#define sdr_sdstp1 0x0021 /* */ -#define SDR_PINSTP 0x0040 -#define sdr_sdcs 0x0060 -#define sdr_ecid0 0x0080 -#define sdr_ecid1 0x0081 -#define sdr_ecid2 0x0082 -#define sdr_jtag 0x00c0 +#define SDR0_SDSTP0 0x0020 /* */ +#define SDR0_SDSTP1 0x0021 /* */ +#define SDR0_PINSTP 0x0040 +#define SDR0_SDCS0 0x0060 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define SDR0_DDRCFG 0x00e0 #endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */ -#define sdr_ebc 0x0100 -#define sdr_uart0 0x0120 /* UART0 Config */ -#define sdr_uart1 0x0121 /* UART1 Config */ -#define sdr_uart2 0x0122 /* UART2 Config */ -#define sdr_uart3 0x0123 /* UART3 Config */ -#define sdr_cp440 0x0180 -#define sdr_xcr 0x01c0 -#define sdr_xpllc 0x01c1 -#define sdr_xplld 0x01c2 -#define sdr_srst 0x0200 -#define sdr_slpipe 0x0220 -#define sdr_amp0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */ -#define sdr_amp1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */ -#define sdr_mirq0 0x0260 -#define sdr_mirq1 0x0261 -#define sdr_maltbl 0x0280 -#define sdr_malrbl 0x02a0 -#define sdr_maltbs 0x02c0 -#define sdr_malrbs 0x02e0 -#define sdr_pci0 0x0300 -#define sdr_usb0 0x0320 -#define sdr_cust0 0x4000 -#define sdr_cust1 0x4002 -#define sdr_pfc0 0x4100 /* Pin Function 0 */ -#define sdr_pfc1 0x4101 /* Pin Function 1 */ -#define sdr_plbtr 0x4200 -#define sdr_mfr 0x4300 /* SDR0_MFR reg */ +#define SDR0_EBC 0x0100 +#define SDR0_UART0 0x0120 /* UART0 Config */ +#define SDR0_UART1 0x0121 /* UART1 Config */ +#define SDR0_UART2 0x0122 /* UART2 Config */ +#define SDR0_UART3 0x0123 /* UART3 Config */ +#define SDR0_CP440 0x0180 +#define SDR0_XCR 0x01c0 +#define SDR0_XPLLC 0x01c1 +#define SDR0_XPLLD 0x01c2 +#define SDR0_SRST 0x0200 +#define SD0_AMP0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */ +#define SD0_AMP1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */ +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define SDR0_PCI0 0x01c0 +#else +#define SDR0_PCI0 0x0300 +#endif +#define SDR0_USB0 0x0320 +#define SDR0_CUST0 0x4000 +#define SDR0_CUST1 0x4002 +#define SDR0_PFC0 0x4100 /* Pin Function 0 */ +#define SDR0_PFC1 0x4101 /* Pin Function 1 */ +#define SDR0_MFR 0x4300 /* SDR0_MFR reg */ #ifdef CONFIG_440GX -#define sdr_amp 0x0240 -#define sdr_xpllc 0x01c1 -#define sdr_xplld 0x01c2 -#define sdr_xcr 0x01c0 -#define sdr_sdstp2 0x4001 -#define sdr_sdstp3 0x4003 +#define SD0_AMP 0x0240 +#define SDR0_XPLLC 0x01c1 +#define SDR0_XPLLD 0x01c2 +#define SDR0_XCR 0x01c0 +#define SDR0_SDSTP2 0x4001 +#define SDR0_SDSTP3 0x4003 #endif /* CONFIG_440GX */ /*----------------------------------------------------------------------------+ @@ -143,101 +134,66 @@ #define MMUCR_STID_MASK 0x000000FF #ifdef CONFIG_440SPE -#undef sdr_sdstp2 -#define sdr_sdstp2 0x0022 -#undef sdr_sdstp3 -#define sdr_sdstp3 0x0023 -#define sdr_ddr0 0x00E1 -#define sdr_uart2 0x0122 -#define sdr_xcr0 0x01c0 -/* #define sdr_xcr1 0x01c3 only one PCIX - SG */ -/* #define sdr_xcr2 0x01c6 only one PCIX - SG */ -#define sdr_xpllc0 0x01c1 -#define sdr_xplld0 0x01c2 -#define sdr_xpllc1 0x01c4 /*notRCW - SG */ -#define sdr_xplld1 0x01c5 /*notRCW - SG */ -#define sdr_xpllc2 0x01c7 /*notRCW - SG */ -#define sdr_xplld2 0x01c8 /*notRCW - SG */ -#define sdr_amp0 0x0240 -#define sdr_amp1 0x0241 -#define sdr_cust2 0x4004 -#define sdr_cust3 0x4006 -#define sdr_sdstp4 0x4001 -#define sdr_sdstp5 0x4003 -#define sdr_sdstp6 0x4005 -#define sdr_sdstp7 0x4007 +#undef SDR0_SDSTP2 +#define SDR0_SDSTP2 0x0022 +#undef SDR0_SDSTP3 +#define SDR0_SDSTP3 0x0023 +#define SDR0_DDR0 0x00E1 +#define SDR0_UART2 0x0122 +#define SDR0_XCR0 0x01c0 +#define SDR0_XCR1 0x01c3 +#define SDR0_XCR2 0x01c6 +#define SDR0_XPLLC0 0x01c1 +#define SDR0_XPLLD0 0x01c2 +#define SDR0_XPLLC1 0x01c4 /*notRCW - SG */ +#define SDR0_XPLLD1 0x01c5 /*notRCW - SG */ +#define SDR0_XPLLC2 0x01c7 /*notRCW - SG */ +#define SDR0_XPLLD2 0x01c8 /*notRCW - SG */ +#define SD0_AMP0 0x0240 +#define SD0_AMP1 0x0241 +#define SDR0_CUST2 0x4004 +#define SDR0_CUST3 0x4006 +#define SDR0_SDSTP4 0x4001 +#define SDR0_SDSTP5 0x4003 +#define SDR0_SDSTP6 0x4005 +#define SDR0_SDSTP7 0x4007 #endif /* CONFIG_440SPE */ /*----------------------------------------------------------------------------- | External Bus Controller +----------------------------------------------------------------------------*/ -/* values for ebccfga register - indirect addressing of these regs */ -#define pb0cr 0x00 /* periph bank 0 config reg */ -#define pb1cr 0x01 /* periph bank 1 config reg */ -#define pb2cr 0x02 /* periph bank 2 config reg */ -#define pb3cr 0x03 /* periph bank 3 config reg */ -#define pb4cr 0x04 /* periph bank 4 config reg */ -#define pb5cr 0x05 /* periph bank 5 config reg */ -#define pb6cr 0x06 /* periph bank 6 config reg */ -#define pb7cr 0x07 /* periph bank 7 config reg */ -#define pb0ap 0x10 /* periph bank 0 access parameters */ -#define pb1ap 0x11 /* periph bank 1 access parameters */ -#define pb2ap 0x12 /* periph bank 2 access parameters */ -#define pb3ap 0x13 /* periph bank 3 access parameters */ -#define pb4ap 0x14 /* periph bank 4 access parameters */ -#define pb5ap 0x15 /* periph bank 5 access parameters */ -#define pb6ap 0x16 /* periph bank 6 access parameters */ -#define pb7ap 0x17 /* periph bank 7 access parameters */ -#define pbear 0x20 /* periph bus error addr reg */ -#define pbesr 0x21 /* periph bus error status reg */ -#define xbcfg 0x23 /* external bus configuration reg */ +/* values for EBC0_CFGADDR register - indirect addressing of these regs */ +#define PB0CR 0x00 /* periph bank 0 config reg */ +#define PB1CR 0x01 /* periph bank 1 config reg */ +#define PB2CR 0x02 /* periph bank 2 config reg */ +#define PB3CR 0x03 /* periph bank 3 config reg */ +#define PB4CR 0x04 /* periph bank 4 config reg */ +#define PB5CR 0x05 /* periph bank 5 config reg */ +#define PB6CR 0x06 /* periph bank 6 config reg */ +#define PB7CR 0x07 /* periph bank 7 config reg */ +#define PB0AP 0x10 /* periph bank 0 access parameters */ +#define PB1AP 0x11 /* periph bank 1 access parameters */ +#define PB2AP 0x12 /* periph bank 2 access parameters */ +#define PB3AP 0x13 /* periph bank 3 access parameters */ +#define PB4AP 0x14 /* periph bank 4 access parameters */ +#define PB5AP 0x15 /* periph bank 5 access parameters */ +#define PB6AP 0x16 /* periph bank 6 access parameters */ +#define PB7AP 0x17 /* periph bank 7 access parameters */ +#define PBEAR 0x20 /* periph bus error addr reg */ +#define PBESR 0x21 /* periph bus error status reg */ #define EBC0_CFG 0x23 /* external bus configuration reg */ -#define xbcid 0x24 /* external bus core id reg */ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -/* PLB4 to PLB3 Bridge OUT */ -#define P4P3_DCR_BASE 0x020 -#define p4p3_esr0_read (P4P3_DCR_BASE+0x0) -#define p4p3_esr0_write (P4P3_DCR_BASE+0x1) -#define p4p3_eadr (P4P3_DCR_BASE+0x2) -#define p4p3_euadr (P4P3_DCR_BASE+0x3) -#define p4p3_esr1_read (P4P3_DCR_BASE+0x4) -#define p4p3_esr1_write (P4P3_DCR_BASE+0x5) -#define p4p3_confg (P4P3_DCR_BASE+0x6) -#define p4p3_pic (P4P3_DCR_BASE+0x7) -#define p4p3_peir (P4P3_DCR_BASE+0x8) -#define p4p3_rev (P4P3_DCR_BASE+0xA) - -/* PLB3 to PLB4 Bridge IN */ -#define P3P4_DCR_BASE 0x030 -#define p3p4_esr0_read (P3P4_DCR_BASE+0x0) -#define p3p4_esr0_write (P3P4_DCR_BASE+0x1) -#define p3p4_eadr (P3P4_DCR_BASE+0x2) -#define p3p4_euadr (P3P4_DCR_BASE+0x3) -#define p3p4_esr1_read (P3P4_DCR_BASE+0x4) -#define p3p4_esr1_write (P3P4_DCR_BASE+0x5) -#define p3p4_confg (P3P4_DCR_BASE+0x6) -#define p3p4_pic (P3P4_DCR_BASE+0x7) -#define p3p4_peir (P3P4_DCR_BASE+0x8) -#define p3p4_rev (P3P4_DCR_BASE+0xA) - /* PLB3 Arbiter */ -#define PLB3_DCR_BASE 0x070 -#define plb3_revid (PLB3_DCR_BASE+0x2) -#define plb3_besr (PLB3_DCR_BASE+0x3) -#define plb3_bear (PLB3_DCR_BASE+0x6) -#define plb3_acr (PLB3_DCR_BASE+0x7) +#define PLB3_DCR_BASE 0x070 +#define PLB3_ACR (PLB3_DCR_BASE + 0x7) /* PLB4 Arbiter - PowerPC440EP Pass1 */ -#define PLB4_DCR_BASE 0x080 -#define plb4_acr (PLB4_DCR_BASE+0x1) -#define plb4_revid (PLB4_DCR_BASE+0x2) -#define plb4_besr (PLB4_DCR_BASE+0x4) -#define plb4_bearl (PLB4_DCR_BASE+0x6) -#define plb4_bearh (PLB4_DCR_BASE+0x7) +#define PLB4_DCR_BASE 0x080 +#define PLB4_ACR (PLB4_DCR_BASE + 0x1) #define PLB4_ACR_WRP (0x80000000 >> 7) @@ -578,24 +534,16 @@ #define CNTRL_DCR_BASE 0x0b0 #endif -#define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */ -#define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */ -#define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */ +#define CPC0_SYS0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */ +#define CPC0_SYS1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */ -#define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */ -#define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */ -#define cpc0_cust0 (CNTRL_DCR_BASE+0x32) /* Customer configuration reg 0 */ -#define cpc0_cust1 (CNTRL_DCR_BASE+0x33) /* Customer configuration reg 1 */ +#define CPC0_STRP0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */ +#define CPC0_STRP1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */ -#define cpc0_strp0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */ -#define cpc0_strp1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */ -#define cpc0_strp2 (CNTRL_DCR_BASE+0x36) /* Power-on config reg 2 (RO) */ -#define cpc0_strp3 (CNTRL_DCR_BASE+0x37) /* Power-on config reg 3 (RO) */ +#define CPC0_GPIO (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */ -#define cpc0_gpio (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */ - -#define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */ -#define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */ +#define CPC0_CR0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */ /*----------------------------------------------------------------------------- | DMA @@ -605,91 +553,59 @@ #else #define DMA_DCR_BASE 0x100 #endif -#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ -#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ -#define dmasah0 (DMA_DCR_BASE+0x02) /* DMA source address high 0 */ -#define dmasal0 (DMA_DCR_BASE+0x03) /* DMA source address low 0 */ -#define dmadah0 (DMA_DCR_BASE+0x04) /* DMA destination address high 0 */ -#define dmadal0 (DMA_DCR_BASE+0x05) /* DMA destination address low 0 */ -#define dmasgh0 (DMA_DCR_BASE+0x06) /* DMA scatter/gather desc addr high 0 */ -#define dmasgl0 (DMA_DCR_BASE+0x07) /* DMA scatter/gather desc addr low 0 */ -#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ -#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ -#define dmasah1 (DMA_DCR_BASE+0x0a) /* DMA source address high 1 */ -#define dmasal1 (DMA_DCR_BASE+0x0b) /* DMA source address low 1 */ -#define dmadah1 (DMA_DCR_BASE+0x0c) /* DMA destination address high 1 */ -#define dmadal1 (DMA_DCR_BASE+0x0d) /* DMA destination address low 1 */ -#define dmasgh1 (DMA_DCR_BASE+0x0e) /* DMA scatter/gather desc addr high 1 */ -#define dmasgl1 (DMA_DCR_BASE+0x0f) /* DMA scatter/gather desc addr low 1 */ -#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ -#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ -#define dmasah2 (DMA_DCR_BASE+0x12) /* DMA source address high 2 */ -#define dmasal2 (DMA_DCR_BASE+0x13) /* DMA source address low 2 */ -#define dmadah2 (DMA_DCR_BASE+0x14) /* DMA destination address high 2 */ -#define dmadal2 (DMA_DCR_BASE+0x15) /* DMA destination address low 2 */ -#define dmasgh2 (DMA_DCR_BASE+0x16) /* DMA scatter/gather desc addr high 2 */ -#define dmasgl2 (DMA_DCR_BASE+0x17) /* DMA scatter/gather desc addr low 2 */ -#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */ -#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 2 */ -#define dmasah3 (DMA_DCR_BASE+0x1a) /* DMA source address high 2 */ -#define dmasal3 (DMA_DCR_BASE+0x1b) /* DMA source address low 2 */ -#define dmadah3 (DMA_DCR_BASE+0x1c) /* DMA destination address high 2 */ -#define dmadal3 (DMA_DCR_BASE+0x1d) /* DMA destination address low 2 */ -#define dmasgh3 (DMA_DCR_BASE+0x1e) /* DMA scatter/gather desc addr high 2 */ -#define dmasgl3 (DMA_DCR_BASE+0x1f) /* DMA scatter/gather desc addr low 2 */ -#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ -#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ -#define dmaslp (DMA_DCR_BASE+0x25) /* DMA sleep mode register */ -#define dmapol (DMA_DCR_BASE+0x26) /* DMA polarity configuration register */ +#define DMACR0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ +#define DMACT0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ +#define DMACR1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ +#define DMACT1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ +#define DMACR2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ +#define DMACT2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ +#define DMACR3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */ +#define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ +#define DMASGC (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ /*----------------------------------------------------------------------------- | Memory Access Layer +----------------------------------------------------------------------------*/ #define MAL_DCR_BASE 0x180 -#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ -#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ -#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ -#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ -#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ -#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ -#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ -#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ -#define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg */ -#define maltxbattr (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg */ -#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ -#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ -#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ -#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ -#define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg */ -#define malrxbattr (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg */ -#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ -#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ -#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ -#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg */ -#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ -#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ -#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ -#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ +#define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */ +#define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Error Status (Read/Clear) */ +#define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */ +#define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ +#define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset) */ +#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status */ +#define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int */ +#define MAL0_TXBADDR (MAL_DCR_BASE + 0x09) /* TX descriptor base addr*/ +#define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */ +#define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */ +#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status */ +#define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int */ +#define MAL0_RXBADDR (MAL_DCR_BASE + 0x15) /* RX descriptor base addr */ +#define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table pointer */ +#define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table pointer */ +#define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table pointer */ +#define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table pointer */ +#define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table pointer */ +#define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table pointer */ +#define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ +#define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */ #if defined(CONFIG_440GX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */ -#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */ -#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table pointer reg */ -#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table pointer reg */ -#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table pointer reg */ -#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ -#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ -#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */ -#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */ -#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ +#define MAL0_RXCTP2R (MAL_DCR_BASE + 0x42) /* RX 2 Channel table pointer */ +#define MAL0_RXCTP3R (MAL_DCR_BASE + 0x43) /* RX 3 Channel table pointer */ +#define MAL0_RXCTP8R (MAL_DCR_BASE + 0x48) /* RX 8 Channel table pointer */ +#define MAL0_RXCTP16R (MAL_DCR_BASE + 0x50) /* RX 16 Channel table pointer*/ +#define MAL0_RXCTP24R (MAL_DCR_BASE + 0x58) /* RX 24 Channel table pointer*/ +#define MAL0_RCBS2 (MAL_DCR_BASE + 0x62) /* RX 2 Channel buffer size */ +#define MAL0_RCBS3 (MAL_DCR_BASE + 0x63) /* RX 3 Channel buffer size */ +#define MAL0_RCBS8 (MAL_DCR_BASE + 0x68) /* RX 8 Channel buffer size */ +#define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */ +#define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */ #endif /* CONFIG_440GX */ /*-----------------------------------------------------------------------------+ | SDR0 Bit Settings +-----------------------------------------------------------------------------*/ #if defined(CONFIG_440SP) -#define SDR0_SRST 0x0200 - #define SDR0_DDR0 0x00E1 #define SDR0_DDR0_DPLLRST 0x80000000 #define SDR0_DDR0_DDRM_MASK 0x60000000 @@ -923,79 +839,6 @@ #define SDR0_UART0 0x0120 #define SDR0_UART1 0x0121 #define SDR0_UART2 0x0122 -#define SDR0_UARTX_UXICS_MASK 0xF0000000 -#define SDR0_UARTX_UXICS_PLB 0x20000000 -#define SDR0_UARTX_UXEC_MASK 0x00800000 -#define SDR0_UARTX_UXEC_INT 0x00000000 -#define SDR0_UARTX_UXEC_EXT 0x00800000 -#define SDR0_UARTX_UXDIV_MASK 0x000000FF -#define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) -#define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1) - -#define SDR0_CP440 0x0180 -#define SDR0_CP440_ERPN_MASK 0x30000000 -#define SDR0_CP440_ERPN_MASK_HI 0x3000 -#define SDR0_CP440_ERPN_MASK_LO 0x0000 -#define SDR0_CP440_ERPN_EBC 0x10000000 -#define SDR0_CP440_ERPN_EBC_HI 0x1000 -#define SDR0_CP440_ERPN_EBC_LO 0x0000 -#define SDR0_CP440_ERPN_PCI 0x20000000 -#define SDR0_CP440_ERPN_PCI_HI 0x2000 -#define SDR0_CP440_ERPN_PCI_LO 0x0000 -#define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28) -#define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03) -#define SDR0_CP440_NTO1_MASK 0x00000002 -#define SDR0_CP440_NTO1_NTOP 0x00000000 -#define SDR0_CP440_NTO1_NTO1 0x00000002 -#define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1) -#define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01) - -#define SDR0_XCR0 0x01C0 -#define SDR0_XCR1 0x01C3 -#define SDR0_XCR2 0x01C6 -#define SDR0_XCRn_PAE_MASK 0x80000000 -#define SDR0_XCRn_PAE_DISABLE 0x00000000 -#define SDR0_XCRn_PAE_ENABLE 0x80000000 -#define SDR0_XCRn_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) -#define SDR0_XCRn_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01) -#define SDR0_XCRn_PHCE_MASK 0x40000000 -#define SDR0_XCRn_PHCE_DISABLE 0x00000000 -#define SDR0_XCRn_PHCE_ENABLE 0x40000000 -#define SDR0_XCRn_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) -#define SDR0_XCRn_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01) -#define SDR0_XCRn_PISE_MASK 0x20000000 -#define SDR0_XCRn_PISE_DISABLE 0x00000000 -#define SDR0_XCRn_PISE_ENABLE 0x20000000 -#define SDR0_XCRn_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) -#define SDR0_XCRn_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01) -#define SDR0_XCRn_PCWE_MASK 0x10000000 -#define SDR0_XCRn_PCWE_DISABLE 0x00000000 -#define SDR0_XCRn_PCWE_ENABLE 0x10000000 -#define SDR0_XCRn_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28) -#define SDR0_XCRn_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01) -#define SDR0_XCRn_PPIM_MASK 0x0F000000 -#define SDR0_XCRn_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24) -#define SDR0_XCRn_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) -#define SDR0_XCRn_PR64E_MASK 0x00800000 -#define SDR0_XCRn_PR64E_DISABLE 0x00000000 -#define SDR0_XCRn_PR64E_ENABLE 0x00800000 -#define SDR0_XCRn_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23) -#define SDR0_XCRn_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01) -#define SDR0_XCRn_PXFS_MASK 0x00600000 -#define SDR0_XCRn_PXFS_100_133 0x00000000 -#define SDR0_XCRn_PXFS_66_100 0x00200000 -#define SDR0_XCRn_PXFS_50_66 0x00400000 -#define SDR0_XCRn_PXFS_0_33 0x00600000 -#define SDR0_XCRn_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21) -#define SDR0_XCRn_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03) - -#define SDR0_XPLLC0 0x01C1 -#define SDR0_XPLLD0 0x01C2 -#define SDR0_XPLLC1 0x01C4 -#define SDR0_XPLLD1 0x01C5 -#define SDR0_XPLLC2 0x01C7 -#define SDR0_XPLLD2 0x01C8 -#define SDR0_SRST 0x0200 #define SDR0_SLPIPE 0x0220 #define SDR0_AMP0 0x0240 @@ -1544,8 +1387,7 @@ #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define SDR0_SRST0 0x0200 -#define SDR0_SRST SDR0_SRST0 /* for compatability reasons */ +#define SDR0_SRST0 SDR0_SRST /* for compatability reasons */ #define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ #define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */ #define SDR0_SRST0_EBC 0x20000000 /* External bus controller */ @@ -1607,8 +1449,6 @@ #define SDR0_SRST1_AHBICM 0x00000002 /* AHB inter-connect matrix */ #define SDR0_SRST1_SATA 0x00000001 /* Serial ATA controller */ -#define SDR0_PCI0 0x1c0 /* PCI Configuration Register */ - #else #define SDR0_SRST_BGO 0x80000000 diff --git a/include/ppc4xx.h b/include/ppc4xx.h index a9954aa3de3..086f8fb7ee3 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -65,49 +65,37 @@ #define PLB_ARBITER_BASE 0x80 -#define plb0_revid (PLB_ARBITER_BASE + 0x00) -#define plb0_acr (PLB_ARBITER_BASE + 0x01) -#define plb0_acr_ppm_mask 0xF0000000 -#define plb0_acr_ppm_fixed 0x00000000 -#define plb0_acr_ppm_fair 0xD0000000 -#define plb0_acr_hbu_mask 0x08000000 -#define plb0_acr_hbu_disabled 0x00000000 -#define plb0_acr_hbu_enabled 0x08000000 -#define plb0_acr_rdp_mask 0x06000000 -#define plb0_acr_rdp_disabled 0x00000000 -#define plb0_acr_rdp_2deep 0x02000000 -#define plb0_acr_rdp_3deep 0x04000000 -#define plb0_acr_rdp_4deep 0x06000000 -#define plb0_acr_wrp_mask 0x01000000 -#define plb0_acr_wrp_disabled 0x00000000 -#define plb0_acr_wrp_2deep 0x01000000 +#define PLB0_ACR (PLB_ARBITER_BASE + 0x01) +#define PLB0_ACR_PPM_MASK 0xF0000000 +#define PLB0_ACR_PPM_FIXED 0x00000000 +#define PLB0_ACR_PPM_FAIR 0xD0000000 +#define PLB0_ACR_HBU_MASK 0x08000000 +#define PLB0_ACR_HBU_DISABLED 0x00000000 +#define PLB0_ACR_HBU_ENABLED 0x08000000 +#define PLB0_ACR_RDP_MASK 0x06000000 +#define PLB0_ACR_RDP_DISABLED 0x00000000 +#define PLB0_ACR_RDP_2DEEP 0x02000000 +#define PLB0_ACR_RDP_3DEEP 0x04000000 +#define PLB0_ACR_RDP_4DEEP 0x06000000 +#define PLB0_ACR_WRP_MASK 0x01000000 +#define PLB0_ACR_WRP_DISABLED 0x00000000 +#define PLB0_ACR_WRP_2DEEP 0x01000000 -#define plb0_besrl (PLB_ARBITER_BASE + 0x02) -#define plb0_besrh (PLB_ARBITER_BASE + 0x03) -#define plb0_bearl (PLB_ARBITER_BASE + 0x04) -#define plb0_bearh (PLB_ARBITER_BASE + 0x05) -#define plb0_ccr (PLB_ARBITER_BASE + 0x08) - -#define plb1_acr (PLB_ARBITER_BASE + 0x09) -#define plb1_acr_ppm_mask 0xF0000000 -#define plb1_acr_ppm_fixed 0x00000000 -#define plb1_acr_ppm_fair 0xD0000000 -#define plb1_acr_hbu_mask 0x08000000 -#define plb1_acr_hbu_disabled 0x00000000 -#define plb1_acr_hbu_enabled 0x08000000 -#define plb1_acr_rdp_mask 0x06000000 -#define plb1_acr_rdp_disabled 0x00000000 -#define plb1_acr_rdp_2deep 0x02000000 -#define plb1_acr_rdp_3deep 0x04000000 -#define plb1_acr_rdp_4deep 0x06000000 -#define plb1_acr_wrp_mask 0x01000000 -#define plb1_acr_wrp_disabled 0x00000000 -#define plb1_acr_wrp_2deep 0x01000000 - -#define plb1_besrl (PLB_ARBITER_BASE + 0x0A) -#define plb1_besrh (PLB_ARBITER_BASE + 0x0B) -#define plb1_bearl (PLB_ARBITER_BASE + 0x0C) -#define plb1_bearh (PLB_ARBITER_BASE + 0x0D) +#define PLB1_ACR (PLB_ARBITER_BASE + 0x09) +#define PLB1_ACR_PPM_MASK 0xF0000000 +#define PLB1_ACR_PPM_FIXED 0x00000000 +#define PLB1_ACR_PPM_FAIR 0xD0000000 +#define PLB1_ACR_HBU_MASK 0x08000000 +#define PLB1_ACR_HBU_DISABLED 0x00000000 +#define PLB1_ACR_HBU_ENABLED 0x08000000 +#define PLB1_ACR_RDP_MASK 0x06000000 +#define PLB1_ACR_RDP_DISABLED 0x00000000 +#define PLB1_ACR_RDP_2DEEP 0x02000000 +#define PLB1_ACR_RDP_3DEEP 0x04000000 +#define PLB1_ACR_RDP_4DEEP 0x06000000 +#define PLB1_ACR_WRP_MASK 0x01000000 +#define PLB1_ACR_WRP_DISABLED 0x00000000 +#define PLB1_ACR_WRP_2DEEP 0x01000000 #endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/ @@ -156,35 +144,35 @@ line aligned data. */ #define CPR0_DCR_BASE 0x0C -#define cprcfga (CPR0_DCR_BASE+0x0) -#define cprcfgd (CPR0_DCR_BASE+0x1) +#define CPR0_CFGADDR (CPR0_DCR_BASE + 0x0) +#define CPR0_CFGDATA (CPR0_DCR_BASE + 0x1) #define SDR_DCR_BASE 0x0E -#define sdrcfga (SDR_DCR_BASE+0x0) -#define sdrcfgd (SDR_DCR_BASE+0x1) +#define SDR0_CFGADDR (SDR_DCR_BASE + 0x0) +#define SDR0_CFGDATA (SDR_DCR_BASE + 0x1) #define SDRAM_DCR_BASE 0x10 -#define memcfga (SDRAM_DCR_BASE+0x0) -#define memcfgd (SDRAM_DCR_BASE+0x1) +#define SDRAM0_CFGADDR (SDRAM_DCR_BASE + 0x0) +#define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1) #define EBC_DCR_BASE 0x12 -#define ebccfga (EBC_DCR_BASE+0x0) -#define ebccfgd (EBC_DCR_BASE+0x1) +#define EBC0_CFGADDR (EBC_DCR_BASE + 0x0) +#define EBC0_CFGDATA (EBC_DCR_BASE + 0x1) /* * Macros for indirect DCR access */ -#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0) -#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0) +#define mtcpr(reg, d) do { mtdcr(CPR0_CFGADDR,reg);mtdcr(CPR0_CFGDATA,d); } while (0) +#define mfcpr(reg, d) do { mtdcr(CPR0_CFGADDR,reg);d = mfdcr(CPR0_CFGDATA); } while (0) -#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0) -#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0) +#define mtebc(reg, d) do { mtdcr(EBC0_CFGADDR,reg);mtdcr(EBC0_CFGDATA,d); } while (0) +#define mfebc(reg, d) do { mtdcr(EBC0_CFGADDR,reg);d = mfdcr(EBC0_CFGDATA); } while (0) -#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0) -#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0) +#define mtsdram(reg, d) do { mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,d); } while (0) +#define mfsdram(reg, d) do { mtdcr(SDRAM0_CFGADDR,reg);d = mfdcr(SDRAM0_CFGDATA); } while (0) -#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0) -#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0) +#define mtsdr(reg, d) do { mtdcr(SDR0_CFGADDR,reg);mtdcr(SDR0_CFGDATA,d); } while (0) +#define mfsdr(reg, d) do { mtdcr(SDR0_CFGADDR,reg);d = mfdcr(SDR0_CFGDATA); } while (0) #ifndef __ASSEMBLY__ diff --git a/nand_spl/board/amcc/bamboo/sdram.c b/nand_spl/board/amcc/bamboo/sdram.c index 54be2566c0c..df03afe0a47 100644 --- a/nand_spl/board/amcc/bamboo/sdram.c +++ b/nand_spl/board/amcc/bamboo/sdram.c @@ -56,8 +56,8 @@ phys_size_t initdram(int board_type) /* * Soft-reset SDRAM controller. */ - mtsdr(sdr_srst, SDR0_SRST_DMC); - mtsdr(sdr_srst, 0x00000000); + mtsdr(SDR0_SRST, SDR0_SRST_DMC); + mtsdr(SDR0_SRST, 0x00000000); /* * Disable memory controller. diff --git a/post/cpu/ppc4xx/ether.c b/post/cpu/ppc4xx/ether.c index e40e19be235..c3665da94a6 100644 --- a/post/cpu/ppc4xx/ether.c +++ b/post/cpu/ppc4xx/ether.c @@ -109,9 +109,9 @@ static void ether_post_init (int devnum, int hw_addr) #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* provide clocks for EMAC internal loopback */ - mfsdr (sdr_mfr, mfr); + mfsdr (SDR0_MFR, mfr); mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum); - mtsdr (sdr_mfr, mfr); + mtsdr (SDR0_MFR, mfr); sync (); #endif /* reset emac */ @@ -150,13 +150,13 @@ static void ether_post_init (int devnum, int hw_addr) #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) - mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | + mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT | 0x00330000); #else - mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); + mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); /* Errata 1.12: MAL_1 -- Disable MAL bursting */ if (get_pvr() == PVR_440GP_RB) { - mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB); + mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB); } #endif /* setup buffer descriptors */ @@ -174,39 +174,39 @@ static void ether_post_init (int devnum, int hw_addr) case 1: /* setup MAL tx & rx channel pointers */ #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR) - mtdcr (maltxctp2r, &tx); + mtdcr (MAL0_TXCTP2R, &tx); #else - mtdcr (maltxctp1r, &tx); + mtdcr (MAL0_TXCTP1R, &tx); #endif #if defined(CONFIG_440) - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); #endif - mtdcr (malrxctp1r, &rx); + mtdcr (MAL0_RXCTP1R, &rx); /* set RX buffer size */ - mtdcr (malrcbs1, PKTSIZE_ALIGN / 16); + mtdcr (MAL0_RCBS1, PKTSIZE_ALIGN / 16); break; case 0: default: /* setup MAL tx & rx channel pointers */ #if defined(CONFIG_440) - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); #endif - mtdcr (maltxctp0r, &tx); - mtdcr (malrxctp0r, &rx); + mtdcr (MAL0_TXCTP0R, &tx); + mtdcr (MAL0_RXCTP0R, &rx); /* set RX buffer size */ - mtdcr (malrcbs0, PKTSIZE_ALIGN / 16); + mtdcr (MAL0_RCBS0, PKTSIZE_ALIGN / 16); break; } /* Enable MAL transmit and receive channels */ #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) - mtdcr (maltxcasr, (MAL_TXRX_CASR >> (devnum*2))); + mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (devnum*2))); #else - mtdcr (maltxcasr, (MAL_TXRX_CASR >> devnum)); + mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> devnum)); #endif - mtdcr (malrxcasr, (MAL_TXRX_CASR >> devnum)); + mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> devnum)); /* set internal loopback mode */ #ifdef CONFIG_SYS_POST_ETHER_EXT_LOOPBACK @@ -257,14 +257,14 @@ static void ether_post_halt (int devnum, int hw_addr) /* 1st reset MAL channel */ /* Note: writing a 0 to a channel has no effect */ #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) - mtdcr (maltxcarr, MAL_TXRX_CASR >> (devnum * 2)); + mtdcr (MAL0_TXCARR, MAL_TXRX_CASR >> (devnum * 2)); #else - mtdcr (maltxcarr, MAL_TXRX_CASR >> devnum); + mtdcr (MAL0_TXCARR, MAL_TXRX_CASR >> devnum); #endif - mtdcr (malrxcarr, MAL_TXRX_CASR >> devnum); + mtdcr (MAL0_RXCARR, MAL_TXRX_CASR >> devnum); /* wait for reset */ - while (mfdcr (malrxcasr) & (MAL_TXRX_CASR >> devnum)) { + while (mfdcr (MAL0_RXCASR) & (MAL_TXRX_CASR >> devnum)) { if (i++ >= 1000) break; udelay (1000); @@ -274,9 +274,9 @@ static void ether_post_halt (int devnum, int hw_addr) #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* remove clocks for EMAC internal loopback */ - mfsdr (sdr_mfr, mfr); + mfsdr (SDR0_MFR, mfr); mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum); - mtsdr (sdr_mfr, mfr); + mtsdr (SDR0_MFR, mfr); #endif } diff --git a/post/cpu/ppc4xx/uart.c b/post/cpu/ppc4xx/uart.c index 84a4d0a0d63..be217fcf8db 100644 --- a/post/cpu/ppc4xx/uart.c +++ b/post/cpu/ppc4xx/uart.c @@ -68,7 +68,7 @@ #define CR0_EXTCLK_ENA 0x00600000 #define CR0_UDIV_POS 16 #define UDIV_SUBTRACT 1 -#define UART0_SDR cntrl0 +#define UART0_SDR CPC0_CR0 #define MFREG(a, d) d = mfdcr(a) #define MTREG(a, d) mtdcr(a, d) #else /* #if defined(CONFIG_440GP) */ @@ -77,16 +77,16 @@ #define CR0_EXTCLK_ENA 0x00800000 #define CR0_UDIV_POS 0 #define UDIV_SUBTRACT 0 -#define UART0_SDR sdr_uart0 -#define UART1_SDR sdr_uart1 +#define UART0_SDR SDR0_UART0 +#define UART1_SDR SDR0_UART1 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) -#define UART2_SDR sdr_uart2 +#define UART2_SDR SDR0_UART2 #endif #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ defined(CONFIG_440GR) || defined(CONFIG_440GRX) -#define UART3_SDR sdr_uart3 +#define UART3_SDR SDR0_UART3 #endif #define MFREG(a, d) mfsdr(a, d) #define MTREG(a, d) mtsdr(a, d) @@ -106,8 +106,8 @@ #define CR0_EXTCLK_ENA 0x00800000 #define CR0_UDIV_POS 0 #define UDIV_SUBTRACT 0 -#define UART0_SDR sdr_uart0 -#define UART1_SDR sdr_uart1 +#define UART0_SDR SDR0_UART0 +#define UART1_SDR SDR0_UART1 #define MFREG(a, d) mfsdr(a, d) #define MTREG(a, d) mtsdr(a, d) #else /* CONFIG_405GP || CONFIG_405CR */ @@ -276,7 +276,7 @@ static int uart_post_init (unsigned long dev_base) clk = tmp = reg = 0; #else #ifdef CONFIG_405EP - reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK); + reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK); clk = gd->cpu_clk; tmp = CONFIG_SYS_BASE_BAUD * 16; udiv = (clk + tmp / 2) / tmp; @@ -284,9 +284,9 @@ static int uart_post_init (unsigned long dev_base) udiv = UDIV_MAX; reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */ reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */ - mtdcr (cpc0_ucr, reg); + mtdcr (CPC0_UCR, reg); #else /* CONFIG_405EP */ - reg = mfdcr(cntrl0) & ~CR0_MASK; + reg = mfdcr(CPC0_CR0) & ~CR0_MASK; #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK clk = CONFIG_SYS_EXT_SERIAL_CLOCK; udiv = 1; @@ -303,7 +303,7 @@ static int uart_post_init (unsigned long dev_base) #endif #endif reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ - mtdcr (cntrl0, reg); + mtdcr (CPC0_CR0, reg); #endif /* CONFIG_405EP */ tmp = gd->baudrate * udiv * 16; bdiv = (clk + tmp / 2) / tmp; From 4c1883670acbf1cc83c04df1876235c3aedde128 Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Wed, 9 Sep 2009 12:36:07 +0200 Subject: [PATCH 083/208] ppc4xx: Rename compactcenter to intip Signed-off-by: Dirk Eibach Signed-off-by: Stefan Roese --- MAINTAINERS | 2 +- MAKEALL | 2 +- Makefile | 16 ++++++++-------- board/gdsys/{compactcenter => intip}/Makefile | 0 .../gdsys/{compactcenter => intip}/chip_config.c | 0 board/gdsys/{compactcenter => intip}/config.mk | 0 board/gdsys/{compactcenter => intip}/init.S | 0 .../compactcenter.c => intip/intip.c} | 2 +- board/gdsys/{compactcenter => intip}/u-boot.lds | 2 +- include/configs/{compactcenter.h => intip.h} | 8 ++++---- 10 files changed, 16 insertions(+), 16 deletions(-) rename board/gdsys/{compactcenter => intip}/Makefile (100%) rename board/gdsys/{compactcenter => intip}/chip_config.c (100%) rename board/gdsys/{compactcenter => intip}/config.mk (100%) rename board/gdsys/{compactcenter => intip}/init.S (100%) rename board/gdsys/{compactcenter/compactcenter.c => intip/intip.c} (99%) rename board/gdsys/{compactcenter => intip}/u-boot.lds (98%) rename include/configs/{compactcenter.h => intip.h} (98%) diff --git a/MAINTAINERS b/MAINTAINERS index e9db27842eb..e0d4786a790 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -141,10 +141,10 @@ Jon Diekema Dirk Eibach - compactcenter PPC460EX devconcenter PPC460EX dlvision PPC405EP gdppc440etx PPC440EP/GR + intip PPC460EX neo PPC405EP Dave Ellis diff --git a/MAKEALL b/MAKEALL index f0ed8ea87fa..b3d35ac05ff 100755 --- a/MAKEALL +++ b/MAKEALL @@ -185,7 +185,6 @@ LIST_4xx=" \ canyonlands \ canyonlands_nand \ CMS700 \ - compactcenter \ CPCI2DP \ CPCI405 \ CPCI4052 \ @@ -214,6 +213,7 @@ LIST_4xx=" \ hcu5 \ HH405 \ HUB405 \ + intip \ JSE \ KAREF \ katmai \ diff --git a/Makefile b/Makefile index 9764cea894f..e8c90a2f260 100644 --- a/Makefile +++ b/Makefile @@ -1308,14 +1308,6 @@ CATcenter_33_config: unconfig CMS700_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx cms700 esd -# Compact-Center & DevCon-Center use different U-Boot images -compactcenter_config \ -devconcenter_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \ - tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h - @$(MKCONFIG) -n $@ -a compactcenter ppc ppc4xx compactcenter gdsys - CPCI2DP_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci2dp esd @@ -1400,6 +1392,14 @@ HH405_config: unconfig HUB405_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx hub405 esd +# Compact-Center(codename intip) & DevCon-Center use different U-Boot images +intip_config \ +devconcenter_config: unconfig + @mkdir -p $(obj)include + @echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \ + tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h + @$(MKCONFIG) -n $@ -a intip ppc ppc4xx intip gdsys + JSE_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx jse diff --git a/board/gdsys/compactcenter/Makefile b/board/gdsys/intip/Makefile similarity index 100% rename from board/gdsys/compactcenter/Makefile rename to board/gdsys/intip/Makefile diff --git a/board/gdsys/compactcenter/chip_config.c b/board/gdsys/intip/chip_config.c similarity index 100% rename from board/gdsys/compactcenter/chip_config.c rename to board/gdsys/intip/chip_config.c diff --git a/board/gdsys/compactcenter/config.mk b/board/gdsys/intip/config.mk similarity index 100% rename from board/gdsys/compactcenter/config.mk rename to board/gdsys/intip/config.mk diff --git a/board/gdsys/compactcenter/init.S b/board/gdsys/intip/init.S similarity index 100% rename from board/gdsys/compactcenter/init.S rename to board/gdsys/intip/init.S diff --git a/board/gdsys/compactcenter/compactcenter.c b/board/gdsys/intip/intip.c similarity index 99% rename from board/gdsys/compactcenter/compactcenter.c rename to board/gdsys/intip/intip.c index 8a5ea300d7a..0de1be85792 100644 --- a/board/gdsys/compactcenter/compactcenter.c +++ b/board/gdsys/intip/intip.c @@ -129,7 +129,7 @@ int checkboard(void) #ifdef CONFIG_DEVCONCENTER printf("Board: DevCon-Center"); #else - printf("Board: CompactCenter"); + printf("Board: Intip"); #endif if (s != NULL) { diff --git a/board/gdsys/compactcenter/u-boot.lds b/board/gdsys/intip/u-boot.lds similarity index 98% rename from board/gdsys/compactcenter/u-boot.lds rename to board/gdsys/intip/u-boot.lds index 0c95d5c298c..c1cbd1c4ace 100644 --- a/board/gdsys/compactcenter/u-boot.lds +++ b/board/gdsys/intip/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/ppc4xx/start.o (.text) - board/gdsys/compactcenter/init.o (.text) + board/gdsys/intip/init.o (.text) *(.text) *(.fixup) diff --git a/include/configs/compactcenter.h b/include/configs/intip.h similarity index 98% rename from include/configs/compactcenter.h rename to include/configs/intip.h index f8a1bbb9829..4f7bc7e28dc 100644 --- a/include/configs/compactcenter.h +++ b/include/configs/intip.h @@ -23,7 +23,7 @@ */ /* - * compactcenter.h - configuration for CompactCenter (460EX) + * intip.h - configuration for CompactCenter aka intip (460EX) and DevCon-Center */ #ifndef __CONFIG_H #define __CONFIG_H @@ -32,15 +32,15 @@ * High Level Configuration Options */ /* - * This config file is used for CompactCenter and DevCon-Center + * This config file is used for CompactCenter(codename intip) and DevCon-Center */ #define CONFIG_460EX 1 /* Specific PPC460EX */ #ifdef CONFIG_DEVCONCENTER #define CONFIG_HOSTNAME devconcenter #define CONFIG_IDENT_STRING " devconcenter 0.02" #else -#define CONFIG_HOSTNAME compactcenter -#define CONFIG_IDENT_STRING " compactcenter 0.02" +#define CONFIG_HOSTNAME intip +#define CONFIG_IDENT_STRING " intip 0.02" #endif #define CONFIG_440 1 #define CONFIG_4xx 1 /* ... PPC4xx family */ From aedb4683097d3e5de8833f4a9e34664d3d2bd077 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 14 Aug 2009 17:02:35 +0200 Subject: [PATCH 084/208] microblaze: Add sbss, scommon and COMMON symbols for clearing Signed-off-by: Michal Simek --- board/xilinx/microblaze-generic/u-boot.lds | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/xilinx/microblaze-generic/u-boot.lds b/board/xilinx/microblaze-generic/u-boot.lds index 5a086801500..c20c6dd1d67 100644 --- a/board/xilinx/microblaze-generic/u-boot.lds +++ b/board/xilinx/microblaze-generic/u-boot.lds @@ -60,7 +60,10 @@ SECTIONS .bss ALIGN(0x4): { __bss_start = .; + *(.sbss) + *(.scommon) *(.bss) + *(COMMON) . = ALIGN(4); __bss_end = .; } From 2fddd44464d02e0f3ade06dabe0e165835fa61f0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 19 Aug 2009 08:10:08 +0200 Subject: [PATCH 085/208] microblaze: Short size of global data and fix malloc size If is full malloc area global, data are rewrite because there was bad size of malloc area. Signed-off-by: Michal Simek --- include/configs/microblaze-generic.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 72715f6ed9d..ca071a31bca 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -136,13 +136,13 @@ #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) /* global pointer */ -#define CONFIG_SYS_GBL_DATA_SIZE 0x1000 /* size of global data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size of global data */ /* start of global data */ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE) /* monitor code */ #define SIZE 0x40000 -#define CONFIG_SYS_MONITOR_LEN SIZE +#define CONFIG_SYS_MONITOR_LEN (SIZE - CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN) #define CONFIG_SYS_MONITOR_END (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) #define CONFIG_SYS_MALLOC_LEN SIZE From 3ceba1d45d007144d10368f91ff9e36f3b5f39a1 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 20 Aug 2009 22:36:20 +0200 Subject: [PATCH 086/208] net: Remove old Xilinx Emac driver Signed-off-by: Michal Simek --- drivers/net/Makefile | 1 - drivers/net/xilinx_emac.c | 464 --------------------------- include/configs/microblaze-generic.h | 5 +- 3 files changed, 1 insertion(+), 469 deletions(-) delete mode 100644 drivers/net/xilinx_emac.c diff --git a/drivers/net/Makefile b/drivers/net/Makefile index f6e9f6796c6..be5c484d186 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -72,7 +72,6 @@ COBJS-$(CONFIG_TSEC_ENET) += tsec.o COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o COBJS-$(CONFIG_ULI526X) += uli526x.o COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o -COBJS-$(CONFIG_XILINX_EMAC) += xilinx_emac.o COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o COBJS := $(COBJS-y) diff --git a/drivers/net/xilinx_emac.c b/drivers/net/xilinx_emac.c deleted file mode 100644 index a489aa97fe9..00000000000 --- a/drivers/net/xilinx_emac.c +++ /dev/null @@ -1,464 +0,0 @@ -/****************************************************************************** - * - * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" - * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND - * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, - * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, - * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION - * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, - * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE - * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY - * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE - * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR - * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF - * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE. - * - * (C) Copyright 2007-2008 Michal Simek - * Michal SIMEK - * - * (c) Copyright 2003 Xilinx Inc. - * All rights reserved. - * - ******************************************************************************/ - -#include -#include -#include -#include - -#include - -#undef DEBUG - -typedef struct { - u32 regbaseaddress; /* Base address of registers */ - u32 databaseaddress; /* Base address of data for FIFOs */ -} xpacketfifov100b; - -typedef struct { - u32 baseaddress; /* Base address (of IPIF) */ - u32 isstarted; /* Device is currently started 0-no, 1-yes */ - xpacketfifov100b recvfifo; /* FIFO used to receive frames */ - xpacketfifov100b sendfifo; /* FIFO used to send frames */ -} xemac; - -#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */ -#define XIIF_V123B_RESET_MASK 0xAUL -#define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */ - -/* This constant is used with the Reset Register */ -#define XPF_RESET_FIFO_MASK 0x0000000A -#define XPF_COUNT_STATUS_REG_OFFSET 4UL - -/* These constants are used with the Occupancy/Vacancy Count Register. This - * register also contains FIFO status */ -#define XPF_COUNT_MASK 0x0000FFFF -#define XPF_DEADLOCK_MASK 0x20000000 - -/* Offset of the MAC registers from the IPIF base address */ -#define XEM_REG_OFFSET 0x1100UL - -/* - * Register offsets for the Ethernet MAC. Each register is 32 bits. - */ -#define XEM_ECR_OFFSET (XEM_REG_OFFSET + 0x4) /* MAC Control */ -#define XEM_SAH_OFFSET (XEM_REG_OFFSET + 0xC) /* Station addr, high */ -#define XEM_SAL_OFFSET (XEM_REG_OFFSET + 0x10) /* Station addr, low */ -#define XEM_RPLR_OFFSET (XEM_REG_OFFSET + 0x1C) /* Rx packet length */ -#define XEM_TPLR_OFFSET (XEM_REG_OFFSET + 0x20) /* Tx packet length */ -#define XEM_TSR_OFFSET (XEM_REG_OFFSET + 0x24) /* Tx status */ - -#define XEM_PFIFO_OFFSET 0x2000UL -/* Tx registers */ -#define XEM_PFIFO_TXREG_OFFSET (XEM_PFIFO_OFFSET + 0x0) -/* Rx registers */ -#define XEM_PFIFO_RXREG_OFFSET (XEM_PFIFO_OFFSET + 0x10) -/* Tx keyhole */ -#define XEM_PFIFO_TXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x100) -/* Rx keyhole */ -#define XEM_PFIFO_RXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x200) - -/* - * EMAC Interrupt Registers (Status and Enable) masks. These registers are - * part of the IPIF IP Interrupt registers - */ -/* A mask for all transmit interrupts, used in polled mode */ -#define XEM_EIR_XMIT_ALL_MASK (XEM_EIR_XMIT_DONE_MASK |\ - XEM_EIR_XMIT_ERROR_MASK | \ - XEM_EIR_XMIT_SFIFO_EMPTY_MASK |\ - XEM_EIR_XMIT_LFIFO_FULL_MASK) - -/* Xmit complete */ -#define XEM_EIR_XMIT_DONE_MASK 0x00000001UL -/* Recv complete */ -#define XEM_EIR_RECV_DONE_MASK 0x00000002UL -/* Xmit error */ -#define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL -/* Recv error */ -#define XEM_EIR_RECV_ERROR_MASK 0x00000008UL -/* Xmit status fifo empty */ -#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL -/* Recv length fifo empty */ -#define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL -/* Xmit length fifo full */ -#define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL -/* Recv length fifo overrun */ -#define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL -/* Recv length fifo underrun */ -#define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL -/* Xmit status fifo overrun */ -#define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL -/* Transmit status fifo underrun */ -#define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL -/* Transmit length fifo overrun */ -#define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL -/* Transmit length fifo underrun */ -#define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL -/* Transmit pause pkt received */ -#define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL - -/* - * EMAC Control Register (ECR) - */ -/* Full duplex mode */ -#define XEM_ECR_FULL_DUPLEX_MASK 0x80000000UL -/* Reset transmitter */ -#define XEM_ECR_XMIT_RESET_MASK 0x40000000UL -/* Enable transmitter */ -#define XEM_ECR_XMIT_ENABLE_MASK 0x20000000UL -/* Reset receiver */ -#define XEM_ECR_RECV_RESET_MASK 0x10000000UL -/* Enable receiver */ -#define XEM_ECR_RECV_ENABLE_MASK 0x08000000UL -/* Enable PHY */ -#define XEM_ECR_PHY_ENABLE_MASK 0x04000000UL -/* Enable xmit pad insert */ -#define XEM_ECR_XMIT_PAD_ENABLE_MASK 0x02000000UL -/* Enable xmit FCS insert */ -#define XEM_ECR_XMIT_FCS_ENABLE_MASK 0x01000000UL -/* Enable unicast addr */ -#define XEM_ECR_UNICAST_ENABLE_MASK 0x00020000UL -/* Enable broadcast addr */ -#define XEM_ECR_BROAD_ENABLE_MASK 0x00008000UL - -/* - * Transmit Status Register (TSR) - */ -/* Transmit excess deferral */ -#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL -/* Transmit late collision */ -#define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL - -#define ENET_MAX_MTU PKTSIZE -#define ENET_ADDR_LENGTH 6 - -static unsigned int etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ - -static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 }; - -static xemac emac; - -void eth_halt(void) -{ - debug ("eth_halt\n"); -} - -int eth_init(bd_t * bis) -{ - uchar enetaddr[6]; - u32 helpreg; - debug ("EMAC Initialization Started\n\r"); - - if (emac.isstarted) { - puts("Emac is started\n"); - return 0; - } - - memset (&emac, 0, sizeof (xemac)); - - emac.baseaddress = XILINX_EMAC_BASEADDR; - - /* Setting up FIFOs */ - emac.recvfifo.regbaseaddress = emac.baseaddress + - XEM_PFIFO_RXREG_OFFSET; - emac.recvfifo.databaseaddress = emac.baseaddress + - XEM_PFIFO_RXDATA_OFFSET; - out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK); - - emac.sendfifo.regbaseaddress = emac.baseaddress + - XEM_PFIFO_TXREG_OFFSET; - emac.sendfifo.databaseaddress = emac.baseaddress + - XEM_PFIFO_TXDATA_OFFSET; - out_be32 (emac.sendfifo.regbaseaddress, XPF_RESET_FIFO_MASK); - - /* Reset the entire IPIF */ - out_be32 (emac.baseaddress + XIIF_V123B_RESETR_OFFSET, - XIIF_V123B_RESET_MASK); - - /* Stopping EMAC for setting up MAC */ - helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET); - helpreg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); - out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg); - - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - memcpy(enetaddr, emacaddr, ENET_ADDR_LENGTH); - eth_setenv_enetaddr("ethaddr", enetaddr); - } - - /* Set the device station address high and low registers */ - helpreg = (enetaddr[0] << 8) | enetaddr[1]; - out_be32 (emac.baseaddress + XEM_SAH_OFFSET, helpreg); - helpreg = (enetaddr[2] << 24) | (enetaddr[3] << 16) | - (enetaddr[4] << 8) | enetaddr[5]; - out_be32 (emac.baseaddress + XEM_SAL_OFFSET, helpreg); - - helpreg = XEM_ECR_UNICAST_ENABLE_MASK | XEM_ECR_BROAD_ENABLE_MASK | - XEM_ECR_FULL_DUPLEX_MASK | XEM_ECR_XMIT_FCS_ENABLE_MASK | - XEM_ECR_XMIT_PAD_ENABLE_MASK | XEM_ECR_PHY_ENABLE_MASK; - out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg); - - emac.isstarted = 1; - - /* Enable the transmitter, and receiver */ - helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET); - helpreg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK); - helpreg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); - out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg); - - printf("EMAC Initialization complete\n\r"); - return 0; -} - -int eth_send(volatile void *ptr, int len) -{ - u32 intrstatus; - u32 xmitstatus; - u32 fifocount; - u32 wordcount; - u32 extrabytecount; - u32 *wordbuffer = (u32 *) ptr; - - if (len > ENET_MAX_MTU) - len = ENET_MAX_MTU; - - /* - * Check for overruns and underruns for the transmit status and length - * FIFOs and make sure the send packet FIFO is not deadlocked. - * Any of these conditions is bad enough that we do not want to - * continue. The upper layer software should reset the device to resolve - * the error. - */ - intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET); - if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK | - XEM_EIR_XMIT_LFIFO_OVER_MASK)) { - debug ("Transmitting overrun error\n"); - return 0; - } else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK | - XEM_EIR_XMIT_LFIFO_UNDER_MASK)) { - debug ("Transmitting underrun error\n"); - return 0; - } else if (in_be32 (emac.sendfifo.regbaseaddress + - XPF_COUNT_STATUS_REG_OFFSET) & XPF_DEADLOCK_MASK) { - debug ("Transmitting fifo error\n"); - return 0; - } - - /* - * Before writing to the data FIFO, make sure the length FIFO is not - * full. The data FIFO might not be full yet even though the length FIFO - * is. This avoids an overrun condition on the length FIFO and keeps the - * FIFOs in sync. - * - * Clear the latched LFIFO_FULL bit so next time around the most - * current status is represented - */ - if (intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) { - out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET, - intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK); - debug ("Fifo is full\n"); - return 0; - } - - /* get the count of how many words may be inserted into the FIFO */ - fifocount = in_be32 (emac.sendfifo.regbaseaddress + - XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK; - wordcount = len >> 2; - extrabytecount = len & 0x3; - - if (fifocount < wordcount) { - debug ("Sending packet is larger then size of FIFO\n"); - return 0; - } - - for (fifocount = 0; fifocount < wordcount; fifocount++) { - out_be32 (emac.sendfifo.databaseaddress, wordbuffer[fifocount]); - } - if (extrabytecount > 0) { - u32 lastword = 0; - u8 *extrabytesbuffer = (u8 *) (wordbuffer + wordcount); - - if (extrabytecount == 1) { - lastword = extrabytesbuffer[0] << 24; - } else if (extrabytecount == 2) { - lastword = extrabytesbuffer[0] << 24 | - extrabytesbuffer[1] << 16; - } else if (extrabytecount == 3) { - lastword = extrabytesbuffer[0] << 24 | - extrabytesbuffer[1] << 16 | - extrabytesbuffer[2] << 8; - } - out_be32 (emac.sendfifo.databaseaddress, lastword); - } - - /* Loop on the MAC's status to wait for any pause to complete */ - intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET); - while ((intrstatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) { - intrstatus = in_be32 ((emac.baseaddress) + - XIIF_V123B_IISR_OFFSET); - /* Clear the pause status from the transmit status register */ - out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET, - intrstatus & XEM_EIR_XMIT_PAUSE_MASK); - } - - /* - * Set the MAC's transmit packet length register to tell it to transmit - */ - out_be32 (emac.baseaddress + XEM_TPLR_OFFSET, len); - - /* - * Loop on the MAC's status to wait for the transmit to complete. - * The transmit status is in the FIFO when the XMIT_DONE bit is set. - */ - do { - intrstatus = in_be32 ((emac.baseaddress) + - XIIF_V123B_IISR_OFFSET); - } - while ((intrstatus & XEM_EIR_XMIT_DONE_MASK) == 0); - - xmitstatus = in_be32 (emac.baseaddress + XEM_TSR_OFFSET); - - if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK | - XEM_EIR_XMIT_LFIFO_OVER_MASK)) { - debug ("Transmitting overrun error\n"); - return 0; - } else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK | - XEM_EIR_XMIT_LFIFO_UNDER_MASK)) { - debug ("Transmitting underrun error\n"); - return 0; - } - - /* Clear the interrupt status register of transmit statuses */ - out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET, - intrstatus & XEM_EIR_XMIT_ALL_MASK); - - /* - * Collision errors are stored in the transmit status register - * instead of the interrupt status register - */ - if ((xmitstatus & XEM_TSR_EXCESS_DEFERRAL_MASK) || - (xmitstatus & XEM_TSR_LATE_COLLISION_MASK)) { - debug ("Transmitting collision error\n"); - return 0; - } - return 1; -} - -int eth_rx(void) -{ - u32 pktlength; - u32 intrstatus; - u32 fifocount; - u32 wordcount; - u32 extrabytecount; - u32 lastword; - u8 *extrabytesbuffer; - - if (in_be32 (emac.recvfifo.regbaseaddress + XPF_COUNT_STATUS_REG_OFFSET) - & XPF_DEADLOCK_MASK) { - out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK); - debug ("Receiving FIFO deadlock\n"); - return 0; - } - - /* - * Get the interrupt status to know what happened (whether an error - * occurred and/or whether frames have been received successfully). - * When clearing the intr status register, clear only statuses that - * pertain to receive. - */ - intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET); - /* - * Before reading from the length FIFO, make sure the length FIFO is not - * empty. We could cause an underrun error if we try to read from an - * empty FIFO. - */ - if (!(intrstatus & XEM_EIR_RECV_DONE_MASK)) { - /* debug ("Receiving FIFO is empty\n"); */ - return 0; - } - - /* - * Determine, from the MAC, the length of the next packet available - * in the data FIFO (there should be a non-zero length here) - */ - pktlength = in_be32 (emac.baseaddress + XEM_RPLR_OFFSET); - if (!pktlength) { - return 0; - } - - /* - * Write the RECV_DONE bit in the status register to clear it. This bit - * indicates the RPLR is non-empty, and we know it's set at this point. - * We clear it so that subsequent entry into this routine will reflect - * the current status. This is done because the non-empty bit is latched - * in the IPIF, which means it may indicate a non-empty condition even - * though there is something in the FIFO. - */ - out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET, - XEM_EIR_RECV_DONE_MASK); - - fifocount = in_be32 (emac.recvfifo.regbaseaddress + - XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK; - - if ((fifocount * 4) < pktlength) { - debug ("Receiving FIFO is smaller than packet size.\n"); - return 0; - } - - wordcount = pktlength >> 2; - extrabytecount = pktlength & 0x3; - - for (fifocount = 0; fifocount < wordcount; fifocount++) { - etherrxbuff[fifocount] = - in_be32 (emac.recvfifo.databaseaddress); - } - - /* - * if there are extra bytes to handle, read the last word from the FIFO - * and insert the extra bytes into the buffer - */ - if (extrabytecount > 0) { - extrabytesbuffer = (u8 *) (etherrxbuff + wordcount); - - lastword = in_be32 (emac.recvfifo.databaseaddress); - - /* - * one extra byte in the last word, put the byte into the next - * location of the buffer, bytes in a word of the FIFO are - * ordered from most significant byte to least - */ - if (extrabytecount == 1) { - extrabytesbuffer[0] = (u8) (lastword >> 24); - } else if (extrabytecount == 2) { - extrabytesbuffer[0] = (u8) (lastword >> 24); - extrabytesbuffer[1] = (u8) (lastword >> 16); - } else if (extrabytecount == 3) { - extrabytesbuffer[0] = (u8) (lastword >> 24); - extrabytesbuffer[1] = (u8) (lastword >> 16); - extrabytesbuffer[2] = (u8) (lastword >> 8); - } - } - NetReceive((uchar *)etherrxbuff, pktlength); - return 1; -} diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index ca071a31bca..4ab8ca39919 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -58,10 +58,7 @@ /*#define CONFIG_SYS_RESET_ADDRESS TEXT_BASE*/ /* ethernet */ -#ifdef XILINX_EMAC_BASEADDR - #define CONFIG_XILINX_EMAC 1 - #define CONFIG_SYS_ENET -#elif XILINX_EMACLITE_BASEADDR +#ifdef XILINX_EMACLITE_BASEADDR #define CONFIG_XILINX_EMACLITE 1 #define CONFIG_SYS_ENET #elif XILINX_LLTEMAC_BASEADDR From 13916abf996b127b681ddc26664c236ded28ba7f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 20 Aug 2009 22:44:02 +0200 Subject: [PATCH 087/208] microblaze: Remove AtmarkTechno Suzaku board Users should use microblaze-generic platform. This platform is longer not supported. Signed-off-by: Michal Simek --- MAINTAINERS | 4 - MAKEALL | 1 - Makefile | 5 -- board/AtmarkTechno/suzaku/Makefile | 44 ----------- board/AtmarkTechno/suzaku/config.mk | 29 ------- board/AtmarkTechno/suzaku/flash.c | 46 ----------- board/AtmarkTechno/suzaku/suzaku.c | 32 -------- board/AtmarkTechno/suzaku/u-boot.lds | 68 ----------------- include/configs/suzaku.h | 110 --------------------------- 9 files changed, 339 deletions(-) delete mode 100644 board/AtmarkTechno/suzaku/Makefile delete mode 100644 board/AtmarkTechno/suzaku/config.mk delete mode 100644 board/AtmarkTechno/suzaku/flash.c delete mode 100644 board/AtmarkTechno/suzaku/suzaku.c delete mode 100644 board/AtmarkTechno/suzaku/u-boot.lds delete mode 100644 include/configs/suzaku.h diff --git a/MAINTAINERS b/MAINTAINERS index e9db27842eb..bf01c7bd423 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -806,10 +806,6 @@ Scott McNutt # Board CPU # ######################################################################### -Yasushi Shoji - - SUZAKU MicroBlaze - Michal Simek microblaze-generic MicroBlaze diff --git a/MAKEALL b/MAKEALL index f0ed8ea87fa..f062a9e1404 100755 --- a/MAKEALL +++ b/MAKEALL @@ -775,7 +775,6 @@ LIST_nios2=" \ LIST_microblaze=" \ microblaze-generic \ - suzaku \ " ######################################################################### diff --git a/Makefile b/Makefile index 9764cea894f..0d4fcb0c4cb 100644 --- a/Makefile +++ b/Makefile @@ -3541,11 +3541,6 @@ microblaze-generic_config: unconfig @mkdir -p $(obj)include @$(MKCONFIG) -a $(@:_config=) microblaze microblaze microblaze-generic xilinx -suzaku_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_SUZAKU 1" > $(obj)include/config.h - @$(MKCONFIG) -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno - #======================================================================== # Blackfin #======================================================================== diff --git a/board/AtmarkTechno/suzaku/Makefile b/board/AtmarkTechno/suzaku/Makefile deleted file mode 100644 index 109cec26405..00000000000 --- a/board/AtmarkTechno/suzaku/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/AtmarkTechno/suzaku/config.mk b/board/AtmarkTechno/suzaku/config.mk deleted file mode 100644 index 7bbf2b130e4..00000000000 --- a/board/AtmarkTechno/suzaku/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2004 Atmark Techno, Inc. -# -# Yasushi SHOJI -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0x80F00000 - -PLATFORM_CPPFLAGS += -mno-xl-soft-mul -PLATFORM_CPPFLAGS += -mno-xl-soft-div -PLATFORM_CPPFLAGS += -mxl-barrel-shift diff --git a/board/AtmarkTechno/suzaku/flash.c b/board/AtmarkTechno/suzaku/flash.c deleted file mode 100644 index ce6fae01b4f..00000000000 --- a/board/AtmarkTechno/suzaku/flash.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -unsigned long flash_init(void) -{ - return 0; -} - -void flash_print_info(flash_info_t *info) -{ -} - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - return 0; -} - -int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - return 0; -} diff --git a/board/AtmarkTechno/suzaku/suzaku.c b/board/AtmarkTechno/suzaku/suzaku.c deleted file mode 100644 index 267c476f06c..00000000000 --- a/board/AtmarkTechno/suzaku/suzaku.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* This is a board specific file. It's OK to include board specific - * header files */ -#include - -void do_reset(void) -{ - *((unsigned long *)(MICROBLAZE_SYSREG_BASE_ADDR)) = MICROBLAZE_SYSREG_RECONFIGURE; -} diff --git a/board/AtmarkTechno/suzaku/u-boot.lds b/board/AtmarkTechno/suzaku/u-boot.lds deleted file mode 100644 index 5a086801500..00000000000 --- a/board/AtmarkTechno/suzaku/u-boot.lds +++ /dev/null @@ -1,68 +0,0 @@ -/* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(microblaze) -ENTRY(_start) - -SECTIONS -{ - .text ALIGN(0x4): - { - __text_start = .; - cpu/microblaze/start.o (.text) - *(.text) - __text_end = .; - } - - .rodata ALIGN(0x4): - { - __rodata_start = .; - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - __rodata_end = .; - } - - .data ALIGN(0x4): - { - __data_start = .; - *(.data) - __data_end = .; - } - - .u_boot_cmd ALIGN(0x4): - { - . = .; - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; - } - - .bss ALIGN(0x4): - { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end = .; - } - __end = . ; -} diff --git a/include/configs/suzaku.h b/include/configs/suzaku.h deleted file mode 100644 index 353e8db4270..00000000000 --- a/include/configs/suzaku.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MICROBLAZE 1 /* This is an MicroBlaze CPU */ -#define CONFIG_SUZAKU 1 /* on an SUZAKU Board */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_SIZE 0x01000000 -#define CONFIG_SYS_FLASH_BASE 0xfff00000 -#define CONFIG_SYS_FLASH_SIZE 0x00400000 -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - (1024 * 1024)) -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - (1024 * 1024)) - -#define CONFIG_XILINX_UARTLITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } - -/* System Register (GPIO) */ -#define MICROBLAZE_SYSREG_BASE_ADDR 0xFFFFA000 -#define MICROBLAZE_SYSREG_RECONFIGURE (1 << 0) - -/* - * Command line configuration. - */ -#include - -#undef CONFIG_CMD_BDI -#undef CONFIG_CMD_SAVEENV -#undef CONFIG_CMD_MEMORY -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_MISC - -#define CONFIG_SYS_UART1_BASE (0xFFFF2000) -#define CONFIG_SERIAL_BASE CONFIG_SYS_UART1_BASE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "SUZAKU> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default load address */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1 /* max number of sectors on one chip */ - -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CONFIG_ENV_IS_NOWHERE 1 -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define XILINX_CLOCK_FREQ 50000000 -#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ - -#endif /* __CONFIG_H */ From 0900bee9ab9818439b2d1298fa8909a88f74ec0d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 14 Aug 2009 13:41:17 +0200 Subject: [PATCH 088/208] microblaze: Enable hush parser With Hush parser is possible to change command line in dtb Signed-off-by: Michal Simek --- include/configs/microblaze-generic.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 4ab8ca39919..b486c7753c8 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -288,7 +288,7 @@ #define CONFIG_SYS_USR_EXCEP /* user exception */ #define CONFIG_SYS_HZ 1000 -#define CONFIG_PREBOOT "echo U-BOOT for $(hostname);setenv preboot;echo" +#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo" #define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\ "nor0=ml401-0\0"\ @@ -298,4 +298,10 @@ #define CONFIG_CMDLINE_EDITING +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + #endif /* __CONFIG_H */ From 78d19a398778a58d7b40b0c78e026515271b1a84 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 7 Sep 2009 09:08:02 +0200 Subject: [PATCH 089/208] net: emaclite: Cleanup license to be GPL compatible Signed-off-by: Stephen Neuendorffer Signed-off-by: Michal Simek --- drivers/net/xilinx_emaclite.c | 39 ++++++++++++++++++----------------- 1 file changed, 20 insertions(+), 19 deletions(-) diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index cf395738040..0820daa2bb8 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -1,26 +1,27 @@ -/****************************************************************************** +/* + * (C) Copyright 2007-2009 Michal Simek + * (C) Copyright 2003 Xilinx Inc. * - * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" - * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND - * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, - * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, - * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION - * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, - * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE - * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY - * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE - * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR - * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF - * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE. - * - * (C) Copyright 2007-2008 Michal Simek * Michal SIMEK * - * (c) Copyright 2003 Xilinx Inc. - * All rights reserved. + * See file CREDITS for list of people who contributed to this + * project. * - ******************************************************************************/ + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ #include #include From 3708e4cdb1f1d3d5128cf87be040d7e6b85f60dd Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 11 Sep 2009 09:13:58 +0200 Subject: [PATCH 090/208] drivers/net/natsemi.c: fix compile warning Fix warning: natsemi.c:757: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Wolfgang Denk Cc: Ben Warren --- drivers/net/natsemi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c index ce12c3b6261..e09da1d2ae4 100644 --- a/drivers/net/natsemi.c +++ b/drivers/net/natsemi.c @@ -754,7 +754,8 @@ natsemi_send(struct eth_device *dev, volatile void *packet, int length) { u32 i, status = 0; u32 tx_status = 0; - vu_long *res = (vu_long *)&tx_status; + u32 *tx_ptr = &tx_status; + vu_long *res = (vu_long *)tx_ptr; /* Stop the transmitter */ OUTL(dev, TxOff, ChipCmd); From 2d6d9f0848e952ea33c658dfba335685a2725b8b Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 11 Sep 2009 09:36:31 +0200 Subject: [PATCH 091/208] sk98lin: fix compile warnings Fix warnings: skge.c: In function 'BoardInitMem': skge.c:1389: warning: dereferencing type-punned pointer will break strict-aliasing rules skge.c:1390: warning: dereferencing type-punned pointer will break strict-aliasing rules skge.c:1391: warning: dereferencing type-punned pointer will break strict-aliasing rules skgesirq.c: In function 'SkGePortCheckUpXmac': skgesirq.c:1301: warning: dereferencing type-punned pointer will break strict-aliasing rules skgesirq.c:1301: warning: dereferencing type-punned pointer will break strict-aliasing rules skgesirq.c:1398: warning: dereferencing type-punned pointer will break strict-aliasing rules skgesirq.c:1398: warning: dereferencing type-punned pointer will break strict-aliasing rules skrlmt.c: In function 'SkRlmtInit': skrlmt.c:661: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c: In function 'SkMacPromiscMode': skxmac2.c:753: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c:753: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c: In function 'SkMacHashing': skxmac2.c:803: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c:803: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c: In function 'SkMacFlushTxFifo': skxmac2.c:1115: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c:1115: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c: In function 'SkMacFlushRxFifo': skxmac2.c:1145: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c:1145: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c: In function 'SkXmInitPauseMd': skxmac2.c:1987: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c:1987: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c: In function 'SkXmOverflowStatus': skxmac2.c:4236: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c:4236: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c:4242: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c:4242: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Wolfgang Denk Cc: Ben Warren --- drivers/net/sk98lin/skge.c | 12 +++++++++--- drivers/net/sk98lin/skgesirq.c | 7 +++++-- drivers/net/sk98lin/skrlmt.c | 3 ++- drivers/net/sk98lin/skxmac2.c | 20 +++++++++++++------- 4 files changed, 29 insertions(+), 13 deletions(-) diff --git a/drivers/net/sk98lin/skge.c b/drivers/net/sk98lin/skge.c index c815480f8b9..df764b4595e 100644 --- a/drivers/net/sk98lin/skge.c +++ b/drivers/net/sk98lin/skge.c @@ -1382,13 +1382,19 @@ int TxDescrSize; /* the size of a tx descriptor rounded up to alignment*/ pAC->TxDescrPerRing = TX_RING_SIZE / RxDescrSize; for (i=0; iGIni.GIMacsFound; i++) { + TXD **txd_head, **txd_tail, **txd_prev; + + txd_head = &pAC->TxPort[i][0].pTxdRingHead; + txd_tail = &pAC->TxPort[i][0].pTxdRingTail; + txd_prev = &pAC->TxPort[i][0].pTxdRingPrev; + SetupRing( pAC, pAC->TxPort[i][0].pTxDescrRing, pAC->TxPort[i][0].VTxDescrRing, - (RXD**)&pAC->TxPort[i][0].pTxdRingHead, - (RXD**)&pAC->TxPort[i][0].pTxdRingTail, - (RXD**)&pAC->TxPort[i][0].pTxdRingPrev, + (RXD**)txd_head, + (RXD**)txd_tail, + (RXD**)txd_prev, &pAC->TxPort[i][0].TxdRingFree, SK_TRUE); SetupRing( diff --git a/drivers/net/sk98lin/skgesirq.c b/drivers/net/sk98lin/skgesirq.c index 106fe48c0d2..53229d28933 100644 --- a/drivers/net/sk98lin/skgesirq.c +++ b/drivers/net/sk98lin/skgesirq.c @@ -1266,6 +1266,7 @@ int Port) /* Which port should be checked */ SK_GEPORT *pPrt; /* GIni Port struct pointer */ int Done; SK_U32 GpReg; /* General Purpose register value */ + SK_U32 *pGpReg; /* Pointer to -- " -- */ SK_U16 Isrc; /* Interrupt source register */ SK_U16 IsrcSum; /* Interrupt source register sum */ SK_U16 LpAb; /* Link Partner Ability */ @@ -1274,6 +1275,8 @@ int Port) /* Which port should be checked */ SK_BOOL AutoNeg; /* Is Auto-negotiation used ? */ SK_U8 NextMode; /* Next AutoSensing Mode */ + pGpReg = &GpReg; + pPrt = &pAC->GIni.GP[Port]; if (pPrt->PHWLinkUp) { @@ -1298,7 +1301,7 @@ int Port) /* Which port should be checked */ if (pPrt->PLinkBroken) { /* Link was broken */ - XM_IN32(IoC, Port, XM_GP_PORT, &GpReg); + XM_IN32(IoC, Port, XM_GP_PORT, pGpReg); if ((GpReg & XM_GP_INP_ASS) == 0) { /* The Link is in sync */ @@ -1395,7 +1398,7 @@ int Port) /* Which port should be checked */ * here we usually can check whether the link is in sync and * auto-negotiation is done. */ - XM_IN32(IoC, Port, XM_GP_PORT, &GpReg); + XM_IN32(IoC, Port, XM_GP_PORT, pGpReg); XM_IN16(IoC, Port, XM_ISRC, &Isrc); IsrcSum |= Isrc; diff --git a/drivers/net/sk98lin/skrlmt.c b/drivers/net/sk98lin/skrlmt.c index 2e7924d011a..a178dff3ccc 100644 --- a/drivers/net/sk98lin/skrlmt.c +++ b/drivers/net/sk98lin/skrlmt.c @@ -657,8 +657,9 @@ int Level) /* Initialization Level */ } for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) { + SK_U64 *pRandom = &Random; Random = SkOsGetTime(pAC); - *(SK_U32*)&pAC->Rlmt.Port[i].Random = *(SK_U32*)&Random; + *(SK_U32*)&pAC->Rlmt.Port[i].Random = *(SK_U32*)pRandom; for (j = 0; j < 4; j++) { pAC->Rlmt.Port[i].Random[j] ^= pAC->Rlmt.Port[i].AddrPort-> diff --git a/drivers/net/sk98lin/skxmac2.c b/drivers/net/sk98lin/skxmac2.c index e0ded42bae5..2f7c0543f4a 100644 --- a/drivers/net/sk98lin/skxmac2.c +++ b/drivers/net/sk98lin/skxmac2.c @@ -747,10 +747,11 @@ SK_BOOL Enable) /* Enable / Disable */ { SK_U16 RcReg; SK_U32 MdReg; + SK_U32 *pMdReg = &MdReg; if (pAC->GIni.GIGenesis) { - XM_IN32(IoC, Port, XM_MODE, &MdReg); + XM_IN32(IoC, Port, XM_MODE, pMdReg); /* enable or disable promiscuous mode */ if (Enable) { MdReg |= XM_MD_ENA_PROM; @@ -797,10 +798,11 @@ SK_BOOL Enable) /* Enable / Disable */ { SK_U16 RcReg; SK_U32 MdReg; + SK_U32 *pMdReg = &MdReg; if (pAC->GIni.GIGenesis) { - XM_IN32(IoC, Port, XM_MODE, &MdReg); + XM_IN32(IoC, Port, XM_MODE, pMdReg); /* enable or disable hashing */ if (Enable) { MdReg |= XM_MD_ENA_HASH; @@ -1109,10 +1111,11 @@ SK_IOC IoC, /* IO context */ int Port) /* Port Index (MAC_1 + n) */ { SK_U32 MdReg; + SK_U32 *pMdReg = &MdReg; if (pAC->GIni.GIGenesis) { - XM_IN32(IoC, Port, XM_MODE, &MdReg); + XM_IN32(IoC, Port, XM_MODE, pMdReg); XM_OUT32(IoC, Port, XM_MODE, MdReg | XM_MD_FTF); } @@ -1139,10 +1142,11 @@ SK_IOC IoC, /* IO context */ int Port) /* Port Index (MAC_1 + n) */ { SK_U32 MdReg; + SK_U32 *pMdReg = &MdReg; if (pAC->GIni.GIGenesis) { - XM_IN32(IoC, Port, XM_MODE, &MdReg); + XM_IN32(IoC, Port, XM_MODE, pMdReg); XM_OUT32(IoC, Port, XM_MODE, MdReg | XM_MD_FRF); } @@ -1961,6 +1965,7 @@ int Port) /* Port Index (MAC_1 + n) */ { SK_GEPORT *pPrt; SK_U32 DWord; + SK_U32 *pDWord = &DWord; SK_U16 Word; pPrt = &pAC->GIni.GP[Port]; @@ -1984,7 +1989,7 @@ int Port) /* Port Index (MAC_1 + n) */ XM_OUT16(IoC, Port, XM_MMU_CMD, Word); - XM_IN32(IoC, Port, XM_MODE, &DWord); + XM_IN32(IoC, Port, XM_MODE, pDWord); if (pPrt->PFlowCtrlStatus == SK_FLOW_STAT_SYMMETRIC || pPrt->PFlowCtrlStatus == SK_FLOW_STAT_LOC_SEND) { @@ -4228,18 +4233,19 @@ SK_U64 *pStatus) /* ptr for return overflow status value */ { SK_U64 Status; /* Overflow status */ SK_U32 RegVal; + SK_U32 *pRegVal = &RegVal; Status = 0; if ((IStatus & XM_IS_RXC_OV) != 0) { - XM_IN32(IoC, Port, XM_RX_CNT_EV, &RegVal); + XM_IN32(IoC, Port, XM_RX_CNT_EV, pRegVal); Status |= (SK_U64)RegVal << 32; } if ((IStatus & XM_IS_TXC_OV) != 0) { - XM_IN32(IoC, Port, XM_TX_CNT_EV, &RegVal); + XM_IN32(IoC, Port, XM_TX_CNT_EV, pRegVal); Status |= (SK_U64)RegVal; } From ba73060cf4163bd5eb1711020126e2f7f62d363e Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 11 Sep 2009 10:13:26 +0200 Subject: [PATCH 092/208] board/esd/common/flash.c: Fix compile warning Fix warning: ../common/flash.c:635: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Wolfgang Denk Cc: Matthias Fuchs Cc: Stefan Roese Acked-by: Matthias Fuchs Acked-by: Stefan Roese --- board/esd/common/flash.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/esd/common/flash.c b/board/esd/common/flash.c index 3ea053b8cc4..38a58fb5e2d 100644 --- a/board/esd/common/flash.c +++ b/board/esd/common/flash.c @@ -630,9 +630,10 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) */ static int write_word (flash_info_t *info, ulong dest, ulong data) { + ulong *data_ptr = &data; volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)&data; + volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr; ulong start; int flag; int i; From 97138fc48091f2b063c4e32f36d05854b9d113fb Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 11 Sep 2009 11:15:31 +0200 Subject: [PATCH 093/208] board/esd/cpci750/ide.c: fix compile warning Fix warning: ide.c:54: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Wolfgang Denk Cc: Matthias Fuchs Cc: Stefan Roese Acked-by: Stefan Roese --- board/esd/cpci750/ide.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c index 638219f65ec..a3bd1b73d58 100644 --- a/board/esd/cpci750/ide.c +++ b/board/esd/cpci750/ide.c @@ -48,14 +48,18 @@ int ide_preinit (void) if (devbusfn == -1) devbusfn = pci_find_device (0x1095, 0x3114, 0); if (devbusfn != -1) { + ulong *ide_bus_offset_ptr; + status = 0; + ide_bus_offset_ptr = &ide_bus_offset[0]; pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, - (u32 *) & ide_bus_offset[0]); + (u32 *)ide_bus_offset_ptr); ide_bus_offset[0] &= 0xfffffffe; ide_bus_offset[0] += CONFIG_SYS_PCI0_IO_SPACE; + ide_bus_offset_ptr = &ide_bus_offset[1]; pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2, - (u32 *) & ide_bus_offset[1]); + (u32 *)ide_bus_offset_ptr); ide_bus_offset[1] &= 0xfffffffe; ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE; } From 5168801f4b71c2f8dcd92a80cfcfda84246e67fe Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 11 Sep 2009 11:28:21 +0200 Subject: [PATCH 094/208] board/dave/common/flash.c: fix compile warning Fix warning: ../common/flash.c:668: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Wolfgang Denk Cc: Andrea Marson --- board/dave/common/flash.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/dave/common/flash.c b/board/dave/common/flash.c index b6af63b3b93..29caf47ef35 100644 --- a/board/dave/common/flash.c +++ b/board/dave/common/flash.c @@ -663,9 +663,10 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) */ static int write_word (flash_info_t *info, ulong dest, ulong data) { + ulong *data_ptr = &data; volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)&data; + volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr; ulong start; int flag; int i; From 0fd3d902d920f3e60f88530c33f1ae7581260951 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 11 Sep 2009 11:37:20 +0200 Subject: [PATCH 095/208] board/etin/debris/phantom.c: Fix compile error Fix build problem caused by commit e84aba13: "Replace BCD2BIN and BIN2BCD macros with inline functions" phantom.c:163: error: redefinition of 'bcd2bin' /home/wd/git/u-boot/work/include/bcd.h:16: error: previous definition of 'bcd2bin' was here phantom.c:168: error: redefinition of 'bin2bcd' /home/wd/git/u-boot/work/include/bcd.h:21: error: previous definition of 'bin2bcd' was here Signed-off-by: Wolfgang Denk Cc: Sangmoon Kim --- board/etin/debris/phantom.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/board/etin/debris/phantom.c b/board/etin/debris/phantom.c index fcb4c40eaae..63feb7c2c35 100644 --- a/board/etin/debris/phantom.c +++ b/board/etin/debris/phantom.c @@ -159,16 +159,6 @@ void rtc_reset(void) } } -inline unsigned bcd2bin (uchar n) -{ - return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); -} - -inline unsigned char bin2bcd (unsigned int n) -{ - return (((n / 10) << 4) | (n % 10)); -} - static int get_century_flag(void) { int flag = 0; From 030ec52f8cc83015f968db30208f4bd07feffa6c Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 11 Sep 2009 11:44:39 +0200 Subject: [PATCH 096/208] board/amcc/taihu/flash.c: Fix compile warning Fix warnings: flash.c: In function 'write_word_1': flash.c:696: warning: dereferencing type-punned pointer will break strict-aliasing rules flash.c: In function 'write_word_2': flash.c:1044: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Wolfgang Denk Cc: Stefan Roese Acked-by: Stefan Roese --- board/amcc/taihu/flash.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/board/amcc/taihu/flash.c b/board/amcc/taihu/flash.c index 110cbe5e9d0..497fdb963cd 100644 --- a/board/amcc/taihu/flash.c +++ b/board/amcc/taihu/flash.c @@ -691,9 +691,10 @@ static int write_word_1(flash_info_t * info, ulong dest, ulong data) static int write_word(flash_info_t * info, ulong dest, ulong data) #endif { - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data; + ulong *data_ptr = &data; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; + volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr; ulong start; int i; @@ -1039,9 +1040,10 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last) static int write_word_2(flash_info_t * info, ulong dest, ulong data) { - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data; + ulong *data_ptr = &data; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; + volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr; ulong start; int i; From 70fb809c563c340538264d2a9436135e74c38bfe Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 11 Sep 2009 11:47:07 +0200 Subject: [PATCH 097/208] board/amcc/yucca/flash.c: Fix compile warning Fix warning: flash.c:919: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Wolfgang Denk Cc: Stefan Roese Acked-by: Stefan Roese --- board/amcc/yucca/flash.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/board/amcc/yucca/flash.c b/board/amcc/yucca/flash.c index eda49eb1746..d8c3b32cc80 100644 --- a/board/amcc/yucca/flash.c +++ b/board/amcc/yucca/flash.c @@ -914,9 +914,10 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last) static int write_word_2(flash_info_t * info, ulong dest, ulong data) { - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data; + ulong *data_ptr = &data; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; + volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr; ulong start; int i; From 6c7bc91fb3dba186d3398a1653f6db236510ffa7 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 11 Sep 2009 11:30:34 +0200 Subject: [PATCH 098/208] board/amcc/common/flash.c: Fix compile warning Fix warning: ../common/flash.c:917: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Wolfgang Denk Cc: Stefan Roese Acked-by: Stefan Roese --- board/amcc/common/flash.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c index 9943c744b7a..9aaf256c225 100644 --- a/board/amcc/common/flash.c +++ b/board/amcc/common/flash.c @@ -912,9 +912,10 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last) static int write_word_2(flash_info_t * info, ulong dest, ulong data) { - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data; + ulong *data_ptr = &data; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; + volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr; ulong start; int i; From ceb2d57c2205db5bbd868577f756c74a2568160c Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 15 Sep 2009 21:13:27 +0200 Subject: [PATCH 099/208] kwbimage.c: Fix compile warning when building on 64 bit systems (again) Commit 51003b89 attempted to fix a build problem on 64 bit systems, but just turned it into a build problem on 32 bit systems (silly me). Now do the Right Thing (TM) and use a "%zu" printf format. Also fix spelling error. Signed-off-by: Wolfgang Denk --- tools/kwbimage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/kwbimage.c b/tools/kwbimage.c index ee067cbd81d..7b26920185b 100644 --- a/tools/kwbimage.c +++ b/tools/kwbimage.c @@ -131,7 +131,7 @@ static uint32_t kwbimage_checksum32 (uint32_t *start, uint32_t len, uint32_t csu return 0; if (len % sizeof(uint32_t)) { - printf ("Error:%s[%d] - lenght is not in multiple of %ld\n", + printf ("Error:%s[%d] - length is not in multiple of %zu\n", __FUNCTION__, len, sizeof(uint32_t)); return 0; } From 804d83a563c47b55e1f14f5de3b6e9d7e2a7ef5e Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 15 Sep 2009 22:12:31 +0200 Subject: [PATCH 100/208] mkconfig: split the board make target to multiple config targets To simplify the top level makefile it useful to be able to parse the top level makefile target to multiple individual target, then put them to the config.h, leave the board config file to handle the different targets. Note that this method uses the '_'(underline) as the delimiter when splits the board make target. Signed-off-by: Mingkai Hu This also reverts commit 511c02f611cb5afa1b8ca5980caaaabaa0de377f. Signed-off-by: Wolfgang Denk --- mkconfig | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/mkconfig b/mkconfig index 9efd2fa7db0..4c5675bd3cc 100755 --- a/mkconfig +++ b/mkconfig @@ -10,12 +10,14 @@ APPEND=no # Default: Create new config file BOARD_NAME="" # Name to print in make output +TARGETS="" while [ $# -gt 0 ] ; do case "$1" in --) shift ; break ;; -a) shift ; APPEND=yes ;; -n) shift ; BOARD_NAME="${1%%_config}" ; shift ;; + -t) shift ; TARGETS="`echo $1 | sed 's:_: :g'` ${TARGETS}" ; shift ;; *) break ;; esac done @@ -82,7 +84,11 @@ else > config.h # Create new config file fi echo "/* Automatically generated - do not edit */" >>config.h -echo "#define CONFIG_MK_${BOARD_NAME} 1" >>config.h + +for i in ${TARGETS} ; do + echo "#define CONFIG_MK_${i} 1" >>config.h ; +done + echo "#include " >>config.h echo "#include " >>config.h From 557555fe0b82940ba7cc69f81d31d6ef4d4933b4 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 4 Sep 2009 19:54:45 -0400 Subject: [PATCH 101/208] standalone: convert to kbuild style Clean up the arch/cpu/board/config checks as well as redundant setting of srec/bin variables by using the kbuild VAR-$(...) style. Signed-off-by: Mike Frysinger --- examples/standalone/Makefile | 95 ++++++++++-------------------------- 1 file changed, 26 insertions(+), 69 deletions(-) diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index bc98120a51f..5e2f2bcaeb4 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -23,83 +23,40 @@ include $(TOPDIR)/config.mk -ELF = hello_world -SREC = hello_world.srec -BIN = hello_world.bin +ELF-$(ARCH) := +ELF-$(BOARD) := +ELF-$(CPU) := +ELF-y := hello_world -ELF += atmel_df_pow2 -SREC += atmel_df_pow2.srec -BIN += atmel_df_pow2.bin +ELF-$(CONFIG_SMC91111) += smc91111_eeprom +ELF-$(CONFIG_SMC911X) += smc911x_eeprom +ELF-$(CONFIG_SPI_FLASH_ATMEL) += atmel_df_pow2 +ELF-i386 += 82559_eeprom +ELF-mpc5xxx += interrupt +ELF-mpc8xx += test_burst timer +ELF-mpc8260 += mem_to_mem_idma2intr +ELF-ppc += sched +ELF-oxc += eepro100_eeprom -ifeq ($(CPU),mpc8xx) -ELF += test_burst -SREC += test_burst.srec -BIN += test_burst.bin -endif +ELF := $(ELF-y) $(ELF-$(ARCH)) $(ELF-$(BOARD)) $(ELF-$(CPU)) +SREC = $(addsuffix .srec,$(ELF)) +BIN = $(addsuffix .bin,$(ELF)) -ifeq ($(ARCH),i386) -ELF += 82559_eeprom -SREC += 82559_eeprom.srec -BIN += 82559_eeprom.bin -endif - -ifeq ($(ARCH),ppc) -ELF += sched -SREC += sched.srec -BIN += sched.bin -endif - -ifeq ($(ARCH),blackfin) -BFIN_BIN = smc91111_eeprom smc911x_eeprom -ELF += $(BFIN_BIN) -SREC += $(addsuffix .srec,$(BFIN_BIN)) -BIN += $(addsuffix .bin,$(BFIN_BIN)) -endif - -# The following example is pretty 8xx specific... -ifeq ($(CPU),mpc8xx) -ELF += timer -SREC += timer.srec -BIN += timer.bin -endif - -# The following example is 8260 specific... -ifeq ($(CPU),mpc8260) -ELF += mem_to_mem_idma2intr -SREC += mem_to_mem_idma2intr.srec -BIN += mem_to_mem_idma2intr.bin -endif - -# Demo for 52xx IRQs -ifeq ($(CPU),mpc5xxx) -ELF += interrupt -SREC += interrupt.srec -BIN += interrupt.bin -endif - -# Utility for resetting i82559 EEPROM -ifeq ($(BOARD),oxc) -ELF += eepro100_eeprom -SREC += eepro100_eeprom.srec -BIN += eepro100_eeprom.bin -endif - - -COBJS := $(SREC:.srec=.o) +COBJS := $(ELF:=.o) LIB = $(obj)libstubs.a -LIBAOBJS= -ifeq ($(ARCH),ppc) -LIBAOBJS+= $(ARCH)_longjmp.o $(ARCH)_setjmp.o -endif -ifeq ($(CPU),mpc8xx) -LIBAOBJS+= test_burst_lib.o -endif -LIBCOBJS= stubs.o + +LIBAOBJS-$(ARCH) := +LIBAOBJS-$(CPU) := +LIBAOBJS-ppc += $(ARCH)_longjmp.o $(ARCH)_setjmp.o +LIBAOBJS-mpc8xx += test_burst_lib.o +LIBAOBJS := $(LIBAOBJS-$(ARCH)) $(LIBAOBJS-$(CPU)) + +LIBCOBJS = stubs.o LIBOBJS = $(addprefix $(obj),$(LIBAOBJS) $(LIBCOBJS)) -SRCS := $(COBJS:.o=.c) $(LIBCOBJS:.o=.c) $(if $(LIBAOBJS),$(LIBAOBJS:.o=.S)) +SRCS := $(COBJS:.o=.c) $(LIBCOBJS:.o=.c) $(LIBAOBJS:.o=.S) OBJS := $(addprefix $(obj),$(COBJS)) ELF := $(addprefix $(obj),$(ELF)) BIN := $(addprefix $(obj),$(BIN)) From 02f99901ed1c9d828e3ea117f94ce2264bf8389e Mon Sep 17 00:00:00 2001 From: Simon Kagstrom Date: Mon, 24 Aug 2009 09:09:50 +0200 Subject: [PATCH 102/208] Move __set/clear_bit from ubifs.h to bitops.h __set_bit and __clear_bit are defined in ubifs.h as well as in asm/include/bitops.h for some architectures. This patch moves the generic implementation to include/linux/bitops.h and uses that unless it's defined by the architecture. Signed-off-by: Simon Kagstrom --- fs/ubifs/ubifs.h | 32 --------------------------- include/asm-arm/bitops.h | 2 ++ include/asm-blackfin/bitops.h | 1 + include/asm-microblaze/bitops.h | 1 + include/asm-mips/bitops.h | 1 + include/linux/bitops.h | 38 +++++++++++++++++++++++++++++++++ 6 files changed, 43 insertions(+), 32 deletions(-) diff --git a/fs/ubifs/ubifs.h b/fs/ubifs/ubifs.h index 43865aa66ed..06772af36f7 100644 --- a/fs/ubifs/ubifs.h +++ b/fs/ubifs/ubifs.h @@ -449,38 +449,6 @@ static inline ino_t parent_ino(struct dentry *dentry) return res; } -/* linux/include/linux/bitops.h */ - -#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) -#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) - -/* linux/include/asm-generic/bitops/non-atomic.h */ - -/** - * __set_bit - Set a bit in memory - * @nr: the bit to set - * @addr: the address to start counting from - * - * Unlike set_bit(), this function is non-atomic and may be reordered. - * If it's called on the same region of memory simultaneously, the effect - * may be that only one operation succeeds. - */ -static inline void __set_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - - *p |= mask; -} - -static inline void __clear_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - - *p &= ~mask; -} - /* debug.c */ #define DEFINE_SPINLOCK(...) diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h index 4b8bab28373..1549da16933 100644 --- a/include/asm-arm/bitops.h +++ b/include/asm-arm/bitops.h @@ -29,6 +29,7 @@ static inline void __set_bit(int nr, volatile void *addr) { ((unsigned char *) addr)[nr >> 3] |= (1U << (nr & 7)); } +#define __set_bit extern void clear_bit(int nr, volatile void * addr); @@ -36,6 +37,7 @@ static inline void __clear_bit(int nr, volatile void *addr) { ((unsigned char *) addr)[nr >> 3] &= ~(1U << (nr & 7)); } +#define __clear_bit extern void change_bit(int nr, volatile void * addr); diff --git a/include/asm-blackfin/bitops.h b/include/asm-blackfin/bitops.h index 2e55b6a6199..cc3685d35d7 100644 --- a/include/asm-blackfin/bitops.h +++ b/include/asm-blackfin/bitops.h @@ -79,6 +79,7 @@ static __inline__ void __set_bit(int nr, volatile void *addr) mask = 1 << (nr & 0x1f); *a |= mask; } +#define __set_bit /* * clear_bit() doesn't provide any barrier for the compiler. diff --git a/include/asm-microblaze/bitops.h b/include/asm-microblaze/bitops.h index 04ea0207eea..aac906102ab 100644 --- a/include/asm-microblaze/bitops.h +++ b/include/asm-microblaze/bitops.h @@ -75,6 +75,7 @@ extern __inline__ void __set_bit(int nr, volatile void * addr) mask = 1 << (nr & 0x1f); *a |= mask; } +#define __set_bit /* * clear_bit() doesn't provide any barrier for the compiler. diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index 659ac9d3201..0c07b686a2d 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -90,6 +90,7 @@ static __inline__ void __set_bit(int nr, volatile void * addr) *m |= 1UL << (nr & 31); } +#define __set_bit /* * clear_bit - Clears a bit in memory diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 7d41ae62ccf..387a81813b9 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -1,6 +1,7 @@ #ifndef _LINUX_BITOPS_H #define _LINUX_BITOPS_H +#include /* * ffs: find first bit set. This is defined the same way as @@ -66,7 +67,44 @@ static inline unsigned int generic_hweight8(unsigned int w) return (res & 0x0F) + ((res >> 4) & 0x0F); } +#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) +#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) + #include +/* linux/include/asm-generic/bitops/non-atomic.h */ + +#ifndef __set_bit +# define __set_bit generic_set_bit +#endif + +#ifndef __clear_bit +# define __clear_bit generic_clear_bit +#endif + +/** + * __set_bit - Set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Unlike set_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +static inline void generic_set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p |= mask; +} + +static inline void generic_clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p &= ~mask; +} #endif From 4b15de08fe4d2c9d12a3764394731018a763216b Mon Sep 17 00:00:00 2001 From: Simon Kagstrom Date: Mon, 24 Aug 2009 09:10:03 +0200 Subject: [PATCH 103/208] arm: Make arm bitops endianness-independent Bring over the bitop implementations from the Linux include/asm-generic/bitops/non-atomic.h to provide endianness-independence. Signed-off-by: Simon Kagstrom --- include/asm-arm/bitops.h | 47 ++++++++++++++++------------------------ 1 file changed, 19 insertions(+), 28 deletions(-) diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h index 1549da16933..854e225c2f6 100644 --- a/include/asm-arm/bitops.h +++ b/include/asm-arm/bitops.h @@ -25,61 +25,52 @@ */ extern void set_bit(int nr, volatile void * addr); -static inline void __set_bit(int nr, volatile void *addr) -{ - ((unsigned char *) addr)[nr >> 3] |= (1U << (nr & 7)); -} -#define __set_bit - extern void clear_bit(int nr, volatile void * addr); -static inline void __clear_bit(int nr, volatile void *addr) -{ - ((unsigned char *) addr)[nr >> 3] &= ~(1U << (nr & 7)); -} -#define __clear_bit - extern void change_bit(int nr, volatile void * addr); static inline void __change_bit(int nr, volatile void *addr) { - ((unsigned char *) addr)[nr >> 3] ^= (1U << (nr & 7)); + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p ^= mask; } extern int test_and_set_bit(int nr, volatile void * addr); static inline int __test_and_set_bit(int nr, volatile void *addr) { - unsigned int mask = 1 << (nr & 7); - unsigned int oldval; + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; - oldval = ((unsigned char *) addr)[nr >> 3]; - ((unsigned char *) addr)[nr >> 3] = oldval | mask; - return oldval & mask; + *p = old | mask; + return (old & mask) != 0; } extern int test_and_clear_bit(int nr, volatile void * addr); static inline int __test_and_clear_bit(int nr, volatile void *addr) { - unsigned int mask = 1 << (nr & 7); - unsigned int oldval; + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; - oldval = ((unsigned char *) addr)[nr >> 3]; - ((unsigned char *) addr)[nr >> 3] = oldval & ~mask; - return oldval & mask; + *p = old & ~mask; + return (old & mask) != 0; } extern int test_and_change_bit(int nr, volatile void * addr); static inline int __test_and_change_bit(int nr, volatile void *addr) { - unsigned int mask = 1 << (nr & 7); - unsigned int oldval; + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; - oldval = ((unsigned char *) addr)[nr >> 3]; - ((unsigned char *) addr)[nr >> 3] = oldval ^ mask; - return oldval & mask; + *p = old ^ mask; + return (old & mask) != 0; } extern int find_first_zero_bit(void * addr, unsigned size); From 52d61227b66d4099b39c8309ab37cb67ee09a405 Mon Sep 17 00:00:00 2001 From: Simon Kagstrom Date: Mon, 24 Aug 2009 09:10:12 +0200 Subject: [PATCH 104/208] Define ffs/fls for all architectures UBIFS requires fls(), which is not defined for arm (and some other architectures) and this patch adds it. The implementation is taken from Linux and is generic. ffs() is also defined for those that miss it. Signed-off-by: Simon Kagstrom --- include/asm-i386/bitops.h | 1 + include/asm-m68k/bitops.h | 1 + include/asm-nios/bitops.h | 1 + include/asm-nios2/bitops.h | 1 + include/asm-ppc/bitops.h | 2 ++ include/asm-sh/bitops.h | 2 ++ include/linux/bitops.h | 45 ++++++++++++++++++++++++++++++++++++++ 7 files changed, 53 insertions(+) diff --git a/include/asm-i386/bitops.h b/include/asm-i386/bitops.h index b768e20fbb6..ac6285aa5f2 100644 --- a/include/asm-i386/bitops.h +++ b/include/asm-i386/bitops.h @@ -349,6 +349,7 @@ static __inline__ int ffs(int x) "1:" : "=r" (r) : "g" (x)); return r+1; } +#define ffs /** * hweightN - returns the hamming weight of a N-bit word diff --git a/include/asm-m68k/bitops.h b/include/asm-m68k/bitops.h index 0f9e8abe9c1..e0c35fa7b05 100644 --- a/include/asm-m68k/bitops.h +++ b/include/asm-m68k/bitops.h @@ -51,6 +51,7 @@ extern __inline__ int ffs(int x) return r; } #define __ffs(x) (ffs(x) - 1) +#define ffs #endif /* __KERNEL__ */ diff --git a/include/asm-nios/bitops.h b/include/asm-nios/bitops.h index 7744212b45a..8315fb7caaf 100644 --- a/include/asm-nios/bitops.h +++ b/include/asm-nios/bitops.h @@ -33,5 +33,6 @@ extern int test_and_set_bit(int nr, volatile void * a); extern int test_and_change_bit(int nr, volatile void * addr); extern int test_bit(int nr, volatile void * a); extern int ffs(int i); +#define ffs #endif /* _ASM_NIOS_BITOPS_H */ diff --git a/include/asm-nios2/bitops.h b/include/asm-nios2/bitops.h index e6c1a850d1b..b01a89d63cd 100644 --- a/include/asm-nios2/bitops.h +++ b/include/asm-nios2/bitops.h @@ -33,5 +33,6 @@ extern int test_and_set_bit(int nr, volatile void * a); extern int test_and_change_bit(int nr, volatile void * addr); extern int test_bit(int nr, volatile void * a); extern int ffs(int i); +#define ffs #endif /* __ASM_NIOS2_BITOPS_H */ diff --git a/include/asm-ppc/bitops.h b/include/asm-ppc/bitops.h index daa66cf9185..9ed2f5d6faa 100644 --- a/include/asm-ppc/bitops.h +++ b/include/asm-ppc/bitops.h @@ -178,6 +178,7 @@ static __inline__ int fls(unsigned int x) { return __ilog2(x) + 1; } +#define fls /** * fls64 - find last set bit in a 64-bit word @@ -230,6 +231,7 @@ extern __inline__ int ffs(int x) { return __ilog2(x & -x) + 1; } +#define ffs /* * hweightN: returns the hamming weight (i.e. the number diff --git a/include/asm-sh/bitops.h b/include/asm-sh/bitops.h index 410fba46eff..95167bd45ac 100644 --- a/include/asm-sh/bitops.h +++ b/include/asm-sh/bitops.h @@ -146,6 +146,8 @@ static inline int ffs (int x) } return r; } +#define ffs + #endif /* __KERNEL__ */ #endif /* __ASM_SH_BITOPS_H */ diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 387a81813b9..e14e6c7b14f 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -38,6 +38,43 @@ static inline int generic_ffs(int x) return r; } +/** + * fls - find last (most-significant) bit set + * @x: the word to search + * + * This is defined the same way as ffs. + * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. + */ +static inline int generic_fls(int x) +{ + int r = 32; + + if (!x) + return 0; + if (!(x & 0xffff0000u)) { + x <<= 16; + r -= 16; + } + if (!(x & 0xff000000u)) { + x <<= 8; + r -= 8; + } + if (!(x & 0xf0000000u)) { + x <<= 4; + r -= 4; + } + if (!(x & 0xc0000000u)) { + x <<= 2; + r -= 2; + } + if (!(x & 0x80000000u)) { + x <<= 1; + r -= 1; + } + return r; +} + + /* * hweightN: returns the hamming weight (i.e. the number * of bits set) of a N-bit word @@ -82,6 +119,14 @@ static inline unsigned int generic_hweight8(unsigned int w) # define __clear_bit generic_clear_bit #endif +#ifndef ffs +# define ffs generic_ffs +#endif + +#ifndef fls +# define fls generic_fls +#endif + /** * __set_bit - Set a bit in memory * @nr: the bit to set From a6e19d69f63c14b7672c65ca4b014621c6fd0201 Mon Sep 17 00:00:00 2001 From: Simon Kagstrom Date: Mon, 24 Aug 2009 09:10:16 +0200 Subject: [PATCH 105/208] arm: Define test_and_set_bit and test_and_clear bit for ARM Needed for (e.g.) ubifs support to work. Signed-off-by: Simon Kagstrom --- include/asm-arm/bitops.h | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h index 854e225c2f6..3c7b00c48d0 100644 --- a/include/asm-arm/bitops.h +++ b/include/asm-arm/bitops.h @@ -17,6 +17,8 @@ #ifdef __KERNEL__ +#include + #define smp_mb__before_clear_bit() do { } while (0) #define smp_mb__after_clear_bit() do { } while (0) @@ -37,8 +39,6 @@ static inline void __change_bit(int nr, volatile void *addr) *p ^= mask; } -extern int test_and_set_bit(int nr, volatile void * addr); - static inline int __test_and_set_bit(int nr, volatile void *addr) { unsigned long mask = BIT_MASK(nr); @@ -49,7 +49,17 @@ static inline int __test_and_set_bit(int nr, volatile void *addr) return (old & mask) != 0; } -extern int test_and_clear_bit(int nr, volatile void * addr); +static inline int test_and_set_bit(int nr, volatile void * addr) +{ + unsigned long flags; + int out; + + local_irq_save(flags); + out = __test_and_set_bit(nr, addr); + local_irq_restore(flags); + + return out; +} static inline int __test_and_clear_bit(int nr, volatile void *addr) { @@ -61,6 +71,18 @@ static inline int __test_and_clear_bit(int nr, volatile void *addr) return (old & mask) != 0; } +static inline int test_and_clear_bit(int nr, volatile void * addr) +{ + unsigned long flags; + int out; + + local_irq_save(flags); + out = __test_and_clear_bit(nr, addr); + local_irq_restore(flags); + + return out; +} + extern int test_and_change_bit(int nr, volatile void * addr); static inline int __test_and_change_bit(int nr, volatile void *addr) From 770931805d292908a57a3d2c5f9a4fcde888b5a2 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 9 Sep 2009 12:20:20 -0400 Subject: [PATCH 106/208] tools/netconsole: make a bit more robust The netcat utility likes to exit when it receives an empty packet (as it thinks this means EOF). This can easily occur when working with command line editing as this behavior will be triggered when using backspace. Or with tabs and command line completion. So create two netcat processes - one to only listen (and put it into a loop), and one to do the sending. Once the user quits the transmitting netcat, the listening one will be killed automatically. Signed-off-by: Mike Frysinger --- tools/netconsole | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/tools/netconsole b/tools/netconsole index 09c89816829..6ef2723f584 100755 --- a/tools/netconsole +++ b/tools/netconsole @@ -31,12 +31,18 @@ if [ -z "${ip}" ] || [ -n "$3" ] ; then fi for nc in netcat nc ; do - type ${nc} >/dev/null && break + type ${nc} >/dev/null 2>&1 && break done trap "stty icanon echo intr ^C" 0 2 3 5 10 13 15 echo "NOTE: the interrupt signal (normally ^C) has been remapped to ^T" stty -icanon -echo intr ^T -${nc} -u -l -p ${port} < /dev/null & -exec ${nc} -u ${ip} ${port} +( +while ${nc} -u -l -p ${port} < /dev/null ; do + : +done +) & +pid=$! +${nc} -u ${ip} ${port} +kill ${pid} 2>/dev/null From 1c20e4a9fbc531e2149ae061e8583f5fad82f163 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 9 Sep 2009 12:20:21 -0400 Subject: [PATCH 107/208] tools/netconsole: use ncb automatically if available The standard netcat, while ubiquitous, doesn't handle broadcast udp packets properly. The local ncb util does however. So if ncb can be located in the standard locations, automatically use that instead. Signed-off-by: Mike Frysinger --- doc/README.NetConsole | 24 +++--------------------- tools/netconsole | 17 ++++++++++++++--- 2 files changed, 17 insertions(+), 24 deletions(-) diff --git a/doc/README.NetConsole b/doc/README.NetConsole index 639cc12a565..c8bcb90a392 100644 --- a/doc/README.NetConsole +++ b/doc/README.NetConsole @@ -36,27 +36,9 @@ you can just remove the -p option from the script. It turns out that 'netcat' cannot be used to listen to broadcast packets. We developed our own tool 'ncb' (see tools directory) that listens to broadcast packets on a given port and dumps them to the -standard output. use it as follows: - -+++++++++++++++++++++++++++++++++++++++++++ -#! /bin/bash - -[ $# = 1 ] || { echo "Usage: $0 target_ip" >&2 ; exit 1 ; } -TARGET_IP=$1 - -stty icanon echo intr ^T -./ncb & -nc -u ${TARGET_IP} 6666 -stty icanon echo intr ^C -kill 0 -+++++++++++++++++++++++++++++++++++++++++++ - -Again, this script takes exactly one argument, which is interpreted -as the target IP address (or host name, assuming DNS is working). The -script can be interrupted by pressing ^T (CTRL-T). - -The 'ncb' tool can be found in the tools directory; it will be built -when compiling for a board which has CONFIG_NETCONSOLE defined. +standard output. It will be built when compiling for a board which +has CONFIG_NETCONSOLE defined. If the netconsole script can find it +in PATH or in the same directory, it will be used instead. For Linux, the network-based console needs special configuration. Minimally, the host IP address needs to be specified. This can be diff --git a/tools/netconsole b/tools/netconsole index 6ef2723f584..c8109bb0956 100755 --- a/tools/netconsole +++ b/tools/netconsole @@ -39,9 +39,20 @@ echo "NOTE: the interrupt signal (normally ^C) has been remapped to ^T" stty -icanon -echo intr ^T ( -while ${nc} -u -l -p ${port} < /dev/null ; do - : -done +if type ncb 2>/dev/null ; then + # see if ncb is in $PATH + exec ncb ${port} + +elif [ -x ${0%/*}/ncb ] ; then + # maybe it's in the same dir as the netconsole script + exec ${0%/*}/ncb ${port} + +else + # blah, just use regular netcat + while ${nc} -u -l -p ${port} < /dev/null ; do + : + done +fi ) & pid=$! ${nc} -u ${ip} ${port} From 3ca55bce9c8bf00df06a20487fafc16fa2f8084b Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 11 Sep 2009 07:50:33 -0400 Subject: [PATCH 108/208] mpc8260: remove Ethernet node fixup to use generic FDT code. Remove Ethernet node fixup from mgcoge and muas3001 boards and modify its configs for the common mpc8260 code to use generic Ethernet fixup. Signed-off-by: Marcel Ziswiler Tested-by: Heiko Schocher --- board/keymile/mgcoge/mgcoge.c | 5 ----- board/muas3001/muas3001.c | 15 --------------- include/configs/mgcoge.h | 1 + include/configs/muas3001.h | 1 + 4 files changed, 2 insertions(+), 20 deletions(-) diff --git a/board/keymile/mgcoge/mgcoge.c b/board/keymile/mgcoge/mgcoge.c index d24a4b57698..b16a01ccc5b 100644 --- a/board/keymile/mgcoge/mgcoge.c +++ b/board/keymile/mgcoge/mgcoge.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) @@ -373,10 +372,6 @@ void ft_blob_update (void *blob, bd_t *bd) flash_reg[5] = cpu_to_be32 (info->size); fdt_set_node_and_value (blob, "/localbus/flash@5,0", "reg", flash_reg, sizeof (flash_reg)); - - /* MAC addr */ - fdt_set_node_and_value (blob, "/soc/cpm/ethernet", "mac-address", - bd->bi_enetaddr, sizeof (u8) * 6); } void ft_board_setup (void *blob, bd_t *bd) diff --git a/board/muas3001/muas3001.c b/board/muas3001/muas3001.c index bf4ccb6e190..36caed813dd 100644 --- a/board/muas3001/muas3001.c +++ b/board/muas3001/muas3001.c @@ -342,21 +342,6 @@ void ft_blob_update (void *blob, bd_t *bd) printf ("ft_blob_update(): cannot find /localbus node " "err:%s\n", fdt_strerror (nodeoffset)); } - /* MAC Adresse */ - nodeoffset = fdt_path_offset (blob, "/soc/cpm/ethernet"); - if (nodeoffset >= 0) { - uchar ethaddr[6]; - eth_getenv_enetaddr("ethaddr", ethaddr); - ret = fdt_setprop (blob, nodeoffset, "mac-address", ethaddr, - sizeof (uchar) * 6); - if (ret < 0) - printf ("ft_blob_update): cannot set /soc/cpm/ethernet/mac-address " - "property err:%s\n", fdt_strerror (ret)); - } else { - /* memory node is required in dts */ - printf ("ft_blob_update(): cannot find /soc/cpm/ethernet node " - "err:%s\n", fdt_strerror (nodeoffset)); - } /* baudrate */ nodeoffset = fdt_path_offset (blob, "/soc/cpm/serial"); diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index ea14948c465..b955749d8fc 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -70,6 +70,7 @@ #define CONFIG_NET_MULTI 1 #define CONFIG_ETHER_INDEX 4 +#define CONFIG_HAS_ETH0 #define CONFIG_SYS_SCC_TOUT_LOOP 10000000 # define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8) diff --git a/include/configs/muas3001.h b/include/configs/muas3001.h index f031a17b271..ae033b2da55 100644 --- a/include/configs/muas3001.h +++ b/include/configs/muas3001.h @@ -74,6 +74,7 @@ #define CONFIG_ETHER_INDEX 1 #define CONFIG_ETHER_ON_FCC1 +#define CONFIG_HAS_ETH0 #define FCC_ENET /* From 1b72dbecca2d7ad7a21c92d80227daa2d8ec5a57 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Thu, 20 Aug 2009 17:44:20 -0500 Subject: [PATCH 109/208] ppc/85xx: Don't enable interrupts before we're ready We cannot handle any exceptions while running in AS1, as the exceptions will transition back to AS0 without a valid mapping. Signed-off-by: Scott Wood --- cpu/mpc85xx/start.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index e21a4eb8767..eaed0e0be5f 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -278,8 +278,8 @@ _start_e500: msync tlbwe - lis r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@h - ori r6,r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@l + lis r6,MSR_IS|MSR_DS@h + ori r6,r6,MSR_IS|MSR_DS@l lis r7,switch_as@h ori r7,r7,switch_as@l From dcc87dd58db466caa2d66755c5ec9455edf42fe8 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Thu, 20 Aug 2009 17:45:05 -0500 Subject: [PATCH 110/208] ppc/85xx: Ensure that MAS8 is zero when writing TLB entries. Its reset value is random, and we sometimes read uninitialized TLB arrays. Make sure that we don't retain MAS8 from reading such an entry if the VF bit in MAS8 is set, attempts to use the mapping will trap. Signed-off-by: Scott Wood --- cpu/mpc85xx/start.S | 4 ++++ cpu/mpc85xx/tlb.c | 3 +++ include/asm-ppc/processor.h | 2 ++ 3 files changed, 9 insertions(+) diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index eaed0e0be5f..7a23b4f811d 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -156,6 +156,10 @@ _start_e500: mtspr MCSR,r0 /* machine check syndrome register */ mtxer r0 /* clear integer exception register */ +#ifdef CONFIG_SYS_BOOK3E_HV + mtspr MAS8,r0 /* make sure MAS8 is clear */ +#endif + /* Enable Time Base and Select Time Base Clock */ lis r0,HID0_EMCP@h /* Enable machine check */ #if defined(CONFIG_ENABLE_36BIT_PHYS) diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index 0497a29ba83..03c2449b5c3 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -50,6 +50,9 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn, mtspr(MAS3, _mas3); #ifdef CONFIG_ENABLE_36BIT_PHYS mtspr(MAS7, _mas7); +#endif +#ifdef CONFIG_SYS_BOOK3E_HV + mtspr(MAS8, 0); #endif asm volatile("isync;msync;tlbwe;isync"); diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 0a4c66c9d9e..3764a5a51d5 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -518,6 +518,7 @@ #define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ #define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */ +#define SPRN_MAS8 0x155 /* MMU Assist Register 8 */ #define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ #define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ @@ -720,6 +721,7 @@ #define MAS5 SPRN_MAS5 #define MAS6 SPRN_MAS6 #define MAS7 SPRN_MAS7 +#define MAS8 SPRN_MAS8 #if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx) #define DAR_DEAR DEAR From 3e3c9c157b89eab2dc2f897899b1b95cd70c1a58 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Thu, 20 Aug 2009 17:45:00 -0500 Subject: [PATCH 111/208] ppc/85xx: Remove some bogus code from external interrupt handler. Skipping the interrupted instruction will accomplish nothing other than turning a spurious interrupt into a crash. External interrupts are not machine checks, so don't count them as such. Signed-off-by: Scott Wood --- cpu/mpc85xx/traps.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c index 1045cc1e7d0..9d16b9b55e7 100644 --- a/cpu/mpc85xx/traps.c +++ b/cpu/mpc85xx/traps.c @@ -287,6 +287,7 @@ UnknownException(struct pt_regs *regs) regs->nip, regs->msr, regs->trap); _exception(0, regs); } + void ExtIntException(struct pt_regs *regs) { @@ -305,14 +306,6 @@ ExtIntException(struct pt_regs *regs) printf(" irq IACK0@%05x=%d\n",(int)&pic->iack0,vect); show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); - machinecheck_count++; -#ifdef EXTINT_NOSKIP - printf("Returning back to 0x%08x\n",regs->nip); -#else - regs->nip += 4; /* skip offending instruction */ - printf("Skipping current instr, Returning to 0x%08lx\n",regs->nip); -#endif - } void From 6d8565a1ed5acb01bad4a4cd74a93be5f7fb7f7c Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 10 Sep 2009 14:54:55 -0500 Subject: [PATCH 112/208] ppc/8xxx: Misc DDR related fixes * Fix setting of ESDMODE (MR1) register - the bit shifting was wrong * Fix the format string to match size in a debug print Signed-off-by: Kumar Gala --- cpu/mpc8xxx/ddr/ctrl_regs.c | 10 +++++----- cpu/mpc8xxx/ddr/ddr3_dimm_params.c | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index 5e63c5df3ad..25050414504 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2009 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -675,12 +675,12 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, esdmode = (0 | ((qoff & 0x1) << 12) | ((tdqs_en & 0x1) << 11) - | ((rtt & 0x4) << 9) /* rtt field is split */ + | ((rtt & 0x4) << 7) /* rtt field is split */ | ((wrlvl_en & 0x1) << 7) - | ((rtt & 0x2) << 6) /* rtt field is split */ - | ((dic & 0x2) << 5) /* DIC field is split */ + | ((rtt & 0x2) << 5) /* rtt field is split */ + | ((dic & 0x2) << 4) /* DIC field is split */ | ((al & 0x3) << 3) - | ((rtt & 0x1) << 2) /* rtt field is split */ + | ((rtt & 0x1) << 2) /* rtt field is split */ | ((dic & 0x1) << 1) /* DIC field is split */ | ((dll_en & 0x1) << 0) ); diff --git a/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/cpu/mpc8xxx/ddr/ddr3_dimm_params.c index 13d234e9331..d4199baa82c 100644 --- a/cpu/mpc8xxx/ddr/ddr3_dimm_params.c +++ b/cpu/mpc8xxx/ddr/ddr3_dimm_params.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2009 Freescale Semiconductor, Inc. * Dave Liu * * calculate the organization and timing parameter @@ -71,7 +71,7 @@ compute_ranksize(const ddr3_spd_eeprom_t *spd) bsize = 1ULL << (nbit_sdram_cap_bsize - 3 + nbit_primary_bus_width - nbit_sdram_width); - debug("DDR: DDR III rank density = 0x%08x\n", bsize); + debug("DDR: DDR III rank density = 0x%16lx\n", bsize); return bsize; } From 0ead6f2ed7cf4e1f70dab5b529ad121e38359485 Mon Sep 17 00:00:00 2001 From: Roy Zang Date: Thu, 10 Sep 2009 14:44:48 +0800 Subject: [PATCH 113/208] ppc/85xx: Enable usb ehci support for p2020ds board Signed-off-by: Roy Zang Signed-off-by: Kumar Gala --- include/configs/P2020DS.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 46af7b9b069..2a2b9acf579 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -618,6 +618,15 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_CMD_EXT2 #endif +/* + * USB + */ +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET + #undef CONFIG_WATCHDOG /* watchdog disabled */ /* From d30f9043539d372cf66406bc2f21bb8c20e67009 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 11 Sep 2009 11:27:00 -0500 Subject: [PATCH 114/208] ppc/85xx: Introduce low level write_tlb function Factor out the code we use to actually write a tlb entry. set_tlb is a logical view of the TLB while write_tlb is a low level matching the MAS registers. Signed-off-by: Kumar Gala --- cpu/mpc85xx/start.S | 24 +++++++++++++++++++++++- cpu/mpc85xx/tlb.c | 16 +++------------- include/asm-ppc/mmu.h | 4 ++++ 3 files changed, 30 insertions(+), 14 deletions(-) diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 7a23b4f811d..eeee7a9764c 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007 Freescale Semiconductor. + * Copyright 2004, 2007-2009 Freescale Semiconductor. * Copyright (C) 2003 Motorola,Inc. * * See file CREDITS for list of people who contributed to this @@ -820,6 +820,28 @@ in32r: /*------------------------------------------------------------------------------*/ +/* + * void write_tlb(mas0, mas1, mas2, mas3, mas7) + */ + .globl write_tlb +write_tlb: + mtspr MAS0,r3 + mtspr MAS1,r4 + mtspr MAS2,r5 + mtspr MAS3,r6 +#ifdef CONFIG_ENABLE_36BIT_PHYS + mtspr MAS7,r7 +#endif + li r3,0 +#ifdef CONFIG_SYS_BOOK3E_HV + mtspr MAS8,r3 +#endif + isync + tlbwe + msync + isync + blr + /* * void relocate_code (addr_sp, gd, addr_moni) * diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index 03c2449b5c3..d39712a5135 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2009 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -42,19 +42,9 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn, _mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize); _mas2 = FSL_BOOKE_MAS2(epn, wimge); _mas3 = FSL_BOOKE_MAS3(rpn, 0, perms); - _mas7 = rpn >> 32; + _mas7 = FSL_BOOKE_MAS7(rpn); - mtspr(MAS0, _mas0); - mtspr(MAS1, _mas1); - mtspr(MAS2, _mas2); - mtspr(MAS3, _mas3); -#ifdef CONFIG_ENABLE_36BIT_PHYS - mtspr(MAS7, _mas7); -#endif -#ifdef CONFIG_SYS_BOOK3E_HV - mtspr(MAS8, 0); -#endif - asm volatile("isync;msync;tlbwe;isync"); + write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7); #ifdef CONFIG_ADDR_MAP if ((tlb == 1) && (gd->flags & GD_FLG_RELOC)) diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index eda2959b7d0..8f382fd6ff8 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -450,6 +450,8 @@ extern void print_bats(void); (((epn) & MAS3_RPN) | (wimge)) #define FSL_BOOKE_MAS3(rpn, user, perms) \ (((rpn) & MAS3_RPN) | (user) | (perms)) +#define FSL_BOOKE_MAS7(rpn) \ + (((u64)(rpn)) >> 32) #define BOOKE_PAGESZ_1K 0 #define BOOKE_PAGESZ_4K 1 @@ -480,6 +482,8 @@ extern int find_tlb_idx(void *addr, u8 tlbsel); extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); +extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7); + #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \ { .tlb = _tlb, .epn = _epn, .rpn = _rpn, .perms = _perms, \ .wimge = _wimge, .ts = _ts, .esel = _esel, .tsize = _sz, .iprot = _iprot } From 206af3527c05e520e28d38a48a1d15433e34675d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 11 Sep 2009 11:30:30 -0500 Subject: [PATCH 115/208] ppc/85xx: Repack tlb_table to save space We can pack the initial tlb_table in MAS register format and use write_tlb to set things up. This savings can be helpful for NAND style first stage boot loaders. Signed-off-by: Kumar Gala --- cpu/mpc85xx/tlb.c | 9 +++++---- include/asm-ppc/mmu.h | 21 ++++++++++----------- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index d39712a5135..f87a10d4f40 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -90,10 +90,11 @@ void init_tlbs(void) int i; for (i = 0; i < num_tlb_entries; i++) { - set_tlb(tlb_table[i].tlb, tlb_table[i].epn, tlb_table[i].rpn, - tlb_table[i].perms, tlb_table[i].wimge, - tlb_table[i].ts, tlb_table[i].esel, tlb_table[i].tsize, - tlb_table[i].iprot); + write_tlb(tlb_table[i].mas0, + tlb_table[i].mas1, + tlb_table[i].mas2, + tlb_table[i].mas3, + tlb_table[i].mas7); } return ; diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 8f382fd6ff8..a019d0b390b 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -485,19 +485,18 @@ extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7); #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \ - { .tlb = _tlb, .epn = _epn, .rpn = _rpn, .perms = _perms, \ - .wimge = _wimge, .ts = _ts, .esel = _esel, .tsize = _sz, .iprot = _iprot } + { .mas0 = FSL_BOOKE_MAS0(_tlb, _esel, 0), \ + .mas1 = FSL_BOOKE_MAS1(1, _iprot, 0, _ts, _sz), \ + .mas2 = FSL_BOOKE_MAS2(_epn, _wimge), \ + .mas3 = FSL_BOOKE_MAS3(_rpn, 0, _perms), \ + .mas7 = FSL_BOOKE_MAS7(_rpn), } struct fsl_e_tlb_entry { - u8 tlb; - u32 epn; - u64 rpn; - u8 perms; - u8 wimge; - u8 ts; - u8 esel; - u8 tsize; - u8 iprot; + u32 mas0; + u32 mas1; + u32 mas2; + u32 mas3; + u32 mas7; }; extern struct fsl_e_tlb_entry tlb_table[]; From b2eec281a811bb52941f61203d8fe35256b3582c Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 11 Sep 2009 12:32:01 -0500 Subject: [PATCH 116/208] ppc/85xx: Move code around to prep for NAND_SPL If we move some of the functions in tlb.c around we need less ifdefs. The first stage loader just needs invalidate_tlb and init_tlbs. Signed-off-by: Kumar Gala --- cpu/mpc85xx/tlb.c | 46 +++++++++++++++++++++++----------------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index f87a10d4f40..44e80b1b745 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -32,6 +32,29 @@ DECLARE_GLOBAL_DATA_PTR; +void invalidate_tlb(u8 tlb) +{ + if (tlb == 0) + mtspr(MMUCSR0, 0x4); + if (tlb == 1) + mtspr(MMUCSR0, 0x2); +} + +void init_tlbs(void) +{ + int i; + + for (i = 0; i < num_tlb_entries; i++) { + write_tlb(tlb_table[i].mas0, + tlb_table[i].mas1, + tlb_table[i].mas2, + tlb_table[i].mas3, + tlb_table[i].mas7); + } + + return ; +} + void set_tlb(u8 tlb, u32 epn, u64 rpn, u8 perms, u8 wimge, u8 ts, u8 esel, u8 tsize, u8 iprot) @@ -77,29 +100,6 @@ void disable_tlb(u8 esel) #endif } -void invalidate_tlb(u8 tlb) -{ - if (tlb == 0) - mtspr(MMUCSR0, 0x4); - if (tlb == 1) - mtspr(MMUCSR0, 0x2); -} - -void init_tlbs(void) -{ - int i; - - for (i = 0; i < num_tlb_entries; i++) { - write_tlb(tlb_table[i].mas0, - tlb_table[i].mas1, - tlb_table[i].mas2, - tlb_table[i].mas3, - tlb_table[i].mas7); - } - - return ; -} - static void tlbsx (const volatile unsigned *addr) { __asm__ __volatile__ ("tlbsx 0,%0" : : "r" (addr), "m" (*addr)); From 7da53351d817c6d77364cfde922891f37d0e5ed8 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Fri, 11 Sep 2009 14:19:10 +0800 Subject: [PATCH 117/208] ppc/85xx: add boot from NAND/eSDHC/eSPI support The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch implements these three bootup methods in a unified way - all of these use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM which lets us use the SPD to initialize the SDRAM. For all three bootup methods, the bootup process can be divided into two stages: the first stage will initialize the corresponding controller, configure the L2SRAM, then copy the second stage image to L2SRAM and jump to it. The second stage image is just like the general U-Boot image to configure all the hardware and boot up to U-Boot command line. When boot from NAND, the eLBC controller will first load the first stage image to internal 4K RAM buffer because it's also stored on the NAND flash. The first stage image, also call 4K NAND loader, will initialize the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K NAND loader's code comes from the corresponding nand_spl directory, along with the code twisted by CONFIG_NAND_SPL. When boot from eSDHC/eSPI, there's no such a first stage image because the CPU ROM code does the same work. It will initialize the L2SRAM according to the config addr/word pairs on the fixed address and initialize the eSDHC/eSPI controller, then load the second stage image to L2SRAM and jump to it. The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the second stage image for all different bootup methods. It's set in the board config file when one of the bootup methods above is selected. Signed-off-by: Mingkai Hu Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu_init.c | 19 +++++ cpu/mpc85xx/start.S | 23 +++++- cpu/mpc85xx/tlb.c | 2 + cpu/mpc85xx/u-boot-nand.lds | 138 ++++++++++++++++++++++++++++++++++++ drivers/misc/fsl_law.c | 2 + 5 files changed, 183 insertions(+), 1 deletion(-) create mode 100644 cpu/mpc85xx/u-boot-nand.lds diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index a54cf5d1570..5f6651182b6 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -291,6 +291,25 @@ int cpu_init_r(void) asm("msync;isync"); cache_ctl = l2cache->l2ctl; + +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + if (cache_ctl & MPC85xx_L2CTL_L2E) { + /* Clear L2 SRAM memory-mapped base address */ + out_be32(&l2cache->l2srbar0, 0x0); + out_be32(&l2cache->l2srbar1, 0x0); + + /* set MBECCDIS=0, SBECCDIS=0 */ + clrbits_be32(&l2cache->l2errdis, + (MPC85xx_L2ERRDIS_MBECC | + MPC85xx_L2ERRDIS_SBECC)); + + /* set L2E=0, L2SRAM=0 */ + clrbits_be32(&l2cache->l2ctl, + (MPC85xx_L2CTL_L2E | + MPC85xx_L2CTL_L2SRAM_ENTIRE)); + } +#endif + l2siz_field = (cache_ctl >> 28) & 0x3; switch (l2siz_field) { diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index eeee7a9764c..c9e91a90da6 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -57,10 +57,12 @@ GOT_ENTRY(_GOT2_TABLE_) GOT_ENTRY(_FIXUP_TABLE_) +#ifndef CONFIG_NAND_SPL GOT_ENTRY(_start) GOT_ENTRY(_start_of_vectors) GOT_ENTRY(_end_of_vectors) GOT_ENTRY(transfer_to_handler) +#endif GOT_ENTRY(__init_end) GOT_ENTRY(_end) @@ -239,10 +241,11 @@ _start_e500: #endif /* CONFIG_MPC8569 */ - /* create a temp mapping in AS=1 to the 4M boot window */ lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l +#ifndef CONFIG_SYS_RAMBOOT + /* create a temp mapping in AS=1 to the 4M boot window */ lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l @@ -252,6 +255,20 @@ _start_e500: /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l +#else + /* + * create a temp mapping in AS=1 to the 1M TEXT_BASE space, the main + * image has been relocated to TEXT_BASE on the second stage. + */ + lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l + + lis r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l + + lis r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l +#endif mtspr MAS0,r6 mtspr MAS1,r7 @@ -363,6 +380,7 @@ _start_cont: bl board_init_f isync +#ifndef CONFIG_NAND_SPL . = EXC_OFF_SYS_RESET .globl _start_of_vectors _start_of_vectors: @@ -817,6 +835,7 @@ in32: in32r: lwbrx r3,r0,r3 blr +#endif /* !CONFIG_NAND_SPL */ /*------------------------------------------------------------------------------*/ @@ -1001,6 +1020,7 @@ clear_bss: mr r4,r10 /* Destination Address */ bl board_init_r +#ifndef CONFIG_NAND_SPL /* * Copy exception vector code to low memory * @@ -1154,3 +1174,4 @@ setup_ivors: #include "fixed_ivor.S" blr +#endif /* !CONFIG_NAND_SPL */ diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index 44e80b1b745..6e94c237ad8 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -55,6 +55,7 @@ void init_tlbs(void) return ; } +#ifndef CONFIG_NAND_SPL void set_tlb(u8 tlb, u32 epn, u64 rpn, u8 perms, u8 wimge, u8 ts, u8 esel, u8 tsize, u8 iprot) @@ -209,3 +210,4 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) */ return memsize_in_meg; } +#endif /* !CONFIG_NAND_SPL */ diff --git a/cpu/mpc85xx/u-boot-nand.lds b/cpu/mpc85xx/u-boot-nand.lds new file mode 100644 index 00000000000..a0fc8f13887 --- /dev/null +++ b/cpu/mpc85xx/u-boot-nand.lds @@ -0,0 +1,138 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.fixup) + *(.got1) + } :text + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } :text + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + .bootpg ADDR(.text) - 0x1000 : + { + cpu/mpc85xx/start.o (.bootpg) + } :text = 0xffff + + . = ADDR(.text) + 0x80000; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } :bss + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); +} diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index 7bdd355c745..aa877c65fd3 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -74,6 +74,7 @@ int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) return idx; } +#ifndef CONFIG_NAND_SPL int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { u32 idx; @@ -166,6 +167,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id) return 0; } +#endif void init_laws(void) { From 6e1385d5f8d137e741dfef02465d7dc328040ad7 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Fri, 11 Sep 2009 10:53:08 +0800 Subject: [PATCH 118/208] NAND boot: change NAND loader's relocate SP to CONFIG param So that we can set the NAND loader's relocate stack pointer to the value other than the relocate address + 0x10000. Signed-off-by: Mingkai Hu Acked-by: Kim Phillips Acked-by: Scott Wood Signed-off-by: Kumar Gala --- board/freescale/mpc8313erdb/mpc8313erdb.c | 2 +- board/sheldon/simpc8313/simpc8313.c | 2 +- include/configs/MPC8313ERDB.h | 1 + include/configs/SIMPC8313.h | 1 + 4 files changed, 4 insertions(+), 2 deletions(-) diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c index 9ffd4bff872..e5f62ae9650 100644 --- a/board/freescale/mpc8313erdb/mpc8313erdb.c +++ b/board/freescale/mpc8313erdb/mpc8313erdb.c @@ -140,7 +140,7 @@ void board_init_f(ulong bootflag) puts("NAND boot... "); init_timebase(); initdram(0); - relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd, + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd, CONFIG_SYS_NAND_U_BOOT_RELOC); } diff --git a/board/sheldon/simpc8313/simpc8313.c b/board/sheldon/simpc8313/simpc8313.c index 25e5c2409dc..1044de2a471 100644 --- a/board/sheldon/simpc8313/simpc8313.c +++ b/board/sheldon/simpc8313/simpc8313.c @@ -112,7 +112,7 @@ void board_init_f(ulong bootflag) puts("NAND boot... "); init_timebase(); initdram(0); - relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd, + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd, CONFIG_SYS_NAND_U_BOOT_RELOC); } diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 4bf05d20336..76b78942ba9 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -242,6 +242,7 @@ #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) #define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \ | (2< Date: Fri, 11 Sep 2009 13:41:49 -0500 Subject: [PATCH 119/208] ppc/85xx: Change cpu_init_early_f so we can use with NAND SPL Use write_tlb and don't use memset so we can use the same code for cpu_init_early_f between NAND SPL and not. Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu_init.c | 34 +++++++++++++++++++++++++--------- 1 file changed, 25 insertions(+), 9 deletions(-) diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 5f6651182b6..07856c2a24c 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2007 Freescale Semiconductor. + * Copyright 2007-2009 Freescale Semiconductor, Inc. * * (C) Copyright 2003 Motorola Inc. * Modified by Xianghua Xiao, X.Xiao@motorola.com @@ -132,15 +132,26 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) /* We run cpu_init_early_f in AS = 1 */ void cpu_init_early_f(void) { + u32 mas0, mas1, mas2, mas3, mas7; + int i; + /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); + /* + * Clear initial global data + * we don't use memset so we can share this code with NAND_SPL + */ + for (i = 0; i < sizeof(gd_t); i++) + ((char *)gd)[i] = 0; - set_tlb(0, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 1, 0, BOOKE_PAGESZ_4K, 0); + mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(0); + mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K); + mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G); + mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); + mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS); + + write_tlb(mas0, mas1, mas2, mas3, mas7); /* set up CCSR if we want it moved */ #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) @@ -149,9 +160,14 @@ void cpu_init_early_f(void) volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000); - set_tlb(0, (u32)ccsr_virt, CONFIG_SYS_CCSRBAR_DEFAULT, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 1, 1, BOOKE_PAGESZ_4K, 0); + mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1); + /* mas1 is the same as above */ + mas2 = FSL_BOOKE_MAS2((u32)ccsr_virt, MAS2_I|MAS2_G); + mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, + MAS3_SW|MAS3_SR); + mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT); + + write_tlb(mas0, mas1, mas2, mas3, mas7); temp = in_be32(ccsr_virt); out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12); From 9f00409a9d04cf533305531da32437130802f3a3 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 11 Sep 2009 13:52:45 -0500 Subject: [PATCH 120/208] ppc/85xx: Split out cpu_init_early into its own file for NAND_SPL By pulling out cpu_init_early we can build just it and not all of cpu_init for NAND_SPL. Signed-off-by: Kumar Gala --- cpu/mpc85xx/Makefile | 1 + cpu/mpc85xx/cpu_init.c | 51 ------------------------ cpu/mpc85xx/cpu_init_early.c | 76 ++++++++++++++++++++++++++++++++++++ 3 files changed, 77 insertions(+), 51 deletions(-) create mode 100644 cpu/mpc85xx/cpu_init_early.c diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index a177f427efe..3ef00e85069 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -65,6 +65,7 @@ COBJS-$(CONFIG_CPM2) += serial_scc.o COBJS = $(COBJS-y) COBJS += cpu.o COBJS += cpu_init.o +COBJS += cpu_init_early.o COBJS += interrupts.o COBJS += speed.o COBJS += tlb.o diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 07856c2a24c..48a82eda6d8 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -129,57 +129,6 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) } #endif -/* We run cpu_init_early_f in AS = 1 */ -void cpu_init_early_f(void) -{ - u32 mas0, mas1, mas2, mas3, mas7; - int i; - - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - - /* - * Clear initial global data - * we don't use memset so we can share this code with NAND_SPL - */ - for (i = 0; i < sizeof(gd_t); i++) - ((char *)gd)[i] = 0; - - mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(0); - mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K); - mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G); - mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); - mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS); - - write_tlb(mas0, mas1, mas2, mas3, mas7); - - /* set up CCSR if we want it moved */ -#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) - { - u32 temp; - volatile u32 *ccsr_virt = - (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000); - - mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1); - /* mas1 is the same as above */ - mas2 = FSL_BOOKE_MAS2((u32)ccsr_virt, MAS2_I|MAS2_G); - mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, - MAS3_SW|MAS3_SR); - mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT); - - write_tlb(mas0, mas1, mas2, mas3, mas7); - - temp = in_be32(ccsr_virt); - out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12); - temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR); - } -#endif - - init_laws(); - invalidate_tlb(0); - init_tlbs(); -} - /* * Breathe some life into the CPU... * diff --git a/cpu/mpc85xx/cpu_init_early.c b/cpu/mpc85xx/cpu_init_early.c new file mode 100644 index 00000000000..7886f868f2a --- /dev/null +++ b/cpu/mpc85xx/cpu_init_early.c @@ -0,0 +1,76 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* We run cpu_init_early_f in AS = 1 */ +void cpu_init_early_f(void) +{ + u32 mas0, mas1, mas2, mas3, mas7; + int i; + + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); + + /* + * Clear initial global data + * we don't use memset so we can share this code with NAND_SPL + */ + for (i = 0; i < sizeof(gd_t); i++) + ((char *)gd)[i] = 0; + + mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(0); + mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K); + mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G); + mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); + mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS); + + write_tlb(mas0, mas1, mas2, mas3, mas7); + + /* set up CCSR if we want it moved */ +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) + { + u32 temp; + volatile u32 *ccsr_virt = + (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000); + + mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1); + /* mas1 is the same as above */ + mas2 = FSL_BOOKE_MAS2((u32)ccsr_virt, MAS2_I|MAS2_G); + mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, + MAS3_SW|MAS3_SR); + mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT); + + write_tlb(mas0, mas1, mas2, mas3, mas7); + + temp = in_be32(ccsr_virt); + out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12); + temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR); + } +#endif + + init_laws(); + invalidate_tlb(0); + init_tlbs(); +} From 15fba3279b56333bdb65ead366f82c945ed320d1 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 11 Sep 2009 15:28:41 -0500 Subject: [PATCH 121/208] ppc/85xx: Disable all async interrupt sources when we boot We should make sure to clear MSR[ME, CE, DE] when we boot an OS image since we have changed the exception vectors and the OSes vectors might not be setup we should avoid async interrupts at all costs. Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu_init.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 48a82eda6d8..a6d1e999b60 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -364,5 +364,16 @@ extern void setup_ivors(void); void arch_preboot_os(void) { + u32 msr; + + /* + * We are changing interrupt offsets and are about to boot the OS so + * we need to make sure we disable all async interrupts. EE is already + * disabled by the time we get called. + */ + msr = mfmsr(); + msr &= ~(MSR_ME|MSR_CE|MSR_DE); + mtmsr(msr); + setup_ivors(); } From 95a4a593b577b6e2f1da2d4b0f5ec86975c33413 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 11 Sep 2009 17:07:55 +0200 Subject: [PATCH 122/208] ppc4xx: Fix 405EZ uart base baud calculation With this fix, Linux correctly configures the baudrate when booting with FDT passed from U-Boot to Linux. Signed-off-by: Stefan Roese --- cpu/ppc4xx/speed.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index 1f751372cad..9c4bc099044 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -914,6 +914,7 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ/1000); unsigned long primad_cpudv; unsigned long m; + unsigned long plloutb; /* * Read PLL Mode registers @@ -999,7 +1000,10 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) sysInfo->freqEBC = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / sysInfo->pllExtBusDiv; - sysInfo->freqUART = sysInfo->freqVCOHz; + plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ? + sysInfo->pllFwdDivB : sysInfo->pllFwdDiv) * sysInfo->pllFbkDiv) / + sysInfo->pllFwdDivB); + sysInfo->freqUART = plloutb; } /******************************************** From 84a45d33c2cc261dbd5411f7c2ad45f6003025b6 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 11 Sep 2009 17:09:45 +0200 Subject: [PATCH 123/208] ppc4xx: Enable commands for FDT enabled Linux booting on AMCC Acadia Acadia still used the "old" arch/ppc bootm commands for booting Linux images without FDT. This patch now enables these fdt-aware boot commands for Acadia as well. Signed-off-by: Stefan Roese --- include/configs/acadia.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/acadia.h b/include/configs/acadia.h index b71010769f0..2fb48b641bc 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -225,7 +225,8 @@ */ #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_AMCC_DEF_ENV \ - CONFIG_AMCC_DEF_ENV_PPC \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_PPC_OLD \ CONFIG_AMCC_DEF_ENV_NOR_UPD \ CONFIG_AMCC_DEF_ENV_NAND_UPD \ "kernel_addr=fff10000\0" \ From e67af44d0167d8237dd2c2ddf8e301d19ca12914 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 14 Sep 2009 11:13:34 +0200 Subject: [PATCH 124/208] ppc4xx: Consolidate get_OPB_freq() All 4xx variants had their own, mostly identical get_OPB_freq() function. Some variants even only had the OPB frequency calculated in this routine and not supplied the sys_info.freqOPB variable correctly (e.g. 405EZ). This resulted in incorrect OPB values passed via the FDT to Linux. This patch now removes all those copies and only uses one function for all 4xx variants (except for IOP480 which doesn't have an OPB). Signed-off-by: Stefan Roese --- cpu/ppc4xx/speed.c | 90 ++++++++-------------------------------------- 1 file changed, 15 insertions(+), 75 deletions(-) diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index 9c4bc099044..988ba9742d2 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -165,29 +165,12 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) } } + sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv; sysInfo->freqEBC = sysInfo->freqPLB / sysInfo->pllExtBusDiv; - sysInfo->freqUART = sysInfo->freqProcessor; } -/******************************************** - * get_OPB_freq - * return OPB bus freq in Hz - *********************************************/ -ulong get_OPB_freq (void) -{ - ulong val = 0; - - PPC4xx_SYS_INFO sys_info; - - get_sys_info (&sys_info); - val = sys_info.freqPLB / sys_info.pllOpbDiv; - - return val; -} - - /******************************************** * get_PCI_freq * return PCI bus freq in Hz @@ -752,14 +735,6 @@ unsigned long determine_pci_clock_per(void) } #endif -ulong get_OPB_freq (void) -{ - - sys_info_t sys_info; - get_sys_info (&sys_info); - return sys_info.freqOPB; -} - #elif defined(CONFIG_XILINX_405) extern void get_sys_info (sys_info_t * sysInfo); extern ulong get_PCI_freq (void); @@ -874,23 +849,6 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) } -/******************************************** - * get_OPB_freq - * return OPB bus freq in Hz - *********************************************/ -ulong get_OPB_freq (void) -{ - ulong val = 0; - - PPC4xx_SYS_INFO sys_info; - - get_sys_info (&sys_info); - val = sys_info.freqPLB / sys_info.pllOpbDiv; - - return val; -} - - /******************************************** * get_PCI_freq * return PCI bus freq in Hz @@ -997,6 +955,9 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * m) / sysInfo->pllFwdDiv / sysInfo->pllPlbDiv; + sysInfo->freqOPB = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / + sysInfo->pllOpbDiv; + sysInfo->freqEBC = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / sysInfo->pllExtBusDiv; @@ -1006,22 +967,6 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) sysInfo->freqUART = plloutb; } -/******************************************** - * get_OPB_freq - * return OPB bus freq in Hz - *********************************************/ -ulong get_OPB_freq (void) -{ - ulong val = 0; - - PPC4xx_SYS_INFO sys_info; - - get_sys_info (&sys_info); - val = (CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / sys_info.pllOpbDiv; - - return val; -} - #elif defined(CONFIG_405EX) /* @@ -1168,22 +1113,6 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqUART = sysInfo->freqPLB; } -/******************************************** - * get_OPB_freq - * return OPB bus freq in Hz - *********************************************/ -ulong get_OPB_freq (void) -{ - ulong val = 0; - - PPC4xx_SYS_INFO sys_info; - - get_sys_info (&sys_info); - val = sys_info.freqPLB / sys_info.pllOpbDiv; - - return val; -} - #endif int get_clocks (void) @@ -1235,3 +1164,14 @@ ulong get_bus_freq (ulong dummy) return val; } + +#if !defined(CONFIG_IOP480) +ulong get_OPB_freq (void) +{ + PPC4xx_SYS_INFO sys_info; + + get_sys_info (&sys_info); + + return sys_info.freqOPB; +} +#endif From 0413cfecea350000eab5e591a0965c3e3ee0ff00 Mon Sep 17 00:00:00 2001 From: Simon Kagstrom Date: Thu, 17 Sep 2009 15:15:52 +0200 Subject: [PATCH 125/208] Correct ffs/fls regression for PowerPC etc Commits 02f99901ed1c9d828e3ea117f94ce2264bf8389e 52d61227b66d4099b39c8309ab37cb67ee09a405 introduced a regression where platform-specific ffs/fls implementations were defined away. This patch corrects that by using PLATFORM_xxx instead of the name itself. Signed-off-by: Simon Kagstrom Acked-by: Kumar Gala Acked-by: Stefan Roese --- include/asm-arm/bitops.h | 8 -------- include/asm-blackfin/bitops.h | 10 +--------- include/asm-i386/bitops.h | 2 +- include/asm-m68k/bitops.h | 2 +- include/asm-microblaze/bitops.h | 3 ++- include/asm-mips/bitops.h | 13 +------------ include/asm-nios/bitops.h | 2 +- include/asm-nios2/bitops.h | 2 +- include/asm-ppc/bitops.h | 4 ++-- include/asm-sh/bitops.h | 2 +- include/linux/bitops.h | 8 ++++---- 11 files changed, 15 insertions(+), 41 deletions(-) diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h index 3c7b00c48d0..270f163eee3 100644 --- a/include/asm-arm/bitops.h +++ b/include/asm-arm/bitops.h @@ -124,14 +124,6 @@ static inline unsigned long ffz(unsigned long word) return k; } -/* - * ffs: find first bit set. This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ - -#define ffs(x) generic_ffs(x) - /* * hweightN: returns the hamming weight (i.e. the number * of bits set) of a N-bit word diff --git a/include/asm-blackfin/bitops.h b/include/asm-blackfin/bitops.h index cc3685d35d7..ab1fea55c87 100644 --- a/include/asm-blackfin/bitops.h +++ b/include/asm-blackfin/bitops.h @@ -79,7 +79,7 @@ static __inline__ void __set_bit(int nr, volatile void *addr) mask = 1 << (nr & 0x1f); *a |= mask; } -#define __set_bit +#define PLATFORM__SET_BIT /* * clear_bit() doesn't provide any barrier for the compiler. @@ -269,14 +269,6 @@ static __inline__ int find_next_zero_bit(void *addr, int size, int offset) return result + ffz(tmp); } -/* - * ffs: find first bit set. This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ - -#define ffs(x) generic_ffs(x) - /* * hweightN: returns the hamming weight (i.e. the number * of bits set) of a N-bit word diff --git a/include/asm-i386/bitops.h b/include/asm-i386/bitops.h index ac6285aa5f2..c7a38f237a5 100644 --- a/include/asm-i386/bitops.h +++ b/include/asm-i386/bitops.h @@ -349,7 +349,7 @@ static __inline__ int ffs(int x) "1:" : "=r" (r) : "g" (x)); return r+1; } -#define ffs +#define PLATFORM_FFS /** * hweightN - returns the hamming weight of a N-bit word diff --git a/include/asm-m68k/bitops.h b/include/asm-m68k/bitops.h index e0c35fa7b05..ad971b4f31f 100644 --- a/include/asm-m68k/bitops.h +++ b/include/asm-m68k/bitops.h @@ -51,7 +51,7 @@ extern __inline__ int ffs(int x) return r; } #define __ffs(x) (ffs(x) - 1) -#define ffs +#define PLATFORM_FFS #endif /* __KERNEL__ */ diff --git a/include/asm-microblaze/bitops.h b/include/asm-microblaze/bitops.h index aac906102ab..5d814f0eb0e 100644 --- a/include/asm-microblaze/bitops.h +++ b/include/asm-microblaze/bitops.h @@ -23,6 +23,7 @@ extern void __set_bit(int nr, volatile void * addr); extern void clear_bit(int nr, volatile void * addr); #define __clear_bit(nr, addr) clear_bit(nr, addr) +#define PLATFORM__CLEAR_BIT extern void change_bit(int nr, volatile void * addr); extern void __change_bit(int nr, volatile void * addr); @@ -75,7 +76,7 @@ extern __inline__ void __set_bit(int nr, volatile void * addr) mask = 1 << (nr & 0x1f); *a |= mask; } -#define __set_bit +#define PLATFORM__SET_BIT /* * clear_bit() doesn't provide any barrier for the compiler. diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index 0c07b686a2d..1c8f4c05003 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -90,7 +90,7 @@ static __inline__ void __set_bit(int nr, volatile void * addr) *m |= 1UL << (nr & 31); } -#define __set_bit +#define PLATFORM__SET_BIT /* * clear_bit - Clears a bit in memory @@ -706,17 +706,6 @@ static __inline__ unsigned long ffz(unsigned long word) #ifdef __KERNEL__ -/** - * ffs - find first bit set - * @x: the word to search - * - * This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ - -#define ffs(x) generic_ffs(x) - /* * hweightN - returns the hamming weight of a N-bit word * @x: the word to weigh diff --git a/include/asm-nios/bitops.h b/include/asm-nios/bitops.h index 8315fb7caaf..0be74f42b8f 100644 --- a/include/asm-nios/bitops.h +++ b/include/asm-nios/bitops.h @@ -33,6 +33,6 @@ extern int test_and_set_bit(int nr, volatile void * a); extern int test_and_change_bit(int nr, volatile void * addr); extern int test_bit(int nr, volatile void * a); extern int ffs(int i); -#define ffs +#define PLATFORM_FFS #endif /* _ASM_NIOS_BITOPS_H */ diff --git a/include/asm-nios2/bitops.h b/include/asm-nios2/bitops.h index b01a89d63cd..5776bda3e3f 100644 --- a/include/asm-nios2/bitops.h +++ b/include/asm-nios2/bitops.h @@ -33,6 +33,6 @@ extern int test_and_set_bit(int nr, volatile void * a); extern int test_and_change_bit(int nr, volatile void * addr); extern int test_bit(int nr, volatile void * a); extern int ffs(int i); -#define ffs +#define PLATFORM_FFS #endif /* __ASM_NIOS2_BITOPS_H */ diff --git a/include/asm-ppc/bitops.h b/include/asm-ppc/bitops.h index 9ed2f5d6faa..adaf0914921 100644 --- a/include/asm-ppc/bitops.h +++ b/include/asm-ppc/bitops.h @@ -178,7 +178,7 @@ static __inline__ int fls(unsigned int x) { return __ilog2(x) + 1; } -#define fls +#define PLATFORM_FLS /** * fls64 - find last set bit in a 64-bit word @@ -231,7 +231,7 @@ extern __inline__ int ffs(int x) { return __ilog2(x & -x) + 1; } -#define ffs +#define PLATFORM_FFS /* * hweightN: returns the hamming weight (i.e. the number diff --git a/include/asm-sh/bitops.h b/include/asm-sh/bitops.h index 95167bd45ac..c57d6284785 100644 --- a/include/asm-sh/bitops.h +++ b/include/asm-sh/bitops.h @@ -146,7 +146,7 @@ static inline int ffs (int x) } return r; } -#define ffs +#define PLATFORM_FFS #endif /* __KERNEL__ */ diff --git a/include/linux/bitops.h b/include/linux/bitops.h index e14e6c7b14f..e7243102986 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -111,19 +111,19 @@ static inline unsigned int generic_hweight8(unsigned int w) /* linux/include/asm-generic/bitops/non-atomic.h */ -#ifndef __set_bit +#ifndef PLATFORM__SET_BIT # define __set_bit generic_set_bit #endif -#ifndef __clear_bit +#ifndef PLATFORM__CLEAR_BIT # define __clear_bit generic_clear_bit #endif -#ifndef ffs +#ifndef PLATFORM_FFS # define ffs generic_ffs #endif -#ifndef fls +#ifndef PLATFORM_FLS # define fls generic_fls #endif From 3b6a9267f0de7b85d387fa4123d0b58379363447 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 15 Sep 2009 00:09:21 +0200 Subject: [PATCH 126/208] board/flagadm/flash.c: fix compile warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix warning: flash.c:531: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Wolfgang Denk Cc: Kári Davíðsson --- board/flagadm/flash.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/board/flagadm/flash.c b/board/flagadm/flash.c index bbefbacea95..a69b1a4e975 100644 --- a/board/flagadm/flash.c +++ b/board/flagadm/flash.c @@ -528,11 +528,17 @@ int write_word (flash_info_t *info, ulong dest, ulong da) ulong start; char csr; int flag; - ushort * d = (ushort*)&da; int i; + union { + u32 data32; + u16 data16[2]; + } data; + + data.data32 = da; /* Check if Flash is (sufficiently) erased */ - if (((*addr & d[0]) != d[0]) || ((*(addr+1) & d[1]) != d[1])) { + if (((*addr & data.data16[0]) != data.data16[0]) || + ((*(addr+1) & data.data16[1]) != data.data16[1])) { return (2); } /* Disable interrupts which might cause a timeout here */ @@ -544,7 +550,7 @@ int write_word (flash_info_t *info, ulong dest, ulong da) *addr = 0x0010; /* Write Data */ - *addr = d[i]; + *addr = data.data16[i]; /* re-enable interrupts if necessary */ if (flag) From b55ae40249545eabb9d6bfb850b1400a32561b1f Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 9 Sep 2009 21:18:41 +0200 Subject: [PATCH 127/208] FDT: remove obsolete OF_CPU and OF_SOC macros. Signed-off-by: Marcel Ziswiler Acked-by: Guennadi Liakhovetski Acked-by: Heiko Schocher --- README | 6 ++++-- include/configs/IDS8247.h | 2 -- include/configs/MPC8260ADS.h | 1 - include/configs/linkstation.h | 2 -- include/configs/mgcoge.h | 2 -- include/configs/mpc7448hpc2.h | 1 - include/configs/muas3001.h | 2 -- include/configs/stxxtc.h | 1 - 8 files changed, 4 insertions(+), 13 deletions(-) diff --git a/README b/README index ff4ed8b95c0..3cb7786d4ed 100644 --- a/README +++ b/README @@ -368,8 +368,10 @@ The following options need to be configured: * Adds the "fdt" command * The bootm command automatically updates the fdt - OF_CPU - The proper name of the cpus node. - OF_SOC - The proper name of the soc node. + OF_CPU - The proper name of the cpus node (only required for + MPC512X and MPC5xxx based boards). + OF_SOC - The proper name of the soc node (only required for + MPC512X and MPC5xxx based boards). OF_TBCLK - The timebase frequency. OF_STDOUT_PATH - The path to the console device diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h index 4c4af054b2a..147a8b267da 100644 --- a/include/configs/IDS8247.h +++ b/include/configs/IDS8247.h @@ -125,8 +125,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "PowerPC,8247@0" -#define OF_SOC "soc@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000" diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index 942a4cc4876..677a1439c75 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -209,7 +209,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 #if defined(CONFIG_OF_LIBFDT) -#define OF_CPU "cpu@0" #define OF_TBCLK (bd->bi_busfreq / 4) #endif diff --git a/include/configs/linkstation.h b/include/configs/linkstation.h index 2feb3ae31d4..16b464cf6da 100644 --- a/include/configs/linkstation.h +++ b/include/configs/linkstation.h @@ -96,8 +96,6 @@ #define CONFIG_OF_LIBFDT 1 -#define OF_CPU "PowerPC,603e" -#define OF_SOC "soc10x@80000000" #define OF_STDOUT_PATH "/soc10x/serial@80004600" /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index b955749d8fc..55d1fc90fc6 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -347,8 +347,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "PowerPC,8247@0" -#define OF_SOC "soc@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc/cpm/serial@11a90" diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index 4f98ba41a5d..be12186aca0 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -79,7 +79,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "PowerPC,7448@0" #define OF_TSI "tsi108@c0000000" #define OF_TBCLK (bd->bi_busfreq / 8) #define OF_STDOUT_PATH "/tsi108@c0000000/serial@7808" diff --git a/include/configs/muas3001.h b/include/configs/muas3001.h index ae033b2da55..c94daa3d033 100644 --- a/include/configs/muas3001.h +++ b/include/configs/muas3001.h @@ -405,8 +405,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "PowerPC,8270@0" -#define OF_SOC "soc@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) #if defined(CONFIG_MUAS_DEV_BOARD) #define OF_STDOUT_PATH "/soc/cpm/serial@11a90" diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index d16262b6cff..585436604f2 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -509,7 +509,6 @@ typedef unsigned int led_id_t; /* pass open firmware flattened device tree */ #define CONFIG_OF_LIBFDT 1 -#define OF_CPU "PowerPC,MPC870@0" #define OF_TBCLK (MPC8XX_HZ / 16) #endif /* __CONFIG_H */ From d3f4941874a20d8a390a36ba71335ae1db2f9ba0 Mon Sep 17 00:00:00 2001 From: Paul Gibson Date: Wed, 16 Sep 2009 10:05:00 +1000 Subject: [PATCH 128/208] mpc512x. Micron nand flash needs a reset before a read command is issued. Micron nand flash needs a reset before a read command is issued. The current mpc5121_nfc driver ignores the reset command. --- drivers/mtd/nand/mpc5121_nfc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c index 856cb36c0c5..7fd8a354791 100644 --- a/drivers/mtd/nand/mpc5121_nfc.c +++ b/drivers/mtd/nand/mpc5121_nfc.c @@ -334,6 +334,7 @@ static void mpc5121_nfc_command(struct mtd_info *mtd, unsigned command, case NAND_CMD_ERASE2: case NAND_CMD_READID: case NAND_CMD_STATUS: + case NAND_CMD_RESET: break; default: From 3202d33169df04da5cf3dea8c5ab0a902b90ecaa Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Wed, 16 Sep 2009 21:38:10 -0500 Subject: [PATCH 129/208] Remove deprecated 'autoscr' command/variables The more standard 'source' command provides identical functionality to the autoscr command. Environment variable names/values on the MVBC_P, MVBML7, kmeter1, mgcoge, and km8xx boards are updated to no longer refernce 'autoscr'. The 'autoscript' and 'autoscript_uname' environment variables are also removed. Signed-off-by: Peter Tyser Acked-by: Andre Schwarz Acked-by: Heiko Schocher --- README | 8 -------- board/LEOX/elpt860/README.LEOX | 2 +- board/matrix_vision/mvbc_p/mvbc_p_autoscript | 4 ++-- board/matrix_vision/mvblm7/mvblm7_autoscript | 4 ++-- board/musenki/README | 2 +- board/pn62/cmd_pn62.c | 18 ------------------ common/cmd_load.c | 18 ------------------ common/cmd_net.c | 15 --------------- common/cmd_source.c | 18 ------------------ doc/README.IPHASE4539 | 2 +- doc/README.m52277evb | 2 +- doc/README.m5373evb | 2 +- doc/README.m54455evb | 2 +- doc/README.m5475evb | 2 +- doc/feature-removal-schedule.txt | 19 ------------------- include/configs/MVBC_P.h | 14 +++++++------- include/configs/MVBLM7.h | 14 +++++++------- include/configs/keymile-common.h | 6 +++--- 18 files changed, 28 insertions(+), 124 deletions(-) diff --git a/README b/README index 3cb7786d4ed..ce86e74baf3 100644 --- a/README +++ b/README @@ -3010,14 +3010,6 @@ Some configuration options can be set using Environment Variables: configuration from the BOOTP server, but not try to load any image using TFTP - autoscript - if set to "yes" commands like "loadb", "loady", - "bootp", "tftpb", "rarpboot" and "nfs" will attempt - to automatically run script images (by internally - calling "source"). - - autoscript_uname - if script image is in a format (FIT) this - variable is used to get script subimage unit name. - autostart - if set to "yes", an image loaded using the "bootp", "rarpboot", "tftpboot" or "diskboot" commands will be automatically started (by internally calling diff --git a/board/LEOX/elpt860/README.LEOX b/board/LEOX/elpt860/README.LEOX index 25524af69c2..e8ab86717d4 100644 --- a/board/LEOX/elpt860/README.LEOX +++ b/board/LEOX/elpt860/README.LEOX @@ -68,7 +68,6 @@ Type "run nfsboot" to mount root filesystem over NFS Hit any key to stop autoboot: 0 LEOX_elpt860: help askenv - get environment variables from stdin -autoscr - run script from memory base - print or set address offset bdinfo - print Board Info structure bootm - boot application image from memory @@ -100,6 +99,7 @@ run - run commands in an environment variable saveenv - save environment variables to persistent storage setenv - set environment variables sleep - delay execution for some time +source - run script from memory tftpboot- boot image via network using TFTP protocol and env variables ipaddr and serverip version - print monitor version diff --git a/board/matrix_vision/mvbc_p/mvbc_p_autoscript b/board/matrix_vision/mvbc_p/mvbc_p_autoscript index 1102354d684..9b21f30ece8 100644 --- a/board/matrix_vision/mvbc_p/mvbc_p_autoscript +++ b/board/matrix_vision/mvbc_p/mvbc_p_autoscript @@ -26,7 +26,7 @@ if test ${oprofile} = yes; then setenv addprofile setenv bootargs \${bootargs} profile=\${profile} fi -if test ${autoscr_boot} != no; +if test ${autoscript_boot} != no; then if test ${netboot} = yes; then @@ -44,5 +44,5 @@ then echo "=== bootfromflash ===" run cpdtb rundtb bootfromflash else - echo "=== boot stopped with autoscr_boot no ===" + echo "=== boot stopped with autoscript_boot no ===" fi diff --git a/board/matrix_vision/mvblm7/mvblm7_autoscript b/board/matrix_vision/mvblm7/mvblm7_autoscript index 6f9357fd0db..dc385fde793 100644 --- a/board/matrix_vision/mvblm7/mvblm7_autoscript +++ b/board/matrix_vision/mvblm7/mvblm7_autoscript @@ -21,7 +21,7 @@ setenv set_static_nm setenv netmask \${static_netmask} setenv set_static_gw setenv gatewayip \${static_gateway} setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask} setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs -if test ${autoscr_boot} != no; +if test ${autoscript_boot} != no; then if test ${netboot} = yes; then @@ -39,5 +39,5 @@ then echo "=== bootfromflash ===" run cpdtb rundtb bootfromflash else - echo "=== boot stopped with autoscr_boot no ===" + echo "=== boot stopped with autoscript_boot no ===" fi diff --git a/board/musenki/README b/board/musenki/README index 135a01aa0b1..084ab54ff78 100644 --- a/board/musenki/README +++ b/board/musenki/README @@ -34,7 +34,6 @@ Out: serial Err: serial Hit any key to stop autoboot: 0 => help -autoscr - run script from memory base - print or set address offset bdinfo - print Board Info structure bootm - boot application image from memory @@ -67,6 +66,7 @@ reset - Perform RESET of the CPU run - run commands in an environment variable saveenv - save environment variables to persistent storage setenv - set environment variables +source - run script from memory tftpboot- boot image via network using TFTP protocol and env variables ipaddr and serverip version - print monitor version diff --git a/board/pn62/cmd_pn62.c b/board/pn62/cmd_pn62.c index a9893517224..43295d6e36d 100644 --- a/board/pn62/cmd_pn62.c +++ b/board/pn62/cmd_pn62.c @@ -152,24 +152,6 @@ int do_loadpci (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) rcode = do_bootm (cmdtp, 0, 1, local_args); } -#ifdef CONFIG_SOURCE - if (load_addr) { - char *s; - - if (((s = getenv("autoscript")) != NULL) && (strcmp(s,"yes") == 0)) { - printf ("Running \"source\" command at addr 0x%08lX", - load_addr); - - s = getenv ("autoscript_uname"); - if (s) - printf (":%s ...\n", s); - else - puts (" ...\n"); - - rcode = source (load_addr, s); - } - } -#endif return rcode; } diff --git a/common/cmd_load.c b/common/cmd_load.c index 73fbf743c9b..d6bbb786da4 100644 --- a/common/cmd_load.c +++ b/common/cmd_load.c @@ -513,24 +513,6 @@ int do_load_serial_bin (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } } -#ifdef CONFIG_SOURCE - if (load_addr) { - char *s; - - if (((s = getenv("autoscript")) != NULL) && (strcmp(s,"yes") == 0)) { - printf ("Running \"source\" command at addr 0x%08lX", - load_addr); - - s = getenv ("autoscript_uname"); - if (s) - printf (":%s ...\n", s); - else - puts (" ...\n"); - - rcode = source (load_addr, s); - } - } -#endif return rcode; } diff --git a/common/cmd_net.c b/common/cmd_net.c index 88f4e5bae57..b80a7ad8e33 100644 --- a/common/cmd_net.c +++ b/common/cmd_net.c @@ -222,21 +222,6 @@ netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char *argv[]) rcode = do_bootm (cmdtp, 0, 1, local_args); } -#ifdef CONFIG_SOURCE - if (((s = getenv("autoscript")) != NULL) && (strcmp(s,"yes") == 0)) { - printf ("Running \"source\" command at addr 0x%08lX", - load_addr); - - s = getenv ("autoscript_uname"); - if (s) - printf (":%s ...\n", s); - else - puts (" ...\n"); - - show_boot_progress (83); - rcode = source (load_addr, s); - } -#endif if (rcode < 0) show_boot_progress (-83); else diff --git a/common/cmd_source.c b/common/cmd_source.c index 965b8b1b045..1424d3038c0 100644 --- a/common/cmd_source.c +++ b/common/cmd_source.c @@ -236,22 +236,4 @@ U_BOOT_CMD( "unit name in the form of addr:" #endif ); - -/* - * Keep for now for backward compatibility; - * remove later when support for "autoscr" goes away. - */ -static int -do_autoscr (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - printf ("\n### WARNING ### " - "\"autoscr\" is deprecated, use \"source\" instead ###\n\n"); - return do_source (cmdtp, flag, argc, argv); -} - -U_BOOT_CMD( - autoscr, 2, 0, do_autoscr, - "DEPRECATED - use \"source\" command instead", - "" -); #endif diff --git a/doc/README.IPHASE4539 b/doc/README.IPHASE4539 index defad3009fa..b804e069a19 100644 --- a/doc/README.IPHASE4539 +++ b/doc/README.IPHASE4539 @@ -54,7 +54,6 @@ connector as follows: ------------------------------------------------------------------------------ => help -autoscr - run script from memory base - print or set address offset bdinfo - print Board Info structure bootm - boot application image from memory @@ -88,6 +87,7 @@ run - run commands in an environment variable saveenv - save environment variables to persistent storage setenv - set environment variables sleep - delay execution for some time +source - run script from memory tftpboot- boot image via network using TFTP protocol and env variables ipaddr and serverip version - print monitor version diff --git a/doc/README.m52277evb b/doc/README.m52277evb index bec77b48aa5..40f9028c6f2 100644 --- a/doc/README.m52277evb +++ b/doc/README.m52277evb @@ -184,7 +184,6 @@ baudrate = 115200 bps -> -> help ? - alias for 'help' -autoscr - run script from memory base - print or set address offset bdinfo - print Board Info structure boot - boot default, i.e., run 'bootcmd' @@ -227,5 +226,6 @@ run - run commands in an environment variable saveenv - save environment variables to persistent storage setenv - set environment variables sleep - delay execution for some time +source - run script from memory version - print monitor version -> diff --git a/doc/README.m5373evb b/doc/README.m5373evb index 0bd1101c793..55917489338 100644 --- a/doc/README.m5373evb +++ b/doc/README.m5373evb @@ -195,7 +195,6 @@ baudrate = 115200 bps -> -> help ? - alias for 'help' -autoscr - run script from memory base - print or set address offset bdinfo - print Board Info structure boot - boot default, i.e., run 'bootcmd' @@ -243,6 +242,7 @@ run - run commands in an environment variable saveenv - save environment variables to persistent storage setenv - set environment variables sleep - delay execution for some time +source - run script from memory tftpboot- boot image via network using TFTP protocol version - print monitor version -> tftp 0x40800000 uImage diff --git a/doc/README.m54455evb b/doc/README.m54455evb index b769ff99571..1888e166253 100644 --- a/doc/README.m54455evb +++ b/doc/README.m54455evb @@ -276,7 +276,6 @@ baudrate = 115200 bps -> -> help ? - alias for 'help' -autoscr - run script from memory base - print or set address offset bdinfo - print Board Info structure boot - boot default, i.e., run 'bootcmd' @@ -332,6 +331,7 @@ run - run commands in an environment variable saveenv - save environment variables to persistent storage setenv - set environment variables sleep - delay execution for some time +source - run script from memory tftpboot- boot image via network using TFTP protocol version - print monitor version ->bootm 4000000 diff --git a/doc/README.m5475evb b/doc/README.m5475evb index 936c01815a8..f3a1d7b28b2 100644 --- a/doc/README.m5475evb +++ b/doc/README.m5475evb @@ -215,7 +215,6 @@ ip_addr = 192.162.1.2 baudrate = 115200 bps -> ? ? - alias for 'help' -autoscr - run script from memory base - print or set address offset bdinfo - print Board Info structure boot - boot default, i.e., run 'bootcmd' @@ -260,6 +259,7 @@ run - run commands in an environment variable saveenv - save environment variables to persistent storage setenv - set environment variables sleep - delay execution for some time +source - run script from memory tftpboot- boot image via network using TFTP protocol usb - USB sub-system usbboot - boot from USB device diff --git a/doc/feature-removal-schedule.txt b/doc/feature-removal-schedule.txt index 0238d97d2f1..5fe21e863f8 100644 --- a/doc/feature-removal-schedule.txt +++ b/doc/feature-removal-schedule.txt @@ -26,25 +26,6 @@ Who: Ben Warren --------------------------- -What: "autoscr" command -When: Release 2009-09 - -Why: "autosrc" is an ugly and completely non-standard name. - The "autoscr" command is deprecated and will be replaced by - - the "source" command as used by other shells such as bash. - - Starting with March 2009, both commands will be supported for - a transition period of 6 months after which "autoscr" will be - removed. During the transition period existing scripts and - environment variable names remain untouched for maximum - compatibiltiy; thse will be changed when support for the - "autoscr" command get's finally dropped. - -Who: Peter Tyser - ---------------------------- - What: GPL cleanup When: August 2009 Why: Over time, a couple of files have sneaked in into the U-Boot diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h index 0c228cb5a0d..8f6b16b93bf 100644 --- a/include/configs/MVBC_P.h +++ b/include/configs/MVBC_P.h @@ -73,8 +73,8 @@ #define MV_INITRD_LENGTH 0x00400000 #define MV_SCRATCH_ADDR 0x00000000 #define MV_SCRATCH_LENGTH MV_INITRD_LENGTH -#define MV_SOURCE_ADDR 0xff840000 -#define MV_SOURCE_ADDR2 0xff850000 +#define MV_SCRIPT_ADDR 0xff840000 +#define MV_SCRIPT_ADDR2 0xff850000 #define MV_DTB_ADDR 0xfffc0000 #define CONFIG_SHOW_BOOT_PROGRESS 1 @@ -130,9 +130,9 @@ #define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_RESET_TO_RETRY 1000 -#define CONFIG_BOOTCOMMAND "if imi ${autoscr_addr}; \ - then source ${autoscr_addr}; \ - else source ${autoscr_addr2}; \ +#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \ + then source ${script_addr}; \ + else source ${script_addr2}; \ fi;" #define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" @@ -150,8 +150,8 @@ "fpga=0\0" \ "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \ "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \ - "autoscr_addr=" MK_STR(MV_SOURCE_ADDR) "\0" \ - "autoscr_addr2=" MK_STR(MV_SOURCE_ADDR2) "\0" \ + "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \ + "script_addr2=" MK_STR(MV_SCRIPT_ADDR2) "\0" \ "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \ "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \ "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \ diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 80334bd607e..9835567838f 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -399,8 +399,8 @@ #define MV_FPGA_SIZE 0 #define MV_KERNEL_ADDR 0xff810000 #define MV_INITRD_ADDR 0xffb00000 -#define MV_SOURCE_ADDR 0xff804000 -#define MV_SOURCE_ADDR2 0xff806000 +#define MV_SCRIPT_ADDR 0xff804000 +#define MV_SCRIPT_ADDR2 0xff806000 #define MV_DTB_ADDR 0xff808000 #define MV_INITRD_LENGTH 0x00400000 @@ -410,9 +410,9 @@ #define MV_DTB_ADDR_RAM 0x00600000 #define MV_INITRD_ADDR_RAM 0x01000000 -#define CONFIG_BOOTCOMMAND "if imi ${autoscr_addr}; \ - then source ${autoscr_addr}; \ - else source ${autoscr_addr2}; \ +#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \ + then source ${script_addr}; \ + else source ${script_addr2}; \ fi;" #define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" @@ -425,8 +425,8 @@ "fpga=0\0" \ "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \ "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \ - "autoscr_addr=" MK_STR(MV_SOURCE_ADDR) "\0" \ - "autoscr_addr2=" MK_STR(MV_SOURCE_ADDR2) "\0" \ + "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \ + "script_addr2=" MK_STR(MV_SCRIPT_ADDR2) "\0" \ "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \ "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \ "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \ diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h index 0cc1b3b59ce..80c41a49688 100644 --- a/include/configs/keymile-common.h +++ b/include/configs/keymile-common.h @@ -171,7 +171,7 @@ "kernel_addr_r=200000\0" \ "fdt_addr_r=600000\0" \ "ram_ws=800000 \0" \ - "autoscr_ws=780000 \0" \ + "script_ws=780000 \0" \ "fdt_file=" xstr(CONFIG_HOSTNAME) "/" \ xstr(CONFIG_HOSTNAME) ".dtb\0" \ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin \0" \ @@ -253,8 +253,8 @@ "set_new_esw_script=setenv new_esw_script " \ "new_esw_0x${IVM_BoardId}_0x${IVM_HWKey}.scr \0" \ "new_esw=run set_new_esw_script; " \ - "tftp ${autoscr_ws} ${new_esw_script}; " \ - "iminfo ${autoscr_ws}; source ${autoscr_ws} \0" \ + "tftp ${script_ws} ${new_esw_script}; " \ + "iminfo ${script_ws}; source ${script_ws} \0" \ "bootlimit=0 \0" \ CONFIG_KM_DEF_ENV_IOMUX \ CONFIG_KM_DEF_ENV_PRIVATE \ From 3a8f28d0a6d9f8505017680233064c13e4587174 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Wed, 16 Sep 2009 22:03:07 -0500 Subject: [PATCH 130/208] ppc: Clean up calling of misc_init_r() during init Remove board-specific #ifdefs for calling misc_init_r() during initializtion Signed-off-by: Peter Tyser Acked-by: Heiko Schocher --- include/configs/CCM.h | 1 + include/configs/CPCI405.h | 1 + include/configs/CPCI4052.h | 1 + include/configs/CPCI405AB.h | 1 + include/configs/CPCI405DT.h | 1 + include/configs/W7OLMC.h | 1 + include/configs/W7OLMG.h | 1 + include/configs/cogent_mpc8260.h | 1 + include/configs/cogent_mpc8xx.h | 1 + include/configs/lwmon.h | 5 +++-- include/configs/pcu_e.h | 2 ++ include/configs/sc3.h | 1 + lib_ppc/board.c | 12 +----------- 13 files changed, 16 insertions(+), 13 deletions(-) diff --git a/include/configs/CCM.h b/include/configs/CCM.h index d1c293ff0ad..8a944207d7f 100644 --- a/include/configs/CCM.h +++ b/include/configs/CCM.h @@ -37,6 +37,7 @@ #define CONFIG_MPC860 1 /* This is a MPC860 CPU ... */ #define CONFIG_CCM 1 /* on a Card Controller Module */ +#define CONFIG_MISC_INIT_R /* Call misc_init_r() */ #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #undef CONFIG_8xx_CONS_SMC2 diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index fca6de0c6bc..d131aeaf43b 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -38,6 +38,7 @@ #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index fd045660897..07c4e359955 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -40,6 +40,7 @@ #undef CONFIG_CPCI405_6U /* enable this for 6U boards */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index d718ed40a3d..c78552bbd42 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -40,6 +40,7 @@ #define CONFIG_CPCI405AB 1 /* ...and special AB version */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 09df47082b6..59e0778f6a3 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -39,6 +39,7 @@ #define CONFIG_CPCI405_VER2 1 /* ...version 2 */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index 40e4735b681..c0179150c2b 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -40,6 +40,7 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* and misc_init_r() */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index a62f1b4d578..1d4ad13ed3b 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -40,6 +40,7 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* and misc_init_r() */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ diff --git a/include/configs/cogent_mpc8260.h b/include/configs/cogent_mpc8260.h index c580230225d..566565aad2c 100644 --- a/include/configs/cogent_mpc8260.h +++ b/include/configs/cogent_mpc8260.h @@ -38,6 +38,7 @@ #define CONFIG_CPM2 1 /* Has a CPM2 */ #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ +#define CONFIG_MISC_INIT_R /* Use misc_init_r() */ /* Cogent Modular Architecture options */ #define CONFIG_CMA282 1 /* ...on a CMA282 CPU module */ diff --git a/include/configs/cogent_mpc8xx.h b/include/configs/cogent_mpc8xx.h index 17bd9a02742..750c0df0c58 100644 --- a/include/configs/cogent_mpc8xx.h +++ b/include/configs/cogent_mpc8xx.h @@ -37,6 +37,7 @@ #define CONFIG_COGENT 1 /* using Cogent Modular Architecture */ #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ +#define CONFIG_MISC_INIT_R /* Use misc_init_r() */ /* Cogent Modular Architecture options */ #define CONFIG_CMA286_60_OLD 1 /* ...on an old CMA286-60 CPU module */ diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h index 8f00773216a..be20d729095 100644 --- a/include/configs/lwmon.h +++ b/include/configs/lwmon.h @@ -47,8 +47,9 @@ #define CONFIG_OVERWRITE_ETHADDR_ONCE 1 #endif -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ +#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init() */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ #define CONFIG_LCD 1 /* use LCD controller ... */ #define CONFIG_HLD1045 1 /* ... with a HLD1045 display */ diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h index 65173811706..11ad9ca927f 100644 --- a/include/configs/pcu_e.h +++ b/include/configs/pcu_e.h @@ -42,6 +42,8 @@ #define CONFIG_MPC860T 1 #define CONFIG_PCU_E 1 /* ...on a PCU E board */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ + #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #define CONFIG_BAUDRATE 9600 diff --git a/include/configs/sc3.h b/include/configs/sc3.h index 7e00ab8c710..57637607af8 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -63,6 +63,7 @@ #define CONFIG_405GP 1 #define CONFIG_BOARD_EARLY_INIT_F 1 +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ /* * Define IDE_USES_ISA_EMULATION for slower IDE access in the ISA-IO address range diff --git a/lib_ppc/board.c b/lib_ppc/board.c index e8509ee0e8d..c6fb6fe5592 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -921,17 +921,7 @@ void board_init_r (gd_t *id, ulong dest_addr) /* Initialize the console (after the relocation and devices init) */ console_init_r (); -#if defined(CONFIG_CCM) || \ - defined(CONFIG_COGENT) || \ - defined(CONFIG_CPCI405) || \ - defined(CONFIG_EVB64260) || \ - defined(CONFIG_KUP4K) || \ - defined(CONFIG_KUP4X) || \ - defined(CONFIG_LWMON) || \ - defined(CONFIG_PCU_E) || \ - defined(CONFIG_SC3) || \ - defined(CONFIG_W7O) || \ - defined(CONFIG_MISC_INIT_R) +#if defined(CONFIG_MISC_INIT_R) /* miscellaneous platform dependent initialisations */ misc_init_r (); #endif From 004eca0c9ba328de457d5dc9ef8805639dfef893 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Wed, 16 Sep 2009 22:03:08 -0500 Subject: [PATCH 131/208] ppc: Clean up calling of phy_reset() during init Remove board-specific #ifdefs for calling phy_reset() during initializtion Signed-off-by: Peter Tyser --- include/configs/CCM.h | 1 + include/configs/ELPT860.h | 1 + include/configs/IP860.h | 1 + include/configs/IVML24.h | 2 ++ include/configs/IVMS8.h | 2 ++ include/configs/MPC8260ADS.h | 1 + include/configs/MPC8266ADS.h | 1 + include/configs/MPC8560ADS.h | 1 + include/configs/RPXsuper.h | 1 + include/configs/SBC8540.h | 1 + include/configs/SPD823TS.h | 2 ++ include/configs/pcu_e.h | 1 + include/configs/sbc8560.h | 1 + include/configs/stxgp3.h | 1 + lib_ppc/board.c | 17 +---------------- 15 files changed, 18 insertions(+), 16 deletions(-) diff --git a/include/configs/CCM.h b/include/configs/CCM.h index 8a944207d7f..3f4a2c103e3 100644 --- a/include/configs/CCM.h +++ b/include/configs/CCM.h @@ -38,6 +38,7 @@ #define CONFIG_MPC860 1 /* This is a MPC860 CPU ... */ #define CONFIG_CCM 1 /* on a Card Controller Module */ #define CONFIG_MISC_INIT_R /* Call misc_init_r() */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #undef CONFIG_8xx_CONS_SMC2 diff --git a/include/configs/ELPT860.h b/include/configs/ELPT860.h index ff58ea92237..0f56302003b 100644 --- a/include/configs/ELPT860.h +++ b/include/configs/ELPT860.h @@ -57,6 +57,7 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ /* BOOT arguments */ #define CONFIG_PREBOOT \ diff --git a/include/configs/IP860.h b/include/configs/IP860.h index 125aa6c8025..be63ea5736b 100644 --- a/include/configs/IP860.h +++ b/include/configs/IP860.h @@ -36,6 +36,7 @@ #define CONFIG_MPC860 1 /* This is a MPC860 CPU */ #define CONFIG_IP860 1 /* ...on a IP860 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #define CONFIG_BAUDRATE 9600 diff --git a/include/configs/IVML24.h b/include/configs/IVML24.h index cd100df0577..1a4924e1e6d 100644 --- a/include/configs/IVML24.h +++ b/include/configs/IVML24.h @@ -52,6 +52,8 @@ #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ #define CONFIG_8xx_GCLK_FREQ 50331648 +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ + #define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ #if 0 diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h index 125cb4b2037..256cabd0368 100644 --- a/include/configs/IVMS8.h +++ b/include/configs/IVMS8.h @@ -49,6 +49,8 @@ #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 115200 +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ + #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ #define CONFIG_8xx_GCLK_FREQ 50331648 diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index 677a1439c75..39b8b8fce4f 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -81,6 +81,7 @@ #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ /* allow serial and ethaddr to be overwritten */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h index 4fd86d3923f..b0162c3971b 100644 --- a/include/configs/MPC8266ADS.h +++ b/include/configs/MPC8266ADS.h @@ -54,6 +54,7 @@ #define CONFIG_CPM2 1 /* Has a CPM2 */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ /* allow serial and ethaddr to be overwritten */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index c1a1a6d923e..8ddce5c699d 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -48,6 +48,7 @@ #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ /* * sysclk for MPC85xx diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h index e97ef9565ad..da962f3b937 100644 --- a/include/configs/RPXsuper.h +++ b/include/configs/RPXsuper.h @@ -189,6 +189,7 @@ #define CONFIG_CPM2 1 /* Has a CPM2 */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ /* * Miscellaneous configurable options diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 7239f8409de..272b5dd56cb 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -77,6 +77,7 @@ #undef CONFIG_BTB /* toggle branch predition */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ diff --git a/include/configs/SPD823TS.h b/include/configs/SPD823TS.h index 4181a400e88..fa77882cfd1 100644 --- a/include/configs/SPD823TS.h +++ b/include/configs/SPD823TS.h @@ -36,6 +36,8 @@ #define CONFIG_MPC823 1 /* This is a MPC823 CPU */ #define CONFIG_SPD823TS 1 /* ...on a SPD823TS board */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ + #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #undef CONFIG_8xx_CONS_SMC2 #undef CONFIG_8xx_CONS_NONE diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h index 11ad9ca927f..3aee206ad76 100644 --- a/include/configs/pcu_e.h +++ b/include/configs/pcu_e.h @@ -43,6 +43,7 @@ #define CONFIG_PCU_E 1 /* ...on a PCU E board */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 4fa501da5eb..46c94bf16be 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -71,6 +71,7 @@ #undef CONFIG_BTB /* toggle branch predition */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 0424e2978e3..86b231ca8ee 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -66,6 +66,7 @@ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ diff --git a/lib_ppc/board.c b/lib_ppc/board.c index c6fb6fe5592..f9dbdb9a86e 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -1000,22 +1000,7 @@ void board_init_r (gd_t *id, ulong dest_addr) eth_initialize (bd); #endif -#if defined(CONFIG_CMD_NET) && ( \ - defined(CONFIG_CCM) || \ - defined(CONFIG_ELPT860) || \ - defined(CONFIG_EP8260) || \ - defined(CONFIG_IP860) || \ - defined(CONFIG_IVML24) || \ - defined(CONFIG_IVMS8) || \ - defined(CONFIG_MPC8260ADS) || \ - defined(CONFIG_MPC8266ADS) || \ - defined(CONFIG_MPC8560ADS) || \ - defined(CONFIG_PCU_E) || \ - defined(CONFIG_RPXSUPER) || \ - defined(CONFIG_STXGP3) || \ - defined(CONFIG_SPD823TS) || \ - defined(CONFIG_RESET_PHY_R) ) - +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) WATCHDOG_RESET (); debug ("Reset Ethernet PHY\n"); reset_phy (); From 184a3a27f5cd2c64666f74df94c86b94c4383ef8 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 15 Sep 2009 00:26:02 +0200 Subject: [PATCH 132/208] board/linkstation/ide.c: Fix compile warning Fix warning: ide.c:60: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Wolfgang Denk Cc: Guennadi Liakhovetski --- board/linkstation/ide.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/board/linkstation/ide.c b/board/linkstation/ide.c index 2c89d62f614..568fdf5f2e8 100644 --- a/board/linkstation/ide.c +++ b/board/linkstation/ide.c @@ -54,11 +54,13 @@ int ide_preinit (void) if (devbusfn == -1) devbusfn = pci_find_device(PCI_VENDOR_ID_ITE,PCI_DEVICE_ID_ITE_8212,0); if (devbusfn != -1) { + u32 ide_bus_offset32; + status = 0; pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, - (u32 *) &ide_bus_offset[0]); - ide_bus_offset[0] &= 0xfffffffe; + &ide_bus_offset32); + ide_bus_offset[0] = ide_bus_offset32 & 0xfffffffe; ide_bus_offset[0] = pci_hose_bus_to_phys(&hose, ide_bus_offset[0] & 0xfffffffe, PCI_REGION_IO); From 91d599044caac4a8c228115b16cf3b073f902080 Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Mon, 21 Sep 2009 13:27:14 +0200 Subject: [PATCH 133/208] ppc4xx: Make DDR2 timing for intip more robust DDR2 timing for intip was on the edge for some of the available chips for this board. Now it is verfied to work with all of them. Signed-off-by: Dirk Eibach Signed-off-by: Stefan Roese --- include/configs/intip.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/include/configs/intip.h b/include/configs/intip.h index 4f7bc7e28dc..19f12fa770a 100644 --- a/include/configs/intip.h +++ b/include/configs/intip.h @@ -172,7 +172,7 @@ #define CONFIG_SYS_SDRAM_R3BAS 0x00000000 #define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000 #define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008 -#define CONFIG_SYS_SDRAM_CONF1LL 0x80001C80 +#define CONFIG_SYS_SDRAM_CONF1LL 0x80001C00 #define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80 #define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000 @@ -181,7 +181,7 @@ #define CONFIG_SYS_SDRAM0_MB1CF 0x00000000 #define CONFIG_SYS_SDRAM0_MB2CF 0x00000000 #define CONFIG_SYS_SDRAM0_MB3CF 0x00000000 -#define CONFIG_SYS_SDRAM0_MCOPT1 0x05122000 +#define CONFIG_SYS_SDRAM0_MCOPT1 0x05120000 #define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000 #define CONFIG_SYS_SDRAM0_MODT0 0x00000000 #define CONFIG_SYS_SDRAM0_MODT1 0x00000000 @@ -193,7 +193,7 @@ #define CONFIG_SYS_SDRAM0_INITPLR1 0x81900400 #define CONFIG_SYS_SDRAM0_INITPLR2 0x81020000 #define CONFIG_SYS_SDRAM0_INITPLR3 0x81030000 -#define CONFIG_SYS_SDRAM0_INITPLR4 0x81010000 +#define CONFIG_SYS_SDRAM0_INITPLR4 0x81010002 #define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000542 #define CONFIG_SYS_SDRAM0_INITPLR6 0x81900400 #define CONFIG_SYS_SDRAM0_INITPLR7 0x8A880000 @@ -201,21 +201,21 @@ #define CONFIG_SYS_SDRAM0_INITPLR9 0x8A880000 #define CONFIG_SYS_SDRAM0_INITPLR10 0x8A880000 #define CONFIG_SYS_SDRAM0_INITPLR11 0x81000442 -#define CONFIG_SYS_SDRAM0_INITPLR12 0x81010380 -#define CONFIG_SYS_SDRAM0_INITPLR13 0x81010000 +#define CONFIG_SYS_SDRAM0_INITPLR12 0x81010382 +#define CONFIG_SYS_SDRAM0_INITPLR13 0x81010002 #define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000 #define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000 #define CONFIG_SYS_SDRAM0_RQDC 0x80000038 -#define CONFIG_SYS_SDRAM0_RFDC 0x003F0000 -#define CONFIG_SYS_SDRAM0_RDCC 0x80000000 +#define CONFIG_SYS_SDRAM0_RFDC 0x00000257 +#define CONFIG_SYS_SDRAM0_RDCC 0x40000000 #define CONFIG_SYS_SDRAM0_DLCR 0x00000000 #define CONFIG_SYS_SDRAM0_CLKTR 0x40000000 -#define CONFIG_SYS_SDRAM0_WRDTR 0x84000800 +#define CONFIG_SYS_SDRAM0_WRDTR 0x84000823 #define CONFIG_SYS_SDRAM0_SDTR1 0x80201000 #define CONFIG_SYS_SDRAM0_SDTR2 0x32204232 -#define CONFIG_SYS_SDRAM0_SDTR3 0x090B0D15 +#define CONFIG_SYS_SDRAM0_SDTR3 0x090C0D15 #define CONFIG_SYS_SDRAM0_MMODE 0x00000442 -#define CONFIG_SYS_SDRAM0_MEMODE 0x00000000 +#define CONFIG_SYS_SDRAM0_MEMODE 0x00000002 #define CONFIG_SYS_MBYTES_SDRAM 256 /* 256MB */ From fcdb36b85ac033c09a9762a0a14808f7cb2ed54c Mon Sep 17 00:00:00 2001 From: Rupjyoti Sarmah Date: Mon, 21 Sep 2009 11:26:19 -0700 Subject: [PATCH 134/208] ppc4xx: Fix PCIE PLL lock on 440SPe Yucca board u-boot reports a PCIE PLL lock error at boot time on Yucca board, and left PCIe nonfunctional. This is fixed by making u-boot function ppc4xx_init_pcie() to wait 300 uS after negating reset before the first check of the PLL lock. Signed-off-by: Rupjyoti Sarmah Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_pcie.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index 07fbb0e643f..e880c288e1f 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -374,28 +374,35 @@ int ppc4xx_init_pcie(void) /* Set PLL clock receiver to LVPECL */ SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28); - if (check_error()) - return -1; + if (check_error()) { + printf("ERROR: failed to set PCIe reference clock receiver --" + "PESDR0_PLLLCT1 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT1)); + + return -1; + } + + /* Did resistance calibration work? */ + if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) { + printf("ERROR: PCIe resistance calibration failed --" + "PESDR0_PLLLCT2 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT2)); - if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) - { - printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n", - SDR_READ(PESDR0_PLLLCT2)); return -1; } /* De-assert reset of PCIe PLL, wait for lock */ SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24)); - udelay(3); + udelay(300); /* 300 uS is maximum time lock should take */ while (time_out) { if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) { time_out--; - udelay(1); + udelay(20); /* Wait 20 uS more if needed */ } else break; } if (!time_out) { - printf("PCIE: VCO output not locked\n"); + printf("ERROR: PCIe PLL VCO output not locked to ref clock --" + "PESDR0_PLLLCTS=0x%08x\n", SDR_READ(PESDR0_PLLLCT3)); + return -1; } return 0; From 9d7952e4c636b8c99289a44dbe28c6f93c43b9f7 Mon Sep 17 00:00:00 2001 From: Simon Kagstrom Date: Tue, 15 Sep 2009 09:53:29 +0200 Subject: [PATCH 135/208] ubifs: Add support for looking up directory and relative symlinks This patch adds support for resolving symlinks to directories as well as relative symlinks. Symlinks are now always resolved during file lookup, so the load stage no longer needs to special-case them. Signed-off-by: Simon Kagstrom Signed-off-by: Stefan Roese --- fs/ubifs/ubifs.c | 68 ++++++++++++++++++++++++++++++------------------ 1 file changed, 43 insertions(+), 25 deletions(-) diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c index 8ede188e147..b03ed0bb8e9 100644 --- a/fs/ubifs/ubifs.c +++ b/fs/ubifs/ubifs.c @@ -379,9 +379,11 @@ static unsigned long ubifs_findfile(struct super_block *sb, char *filename) int ret; char *next; char fpath[128]; + char symlinkpath[128]; char *name = fpath; unsigned long root_inum = 1; unsigned long inum; + int symlink_count = 0; /* Don't allow symlink recursion */ strcpy(fpath, filename); @@ -397,6 +399,9 @@ static unsigned long ubifs_findfile(struct super_block *sb, char *filename) return inum; for (;;) { + struct inode *inode; + struct ubifs_inode *ui; + /* Extract the actual part from the pathname. */ next = strchr(name, '/'); if (next) { @@ -406,18 +411,48 @@ static unsigned long ubifs_findfile(struct super_block *sb, char *filename) } ret = ubifs_finddir(sb, name, root_inum, &inum); + if (!ret) + return 0; + inode = ubifs_iget(sb, inum); + + if (!inode) + return 0; + ui = ubifs_inode(inode); + + if ((inode->i_mode & S_IFMT) == S_IFLNK) { + char link_name[64]; + char buf[128]; + + /* We have some sort of symlink recursion, bail out */ + if (symlink_count++ > 8) { + printf("Symlink recursion, aborting\n"); + return 0; + } + memcpy(link_name, ui->data, ui->data_len); + link_name[ui->data_len] = '\0'; + + if (link_name[0] == '/') { + /* Absolute path, redo everything without + * the leading slash */ + next = name = link_name + 1; + root_inum = 1; + continue; + } + /* Relative to cur dir */ + sprintf(buf, "%s%s", + link_name, next == NULL ? "" : next); + memcpy(symlinkpath, buf, sizeof(buf)); + next = name = symlinkpath; + continue; + } /* * Check if directory with this name exists */ /* Found the node! */ - if (!next || *next == '\0') { - if (ret) - return inum; - - break; - } + if (!next || *next == '\0') + return inum; root_inum = inum; name = next; @@ -614,10 +649,10 @@ int ubifs_load(char *filename, u32 addr, u32 size) int err = 0; int i; int count; - char link_name[64]; - struct ubifs_inode *ui; c->ubi = ubi_open_volume(c->vi.ubi_num, c->vi.vol_id, UBI_READONLY); + /* ubifs_findfile will resolve symlinks, so we know that we get + * the real file here */ inum = ubifs_findfile(ubifs_sb, filename); if (!inum) { err = -1; @@ -634,23 +669,6 @@ int ubifs_load(char *filename, u32 addr, u32 size) goto out; } - /* - * Check for symbolic link - */ - ui = ubifs_inode(inode); - if (((inode->i_mode & S_IFMT) == S_IFLNK) && ui->data_len) { - memcpy(link_name, ui->data, ui->data_len); - link_name[ui->data_len] = '\0'; - printf("%s is linked to %s!\n", filename, link_name); - ubifs_iput(inode); - - /* - * Now we have the "real" filename, call ubifs_load() - * again (recursive call) to load this file instead - */ - return ubifs_load(link_name, addr, size); - } - /* * If no size was specified or if size bigger than filesize * set size to filesize From b0078c8792badd81aed51b7eabe85e960036361c Mon Sep 17 00:00:00 2001 From: Werner Pfister Date: Mon, 21 Sep 2009 14:49:55 +0200 Subject: [PATCH 136/208] rtc/ds1337.c: Allow to set TCR register This is needed to correctly start the charging of an attached capacitor or battery. Signed-off-by: Werner Pfister Signed-off-by: Detlev Zundel --- drivers/rtc/ds1337.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c index a71ab5daa3f..7abf041aabd 100644 --- a/drivers/rtc/ds1337.c +++ b/drivers/rtc/ds1337.c @@ -56,6 +56,7 @@ #define RTC_YR_REG_ADDR 0x6 #define RTC_CTL_REG_ADDR 0x0e #define RTC_STAT_REG_ADDR 0x0f +#define RTC_TC_REG_ADDR 0x10 /* * RTC control register bits @@ -169,6 +170,9 @@ int rtc_set (struct rtc_time *tmp) void rtc_reset (void) { rtc_write (RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL); +#ifdef CONFIG_SYS_DS1339_TCR_VAL + rtc_write (RTC_TC_REG_ADDR, CONFIG_SYS_DS1339_TCR_VAL); +#endif } From c569ad6e1e8768a0fec513ffc156412240b7eb35 Mon Sep 17 00:00:00 2001 From: Werner Pfister Date: Mon, 21 Sep 2009 14:49:56 +0200 Subject: [PATCH 137/208] digsy_mtc: Add TCR register value for RTC (DS1339) Signed-off-by: Werner Pfister Signed-off-by: Detlev Zundel --- include/configs/digsy_mtc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h index 2bdaaace33b..7a1a7c33315 100644 --- a/include/configs/digsy_mtc.h +++ b/include/configs/digsy_mtc.h @@ -244,6 +244,7 @@ */ #define CONFIG_RTC_DS1337 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_DS1339_TCR_VAL 0xAB /* diode + 4k resistor */ /* * Flash configuration From 71ce9bd7f551e44c4ddb4c985c095da6d3452d79 Mon Sep 17 00:00:00 2001 From: Eric Millbrandt Date: Mon, 21 Sep 2009 11:05:55 -0500 Subject: [PATCH 138/208] galaxy5200: enable version environment variable Add version environment variable configuration to the galaxy5200 board header file. Signed-off-by: Eric Millbrandt Edited commit message. Signed-off-by: Wolfgang Denk --- include/configs/galaxy5200.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h index f4b520d39f2..3b67ea90bcc 100644 --- a/include/configs/galaxy5200.h +++ b/include/configs/galaxy5200.h @@ -367,6 +367,8 @@ CONFIG_BOOTP_DNS2 | \ CONFIG_BOOTP_SEND_HOSTNAME ) +#define CONFIG_VERSION_VARIABLE 1 + /* * Various low-level settings */ From 40a28f0885e62b6607e12ed6baa6284927f5263e Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 21 Sep 2009 12:04:32 -0500 Subject: [PATCH 139/208] MAKEALL: Add summary information This change adds some basic summary information to the MAKEALL script. The summary information includes how many boards were compiled, how many boards had compile warnings or errors, and which specific boards had compile warnings or errors. This information is useful when doing compile testing to quickly determine which boards are broken. As a side benefit, no empty $BOARD.ERR files are generated by MAKEALL. Previously, each board had a corresponding $BOARD.ERR file, even if the board compiled cleanly. Signed-off-by: Peter Tyser --- MAKEALL | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/MAKEALL b/MAKEALL index 1d50c343039..4688d422ff8 100755 --- a/MAKEALL +++ b/MAKEALL @@ -1,5 +1,9 @@ #!/bin/sh +# Print statistics when we exit +trap exit 1 2 3 15 +trap print_stats 0 + # Determine number of CPU cores if no default was set : ${BUILD_NCPUS:="`getconf _NPROCESSORS_ONLN`"} @@ -31,6 +35,11 @@ fi LIST="" +# Keep track of the number of builds and errors +ERR_CNT=0 +ERR_LIST="" +TOTAL_CNT=0 + ######################################################################### ## MPC5xx Systems ######################################################################### @@ -900,6 +909,14 @@ build_target() { ${MAKE} ${JOBS} all 2>&1 >${LOG_DIR}/$target.MAKELOG \ | tee ${LOG_DIR}/$target.ERR + if [ -s ${LOG_DIR}/$target.ERR ] ; then + ERR_CNT=$((ERR_CNT + 1)) + ERR_LIST="${ERR_LIST} $target" + else + rm ${LOG_DIR}/$target.ERR + fi + + TOTAL_CNT=$((TOTAL_CNT + 1)) ${CROSS_COMPILE}size ${BUILD_DIR}/u-boot \ | tee -a ${LOG_DIR}/$target.MAKELOG @@ -907,7 +924,17 @@ build_target() { #----------------------------------------------------------------------- +print_stats() { + echo "" + echo "--------------------- SUMMARY ----------------------------" + echo "Boards compiled: ${TOTAL_CNT}" + if [ ${ERR_CNT} -gt 0 ] ; then + echo "Boards with warnings or errors: ${ERR_CNT} (${ERR_LIST} )" + fi + echo "----------------------------------------------------------" +} +#----------------------------------------------------------------------- for arg in $@ do case "$arg" in From 55f786d8ba8ce58a81428536da34a2192b9bad9f Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 21 Sep 2009 12:04:33 -0500 Subject: [PATCH 140/208] MAKEALL: Use POSIX math Signed-off-by: Peter Tyser --- MAKEALL | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAKEALL b/MAKEALL index 4688d422ff8..dbcad87f181 100755 --- a/MAKEALL +++ b/MAKEALL @@ -9,7 +9,7 @@ trap print_stats 0 if [ "$BUILD_NCPUS" -gt 1 ] then - JOBS=-j`expr "$BUILD_NCPUS" + 1` + JOBS="-j $((BUILD_NCPUS + 1))" else JOBS="" fi From 202d94875c98b7b573f136c4f353609758ed9733 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 15 Sep 2009 22:21:58 -0500 Subject: [PATCH 141/208] ppc/85xx: Fix LCRR_CLKDIV defines For some reason the CLKDIV field varies between SoC in how it interprets the bit values. All 83xx and early (e500v1) PQ3 devices support: clk/2: CLKDIV = 2 clk/4: CLKDIV = 4 clk/8: CLKDIV = 8 Newer PQ3 (e500v2) and MPC86xx support: clk/4: CLKDIV = 2 clk/8: CLKDIV = 4 clk/16: CLKDIV = 8 Ensure that the MPC86xx and MPC85xx still get the same behavior and make the defines reflect their logical view (not the value of the field). Signed-off-by: Kumar Gala Acked-by: Peter Tyser --- include/asm-ppc/fsl_lbc.h | 8 ++++++++ include/configs/XPEDITE5170.h | 2 +- include/configs/XPEDITE5200.h | 2 +- include/configs/XPEDITE5370.h | 2 +- 4 files changed, 11 insertions(+), 3 deletions(-) diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h index a28082e56e6..08d31e12e4c 100644 --- a/include/asm-ppc/fsl_lbc.h +++ b/include/asm-ppc/fsl_lbc.h @@ -311,9 +311,17 @@ */ #define LCRR_CLKDIV 0x0000001F #define LCRR_CLKDIV_SHIFT 0 +#if defined(CONFIG_MPC83xx) || defined (CONFIG_MPC8540) || \ + defined(CONFIG_MPC8541) || defined (CONFIG_MPC8555) || \ + defined(CONFIG_MPC8560) #define LCRR_CLKDIV_2 0x00000002 #define LCRR_CLKDIV_4 0x00000004 #define LCRR_CLKDIV_8 0x00000008 +#else +#define LCRR_CLKDIV_4 0x00000002 +#define LCRR_CLKDIV_8 0x00000004 +#define LCRR_CLKDIV_16 0x00000008 +#endif /* LTEDR - Transfer Error Check Disable Register */ diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h index 242466ae120..30642cdfef4 100644 --- a/include/configs/XPEDITE5170.h +++ b/include/configs/XPEDITE5170.h @@ -122,7 +122,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable */ -#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_2 | LCRR_EADC_3) +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3) /* * NAND flash configuration diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h index deda20843af..d79231b8b8b 100644 --- a/include/configs/XPEDITE5200.h +++ b/include/configs/XPEDITE5200.h @@ -103,7 +103,7 @@ * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable */ -#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3) +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) /* * NAND flash configuration diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h index 3c58ebe39b2..65e1afddc69 100644 --- a/include/configs/XPEDITE5370.h +++ b/include/configs/XPEDITE5370.h @@ -116,7 +116,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable */ -#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3) +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) /* * NAND flash configuration From 0e905ac28b1e039d74e63232293972bff6b5a0ce Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Fri, 18 Sep 2009 11:45:09 +0800 Subject: [PATCH 142/208] ppc/85xx: simplify the top makefile for 36-bit config for mpc8536ds Signed-off-by: Mingkai Hu Signed-off-by: Kumar Gala --- Makefile | 4 +--- include/configs/MPC8536DS.h | 2 +- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 0b61d057f30..99837a38346 100644 --- a/Makefile +++ b/Makefile @@ -2448,9 +2448,7 @@ ATUM8548_config: unconfig MPC8536DS_36BIT_config \ MPC8536DS_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h - @$(MKCONFIG) -a MPC8536DS ppc mpc85xx mpc8536ds freescale + @$(MKCONFIG) -t $(@:_config=) MPC8536DS ppc mpc85xx mpc8536ds freescale MPC8540ADS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads freescale diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 4746e2ead56..faca8059a1f 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -27,7 +27,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#ifdef CONFIG_MPC8536DS_36BIT +#ifdef CONFIG_MK_36BIT #define CONFIG_PHYS_64BIT 1 #endif From f9edcc10e6cb497dd7dcbaf691cfd1859abae27a Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 10 Sep 2009 16:23:45 -0500 Subject: [PATCH 143/208] ppc/85xx: Simplify the top makefile for 36-bit config for MPC8572DS Signed-off-by: Kumar Gala --- Makefile | 7 +------ include/configs/MPC8572DS.h | 4 ++++ 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/Makefile b/Makefile index 99837a38346..8672336f15a 100644 --- a/Makefile +++ b/Makefile @@ -2514,12 +2514,7 @@ MPC8569MDS_config: unconfig MPC8572DS_36BIT_config \ MPC8572DS_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _36BIT_,$@)" ] ; then \ - echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \ - $(XECHO) "... enabling 36-bit physical addressing." ; \ - fi - @$(MKCONFIG) -a MPC8572DS ppc mpc85xx mpc8572ds freescale + @$(MKCONFIG) -t $(@:_config=) MPC8572DS ppc mpc85xx mpc8572ds freescale P2020DS_36BIT_config \ P2020DS_config: unconfig diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 55c1f29b192..000f8f62d62 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -27,6 +27,10 @@ #ifndef __CONFIG_H #define __CONFIG_H +#ifdef CONFIG_MK_36BIT +#define CONFIG_PHYS_64BIT +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ From a0f9e0e0f06033807de0ae017ad4d9cf5ddff84b Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 10 Sep 2009 16:26:37 -0500 Subject: [PATCH 144/208] ppc/85xx: Simplify the top makefile for 36-bit config for P2020DS Signed-off-by: Kumar Gala --- Makefile | 7 +------ include/configs/P2020DS.h | 4 ++++ 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/Makefile b/Makefile index 8672336f15a..1e256698f05 100644 --- a/Makefile +++ b/Makefile @@ -2518,12 +2518,7 @@ MPC8572DS_config: unconfig P2020DS_36BIT_config \ P2020DS_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _36BIT_,$@)" ] ; then \ - echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \ - $(XECHO) "... enabling 36-bit physical addressing." ; \ - fi - @$(MKCONFIG) -a P2020DS ppc mpc85xx p2020ds freescale + @$(MKCONFIG) -t $(@:_config=) P2020DS ppc mpc85xx p2020ds freescale P1011RDB_config: unconfig @mkdir -p $(obj)include diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 2a2b9acf579..b48c1999f8f 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -27,6 +27,10 @@ #ifndef __CONFIG_H #define __CONFIG_H +#ifdef CONFIG_MK_36BIT +#define CONFIG_PHYS_64BIT +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ From 62ca21c442e18fec118ec83e183d64ea49966ce7 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 10 Sep 2009 16:31:53 -0500 Subject: [PATCH 145/208] ppc/85xx: Simplify the top makefile for P1_P2_RDB boards Signed-off-by: Kumar Gala --- Makefile | 22 ++++------------------ include/configs/P1_P2_RDB.h | 13 +++++++++++++ 2 files changed, 17 insertions(+), 18 deletions(-) diff --git a/Makefile b/Makefile index 1e256698f05..d8daa89502e 100644 --- a/Makefile +++ b/Makefile @@ -2520,25 +2520,11 @@ P2020DS_36BIT_config \ P2020DS_config: unconfig @$(MKCONFIG) -t $(@:_config=) P2020DS ppc mpc85xx p2020ds freescale -P1011RDB_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_P1011" >>$(obj)include/config.h ; - @$(MKCONFIG) -a P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale - -P1020RDB_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_P1020" >>$(obj)include/config.h ; - @$(MKCONFIG) -a P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale - -P2010RDB_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_P2010" >>$(obj)include/config.h ; - @$(MKCONFIG) -a P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale - +P1011RDB_config \ +P1020RDB_config \ +P2010RDB_config \ P2020RDB_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_P2020" >>$(obj)include/config.h ; - @$(MKCONFIG) -a P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale + @$(MKCONFIG) -t $(@:_config=) P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale PM854_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854 diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 6d44d6c8ddb..8e97ad06819 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -30,6 +30,19 @@ #ifndef __CONFIG_H #define __CONFIG_H +#ifdef CONFIG_MK_P1011RDB +#define CONFIG_P1011 +#endif +#ifdef CONFIG_MK_P1020RDB +#define CONFIG_P1020 +#endif +#ifdef CONFIG_MK_P2010RDB +#define CONFIG_P2010 +#endif +#ifdef CONFIG_MK_P2020RDB +#define CONFIG_P2020 +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ From 93a83872c707891bad22f7776d79a650c870601f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 3 Sep 2009 10:09:04 -0500 Subject: [PATCH 146/208] ppc/85xx: Clean up p1_p2_rdb PCI setup General code cleanup to use in/out IO accessors as well as making the code that prints out info sane between board and generic fsl pci code. Signed-off-by: Kumar Gala --- board/freescale/p1_p2_rdb/pci.c | 42 +++++++++++++++++---------------- drivers/pci/fsl_pci_init.c | 2 +- 2 files changed, 23 insertions(+), 21 deletions(-) diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c index a3617d57037..4c08f9efa0b 100644 --- a/board/freescale/p1_p2_rdb/pci.c +++ b/board/freescale/p1_p2_rdb/pci.c @@ -41,60 +41,62 @@ static struct pci_controller pcie2_hose; void pci_init_board(void) { - struct fsl_pci_info pci_info[2]; volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint devdisr = in_be32(&gur->devdisr); - uint io_sel = (in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16; - int num = 0; + struct fsl_pci_info pci_info[2]; + u32 devdisr, pordevsr, io_sel, host_agent; int first_free_busno = 0; + int num = 0; int pcie_ep, pcie_configured; + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16; + debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", devdisr, io_sel, host_agent); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) printf (" eTSEC2 is in sgmii mode.\n"); + puts("\n"); #ifdef CONFIG_PCIE2 - SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - puts ("\n PCIE2 connected to Slot 1 as "); - printf ("%s (base address %lx)", - pcie_ep ? "End Point": "Root Complex", pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num], + SET_STD_PCIE_INFO(pci_info[num], 2); + printf(" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie2_hose, first_free_busno); - num++; } else { printf (" PCIE2: disabled\n"); } + puts("\n"); #else - set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ #endif #ifdef CONFIG_PCIE1 - SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - puts ("\n PCIE1 connected to Slot 2 as "); - printf ("%s (base address %lx)", + SET_STD_PCIE_INFO(pci_info[num], 1); + printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num], + first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); - num++; } else { printf (" PCIE1: disabled\n"); } + puts("\n"); #else - set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif } diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 885542c1e9f..87944bfad57 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -450,7 +450,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - printf("\n PCIE%x on bus %02x - %02x\n", pci_info->pci_num, + printf(" PCIE%x on bus %02x - %02x\n", pci_info->pci_num, hose->first_busno, hose->last_busno); return(hose->last_busno + 1); From 4958af8735207640181c4423e41b24ee7418361a Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 3 Sep 2009 09:42:01 -0500 Subject: [PATCH 147/208] ppc/85xx: Clean up p2020ds PCI setup code Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala --- board/freescale/p2020ds/p2020ds.c | 150 +++++++----------------------- 1 file changed, 33 insertions(+), 117 deletions(-) diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index 7ad9be88c32..e38c0145edc 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -192,69 +192,42 @@ static struct pci_controller pcie2_hose; static struct pci_controller pcie3_hose; #endif -int first_free_busno = 0; - #ifdef CONFIG_PCI void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + struct fsl_pci_info pci_info[3]; + u32 devdisr, pordevsr, io_sel, host_agent; + int first_free_busno = 0; + int num = 0; - volatile ccsr_fsl_pci_t *pci; - struct pci_controller *hose; int pcie_ep, pcie_configured; - struct pci_region *r; -/* u32 temp32; */ + + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16; debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", devdisr, io_sel, host_agent); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) printf(" eTSEC2 is in sgmii mode.\n"); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) printf(" eTSEC3 is in sgmii mode.\n"); + puts("\n"); #ifdef CONFIG_PCIE2 - pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; - hose = &pcie2_hose; pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); - r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { - printf("\n PCIE2 connected to ULI as %s (base addr %x)", + SET_STD_PCIE_INFO(pci_info[num], 2); + printf(" PCIE2 connected to ULI as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug(" with errors. Clearing. Now 0x%08x", - pci->pme_msg_det); - } - printf("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BUS, - CONFIG_SYS_PCIE2_MEM_PHYS, - CONFIG_SYS_PCIE2_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_IO_BUS, - CONFIG_SYS_PCIE2_IO_PHYS, - CONFIG_SYS_PCIE2_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - hose->first_busno = first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno = hose->last_busno+1; - printf(" PCIE2 on bus %02x - %02x\n", - hose->first_busno, hose->last_busno); + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie2_hose, first_free_busno); /* * The workaround doesn't work on p2020 because the location @@ -279,104 +252,47 @@ void pci_init_board(void) } else { printf(" PCIE2: disabled\n"); } + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ #endif #ifdef CONFIG_PCIE3 - pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; - hose = &pcie3_hose; pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); - r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { - printf("\n PCIE3 connected to Slot 1 as %s (base addr %x)", + SET_STD_PCIE_INFO(pci_info[num], 3); + printf(" PCIE3 connected to Slot 1 as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug(" with errors. Clearing. Now 0x%08x", - pci->pme_msg_det); - } - printf("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE3_MEM_BUS, - CONFIG_SYS_PCIE3_MEM_PHYS, - CONFIG_SYS_PCIE3_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE3_IO_BUS, - CONFIG_SYS_PCIE3_IO_PHYS, - CONFIG_SYS_PCIE3_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - hose->first_busno = first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno = hose->last_busno+1; - printf(" PCIE3 on bus %02x - %02x\n", - hose->first_busno, hose->last_busno); - + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie3_hose, first_free_busno); } else { printf(" PCIE3: disabled\n"); } + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ #endif #ifdef CONFIG_PCIE1 - pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - hose = &pcie1_hose; pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) { - printf("\n PCIE1 connected to Slot 2 as %s (base addr %x)", + SET_STD_PCIE_INFO(pci_info[num], 1); + printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug(" with errors. Clearing. Now 0x%08x", - pci->pme_msg_det); - } - printf("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BUS, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BUS, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - hose->first_busno = first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno = hose->last_busno+1; - printf(" PCIE1 on bus %02x - %02x\n", - hose->first_busno, hose->last_busno); - + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); } else { printf(" PCIE1: disabled\n"); } + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif } #endif From f61dae7c9dc526410faec15ce352b11fc36a560b Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 3 Sep 2009 10:20:09 -0500 Subject: [PATCH 148/208] ppc/85xx: Clean up mpc8572DS PCI setup code Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala --- board/freescale/mpc8572ds/mpc8572ds.c | 224 ++++++++------------------ 1 file changed, 70 insertions(+), 154 deletions(-) diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index c69934ca62d..933dd127ec9 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -160,189 +160,105 @@ static struct pci_controller pcie2_hose; static struct pci_controller pcie3_hose; #endif -int first_free_busno=0; #ifdef CONFIG_PCI void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + struct fsl_pci_info pci_info[3]; + u32 devdisr, pordevsr, io_sel, host_agent, temp32; + int first_free_busno = 0; + int num = 0; + + int pcie_ep, pcie_configured; + + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16; debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", devdisr, io_sel, host_agent); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) printf (" eTSEC1 is in sgmii mode.\n"); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) printf (" eTSEC2 is in sgmii mode.\n"); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) printf (" eTSEC3 is in sgmii mode.\n"); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) printf (" eTSEC4 is in sgmii mode.\n"); - + puts("\n"); #ifdef CONFIG_PCIE3 - { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; - struct pci_controller *hose = &pcie3_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); - struct pci_region *r = hose->regions; - u32 temp32; + pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ - printf ("\n PCIE3 connected to ULI as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE3_MEM_BUS, - CONFIG_SYS_PCIE3_MEM_PHYS, - CONFIG_SYS_PCIE3_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE3_IO_BUS, - CONFIG_SYS_PCIE3_IO_PHYS, - CONFIG_SYS_PCIE3_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno=hose->last_busno+1; - printf (" PCIE3 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); - - /* - * Activate ULI1575 legacy chip by performing a fake - * memory access. Needed to make ULI RTC work. - * Device 1d has the first on-board memory BAR. - */ - - pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ), - PCI_BASE_ADDRESS_1, &temp32); - if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { - void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0), - temp32, 4, 0); - debug(" uli1572 read to %p\n", p); - in_be32(p); - } - } else { - printf (" PCIE3: disabled\n"); + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ + SET_STD_PCIE_INFO(pci_info[num], 3); + printf (" PCIE3 connected to ULI as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie3_hose, first_free_busno); + /* + * Activate ULI1575 legacy chip by performing a fake + * memory access. Needed to make ULI RTC work. + * Device 1d has the first on-board memory BAR. + */ + pci_hose_read_config_dword(&pcie3_hose, PCI_BDF(2, 0x1d, 0), + PCI_BASE_ADDRESS_1, &temp32); + if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { + void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0), + temp32, 4, 0); + debug(" uli1572 read to %p\n", p); + in_be32(p); } - + } else { + printf (" PCIE3: disabled\n"); } + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ #endif #ifdef CONFIG_PCIE2 - { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; - struct pci_controller *hose = &pcie2_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); - struct pci_region *r = hose->regions; - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ - printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BUS, - CONFIG_SYS_PCIE2_MEM_PHYS, - CONFIG_SYS_PCIE2_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_IO_BUS, - CONFIG_SYS_PCIE2_IO_PHYS, - CONFIG_SYS_PCIE2_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno=hose->last_busno+1; - printf (" PCIE2 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); - - } else { - printf (" PCIE2: disabled\n"); - } + pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ + SET_STD_PCIE_INFO(pci_info[num], 2); + printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie2_hose, first_free_busno); + } else { + printf (" PCIE2: disabled\n"); } + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ #endif + #ifdef CONFIG_PCIE1 - { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - struct pci_controller *hose = &pcie1_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - struct pci_region *r = hose->regions; - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BUS, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BUS, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno=hose->last_busno+1; - printf(" PCIE1 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); - - } else { - printf (" PCIE1: disabled\n"); - } + pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + SET_STD_PCIE_INFO(pci_info[num], 1); + printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); + } else { + printf (" PCIE1: disabled\n"); } + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif } #endif From 002741ae862c1c7e3dad89d020e392e6add1c05d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Sat, 19 Sep 2009 11:20:54 -0500 Subject: [PATCH 149/208] ppc/85xx: Clean up use of LAWAR defines On 85xx platforms we shouldn't be using any LAWAR_* defines but using the LAW_* ones provided by fsl-law.h. Rename any such uses and limit the LAWAR_ to the 83xx platform as the only user so we will get compile errors in the future. Signed-off-by: Kumar Gala --- board/atum8548/law.c | 2 +- board/freescale/mpc8536ds/law.c | 6 +++--- board/freescale/mpc8540ads/law.c | 2 +- board/freescale/mpc8544ds/law.c | 6 +++--- board/freescale/mpc8560ads/law.c | 2 +- board/freescale/mpc8572ds/law.c | 6 +++--- board/freescale/p1_p2_rdb/law.c | 4 ++-- board/freescale/p2020ds/law.c | 6 +++--- board/pm854/law.c | 2 +- board/pm856/law.c | 2 +- board/socrates/law.c | 4 ++-- board/stx/stxgp3/law.c | 2 +- board/stx/stxssa/law.c | 2 +- board/xes/xpedite5200/law.c | 2 +- include/asm-ppc/mmu.h | 9 ++------- 15 files changed, 26 insertions(+), 31 deletions(-) diff --git a/board/atum8548/law.c b/board/atum8548/law.c index b70b0910d9e..724b1bf0b69 100644 --- a/board/atum8548/law.c +++ b/board/atum8548/law.c @@ -49,7 +49,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAWAR_SIZE_1M, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1), SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c index 31614d23887..1f11563f5a0 100644 --- a/board/freescale/mpc8536ds/law.c +++ b/board/freescale/mpc8536ds/law.c @@ -31,11 +31,11 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI), SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_2), SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3), + SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3), SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c index f5644e15495..4640c1daf5f 100644 --- a/board/freescale/mpc8540ads/law.c +++ b/board/freescale/mpc8540ads/law.c @@ -52,7 +52,7 @@ struct law_entry law_table[] = { /* This is not so much the SDRAM map as it is the whole localbus map. */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8544ds/law.c b/board/freescale/mpc8544ds/law.c index 317ba2696fb..3d308c8e502 100644 --- a/board/freescale/mpc8544ds/law.c +++ b/board/freescale/mpc8544ds/law.c @@ -30,10 +30,10 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_LBC_NONCACHE_BASE, LAWAR_SIZE_128M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_256M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_LBC_NONCACHE_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2), SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), /* contains both PCIE3 MEM & IO space */ SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_PCIE_3), diff --git a/board/freescale/mpc8560ads/law.c b/board/freescale/mpc8560ads/law.c index f5644e15495..4640c1daf5f 100644 --- a/board/freescale/mpc8560ads/law.c +++ b/board/freescale/mpc8560ads/law.c @@ -52,7 +52,7 @@ struct law_entry law_table[] = { /* This is not so much the SDRAM map as it is the whole localbus map. */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8572ds/law.c b/board/freescale/mpc8572ds/law.c index 02ea0ec59ed..e13bb533661 100644 --- a/board/freescale/mpc8572ds/law.c +++ b/board/freescale/mpc8572ds/law.c @@ -29,11 +29,11 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2), SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3), + SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3), SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), diff --git a/board/freescale/p1_p2_rdb/law.c b/board/freescale/p1_p2_rdb/law.c index 12d2bf478bb..1320d5da041 100644 --- a/board/freescale/p1_p2_rdb/law.c +++ b/board/freescale/p1_p2_rdb/law.c @@ -26,9 +26,9 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2), SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), diff --git a/board/freescale/p2020ds/law.c b/board/freescale/p2020ds/law.c index da297c5ab81..28ed2ed5ee8 100644 --- a/board/freescale/p2020ds/law.c +++ b/board/freescale/p2020ds/law.c @@ -29,11 +29,11 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2), SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3), + SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3), SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), diff --git a/board/pm854/law.c b/board/pm854/law.c index 39e8dbbd532..ac21d7a270e 100644 --- a/board/pm854/law.c +++ b/board/pm854/law.c @@ -52,7 +52,7 @@ struct law_entry law_table[] = { /* This is not so much the SDRAM map as it is the whole localbus map. */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/pm856/law.c b/board/pm856/law.c index 39e8dbbd532..ac21d7a270e 100644 --- a/board/pm856/law.c +++ b/board/pm856/law.c @@ -52,7 +52,7 @@ struct law_entry law_table[] = { /* This is not so much the SDRAM map as it is the whole localbus map. */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/socrates/law.c b/board/socrates/law.c index 71cff8cf0b9..cb55fd43d64 100644 --- a/board/socrates/law.c +++ b/board/socrates/law.c @@ -52,9 +52,9 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), #if defined(CONFIG_SYS_FPGA_BASE) - SET_LAW(CONFIG_SYS_FPGA_BASE, LAWAR_SIZE_1M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif - SET_LAW(CONFIG_SYS_LIME_BASE, LAWAR_SIZE_64M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/stx/stxgp3/law.c b/board/stx/stxgp3/law.c index ba89f0edc0f..af0ac099871 100644 --- a/board/stx/stxgp3/law.c +++ b/board/stx/stxgp3/law.c @@ -52,7 +52,7 @@ struct law_entry law_table[] = { /* This is not so much the SDRAM map as it is the whole localbus map. */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/stx/stxssa/law.c b/board/stx/stxssa/law.c index 55dde667563..e3c34ed87b2 100644 --- a/board/stx/stxssa/law.c +++ b/board/stx/stxssa/law.c @@ -54,7 +54,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), /* Map the whole localbus, including flash and reset latch. */ - SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/xes/xpedite5200/law.c b/board/xes/xpedite5200/law.c index 386f9c5873c..bbfcb9da83c 100644 --- a/board/xes/xpedite5200/law.c +++ b/board/xes/xpedite5200/law.c @@ -40,7 +40,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #if CONFIG_SYS_PCI1_MEM_PHYS SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAWAR_SIZE_8M, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_1), #endif #if CONFIG_SYS_PCI2_MEM_PHYS SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2), diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index a019d0b390b..d516d91403d 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -504,13 +504,7 @@ extern int num_tlb_entries; #endif #endif -#if defined(CONFIG_MPC86xx) -#define LAWBAR_BASE_ADDR 0x00FFFFFF -#define LAWAR_TRGT_IF 0x01F00000 -#else -#define LAWBAR_BASE_ADDR 0x000FFFFF -#define LAWAR_TRGT_IF 0x00F00000 -#endif +#ifdef CONFIG_MPC83xx #define LAWAR_EN 0x80000000 #define LAWAR_SIZE 0x0000003F @@ -554,6 +548,7 @@ extern int num_tlb_entries; #define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22) #define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23) #define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24) +#endif #ifdef CONFIG_440 /* General */ From bd42bbb858dde713f023fc2e4f512ec174a1a8d2 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 18 Sep 2009 19:08:46 -0400 Subject: [PATCH 150/208] sbc8548: replace README with completely new document The previous README.sbc8548 was pretty much content-free. Replace it with something that actually gives the end user some relevant hardware details, and also lists the u-boot configuration choices. Also in the cosmetic department, fix the bogus line in the Makefile that was carried over from the SBC8560 Makefile, and the typo in the sbc8548.c copyright. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/Makefile | 4 +- board/sbc8548/sbc8548.c | 3 +- doc/README.sbc8548 | 189 +++++++++++++++++++++++++++++++++++----- 3 files changed, 173 insertions(+), 23 deletions(-) diff --git a/board/sbc8548/Makefile b/board/sbc8548/Makefile index 9919a6efe08..09e5c2e18bd 100644 --- a/board/sbc8548/Makefile +++ b/board/sbc8548/Makefile @@ -2,8 +2,8 @@ # (C) Copyright 2004-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # -# (C) Copyright 2004 Wind River Systems Inc . -# Added support for Wind River SBC8560 board +# (C) Copyright 2007 Wind River Systems Inc . +# Added support for Wind River SBC8548 board # # See file CREDITS for list of people who contributed to this # project. diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index e5b21b555e9..4192eea8c33 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -1,5 +1,6 @@ /* - * Copyright 2007 Wind River Systemes, Inc. + * Copyright 2007,2009 Wind River Systems, Inc. + * * Copyright 2007 Embedded Specialties, Inc. * * Copyright 2004, 2007 Freescale Semiconductor. diff --git a/doc/README.sbc8548 b/doc/README.sbc8548 index b34d0406cbb..d72d97d027e 100644 --- a/doc/README.sbc8548 +++ b/doc/README.sbc8548 @@ -1,27 +1,176 @@ -Wind River SBC8548 reference board -=========================== +Intro: +====== -Copyright 2007, Embedded Specialties, Inc. -Copyright 2007 Wind River Systemes, Inc. ------------------------------ +The SBC8548 is a stand alone single board computer with a 1GHz +MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz +memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e, +and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC +ethernet connections. -1. Building U-Boot ------------------- -The SBC8548 code is known to build using ELDK 4.1. +U-boot Configuration: +===================== - $ make sbc8548_config - Configuring for sbc8548 board... +The following possible u-boot configuration targets are available: - $ make + 1) sbc8548_config + 2) sbc8548_PCI_33_config + 3) sbc8548_PCI_66_config + 4) sbc8548_PCI_33_PCIE_config + 5) sbc8548_PCI_66_PCIE_config + +Generally speaking, most people should choose to use #5. Details +of each choice are listed below. + +Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot +will be left empty (M66EN high), and so the board will operate with +a base clock of 66MHz. Note that you need both PCI enabled in u-boot +and linux in order to have functional PCI under linux. + +The second enables PCI support and builds for a 33MHz clock rate. Note +that if a 33MHz 32bit card is inserted in the slot, then the whole board +will clock down to a 33MHz base clock instead of the default 66MHz. This +will change the baud clocks and mess up your serial console output if you +were previously running at 66MHz. If you want to use a 33MHz PCI card, +then you should build a U-Boot with a _PCI_33_ config and store this +to flash prior to powering down the board and inserting the 33MHz PCI +card. [The above discussion assumes that the SW2[1-4] has not been changed +to reflect a different CCB:SYSCLK ratio] + +The third option builds PCI support in, and leaves the clocking at the +default 66MHz. Options four and five are just repeats of option two +and three, but with PCI-e support enabled as well. + +PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx +is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with +a 33MHz PCI configuration is currently untested.) + + => pci 0 + Scanning PCI devices on bus 0 + BusDevFun VendorId DeviceId Device Class Sub-Class + _____________________________________________________________ + 00.00.00 0x1057 0x0012 Processor 0x20 + 00.01.00 0x8086 0x1026 Network controller 0x00 + => pci 1 + Scanning PCI devices on bus 1 + BusDevFun VendorId DeviceId Device Class Sub-Class + _____________________________________________________________ + 01.00.00 0x1957 0x0012 Processor 0x20 + => pci 2 + Scanning PCI devices on bus 2 + BusDevFun VendorId DeviceId Device Class Sub-Class + _____________________________________________________________ + 02.00.00 0x1148 0x9e00 Network controller 0x00 + => -2. Switch and Jumper Settings ------------------------------ -All Jumpers & Switches are in their default positions. Please refer to -the board documentation for details. Some settings control CPU voltages -and settings may change with board revisions. +Hardware Reference: +=================== -3. Known limitations --------------------- -PCI: - The code to support PCI is currently disabled and has not been verified. +The following contains some summary information on hardware settings +that are relevant to u-boot, based on the board manual. For the +most up to date and complete details of the board, please request the +reference manual ERG-00327-001.pdf from www.windriver.com + +Boot flash: + intel V28F640Jx, 8192x8 (one device) at 0xff80_0000 + +Sodimm flash: + intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000 + + + Jumpers: + +Jumper Name ON OFF +---------------------------------------------------------------- +JP12 CS0/CS6 swap see note[*] see note[*] + +JP13 SODIMM flash write OK writes disabled + write prot. + +JP14 HRESET/TRST joined isolated + +JP15 PWR ON when AC pwr use S1 for on/off + +JP16 Demo LEDs lit not lit + +JP19 PCI mode PCI PCI-X + + +[*]JP12, when jumpered parallel to the SODIMM, puts the boot flash +onto /CS0 and the SODIMM flash on /CS6 (default). When JP12 +is jumpered parallel to the LBC-SDRAM, then /CS0 is for the +SODIMM flash and /CS6 is for the boot flash. Note that in this +alternate setting, you also need to switch SW2.8 to ON. Currently +u-boot doesn't support booting off the SODIMM in this alternate +setting without manually altering BR0/OR0 and BR6/OR6 in the +board config file appropriately. + + + Switches: + +The defaults are marked with a * + +Name Desc. ON OFF +------------------------------------------------------------------ +S1 Pwr toggle n/a n/a + +SW2.1 CFG_SYS_PLL0 1 0* +SW2.2 CFG_SYS_PLL1 1* 0 +SW2.3 CFG_SYS_PLL2 1* 0 +SW2.4 CFG_SYS_PLL3 1 0* +SW2.5 CFG_CORE_PLL0 1* 0 +SW2.6 CFG_CORE_PLL1 1 0* +SW2.7 CFG_CORE_PLL2 1* 0 +SW2.8 CFG_ROM_LOC1 1 0* + +SW3.1 CFG_HOST_AGT0 1* 0 +SW3.2 CFG_HOST_AGT1 1* 0 +SW3.3 CFG_HOST_AGT2 1* 0 +SW3.4 CFG_IO_PORTS0 1* 0 +SW3.5 CFG_IO_PORTS0 1 0* +SW3.6 CFG_IO_PORTS0 1 0* + +SerDes CLK(MHz) SW5.1 SW5.2 +---------------------------------------------- +25 0 0 +100* 1 0 +125 0 1 +200 1 1 + +SerDes CLK spread SW5.3 SW5.4 +---------------------------------------------- ++/- 0.25% 0 0 +-0.50% 1 0 +-0.75% 0 1 +No Spread* 1 1 + +SW4 settings are readable from the EPLD and are currently not used for +any hardware settings (i.e. user configuration switches). + + LEDs: + +Name Desc. ON OFF +------------------------------------------------------------------ +D13 PCI/PCI-X PCI-X PCI +D14 3.3V PWR 3.3V no power +D15 SYSCLK 66MHz 33MHz + + + Default Memory Map: + +start end CS width Desc. +---------------------------------------------------------------------- +0000_0000 0fff_ffff MCS0,1 64 DDR2 (256MB) +f000_0000 f7ff_ffff CS3,4 32 LB SDRAM (128MB) +f800_0000 f8b0_1fff CS5 - EPLD +fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB) +ff80_0000 ffff_ffff CS0 8 Boot flash (8MB) + +The EPLD on CS5 demuxes the following devices at the following offsets: + +offset size width device +-------------------------------------------------------- +0 1fff 8 7 segment display LED +10_0000 1fff 4 user switches +30_0000 1fff 4 HW Rev. register +b0_0000 1fff 8 8kB EEPROM From 82b7725b6d46d9ad2b962b4cdfa896bd5ee32fb5 Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Sat, 19 Sep 2009 17:50:17 +0530 Subject: [PATCH 151/208] ppc/85xx: 32bit DDR changes for P1020/P1011 The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/P2010 where max DDR data width supported is 64bit. As a next step the DDR data width initialization would be made more dynamic with more flexibility from the board perspective and user choice. Going forward we would also remove the hardcodings for platforms with onboard memories and try to use the FSL SPD code for DDR initialization. Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- board/freescale/p1_p2_rdb/ddr.c | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index d1e659b46b0..37c4b0a3ba9 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -23,10 +23,13 @@ #include #include #include +#include #include #include #include +DECLARE_GLOBAL_DATA_PTR; + extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num); @@ -203,24 +206,40 @@ phys_size_t fixed_sdram (void) { sys_info_t sysinfo; char buf[32]; + fsl_ddr_cfg_regs_t *ddr_cfg_regs = NULL; + size_t ddr_size; + struct cpu_type *cpu; get_sys_info(&sysinfo); printf("Configuring DDR for %s MT/s data rate\n", strmhz(buf, sysinfo.freqDDRBus)); if(sysinfo.freqDDRBus <= DATARATE_400MHZ) - fsl_ddr_set_memctl_regs(&ddr_cfg_regs_400, 0); + ddr_cfg_regs = &ddr_cfg_regs_400; else if(sysinfo.freqDDRBus <= DATARATE_533MHZ) - fsl_ddr_set_memctl_regs(&ddr_cfg_regs_533, 0); + ddr_cfg_regs = &ddr_cfg_regs_533; else if(sysinfo.freqDDRBus <= DATARATE_667MHZ) - fsl_ddr_set_memctl_regs(&ddr_cfg_regs_667, 0); + ddr_cfg_regs = &ddr_cfg_regs_667; else if(sysinfo.freqDDRBus <= DATARATE_800MHZ) - fsl_ddr_set_memctl_regs(&ddr_cfg_regs_800, 0); + ddr_cfg_regs = &ddr_cfg_regs_800; else panic("Unsupported DDR data rate %s MT/s data rate\n", strmhz(buf, sysinfo.freqDDRBus)); - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + cpu = gd->cpu; + /* P1020 and it's derivatives support max 32bit DDR width */ + if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E || + cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) { + ddr_cfg_regs->ddr_sdram_cfg |= SDRAM_CFG_32_BE; + ddr_cfg_regs->cs[0].bnds = 0x0000001F; + ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2); + } + else + ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + + fsl_ddr_set_memctl_regs(ddr_cfg_regs, 0); + + return ddr_size; } phys_size_t initdram(int board_type) From 94ca091456d5c3040ddd6351c80cf3e74393f9be Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 18 Sep 2009 19:08:44 -0400 Subject: [PATCH 152/208] sbc8548: enable use of PCI network cards Create a board_eth_init to allow a place to hook in the PCI ethernet init after all the eTSEC are up and configured. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/sbc8548.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 4192eea8c33..fc78a7c6a15 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -33,6 +33,8 @@ #include #include #include +#include +#include #include #include #include @@ -491,6 +493,13 @@ pci_init_board(void) } +int board_eth_init(bd_t *bis) +{ + tsec_standard_init(bis); + pci_eth_init(bis); + return 0; /* otherwise cpu_eth_init gets run */ +} + int last_stage_init(void) { return 0; From 7b1f1399e876587e0a268a5a471dd444bfbc3114 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 18 Sep 2009 19:08:39 -0400 Subject: [PATCH 153/208] sbc8548: delete unused MPC8548CDS info carried over from port There are a couple defines and PCI bridge quirks related to the PCI backplane of the MPC8548CDS that have no meaning in the context of the port to the sbc8548 board, so delete them. Also, the form factor of the sbc8548 is a standalone board with a single PCI-X and a single PCI-e slot. That pretty much guarantees that it will never be a PCI agent itself, so the host/agent and root complex/end node distinctions have been removed. Similarly, since there is no physical connector mapping to PCI2, so all references of PCI2 in the board support files have been removed as well. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/sbc8548.c | 63 ++++----------------------------------- include/configs/sbc8548.h | 9 ------ 2 files changed, 6 insertions(+), 66 deletions(-) diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index fc78a7c6a15..fff7dab9829 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -314,35 +314,9 @@ long int fixed_sdram (void) } #endif -#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) -/* For some reason the Tundra PCI bridge shows up on itself as a - * different device. Work around that by refusing to configure it. - */ -void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } - -static struct pci_config_table pci_sbc8548_config_table[] = { - {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, - {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, - {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, - mpc85xx_config_via_usbide, {0,0,0}}, - {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, - mpc85xx_config_via_usb, {0,0,0}}, - {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, - mpc85xx_config_via_usb2, {0,0,0}}, - {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, - mpc85xx_config_via_power, {0,0,0}}, - {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, - mpc85xx_config_via_ac97, {0,0,0}}, - {}, -}; - -static struct pci_controller pci1_hose = { - config_table: pci_sbc8548_config_table}; -#endif /* CONFIG_PCI */ - -#ifdef CONFIG_PCI2 -static struct pci_controller pci2_hose; -#endif /* CONFIG_PCI2 */ +#ifdef CONFIG_PCI1 +static struct pci_controller pci1_hose; +#endif /* CONFIG_PCI1 */ #ifdef CONFIG_PCIE1 static struct pci_controller pcie1_hose; @@ -359,24 +333,20 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; - struct pci_config_table *table; struct pci_region *r = hose->regions; uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ - uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); - uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { - printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", + printf (" PCI host: %d bit, %s MHz, %s, %s\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", - pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter" ); @@ -395,12 +365,6 @@ pci_init_board(void) PCI_REGION_IO); hose->region_count = r - hose->regions; - /* relocate config table pointers */ - hose->config_table = \ - (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off); - for (table = hose->config_table; table && table->vendor; table++) - table->config_device += gd->reloc_off; - hose->first_busno=first_free_busno; fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); @@ -425,33 +389,18 @@ pci_init_board(void) gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ #endif -#ifdef CONFIG_PCI2 -{ - uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ - uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ - if (pci_dual) { - printf (" PCI2: 32 bit, 66 MHz, %s\n", - pci2_clk_sel ? "sync" : "async"); - } else { - printf (" PCI2: disabled\n"); - } -} -#else - gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */ -#endif /* CONFIG_PCI2 */ + gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable PCI2 */ #ifdef CONFIG_PCIE1 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); struct pci_region *r = hose->regions; int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE connected to slot as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", + printf ("\n PCIE at base address %x", (uint)pci); if (pci->pme_msg_det) { diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 838b4db9ad4..3d05afbba16 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -42,7 +42,6 @@ #undef CONFIG_PCI1 /* PCI controller 1 */ #undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ #undef CONFIG_RIO -#undef CONFIG_PCI2 #undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ @@ -343,14 +342,6 @@ #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ #endif -#ifdef CONFIG_LEGACY -#define BRIDGE_ID 17 -#define VIA_ID 2 -#else -#define BRIDGE_ID 28 -#define VIA_ID 4 -#endif - #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI From 2c40acd3525b75db3fcd3f5a5bd40445679b5547 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 18 Sep 2009 19:08:40 -0400 Subject: [PATCH 154/208] sbc8548: get_clock_freq is not valid for this board The get_clock_freq() comes from freescale/common/cadmus.c and is only valid for the CDS based 85xx reference platforms. It would be nice if we could read the 33 vs. 66MHz status somehow, but in the meantime, tie it to CONFIG_SYS_CLK_FREQ like all the other non-CDS boards do. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/sbc8548.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index fff7dab9829..031658107ec 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -339,13 +339,13 @@ pci_init_board(void) uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ - uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ + uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */ if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { printf (" PCI host: %d bit, %s MHz, %s, %s\n", (pci_32) ? 32 : 64, - (pci_speed == 33333000) ? "33" : - (pci_speed == 66666000) ? "66" : "unknown", + (pci_speed == 33000000) ? "33" : + (pci_speed == 66000000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_arb ? "arbiter" : "external-arbiter" ); From ded58f4153923dfff16d2f96495bd7acf1f7e10e Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Wed, 23 Sep 2009 17:30:57 -0400 Subject: [PATCH 155/208] sbc8548: cosmetic line re-wrap Fix the extra long lines to be consistent with u-boot coding style. No functional change here. Signed-off-by: Paul Gortmaker --- board/sbc8548/tlb.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index 18d11f6dc76..ddcb532eefd 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -31,13 +31,16 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -62,7 +65,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), From 9b3ba24f18900633a394416cc056c44a1a6eb754 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 18 Sep 2009 19:08:41 -0400 Subject: [PATCH 156/208] sbc8548: enable access to second bank of flash The sbc8548 has a 64MB SODIMM flash module off of CS6 that previously wasn't enumerated by u-boot. There were already BR6/OR6 settings for it [used by cpu_init_f()] but there was no TLB entry and it wasn't in the list of flash banks reported to u-boot. The location of the 64MB flash is "pulled back" 8MB from a 64MB boundary, in order to allow address space for the 8MB boot flash that is at the end of 32 bit address space. This means creating two 4MB TLB entries for the 8MB chunk, and then expanding the original boot flash entry to 64MB in order to cover the 8MB boot flash and the remainder (56MB) of the user flash. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/tlb.c | 28 ++++++++++++++++++++++++---- include/configs/sbc8548.h | 8 +++++--- 2 files changed, 29 insertions(+), 7 deletions(-) diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index ddcb532eefd..a0b4e36e7b0 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -45,13 +45,15 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 0, BOOKE_PAGESZ_4K, 0), /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff800000 16M TLB for 8MB FLASH + * TLB 0: 64M Non-cacheable, guarded + * 0xfc000000 56M 8MB -> 64MB of user flash + * 0xff800000 8M boot FLASH * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x800000, + CONFIG_SYS_ALT_FLASH + 0x800000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), + 0, 0, BOOKE_PAGESZ_64M, 1), /* * TLB 1: 256M Non-cacheable, guarded @@ -107,6 +109,24 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_16M, 1), + + /* + * TLB 7: 4M Non-cacheable, guarded + * 0xfb800000 4M 1st 4MB block of 64MB user FLASH + */ + SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_4M, 1), + + /* + * TLB 8: 4M Non-cacheable, guarded + * 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH + */ + SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, + CONFIG_SYS_ALT_FLASH + 0x400000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_4M, 1), + }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 3d05afbba16..5c1411f6689 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -163,6 +163,7 @@ */ #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ +#define CONFIG_SYS_ALT_FLASH 0xfb800000 /* 64MB "user" flash */ #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ #define CONFIG_SYS_BR0_PRELIM 0xff800801 @@ -171,9 +172,10 @@ #define CONFIG_SYS_OR0_PRELIM 0xff806e65 #define CONFIG_SYS_OR6_PRELIM 0xf8006e65 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_ALT_FLASH} +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ #undef CONFIG_SYS_FLASH_CHECKSUM #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ From fc38eb98ff226f2c53eecbee033a6ab7619473dc Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Sun, 20 Sep 2009 20:36:02 -0400 Subject: [PATCH 157/208] sbc8548: remove eTSEC3/4 voltage hack With only eTSEC1 and 2 being brought out to RJ-45 connectors, we aren't interested in the eTSEC3/4 voltage hack on this board Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/sbc8548.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 031658107ec..96a5f421af2 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -52,7 +52,6 @@ int board_early_init_f (void) int checkboard (void) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); volatile u_char *rev= (void *)CONFIG_SYS_BD_REV; @@ -64,11 +63,6 @@ int checkboard (void) */ local_bus_init (); - /* - * Hack TSEC 3 and 4 IO voltages. - */ - gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ - ecm->eedr = 0xffffffff; /* clear ecm errors */ ecm->eeer = 0xffffffff; /* enable ecm errors */ return 0; From 0c7e4d45d9fb3c9e503ee93d50572d346dae150e Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Sun, 20 Sep 2009 20:36:03 -0400 Subject: [PATCH 158/208] sbc8548: use I/O accessors Sweep throught the board specific file and replace the various register proddings with the equivalent I/O accessors. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/sbc8548.c | 91 ++++++++++++++++++++--------------------- 1 file changed, 45 insertions(+), 46 deletions(-) diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 96a5f421af2..ce998e1c2f9 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -56,15 +56,15 @@ int checkboard (void) volatile u_char *rev= (void *)CONFIG_SYS_BD_REV; printf ("Board: Wind River SBC8548 Rev. 0x%01x\n", - (*rev) >> 4); + in_8(rev) >> 4); /* * Initialize local bus. */ local_bus_init (); - ecm->eedr = 0xffffffff; /* clear ecm errors */ - ecm->eeer = 0xffffffff; /* enable ecm errors */ + out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */ + out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */ return 0; } @@ -86,7 +86,7 @@ initdram(int board_type) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - gur->ddrdllcr = 0x81000000; + out_be32(&gur->ddrdllcr, 0x81000000); asm("sync;isync;msync"); udelay(200); } @@ -123,24 +123,24 @@ local_bus_init(void) sys_info_t sysinfo; get_sys_info(&sysinfo); - clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; + clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; - gur->lbiuiplldcr1 = 0x00078080; + out_be32(&gur->lbiuiplldcr1, 0x00078080); if (clkdiv == 16) { - gur->lbiuiplldcr0 = 0x7c0f1bf0; + out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0); } else if (clkdiv == 8) { - gur->lbiuiplldcr0 = 0x6c0f1bf0; + out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0); } else if (clkdiv == 4) { - gur->lbiuiplldcr0 = 0x5c0f1bf0; + out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0); } - lbc->lcrr |= 0x00030000; + setbits_be32(&lbc->lcrr, 0x00030000); asm("sync;isync;msync"); - lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ - lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ + out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */ + out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */ } /* @@ -163,18 +163,18 @@ sdram_init(void) /* * Setup SDRAM Base and Option Registers */ - lbc->or3 = CONFIG_SYS_OR3_PRELIM; + out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM); asm("msync"); - lbc->br3 = CONFIG_SYS_BR3_PRELIM; + out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM); asm("msync"); - lbc->lbcr = CONFIG_SYS_LBC_LBCR; + out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); asm("msync"); - lbc->lsrt = CONFIG_SYS_LBC_LSRT; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; + out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT); + out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); asm("msync"); /* @@ -186,7 +186,7 @@ sdram_init(void) /* * Issue PRECHARGE ALL command. */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; + out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_PCHALL); asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -196,7 +196,7 @@ sdram_init(void) * Issue 8 AUTO REFRESH commands. */ for (idx = 0; idx < 8; idx++) { - lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; + out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_ARFRSH); asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -206,7 +206,7 @@ sdram_init(void) /* * Issue 8 MODE-set command. */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; + out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_MRW); asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -215,7 +215,7 @@ sdram_init(void) /* * Issue NORMAL OP command. */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; + out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_NORMAL); asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -263,45 +263,44 @@ testdram(void) } #endif -#if !defined(CONFIG_SPD_EEPROM) +#if !defined(CONFIG_SPD_EEPROM) +#define CONFIG_SYS_DDR_CONTROL 0xc300c000 /************************************************************************* * fixed_sdram init -- doesn't use serial presence detect. * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. ************************************************************************/ long int fixed_sdram (void) { - #define CONFIG_SYS_DDR_CONTROL 0xc300c000 - volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); - ddr->cs0_bnds = 0x0000007f; - ddr->cs1_bnds = 0x008000ff; - ddr->cs2_bnds = 0x00000000; - ddr->cs3_bnds = 0x00000000; - ddr->cs0_config = 0x80010101; - ddr->cs1_config = 0x80010101; - ddr->cs2_config = 0x00000000; - ddr->cs3_config = 0x00000000; - ddr->timing_cfg_3 = 0x00000000; - ddr->timing_cfg_0 = 0x00220802; - ddr->timing_cfg_1 = 0x38377322; - ddr->timing_cfg_2 = 0x0fa044C7; - ddr->sdram_cfg = 0x4300C000; - ddr->sdram_cfg_2 = 0x24401000; - ddr->sdram_mode = 0x23C00542; - ddr->sdram_mode_2 = 0x00000000; - ddr->sdram_interval = 0x05080100; - ddr->sdram_md_cntl = 0x00000000; - ddr->sdram_data_init = 0x00000000; - ddr->sdram_clk_cntl = 0x03800000; + out_be32(&ddr->cs0_bnds, 0x0000007f); + out_be32(&ddr->cs1_bnds, 0x008000ff); + out_be32(&ddr->cs2_bnds, 0x00000000); + out_be32(&ddr->cs3_bnds, 0x00000000); + out_be32(&ddr->cs0_config, 0x80010101); + out_be32(&ddr->cs1_config, 0x80010101); + out_be32(&ddr->cs2_config, 0x00000000); + out_be32(&ddr->cs3_config, 0x00000000); + out_be32(&ddr->timing_cfg_3, 0x00000000); + out_be32(&ddr->timing_cfg_0, 0x00220802); + out_be32(&ddr->timing_cfg_1, 0x38377322); + out_be32(&ddr->timing_cfg_2, 0x0fa044C7); + out_be32(&ddr->sdram_cfg, 0x4300C000); + out_be32(&ddr->sdram_cfg_2, 0x24401000); + out_be32(&ddr->sdram_mode, 0x23C00542); + out_be32(&ddr->sdram_mode_2, 0x00000000); + out_be32(&ddr->sdram_interval, 0x05080100); + out_be32(&ddr->sdram_md_cntl, 0x00000000); + out_be32(&ddr->sdram_data_init, 0x00000000); + out_be32(&ddr->sdram_clk_cntl, 0x03800000); asm("sync;isync;msync"); udelay(500); #if defined (CONFIG_DDR_ECC) /* Enable ECC checking */ - ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); + out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000); #else - ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; + out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); #endif return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; From 11d5a629f8a40f9d7cffc74e58f4e3ed258e56ab Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Sun, 20 Sep 2009 20:36:04 -0400 Subject: [PATCH 159/208] sbc8548: correct local bus SDRAM size from 64M to 128M The size of the LB SDRAM on this board is 128MB, spanning CS3 and CS4. It was previously only being configured for 64MB on CS3, since that was what the original codebase of the MPC8548CDS had. In addition to setting up BR4/OR4, this also adds the TLB entry for the second half of the SDRAM. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/sbc8548.c | 8 +++++++- board/sbc8548/tlb.c | 23 ++++++++++++++------- include/configs/sbc8548.h | 42 +++++++++++++++++++++++++++++++++++---- 3 files changed, 61 insertions(+), 12 deletions(-) diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index ce998e1c2f9..f4bfd925af6 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -149,7 +149,7 @@ local_bus_init(void) void sdram_init(void) { -#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) +#if defined(CONFIG_SYS_LBC_SDRAM_SIZE) uint idx; volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); @@ -169,6 +169,12 @@ sdram_init(void) out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM); asm("msync"); + out_be32(&lbc->or4, CONFIG_SYS_OR4_PRELIM); + asm("msync"); + + out_be32(&lbc->br4, CONFIG_SYS_BR4_PRELIM); + asm("msync"); + out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); asm("msync"); diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index a0b4e36e7b0..a1795fcfb28 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -93,14 +93,23 @@ struct fsl_e_tlb_entry tlb_table[] = { /* * TLB 5: 64M Cacheable, non-guarded - * 0xf0000000 64M LBC SDRAM + * 0xf0000000 64M LBC SDRAM First half */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 5, BOOKE_PAGESZ_64M, 1), /* - * TLB 6: 16M Cacheable, non-guarded + * TLB 6: 64M Cacheable, non-guarded + * 0xf4000000 64M LBC SDRAM Second half + */ + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, + CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 7: 16M Cacheable, non-guarded * 0xf8000000 1M 7-segment LED display * 0xf8100000 1M User switches * 0xf8300000 1M Board revision @@ -108,24 +117,24 @@ struct fsl_e_tlb_entry tlb_table[] = { */ SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_16M, 1), + 0, 7, BOOKE_PAGESZ_16M, 1), /* - * TLB 7: 4M Non-cacheable, guarded + * TLB 8: 4M Non-cacheable, guarded * 0xfb800000 4M 1st 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_4M, 1), + 0, 8, BOOKE_PAGESZ_4M, 1), /* - * TLB 8: 4M Non-cacheable, guarded + * TLB 9: 4M Non-cacheable, guarded * 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, CONFIG_SYS_ALT_FLASH + 0x400000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_4M, 1), + 0, 9, BOOKE_PAGESZ_4M, 1), }; diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 5c1411f6689..009931df55c 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -197,13 +197,13 @@ #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 /* - * SDRAM on the Local Bus + * SDRAM on the Local Bus (CS3 and CS4) */ #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ +#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ /* - * Base Register 3 and Option Register 3 configure SDRAM. + * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. * * For BR3, need: @@ -221,7 +221,7 @@ #define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. * * For OR3, need: * 64MB mask for AM, OR3[0:7] = 1111 1100 @@ -236,6 +236,40 @@ #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 +/* + * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. + * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. + * + * For BR4, need: + * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 + * + */ + +#define CONFIG_SYS_BR4_PRELIM 0xf4001861 + +/* + * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * + * For OR4, need: + * 64MB mask for AM, OR3[0:7] = 1111 1100 + * XAM, OR3[17:18] = 11 + * 10 columns OR3[19-21] = 011 + * 12 rows OR3[23-25] = 011 + * EAD set for extra time OR[31] = 0 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 + */ + +#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 + #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ From a8b3e90f798e0cca5f11c912f9d0823a1c5b6c24 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Sun, 20 Sep 2009 20:36:01 -0400 Subject: [PATCH 160/208] fsl_pci: create a SET_STD_PCI_INFO() helper wrapper Recycle the recently added PCI-e wrapper used to reduce board duplication of code by creating a similar version for plain PCI. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- include/asm-ppc/fsl_pci.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/asm-ppc/fsl_pci.h b/include/asm-ppc/fsl_pci.h index b9972dabe37..2790da7ed16 100644 --- a/include/asm-ppc/fsl_pci.h +++ b/include/asm-ppc/fsl_pci.h @@ -173,6 +173,18 @@ struct fsl_pci_info { int fsl_pci_init_port(struct fsl_pci_info *pci_info, struct pci_controller *hose, int busno); +#define SET_STD_PCI_INFO(x, num) \ +{ \ + x.regs = CONFIG_SYS_PCI##num##_ADDR; \ + x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \ + x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \ + x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \ + x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \ + x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \ + x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \ + x.pci_num = num; \ +} + #define SET_STD_PCIE_INFO(x, num) \ { \ x.regs = CONFIG_SYS_PCIE##num##_ADDR; \ From fdc7eb90b504daa020f290604d50da8f7cb70d8a Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Sun, 20 Sep 2009 20:36:05 -0400 Subject: [PATCH 161/208] sbc8548: update PCI/PCI-e support code The PCI/PCI-e support for the sbc8548 was based on an earlier version of what the MPC8548CDS board was using, and in its current state it won't even compile. This re-syncs it to match the latest codebase and makes use of the new shared PCI functions to reduce board duplication. It borrows from the MPC8568MDS, in that it pulls the PCI-e I/O back to 0xe280_0000 (where PCI2 would be on MPC8548CDS), and similarly it coalesces the PCI and PCI-e mem into one single TLB. Both PCI-x and PCI-e have been tested with intel e1000 cards under linux (with an accompanying dts change in place) Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/law.c | 12 +++- board/sbc8548/sbc8548.c | 131 ++++++++++++-------------------------- board/sbc8548/tlb.c | 53 +++++++-------- include/configs/sbc8548.h | 45 +++++++------ 4 files changed, 97 insertions(+), 144 deletions(-) diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c index e8c7ae2a2ee..6d1efc0c69e 100644 --- a/board/sbc8548/law.c +++ b/board/sbc8548/law.c @@ -32,8 +32,10 @@ * * 0x0000_0000 0x0fff_ffff DDR 256M * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCIe MEM 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xe200_0000 0xe27f_ffff PCI1 IO 8M + * 0xe280_0000 0xe2ff_ffff PCIe IO 8M * 0xf000_0000 0xf7ff_ffff SDRAM 128M * 0xf8b0_0000 0xf80f_ffff EEPROM 1M * 0xfb80_0000 0xff7f_ffff FLASH (2nd bank) 64M @@ -48,8 +50,14 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif +#ifdef CONFIG_SYS_PCI1_MEM_PHYS SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI), +#endif +#ifdef CONFIG_SYS_PCIE1_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), +#endif /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index f4bfd925af6..194f6ab961f 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -321,125 +321,74 @@ static struct pci_controller pci1_hose; static struct pci_controller pcie1_hose; #endif /* CONFIG_PCIE1 */ -int first_free_busno=0; +#ifdef CONFIG_PCI void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + struct fsl_pci_info pci_info[2]; + u32 devdisr, pordevsr, porpllsr, io_sel; + int first_free_busno = 0; + int num = 0; + +#ifdef CONFIG_PCIE1 + int pcie_configured; +#endif + + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + porpllsr = in_be32(&gur->porpllsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + + debug(" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); #ifdef CONFIG_PCI1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; - struct pci_controller *hose = &pci1_hose; - struct pci_region *r = hose->regions; + if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { + uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; + uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; + uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; + uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */ - uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ - uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ - uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ - - uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */ - - if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { printf (" PCI host: %d bit, %s MHz, %s, %s\n", (pci_32) ? 32 : 64, (pci_speed == 33000000) ? "33" : (pci_speed == 66000000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", - pci_arb ? "arbiter" : "external-arbiter" - ); + pci_arb ? "arbiter" : "external-arbiter"); - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BASE, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, - PCI_REGION_IO); - hose->region_count = r - hose->regions; - - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno=hose->last_busno+1; - printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); -#ifdef CONFIG_PCIX_CHECK - if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) { - /* PCI-X init */ - if (CONFIG_SYS_CLK_FREQ < 66000000) - printf("PCI-X will only work at 66 MHz\n"); - - reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ - | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; - pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); - } -#endif + SET_STD_PCI_INFO(pci_info[num], 1); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pci1_hose, first_free_busno); } else { printf (" PCI: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ #endif - gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable PCI2 */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */ #ifdef CONFIG_PCIE1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - struct pci_controller *hose = &pcie1_hose; - struct pci_region *r = hose->regions; - - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - - if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE at base address %x", - (uint)pci); - - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BASE, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); - - first_free_busno=hose->last_busno+1; + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + SET_STD_PCIE_INFO(pci_info[num], 1); + printf (" PCIE at base address %lx\n", pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); } else { printf (" PCIE: disabled\n"); } - } -#else - gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ -#endif + puts("\n"); +#else + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ +#endif } +#endif int board_eth_init(bd_t *bis) { diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index a1795fcfb28..38bdeb37c30 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -56,60 +56,53 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 0, BOOKE_PAGESZ_64M, 1), /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half + * TLB 1: 1G Non-cacheable, guarded + * 0x80000000 512M PCI1 MEM + * 0xa0000000 512M PCIe MEM */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), + 0, 1, BOOKE_PAGESZ_1G, 1), /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Cacheable, non-guarded + * TLB 2: 256M Cacheable, non-guarded * 0x0 256M DDR SDRAM */ - #if !defined(CONFIG_SPD_EEPROM) +#if !defined(CONFIG_SPD_EEPROM) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 3, BOOKE_PAGESZ_256M, 1), - #endif + 0, 2, BOOKE_PAGESZ_256M, 1), +#endif /* - * TLB 4: 64M Non-cacheable, guarded + * TLB 3: 64M Non-cacheable, guarded * 0xe0000000 1M CCSRBAR - * 0xe2000000 16M PCI1 IO + * 0xe2000000 8M PCI1 IO + * 0xe2800000 8M PCIe IO */ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_64M, 1), + 0, 3, BOOKE_PAGESZ_64M, 1), /* - * TLB 5: 64M Cacheable, non-guarded + * TLB 4: 64M Cacheable, non-guarded * 0xf0000000 64M LBC SDRAM First half */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 5, BOOKE_PAGESZ_64M, 1), + 0, 4, BOOKE_PAGESZ_64M, 1), /* - * TLB 6: 64M Cacheable, non-guarded + * TLB 5: 64M Cacheable, non-guarded * 0xf4000000 64M LBC SDRAM Second half */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 6, BOOKE_PAGESZ_64M, 1), + 0, 5, BOOKE_PAGESZ_64M, 1), /* - * TLB 7: 16M Cacheable, non-guarded + * TLB 6: 16M Cacheable, non-guarded * 0xf8000000 1M 7-segment LED display * 0xf8100000 1M User switches * 0xf8300000 1M Board revision @@ -117,24 +110,24 @@ struct fsl_e_tlb_entry tlb_table[] = { */ SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_16M, 1), + 0, 6, BOOKE_PAGESZ_16M, 1), /* - * TLB 8: 4M Non-cacheable, guarded + * TLB 7: 4M Non-cacheable, guarded * 0xfb800000 4M 1st 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_4M, 1), + 0, 7, BOOKE_PAGESZ_4M, 1), /* - * TLB 9: 4M Non-cacheable, guarded + * TLB 8: 4M Non-cacheable, guarded * 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, CONFIG_SYS_ALT_FLASH + 0x400000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 9, BOOKE_PAGESZ_4M, 1), + 0, 8, BOOKE_PAGESZ_4M, 1), }; diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 009931df55c..1f340ed7fba 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -42,7 +42,14 @@ #undef CONFIG_PCI1 /* PCI controller 1 */ #undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ #undef CONFIG_RIO -#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */ + +#ifdef CONFIG_PCI +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#endif +#ifdef CONFIG_PCIE1 +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ +#endif #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE @@ -343,31 +350,27 @@ * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ +#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#ifdef CONFIG_PCI2 -#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE -#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ -#endif +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ #endif #ifdef CONFIG_RIO @@ -386,7 +389,7 @@ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ From 2738bc8df65ec905094d83f62f87fed123a03b9c Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Sun, 20 Sep 2009 20:36:06 -0400 Subject: [PATCH 162/208] sbc8548: allow enabling PCI via a make config option Prior to this commit, to enable PCI, you had to go manually edit the board config header, and if you had 33MHz PCI, you had to manually change CONFIG_SYS_NS16550_CLK too, which was not real user friendly, This adds the typical PCI and clock speed make targets to the toplevel Makefile in accordance with what is being done with other boards (i.e. using the "-t" to mkconfig). Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- MAKEALL | 4 ++++ Makefile | 8 ++++++-- include/configs/sbc8548.h | 43 ++++++++++++++++++++++++++++++--------- 3 files changed, 43 insertions(+), 12 deletions(-) diff --git a/MAKEALL b/MAKEALL index 1d50c343039..b394adbef78 100755 --- a/MAKEALL +++ b/MAKEALL @@ -399,6 +399,10 @@ LIST_85xx=" \ PM856 \ sbc8540 \ sbc8548 \ + sbc8548_PCI_33 \ + sbc8548_PCI_66 \ + sbc8548_PCI_33_PCIE \ + sbc8548_PCI_66_PCIE \ sbc8560 \ socrates \ stxgp3 \ diff --git a/Makefile b/Makefile index d8daa89502e..55ee25d8ab1 100644 --- a/Makefile +++ b/Makefile @@ -2544,8 +2544,12 @@ sbc8540_66_config: unconfig fi @$(MKCONFIG) -a SBC8540 ppc mpc85xx sbc8560 -sbc8548_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx sbc8548 +sbc8548_config \ +sbc8548_PCI_33_config \ +sbc8548_PCI_66_config \ +sbc8548_PCI_33_PCIE_config \ +sbc8548_PCI_66_PCIE_config: unconfig + @$(MKCONFIG) -t $(@:_config=) sbc8548 ppc mpc85xx sbc8548 sbc8560_config \ sbc8560_33_config \ diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 1f340ed7fba..d10792a22da 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -1,5 +1,5 @@ /* - * Copyright 2007 Wind River Systems + * Copyright 2007,2009 Wind River Systems * Copyright 2007 Embedded Specialties, Inc. * Copyright 2004, 2007 Freescale Semiconductor. * @@ -24,23 +24,40 @@ /* * sbc8548 board configuration file - * - * Please refer to doc/README.sbc85xx for more info. - * + * Please refer to doc/README.sbc8548 for more info. */ #ifndef __CONFIG_H #define __CONFIG_H -/* High Level Configuration Options */ +/* + * Top level Makefile configuration choices + */ +#ifdef CONFIG_MK_PCI +#define CONFIG_PCI +#define CONFIG_PCI1 +#endif + +#ifdef CONFIG_MK_66 +#define CONFIG_SYS_CLK_DIV 1 +#endif + +#ifdef CONFIG_MK_33 +#define CONFIG_SYS_CLK_DIV 2 +#endif + +#ifdef CONFIG_MK_PCIE +#define CONFIG_PCIE1 +#endif + +/* + * High Level Configuration Options + */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ #define CONFIG_MPC8548 1 /* MPC8548 specific */ #define CONFIG_SBC8548 1 /* SBC8548 board specific */ -#undef CONFIG_PCI /* enable any pci type devices */ -#undef CONFIG_PCI1 /* PCI controller 1 */ -#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ #undef CONFIG_RIO #ifdef CONFIG_PCI @@ -58,7 +75,13 @@ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_SYS_CLK_FREQ 66000000 /* SBC8548 default SYSCLK */ +/* + * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] + */ +#ifndef CONFIG_SYS_CLK_DIV +#define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ +#endif +#define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV) /* * These can be toggled for performance analysis, otherwise use default. @@ -316,7 +339,7 @@ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK 400000000 /* get_bus_freq(0) */ +#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} From 928435d11b898870415910efff87a4d6399cecb8 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Mon, 21 Sep 2009 17:19:17 -0400 Subject: [PATCH 163/208] sbc85x0: tidy up Makefile to use new configuration script. Commit 804d83a5 allows us to move all the configuration variation tweaks out of the top level Makefile and down into the boards config header. This takes advantage of that for the sbc8540/sbc8560 boards. There were a couple of cheezy comments pointing at incorrect files, or files that don't exist, so I've cleaned those up too. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- Makefile | 18 ++---------------- include/configs/SBC8540.h | 19 +++++++++++-------- include/configs/sbc8560.h | 17 ++++++++++++----- 3 files changed, 25 insertions(+), 29 deletions(-) diff --git a/Makefile b/Makefile index 55ee25d8ab1..9c5b2a5c9a3 100644 --- a/Makefile +++ b/Makefile @@ -2535,14 +2535,7 @@ PM856_config: unconfig sbc8540_config \ sbc8540_33_config \ sbc8540_66_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _66_,$@)" ] ; then \ - echo "#define CONFIG_PCI_66" >>$(obj)include/config.h ; \ - $(XECHO) "... 66 MHz PCI" ; \ - else \ - $(XECHO) "... 33 MHz PCI" ; \ - fi - @$(MKCONFIG) -a SBC8540 ppc mpc85xx sbc8560 + @$(MKCONFIG) -t $(@:_config=) SBC8540 ppc mpc85xx sbc8560 sbc8548_config \ sbc8548_PCI_33_config \ @@ -2554,14 +2547,7 @@ sbc8548_PCI_66_PCIE_config: unconfig sbc8560_config \ sbc8560_33_config \ sbc8560_66_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _66_,$@)" ] ; then \ - echo "#define CONFIG_PCI_66" >>$(obj)include/config.h ; \ - $(XECHO) "... 66 MHz PCI" ; \ - else \ - $(XECHO) "... 33 MHz PCI" ; \ - fi - @$(MKCONFIG) -a sbc8560 ppc mpc85xx sbc8560 + @$(MKCONFIG) -t $(@:_config=) sbc8560 ppc mpc85xx sbc8560 socrates_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx socrates diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 272b5dd56cb..7cde39bf2a5 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -24,22 +24,25 @@ * MA 02111-1307 USA */ -/* mpc8560ads board configuration file */ -/* please refer to doc/README.mpc85xx for more info */ -/* make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file +/* + * sbc8540 board configuration file. */ #ifndef __CONFIG_H #define __CONFIG_H -#if XXX -#define DEBUG /* General debug */ -#define ET_DEBUG +/* + * Top level Makefile configuration choices + */ +#ifdef CONFIG_MK_66 +#define CONFIG_PCI_66 #endif + #define TSEC_DEBUG -/* High Level Configuration Options */ +/* + * High Level Configuration Options + */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 46c94bf16be..a6b15f74c9c 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -24,16 +24,23 @@ * MA 02111-1307 USA */ -/* sbc8560 board configuration file */ -/* please refer to doc/README.sbc8560 for more info */ -/* make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file +/* + * sbc8560 board configuration file. */ #ifndef __CONFIG_H #define __CONFIG_H -/* High Level Configuration Options */ +/* + * Top level Makefile configuration choices + */ +#ifdef CONFIG_MK_66 +#define CONFIG_PCI_66 +#endif + +/* + * High Level Configuration Options + */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ From 8439f05cfd8cbb38485376a34d9fe297ba262737 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 21 Sep 2009 23:09:28 -0500 Subject: [PATCH 164/208] mpc8610hpcd: Use common 86xx fdt fixup code Using the common 86xx fdt fixups removes some board-specific code and should make the mpc8610hpcd easier to maintain in the long run. Signed-off-by: Peter Tyser Signed-off-by: Kumar Gala --- board/freescale/mpc8610hpcd/mpc8610hpcd.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 98111eb60bd..358148faf2a 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -387,19 +387,7 @@ void pci_init_board(void) void ft_board_setup(void *blob, bd_t *bd) { - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "timebase-frequency", bd->bi_busfreq / 4, 1); - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "bus-frequency", bd->bi_busfreq, 1); - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "clock-frequency", bd->bi_intfreq, 1); - do_fixup_by_prop_u32(blob, "device_type", "soc", 4, - "bus-frequency", bd->bi_busfreq, 1); - - do_fixup_by_compat_u32(blob, "ns16550", - "clock-frequency", bd->bi_busfreq, 1); - - fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize); + ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI1 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); From 098bcbae3172d73d24ca8ba196328d901eed4132 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Tue, 22 Sep 2009 14:53:10 +0800 Subject: [PATCH 165/208] ppc/85xx: add ld script file for boot from NAND The first stage 4K image uses a seperate ld script file to generate 4K image. This patch moves it to the cpu/mpc85xx/* to make it avaliable for 85xx platform. Signed-off-by: Mingkai Hu Signed-off-by: Kumar Gala --- cpu/mpc85xx/u-boot-nand_spl.lds | 67 +++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 cpu/mpc85xx/u-boot-nand_spl.lds diff --git a/cpu/mpc85xx/u-boot-nand_spl.lds b/cpu/mpc85xx/u-boot-nand_spl.lds new file mode 100644 index 00000000000..fef3e42e09c --- /dev/null +++ b/cpu/mpc85xx/u-boot-nand_spl.lds @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de + * + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + . = 0xfff00000; + .text : { + *(.text) + } + _etext = .; + + .reloc : { + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + . = ALIGN(8); + .data : { + *(.rodata*) + *(.data*) + *(.sdata*) + } + _edata = .; + + . = ALIGN(8); + __init_begin = .; + __init_end = .; + + .resetvec ADDR(.text) + 0xffc : { + *(.resetvec) + } = 0xffff + + __bss_start = .; + .bss : { + *(.sbss) + *(.bss) + } + _end = .; +} +ASSERT(__init_end <= 0xfff00ffc, "NAND bootstrap too big"); From 266139b88b43ae1d87abb5f5431e6f57b801795f Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Tue, 22 Sep 2009 14:53:34 +0800 Subject: [PATCH 166/208] immap_85xx: add porpllsr's plat ratio definition Signed-off-by: Mingkai Hu Signed-off-by: Kumar Gala --- include/asm-ppc/immap_85xx.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index e7d412dba23..39fdb8e94f4 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1542,6 +1542,8 @@ typedef struct ccsr_gur { #endif #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000 #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25 +#define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e +#define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1 uint porbmsr; /* 0xe0004 - POR boot mode status register */ #define MPC85xx_PORBMSR_HA 0x00070000 #define MPC85xx_PORBMSR_HA_SHIFT 16 From 234a89d911ce28e46372f555d7c14e28424f2b0d Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Tue, 22 Sep 2009 14:53:21 +0800 Subject: [PATCH 167/208] ppc/85xx: add cpu init config file for boot from NAND When boot from NAND, the NAND flash must be connected to br/or0. Also init RAM(L2 SRAM or DDR SDRAM) for load the second image to it. Signed-off-by: Mingkai Hu Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu_init_nand.c | 63 +++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 cpu/mpc85xx/cpu_init_nand.c diff --git a/cpu/mpc85xx/cpu_init_nand.c b/cpu/mpc85xx/cpu_init_nand.c new file mode 100644 index 00000000000..184cca4c543 --- /dev/null +++ b/cpu/mpc85xx/cpu_init_nand.c @@ -0,0 +1,63 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +void cpu_init_f(void) +{ + ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + + /* + * LCRR - Clock Ratio Register - set up local bus timing + * when needed + */ + out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8); + +#if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM) + out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM); + out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM); +#else +#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined +#endif + +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; + char *l2srbar; + int i; + + out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR); + + /* set MBECCDIS=1, SBECCDIS=1 */ + out_be32(&l2cache->l2errdis, + (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC)); + + /* set L2E=1 & L2SRAM=001 */ + out_be32(&l2cache->l2ctl, + (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); + + /* Initialize L2 SRAM to zero */ + l2srbar = (char *)CONFIG_SYS_INIT_L2_ADDR; + for (i = 0; i < CONFIG_SYS_L2_SIZE; i++) + l2srbar[i] = 0; +#endif +} From cb0ff65c619efacdc0ba69aa8ee6ede7dd364a38 Mon Sep 17 00:00:00 2001 From: Vivek Mahajan Date: Tue, 22 Sep 2009 12:48:27 +0530 Subject: [PATCH 168/208] 85xx-fdt: Fixed l2-ctlr's compatible prop for QorIQ The code assumed names where just numbers and always prefixed 'mpc'. However newer QorIQ don't follow the mpc naming scheme. Signed-off-by: Vivek Mahajan Signed-off-by: Kumar Gala --- cpu/mpc85xx/fdt.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 723f473dabf..61e0fb0636d 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2007 Freescale Semiconductor, Inc. + * Copyright 2007-2009 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -27,6 +27,7 @@ #include #include #include +#include #ifdef CONFIG_FSL_ESDHC #include #endif @@ -148,8 +149,14 @@ static inline void ft_fixup_l2cache(void *blob) } if (cpu) { - len = sprintf(compat_buf, "fsl,mpc%s-l2-cache-controller", - cpu->name); + if (isdigit(cpu->name[0])) + len = sprintf(compat_buf, + "fsl,mpc%s-l2-cache-controller", cpu->name); + else + len = sprintf(compat_buf, + "fsl,%c%s-l2-cache-controller", + tolower(cpu->name[0]), cpu->name + 1); + sprintf(&compat_buf[len + 1], "cache"); } fdt_setprop(blob, off, "cache-unified", NULL, 0); From 25bacf7a2b096496e2c58f2de4e5b2bce8fba038 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 22 Sep 2009 15:45:44 -0500 Subject: [PATCH 169/208] ppc/85xx: Fix enabling of L2 cache We need to flash invalidate the locks in addition to the cache before we enable. Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu_init.c | 4 ++-- cpu/mpc85xx/release.S | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index a6d1e999b60..a8d83b1c8a3 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -336,8 +336,8 @@ int cpu_init_r(void) u32 l2cfg0 = mfspr(SPRN_L2CFG0); /* invalidate the L2 cache */ - mtspr(SPRN_L2CSR0, L2CSR0_L2FI); - while (mfspr(SPRN_L2CSR0) & L2CSR0_L2FI) + mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); + while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) ; /* enable the cache */ diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 074b056b749..ecbd0d58577 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -102,7 +102,8 @@ __secondary_start_page: #ifdef CONFIG_BACKSIDE_L2_CACHE /* Enable/invalidate the L2 cache */ msync - lis r3,L2CSR0_L2FI@h + lis r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@h + ori r3,r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@l mtspr SPRN_L2CSR0,r3 1: mfspr r3,SPRN_L2CSR0 From 01df521217957d77d53c2d570183eded7030938f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 16 Sep 2009 09:43:12 -0500 Subject: [PATCH 170/208] ppc/p4080: Add p4080 platform immap definitions The p4080 SoC has a significant amount of commonality with the 85xx/PQ3 platform. We reuse the 85xx immap and just add new definitions for local access and global utils. The global utils is now broken into global utils, clocking and run control/power management. The offsets from CCSR for a number of blocks have also changed. We introduce the CONFIG_FSL_CORENET define to distinquish the PQ3 style of platform from the new p4080 platform. We don't use QoirQ as there are products (like p2020) that are PQ3 based platforms but have the QoirQ name. Signed-off-by: Kumar Gala --- include/asm-ppc/fsl_lbc.h | 4 + include/asm-ppc/immap_85xx.h | 287 ++++++++++++++++++++++++++++++++--- 2 files changed, 271 insertions(+), 20 deletions(-) diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h index 08d31e12e4c..5723de643a4 100644 --- a/include/asm-ppc/fsl_lbc.h +++ b/include/asm-ppc/fsl_lbc.h @@ -317,6 +317,10 @@ #define LCRR_CLKDIV_2 0x00000002 #define LCRR_CLKDIV_4 0x00000004 #define LCRR_CLKDIV_8 0x00000008 +#elif defined(CONFIG_FSL_CORENET) +#define LCRR_CLKDIV_8 0x00000002 +#define LCRR_CLKDIV_16 0x00000004 +#define LCRR_CLKDIV_32 0x00000008 #else #define LCRR_CLKDIV_4 0x00000002 #define LCRR_CLKDIV_8 0x00000004 diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 39fdb8e94f4..100dfe10692 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -16,6 +16,29 @@ #include #include +typedef struct ccsr_local { + u32 ccsrbarh; /* 0x0 - Control Configuration Status Registers Base Address Register High */ + u32 ccsrbarl; /* 0x4 - Control Configuration Status Registers Base Address Register Low */ + u32 ccsrar; /* 0x8 - Configuration, Control, and Status Attribute Register */ +#define CCSRAR_C 0x80000000 /* Commit */ + u8 res1[4]; + u32 altcbarh; /* 0x10 - Alternate Configuration Base Address Register High */ + u32 altcbarl; /* 0x14 - Alternate Configuration Base Address Register Low */ + u32 altcar; /* 0x18 - Alternate Configuration Attribute Register */ + u8 res2[4]; + u32 bstrh; /* 0x20 - Boot space translation register high */ + u32 bstrl; /* 0x24 - Boot space translation register Low */ + u32 bstrar; /* 0x28 - Boot space translation attributes register */ + u8 res3[0xbd4]; + struct { + u32 lawbarh; /* 0xc00 + n * 0x10 - LAW0 base address register high */ + u32 lawbarl; /* 0xc04 + n * 0x10 - LAW0 base address register low */ + u32 lawar; /* 0xc08 + n * 0x10 - LAW0 attributes register */ + u8 res4[4]; + } law[32]; + u8 res35[0x204]; +} ccsr_local_t; + /* * Local-Access Registers and ECM Registers(0x0000-0x2000) */ @@ -165,7 +188,21 @@ typedef struct ccsr_ddr { uint debug_2; uint debug_3; uint debug_4; - char res12[240]; + uint debug_5; + uint debug_6; + uint debug_7; + uint debug_8; + uint debug_9; + uint debug_10; + uint debug_11; + uint debug_12; + uint debug_13; /* +0xF30 */ + uint debug_14; + uint debug_15; + uint debug_16; + uint debug_17; + uint debug_18; /* +0xF44 */ + char res12[184]; } ccsr_ddr_t; /* @@ -1531,6 +1568,193 @@ typedef struct par_io { /* * Global Utilities Register Block(0xe_0000-0xf_ffff) */ +#ifdef CONFIG_FSL_CORENET +typedef struct ccsr_gur { + u32 porsr1; /* 0xe0000 - POR status register */ + u8 res1[28]; /* 0xe0004 - 0xe001c Reserved: PORSRn */ + u32 gpporcr1; /* 0xe0020 - General-purpose POR configuration register */ + u8 res2[12]; + u32 gpiocr; /* 0xe0030 - GPIO control register */ + u8 res3[12]; + u32 gpoutdr; /* 0xe0040 - General-purpose output data register */ + u8 res4[12]; + u32 gpindr; /* 0xe0050 - General-purpose input data register */ + u8 res5[12]; + u32 pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ + u8 res6[12]; + u32 devdisr; /* 0xe0070 - Device disable control */ +#define FSL_CORENET_DEVDISR_PCIE1 0x80000000 +#define FSL_CORENET_DEVDISR_PCIE2 0x40000000 +#define FSL_CORENET_DEVDISR_PCIE3 0x20000000 +#define FSL_CORENET_DEVDISR_RMU 0x08000000 +#define FSL_CORENET_DEVDISR_SRIO1 0x04000000 +#define FSL_CORENET_DEVDISR_SRIO2 0x02000000 +#define FSL_CORENET_DEVDISR_DMA1 0x00400000 +#define FSL_CORENET_DEVDISR_DMA2 0x00200000 +#define FSL_CORENET_DEVDISR_DDR1 0x00100000 +#define FSL_CORENET_DEVDISR_DDR2 0x00080000 +#define FSL_CORENET_DEVDISR_DBG 0x00010000 +#define FSL_CORENET_DEVDISR_NAL 0x00008000 +#define FSL_CORENET_DEVDISR_ELBC 0x00001000 +#define FSL_CORENET_DEVDISR_USB1 0x00000800 +#define FSL_CORENET_DEVDISR_USB2 0x00000400 +#define FSL_CORENET_DEVDISR_ESDHC 0x00000100 +#define FSL_CORENET_DEVDISR_GPIO 0x00000080 +#define FSL_CORENET_DEVDISR_ESPI 0x00000040 +#define FSL_CORENET_DEVDISR_I2C1 0x00000020 +#define FSL_CORENET_DEVDISR_I2C2 0x00000010 +#define FSL_CORENET_DEVDISR_DUART1 0x00000002 +#define FSL_CORENET_DEVDISR_DUART2 0x00000001 + u8 res7[12]; + u32 powmgtcsr; /* 0xe0080 - Power management status and control register */ + u8 res8[12]; + u32 coredisru; /* 0xe0090 - uppper portion for support of 64 cores */ + u32 coredisrl; /* 0xe0094 - lower portion for support of 64 cores */ + u8 res9[8]; + u32 pvr; /* 0xe00a0 - Processor version register */ + u32 svr; /* 0xe00a4 - System version register */ + u8 res10[8]; + u32 rstcr; /* 0xe00b0 - Reset control register */ + u32 rstrqpblsr; /* 0xe00b4 - Reset request preboot loader status register */ + u8 res11[8]; + u32 rstrqmr1; /* 0xe00c0 - Reset request mask register */ + u8 res12[4]; /* Reserved: RSTRQMR2 */ + u32 rstrqsr1; /* 0xe00c8 - Reset request status register */ + u8 res13[4]; /* Reserved: RSTRQSR2 */ + u8 res14[4]; /* Reserved: RSTRQWDTMRU */ + u32 rstrqwdtmrl; /* 0xe00d4 - Reset request WDT mask register */ + u8 res15[4]; /* Reserved: RSTRQWDTSRU */ + u32 rstrqwdtsrl; /* 0xe00dc - Reset request WDT status register */ + u8 res16[4]; /* Reserved: BRRU max total of 2 for up to 64 cores */ + u32 brrl; /* 0xe00e4 Boot release register */ + u8 res17[24]; + u32 rcwsr[16]; /* 0xe0100 - 0xe013c: Reset control word status register */ +#define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000 +#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00008000 +#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 15 +#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000 +#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000 +#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000 + u8 res18[192]; /* Reserved: RCWSRn (max total of 64)*/ + u32 scratchrw[4]; /* 0xe0200 - 0xe020c: Scratch Read/Write register */ + u8 res19[240]; /* Reserved: SCRATCHRWn (max total of 64)*/ + u32 scratchw1r[4]; /* 0xe0300 - 0xe030c: Scratch Read register (Write once) */ + u8 res20[240]; /* Reserved: SCRATCHW1Rn (max total of 64)*/ + u32 scrtsr[8]; /* 0xe0400 - 0xe041c: Core reset status register */ + u8 res21[224]; /* Reserved: CRSTSRn (max total of 64 for up to 64 cores)*/ + u32 pex1liodnr; /* 0xe0500 PCI Express 1 Logical I/O Device Number register*/ + u32 pex2liodnr; /* 0xe0504 PCI Express 2 Logical I/O Device Number register*/ + u32 pex3liodnr; /* 0xe0508 PCI Express 3 Logical I/O Device Number register*/ + u32 pex4liodnr; /* 0xe050c PCI Express 4 Logical I/O Device Number register*/ + u32 rio1liodnr; /* 0xe0510 RIO 1 Logical I/O Device Number register*/ + u32 rio2liodnr; /* 0xe0514 RIO 2 Logical I/O Device Number register*/ + u32 rio3liodnr; /* 0xe0518 RIO 3 Logical I/O Device Number register*/ + u32 rio4liodnr; /* 0xe051c RIO 4 Logical I/O Device Number register*/ + u32 usb1liodnr; /* 0xe0520 USB 1 Logical I/O Device Number register*/ + u32 usb2liodnr; /* 0xe0524 USB 2 Logical I/O Device Number register*/ + u32 usb3liodnr; /* 0xe0528 USB 3 Logical I/O Device Number register*/ + u32 usb4liodnr; /* 0xe052c USB 4 Logical I/O Device Number register*/ + u32 sdmmc1liodnr; /* 0xe0530 SD/MMC 1 Logical I/O Device Number register*/ + u32 sdmmc2liodnr; /* 0xe0534 SD/MMC 2 Logical I/O Device Number register*/ + u32 sdmmc3liodnr; /* 0xe0538 SD/MMC 3 Logical I/O Device Number register*/ + u32 sdmmc4liodnr; /* 0xe053c SD/MMC 4 Logical I/O Device Number register*/ + u32 rmuliodnr; /* 0xe0540 RIO Message Unit Logical I/O Device Number register*/ + u32 rduliodnr; /* 0xe0544 RIO Doorbell Unit Logical I/O Device Number register*/ + u32 rpwuliodnr; /* 0xe0548 RIO Port Write Unit Logical I/O Device Number register*/ + u8 res22[52]; /* Reserved: for future LIODN register expansion */ + u32 dma1liodnr; /* 0xe0580 DMA 1 Logical I/O Device Number register*/ + u32 dma2liodnr; /* 0xe0584 DMA 2 Logical I/O Device Number register*/ + u32 dma3liodnr; /* 0xe0588 DMA 3 Logical I/O Device Number register*/ + u32 dma4liodnr; /* 0xe058c DMA 4 Logical I/O Device Number register*/ + u8 res23[48]; /* Reserved: for future LIODN register expansion */ + u8 res24[64]; /* Reserved */ + u32 pblsr; /* 0xe0600 Preboot loader status register*/ + u32 pamubypenr; /* 0xe0604 PAMU bypass enable register*/ + u32 dmacr1; /* 0xe0608 DMA control register*/ + u8 res25[4]; /* Reserved: DMACR2 (max total of 2)*/ + u32 gensr1; /* 0xe0610 General status register*/ + u8 res26[12]; /* Reserved: GENSRn (max total of 4)*/ + u32 gencr1; /* 0xe0620 General control register*/ + u8 res27[12]; /* Reserved: GENCRn (max total of 4)*/ + u8 res28[4]; /* Reserved: CGENSRU (upper portion for support of 64 cores) */ + u32 cgensrl; /* 0xe0634 Core general status register*/ + u8 res29[8]; /* Reserved */ + u8 res30[4]; /* Reserved: CGENCRU (upper portion for support of 64 cores) */ + u32 cgencrl; /* 0xe0634 Core general control register*/ + u8 res31[184]; /* Reserved 0xe0648 - 0xe06fc */ + u32 sriopstecr; /* 0xe0700 SRIO prescaler timer enable control register*/ + u8 res32[2300]; /* Reserved 0xe0704 - 0xe0ffc */ +} ccsr_gur_t; + +typedef struct ccsr_clk { + u32 clkc0csr; /* 0xe1000 - Core 0 Clock control/status register */ + u8 res1[0x1c]; + u32 clkc1csr; /* 0xe1020 - Core 1 Clock control/status register */ + u8 res2[0x1c]; + u32 clkc2csr; /* 0xe1040 - Core 2 Clock control/status register */ + u8 res3[0x1c]; + u32 clkc3csr; /* 0xe1060 - Core 3 Clock control/status register */ + u8 res4[0x1c]; + u32 clkc4csr; /* 0xe1080 - Core 4 Clock control/status register */ + u8 res5[0x1c]; + u32 clkc5csr; /* 0xe10a0 - Core 5 Clock control/status register */ + u8 res6[0x1c]; + u32 clkc6csr; /* 0xe10c0 - Core 6 Clock control/status register */ + u8 res7[0x1c]; + u32 clkc7csr; /* 0xe10e0 - Core 7 Clock control/status register */ + u8 res8[0x71c]; + u32 pllc1gsr; /* 0xe1800 - Cluster PLL 1 General Status Register */ + u8 res10[0x1c]; + u32 pllc2gsr; /* 0xe1820 - Cluster PLL 2 General Status Register */ + u8 res11[0x1c]; + u32 pllc3gsr; /* 0xe1840 - Cluster PLL 3 General Status Register */ + u8 res12[0x1c]; + u32 pllc4gsr; /* 0xe1860 - Cluster PLL 4 General Status Register */ + u8 res13[0x39c]; + u32 pllpgsr; /* 0xe1c00 - Platform PLL General Status Register */ + u8 res14[0x1c]; + u32 plldgsr; /* 0xe1c20 - DDR PLL General Status Register */ + u8 res15[0x3dc]; +} ccsr_clk_t; + +typedef struct ccsr_rcpm { + u8 res1[4]; /* 0xe2000 - Reserved */ + u32 cdozsrl; /* 0xe2004 - Core Doze Status Register */ + u8 res2[4]; /* 0xe2008 - Reserved */ + u32 cdozcrl; /* 0xe200c - Core Doze Control Register */ + u8 res3[4]; /* 0xe2010 - Reserved */ + u32 cnapsrl; /* 0xe2014 - Core Nap Status Register */ + u8 res4[4]; /* 0xe2018 - Reserved */ + u32 cnapcrl; /* 0xe201c - Core Nap Control Register */ + u8 res5[4]; /* 0xe2020 - Reserved */ + u32 cdozpsrl; /* 0xe2024 - Core Doze Previous Status Register */ + u8 res6[4]; /* 0xe2028 - Reserved */ + u32 cdozpcrl; /* 0xe202c - Core Doze Previous Control Register */ + u8 res7[4]; /* 0xe2030 - Reserved */ + u32 cwaitsrl; /* 0xe2034 - Core Wait Status Register */ + u8 res8[8]; /* Reserved */ + u32 powmgtcsr; /* 0xe2040 - Power Mangement Control & Status Register */ + u8 res9[12]; /* Reserved */ + u32 ippdexpcr0; /* 0xe2050 - IP Powerdown Exception Control Register 0 */ + u8 res10[12]; /* Reserved */ + u8 res11[4]; /* Reserved */ + u32 cpmimrl; /* 0xe2064 - Core Power Management Interrupt Masking Register */ + u8 res12[4]; /* Reserved */ + u32 cpmcimrl; /* 0xe206c - Core Power Management Critical Interrupt Masking Register */ + u8 res13[4]; /* Reserved */ + u32 cpmmcimrl; /* 0xe2074 - Core Power Management Machine Check Interrupt Masking Register */ + u8 res14[4]; /* Reserved */ + u32 cpmnmimrl; /* 0xe207c - Core Power Management NMI Masking Register */ + u8 res15[4]; /* Reserved */ + u32 ctbenrl; /* 0xe2084 - Core Time Base Enable Register */ + u8 res16[4]; /* Reserved */ + u32 ctbclkselrl; /* 0xe208c - Core Time Base Clock Select Register */ + u8 res17[4]; /* Reserved */ + u32 ctbhltcrl; /* 0xe2094 - Core Time Base Halt Control Register */ + u8 res18[0xf68]; +} ccsr_rcpm_t; + +#else typedef struct ccsr_gur { uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ #ifdef CONFIG_MPC8536 @@ -1647,42 +1871,65 @@ typedef struct ccsr_gur { uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */ char res15[61648]; /* 0xe0f30 to 0xefffff */ } ccsr_gur_t; +#endif -#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000) +#ifdef CONFIG_FSL_CORENET +#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 +#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000 +#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000 +#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000 +#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 +#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x100000 +#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000 +#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 +#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 +#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 +#define CONFIG_SYS_MPC85xx_QMAN_OFFSET 0x318000 +#define CONFIG_SYS_MPC85xx_BMAN_OFFSET 0x31a000 +#else +#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000 +#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000 +#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000 +#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x6000 +#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000 +#define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000 +#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000 +#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000 +#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000 +#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000 +#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 +#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 +#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 +#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 +#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 +#define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000 +#endif + +#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 +#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 + +#define CONFIG_SYS_MPC85xx_QMAN_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_QMAN_OFFSET) +#define CONFIG_SYS_MPC85xx_BMAN_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_BMAN_OFFSET) #define CONFIG_SYS_MPC85xx_GUTS_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) -#define CONFIG_SYS_MPC85xx_ECM_OFFSET (0x0000) +#define CONFIG_SYS_FSL_CORENET_CCM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET) +#define CONFIG_SYS_FSL_CORENET_CLK_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET) +#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET) #define CONFIG_SYS_MPC85xx_ECM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) -#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x2000) #define CONFIG_SYS_MPC85xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET) -#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x6000) #define CONFIG_SYS_MPC85xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) -#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x5000) #define CONFIG_SYS_MPC85xx_LBC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) -#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x7000) #define CONFIG_SYS_MPC85xx_ESPI_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) -#define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000) #define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) -#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000) #define CONFIG_SYS_MPC85xx_PCIX2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) -#define CONFIG_SYS_MPC85xx_GPIO_OFFSET (0xF000) -#define CONFIG_SYS_MPC85xx_GPIO_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET) -#define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000) +#define CONFIG_SYS_MPC85xx_GPIO_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET) #define CONFIG_SYS_MPC85xx_SATA1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) -#define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000) #define CONFIG_SYS_MPC85xx_SATA2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET) -#define CONFIG_SYS_MPC85xx_L2_OFFSET (0x20000) #define CONFIG_SYS_MPC85xx_L2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET) -#define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x21000) #define CONFIG_SYS_MPC85xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) -#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x2e000) #define CONFIG_SYS_MPC85xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) -#define CONFIG_SYS_MPC85xx_PIC_OFFSET (0x40000) #define CONFIG_SYS_MPC85xx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) -#define CONFIG_SYS_MPC85xx_CPM_OFFSET (0x80000) #define CONFIG_SYS_MPC85xx_CPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) -#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET (0xE3000) #define CONFIG_SYS_MPC85xx_SERDES1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) -#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET (0xE3100) #define CONFIG_SYS_MPC85xx_SERDES2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000 #define CONFIG_SYS_MPC85xx_USB_ADDR \ From 418ec8584343f04048e2cc7ee96b6b29be54ad97 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 19 Mar 2009 02:32:23 -0500 Subject: [PATCH 171/208] ppc/p4080: Add support for CoreNet style platform LAWs On CoreNet based platforms the LAW address is split between an high & low register and we no longer shift the address. Also, the target IDs on CoreNet platforms have been completely re-assigned. Additionally, added a new find_law() API to which LAW an address hits in. This is need for the CoreNet style boot release code since it will need to determine what the target ID should be set to for boot window translation. Finally, enamed LAWAR_EN to LAW_EN and moved to header so we can use it elsewhere. Signed-off-by: Kumar Gala --- drivers/misc/fsl_law.c | 126 ++++++++++++++++++++++++++++++++++---- include/asm-ppc/fsl_law.h | 31 ++++++++++ 2 files changed, 146 insertions(+), 11 deletions(-) diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index aa877c65fd3..7c59c887f13 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2009 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -29,7 +29,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define LAWAR_EN 0x80000000 /* number of LAWs in the hw implementation */ #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) @@ -46,6 +45,56 @@ DECLARE_GLOBAL_DATA_PTR; #error FSL_HW_NUM_LAWS not defined for this platform #endif +#ifdef CONFIG_FSL_CORENET +void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) +{ + volatile ccsr_local_t *ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); + + gd->used_laws |= (1 << idx); + + out_be32(&ccm->law[idx].lawar, 0); + out_be32(&ccm->law[idx].lawbarh, ((u64)addr >> 32)); + out_be32(&ccm->law[idx].lawbarl, addr & 0xffffffff); + out_be32(&ccm->law[idx].lawar, LAW_EN | ((u32)id << 20) | (u32)sz); + + /* Read back so that we sync the writes */ + in_be32(&ccm->law[idx].lawar); +} + +void disable_law(u8 idx) +{ + volatile ccsr_local_t *ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); + + gd->used_laws &= ~(1 << idx); + + out_be32(&ccm->law[idx].lawar, 0); + out_be32(&ccm->law[idx].lawbarh, 0); + out_be32(&ccm->law[idx].lawbarl, 0); + + /* Read back so that we sync the writes */ + in_be32(&ccm->law[idx].lawar); + + return; +} + +static int get_law_entry(u8 i, struct law_entry *e) +{ + volatile ccsr_local_t *ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); + u32 lawar; + + lawar = in_be32(&ccm->law[i].lawar); + + if (!(lawar & LAW_EN)) + return 0; + + e->addr = ((u64)in_be32(&ccm->law[i].lawbarh) << 32) | + in_be32(&ccm->law[i].lawbarl); + e->size = lawar & 0x3f; + e->trgt_id = (lawar >> 20) & 0xff; + + return 1; +} +#else void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08); @@ -56,12 +105,49 @@ void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) out_be32(lawar, 0); out_be32(lawbar, addr >> 12); - out_be32(lawar, LAWAR_EN | ((u32)id << 20) | (u32)sz); + out_be32(lawar, LAW_EN | ((u32)id << 20) | (u32)sz); /* Read back so that we sync the writes */ in_be32(lawar); } +void disable_law(u8 idx) +{ + volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08); + volatile u32 *lawbar = base + 8 * idx; + volatile u32 *lawar = base + 8 * idx + 2; + + gd->used_laws &= ~(1 << idx); + + out_be32(lawar, 0); + out_be32(lawbar, 0); + + /* Read back so that we sync the writes */ + in_be32(lawar); + + return; +} + +static int get_law_entry(u8 i, struct law_entry *e) +{ + volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08); + volatile u32 *lawbar = base + 8 * i; + volatile u32 *lawar = base + 8 * i + 2; + u32 temp; + + temp = in_be32(lawar); + + if (!(temp & LAW_EN)) + return 0; + + e->addr = (u64)in_be32(lawbar) << 12; + e->size = temp & 0x3f; + e->trgt_id = (temp >> 20) & 0xff; + + return 1; +} +#endif + int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { u32 idx = ffz(gd->used_laws); @@ -94,18 +180,30 @@ int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) return idx; } -void disable_law(u8 idx) +struct law_entry find_law(phys_addr_t addr) { - volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08); - volatile u32 *lawbar = base + 8 * idx; - volatile u32 *lawar = base + 8 * idx + 2; + struct law_entry entry; + int i; - gd->used_laws &= ~(1 << idx); + entry.index = -1; + entry.addr = 0; + entry.size = 0; + entry.trgt_id = 0; - out_be32(lawar, 0); - out_be32(lawbar, 0); + for (i = 0; i < FSL_HW_NUM_LAWS; i++) { + u64 upper; - return; + if (!get_law_entry(i, &entry)) + continue; + + upper = entry.addr + (2ull << entry.size); + if ((addr >= entry.addr) && (addr < upper)) { + entry.index = i; + break; + } + } + + return entry; } void print_laws(void) @@ -173,7 +271,13 @@ void init_laws(void) { int i; +#if FSL_HW_NUM_LAWS < 32 gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1); +#elif FSL_HW_NUM_LAWS == 32 + gd->used_laws = 0; +#else +#error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes +#endif for (i = 0; i < num_law_entries; i++) { if (law_table[i].index == -1) diff --git a/include/asm-ppc/fsl_law.h b/include/asm-ppc/fsl_law.h index e06a1a6e0e1..31bb7545b53 100644 --- a/include/asm-ppc/fsl_law.h +++ b/include/asm-ppc/fsl_law.h @@ -1,8 +1,18 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + #ifndef _FSL_LAW_H_ #define _FSL_LAW_H_ #include +#define LAW_EN 0x80000000 + #define SET_LAW_ENTRY(idx, a, sz, trgt) \ { .index = idx, .addr = a, .size = sz, .trgt_id = trgt } @@ -36,6 +46,25 @@ enum law_size { LAW_SIZE_32G, }; +#ifdef CONFIG_FSL_CORENET +enum law_trgt_if { + LAW_TRGT_IF_PCIE_1 = 0x00, + LAW_TRGT_IF_PCIE_2 = 0x01, + LAW_TRGT_IF_PCIE_3 = 0x02, + LAW_TRGT_IF_RIO_1 = 0x08, + LAW_TRGT_IF_RIO_2 = 0x09, + + LAW_TRGT_IF_DDR_1 = 0x10, + LAW_TRGT_IF_DDR_2 = 0x11, /* 2nd controller */ + LAW_TRGT_IF_DDR_INTRLV = 0x14, + + LAW_TRGT_IF_BMAN = 0x18, + LAW_TRGT_IF_DCSR = 0x1d, + LAW_TRGT_IF_LBC = 0x1f, + LAW_TRGT_IF_QMAN = 0x3c, +}; +#define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1 +#else enum law_trgt_if { LAW_TRGT_IF_PCI = 0x00, LAW_TRGT_IF_PCI_2 = 0x01, @@ -64,6 +93,7 @@ enum law_trgt_if { #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) #define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI #endif +#endif /* CONFIG_FSL_CORENET */ struct law_entry { int index; @@ -76,6 +106,7 @@ extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id); extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id); extern int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id); +extern struct law_entry find_law(phys_addr_t addr); extern void disable_law(u8 idx); extern void init_laws(void); extern void print_laws(void); From a880cf3e0e1c220d780eccd0b101170c4499485d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 17 Sep 2009 01:44:00 -0500 Subject: [PATCH 172/208] ppc/p4080: CoreNet platfrom style CCSRBAR setting On CoreNet based platforms the CCSRBAR address is split between an high & low register and we no longer shift the address. Signed-off-by: Kumar Gala Signed-off-by: Scott Wood --- cpu/mpc85xx/cpu_init_early.c | 68 +++++++++++++++++++++++++++--------- 1 file changed, 52 insertions(+), 16 deletions(-) diff --git a/cpu/mpc85xx/cpu_init_early.c b/cpu/mpc85xx/cpu_init_early.c index 7886f868f2a..32aa94b612c 100644 --- a/cpu/mpc85xx/cpu_init_early.c +++ b/cpu/mpc85xx/cpu_init_early.c @@ -24,6 +24,51 @@ DECLARE_GLOBAL_DATA_PTR; +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) +#ifdef CONFIG_FSL_CORENET +static void setup_ccsrbar(void) +{ + u32 temp; + volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000); + volatile ccsr_local_t *ccm; + + /* + * We can't call set_law() because we haven't moved + * CCSR yet. + */ + ccm = (void *)ccsr_virt; + + out_be32(&ccm->law[0].lawbarh, + (u64)CONFIG_SYS_CCSRBAR_PHYS >> 32); + out_be32(&ccm->law[0].lawbarl, (u32)CONFIG_SYS_CCSRBAR_PHYS); + out_be32(&ccm->law[0].lawar, + LAW_EN | (0x1e << 20) | LAW_SIZE_4K); + + in_be32((u32 *)(ccsr_virt + 0)); + in_be32((u32 *)(ccsr_virt + 1)); + isync(); + + ccm = (void *)CONFIG_SYS_CCSRBAR; + /* Now use the temporary LAW to move CCSR */ + out_be32(&ccm->ccsrbarh, (u64)CONFIG_SYS_CCSRBAR_PHYS >> 32); + out_be32(&ccm->ccsrbarl, (u32)CONFIG_SYS_CCSRBAR_PHYS); + out_be32(&ccm->ccsrar, CCSRAR_C); + temp = in_be32(&ccm->ccsrar); + disable_law(0); +} +#else +static void setup_ccsrbar(void) +{ + u32 temp; + volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000); + + temp = in_be32(ccsr_virt); + out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12); + temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR); +} +#endif +#endif + /* We run cpu_init_early_f in AS = 1 */ void cpu_init_early_f(void) { @@ -50,24 +95,15 @@ void cpu_init_early_f(void) /* set up CCSR if we want it moved */ #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) - { - u32 temp; - volatile u32 *ccsr_virt = - (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000); + mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1); + /* mas1 is the same as above */ + mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G); + mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, MAS3_SW|MAS3_SR); + mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT); - mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1); - /* mas1 is the same as above */ - mas2 = FSL_BOOKE_MAS2((u32)ccsr_virt, MAS2_I|MAS2_G); - mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, - MAS3_SW|MAS3_SR); - mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT); + write_tlb(mas0, mas1, mas2, mas3, mas7); - write_tlb(mas0, mas1, mas2, mas3, mas7); - - temp = in_be32(ccsr_virt); - out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12); - temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR); - } + setup_ccsrbar(); #endif init_laws(); From 39a7e7fd538cdf49e7e8a2f0634ea5e15e12b4ec Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 17 Sep 2009 01:44:39 -0500 Subject: [PATCH 173/208] ppc/p4080: CoreNet platfrom style secondary core release The CoreNet platform style of bringing secondary cores out of reset is a bit different that the PQ3 style. Mostly the registers that we use to setup boot translation, enable time bases, and boot release the cores have moved around. Signed-off-by: Kumar Gala --- cpu/mpc85xx/mp.c | 68 +++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 65 insertions(+), 3 deletions(-) diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index fa65bed083b..b5c6020c7f1 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -26,6 +26,7 @@ #include #include #include +#include #include "mp.h" DECLARE_GLOBAL_DATA_PTR; @@ -135,7 +136,67 @@ ulong get_spin_addr(void) return addr; } -static void pq3_mp_up(unsigned long bootpg) +#ifdef CONFIG_FSL_CORENET +static void plat_mp_up(unsigned long bootpg) +{ + u32 up, cpu_up_mask, whoami; + u32 *table = (u32 *)get_spin_addr(); + volatile ccsr_gur_t *gur; + volatile ccsr_local_t *ccm; + volatile ccsr_rcpm_t *rcpm; + volatile ccsr_pic_t *pic; + int timeout = 10; + u32 nr_cpus; + struct law_entry e; + + gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); + rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); + pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + + nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1; + + whoami = in_be32(&pic->whoami); + cpu_up_mask = 1 << whoami; + out_be32(&ccm->bstrl, bootpg); + + e = find_law(bootpg); + out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | LAW_SIZE_4K); + + /* disable time base at the platform */ + out_be32(&rcpm->ctbenrl, cpu_up_mask); + + /* release the hounds */ + up = ((1 << nr_cpus) - 1); + out_be32(&gur->brrl, up); + + /* wait for everyone */ + while (timeout) { + int i; + for (i = 0; i < nr_cpus; i++) { + if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) + cpu_up_mask |= (1 << i); + }; + + if ((cpu_up_mask & up) == up) + break; + + udelay(100); + timeout--; + } + + if (timeout == 0) + printf("CPU up timeout. CPU up mask is %x should be %x\n", + cpu_up_mask, up); + + /* enable time base at the platform */ + out_be32(&rcpm->ctbenrl, 0); + mtspr(SPRN_TBWU, 0); + mtspr(SPRN_TBWL, 0); + out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1); +} +#else +static void plat_mp_up(unsigned long bootpg) { u32 up, cpu_up_mask, whoami; u32 *table = (u32 *)get_spin_addr(); @@ -196,6 +257,7 @@ static void pq3_mp_up(unsigned long bootpg) devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1); out_be32(&gur->devdisr, devdisr); } +#endif void cpu_mp_lmb_reserve(struct lmb *lmb) { @@ -217,7 +279,7 @@ void setup_mp(void) if (i != -1) { /* map reset page to bootpg so we can copy code there */ disable_tlb(i); - + set_tlb(1, 0xfffff000, bootpg, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, /* perms, wimge */ 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ @@ -234,7 +296,7 @@ void setup_mp(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */ 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ - pq3_mp_up(bootpg); + plat_mp_up(bootpg); } else { puts("WARNING: No reset page TLB. " "Skipping secondary core setup\n"); From 7e4259bba4c56536760e42d32dacfb3233f216fd Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 19 Mar 2009 02:39:17 -0500 Subject: [PATCH 174/208] ppc/p4080: Add various p4080 related defines (and p4040) There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added p4080 & p4040 to cpu_type_list and SVR list * Added number of LAWs for p4080 * Set CONFIG_MAX_CPUS to 8 for p4080 Signed-off-by: Kumar Gala --- cpu/mpc85xx/Makefile | 1 + cpu/mpc8xxx/cpu.c | 4 ++++ drivers/misc/fsl_law.c | 2 ++ include/asm-ppc/config.h | 6 ++++-- include/asm-ppc/processor.h | 4 ++++ 5 files changed, 15 insertions(+), 2 deletions(-) diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 3ef00e85069..56de7eb3818 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -53,6 +53,7 @@ COBJS-$(CONFIG_P1011) += ddr-gen3.o COBJS-$(CONFIG_P1020) += ddr-gen3.o COBJS-$(CONFIG_P2010) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o +COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o COBJS-$(CONFIG_CPM2) += ether_fcc.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/cpu/mpc8xxx/cpu.c b/cpu/mpc8xxx/cpu.c index 00791e11bd5..d191263f508 100644 --- a/cpu/mpc8xxx/cpu.c +++ b/cpu/mpc8xxx/cpu.c @@ -72,6 +72,10 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P2010, P2010_E, 1), CPU_TYPE_ENTRY(P2020, P2020, 2), CPU_TYPE_ENTRY(P2020, P2020_E, 2), + CPU_TYPE_ENTRY(P4040, P4040, 4), + CPU_TYPE_ENTRY(P4040, P4040_E, 4), + CPU_TYPE_ENTRY(P4080, P4080, 8), + CPU_TYPE_ENTRY(P4080, P4080_E, 8), #elif defined(CONFIG_MPC86xx) CPU_TYPE_ENTRY(8610, 8610, 1), CPU_TYPE_ENTRY(8641, 8641, 2), diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index 7c59c887f13..425eb181bf0 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -41,6 +41,8 @@ DECLARE_GLOBAL_DATA_PTR; defined(CONFIG_P1011) || defined(CONFIG_P1020) || \ defined(CONFIG_P2010) || defined(CONFIG_P2020) #define FSL_HW_NUM_LAWS 12 +#elif defined(CONFIG_PPC_P4080) +#define FSL_HW_NUM_LAWS 32 #else #error FSL_HW_NUM_LAWS not defined for this platform #endif diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h index 5670d06a441..e35b0b77fc8 100644 --- a/include/asm-ppc/config.h +++ b/include/asm-ppc/config.h @@ -40,9 +40,11 @@ #if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \ defined(CONFIG_P2020) || defined(CONFIG_MPC8641) -#define CONFIG_MAX_CPUS 2 +#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_PPC_P4080) +#define CONFIG_MAX_CPUS 8 #else -#define CONFIG_MAX_CPUS 1 +#define CONFIG_MAX_CPUS 1 #endif #endif /* _ASM_CONFIG_H_ */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 3764a5a51d5..d009957d8b0 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -1031,6 +1031,10 @@ #define SVR_P2010_E 0x80EB00 #define SVR_P2020 0x80E200 #define SVR_P2020_E 0x80EA00 +#define SVR_P4040 0x820100 +#define SVR_P4040_E 0x820900 +#define SVR_P4080 0x820000 +#define SVR_P4080_E 0x820800 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 From 3c2a67eec8a0facc865b400caca52e7f6b7adf01 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 17 Sep 2009 01:52:37 -0500 Subject: [PATCH 175/208] ppc/p4080: Handle timebase enabling and frequency reporting On CoreNet style platforms the timebase frequency is the bus frequency defined by 16 (on PQ3 it is divide by 8). Also on the CoreNet platforms the core not longer controls the enabling of the timebase. We now need to enable the boot core's timebase via CCSR register writes. Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu.c | 4 ++++ cpu/mpc85xx/cpu_init.c | 17 +++++++++++++++++ cpu/mpc85xx/fdt.c | 2 +- 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index bdd9ee4c833..25c04169fd9 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -184,7 +184,11 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) */ unsigned long get_tbclk (void) { +#ifdef CONFIG_FSL_CORENET + return (gd->bus_clk + 8) / 16; +#else return (gd->bus_clk + 4UL)/8UL; +#endif } diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index a8d83b1c8a3..53369349d13 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -136,6 +136,20 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) * initialize a bunch of registers */ +#ifdef CONFIG_FSL_CORENET +static void corenet_tb_init(void) +{ + volatile ccsr_rcpm_t *rcpm = + (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); + volatile ccsr_pic_t *pic = + (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + u32 whoami = in_be32(&pic->whoami); + + /* Enable the timebase register for this core */ + out_be32(&rcpm->ctbenrl, (1 << whoami)); +} +#endif + void cpu_init_f (void) { volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); @@ -229,6 +243,9 @@ void cpu_init_f (void) #if defined(CONFIG_FSL_DMA) dma_init(); #endif +#ifdef CONFIG_FSL_CORENET + corenet_tb_init(); +#endif } diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 61e0fb0636d..efb65188226 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -294,7 +294,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_add_enet_stashing(blob); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "timebase-frequency", bd->bi_busfreq / 8, 1); + "timebase-frequency", get_tbclk(), 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "bus-frequency", bd->bi_busfreq, 1); get_sys_info(&sysinfo); From 39aaca1f66a0e5b1204b0789f6c0097938c00ad1 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 19 Mar 2009 02:46:19 -0500 Subject: [PATCH 176/208] ppc/p4080: Determine various chip frequencies on CoreNet platforms The means to determine the core, bus, and DDR frequencies are completely new on CoreNet style platforms. Additionally on p4080 we can have different frequencies for FMAN and PME IP blocks. We need to keep track of the FMAN & PME frequencies since they are used for time stamping capabilities inside each block. Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu.c | 45 +++++++++++++++++++++--- cpu/mpc85xx/speed.c | 86 +++++++++++++++++++++++++++++++++++++++++++++ include/e500.h | 6 ++++ 3 files changed, 133 insertions(+), 4 deletions(-) diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 25c04169fd9..0cc6e0323f2 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -46,11 +46,20 @@ int checkcpu (void) char buf1[32], buf2[32]; #ifdef CONFIG_DDR_CLK_FREQ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#ifdef CONFIG_FSL_CORENET + u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) + >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; +#else u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; +#endif +#else +#ifdef CONFIG_FSL_CORENET + u32 ddr_sync = 0; #else u32 ddr_ratio = 0; #endif +#endif /* CONFIG_DDR_CLK_FREQ */ int i; svr = get_svr(); @@ -111,6 +120,19 @@ int checkcpu (void) } printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); +#ifdef CONFIG_FSL_CORENET + if (ddr_sync == 1) { + printf(" DDR:%-4s MHz (%s MT/s data rate) " + "(Synchronous), ", + strmhz(buf1, sysinfo.freqDDRBus/2), + strmhz(buf2, sysinfo.freqDDRBus)); + } else { + printf(" DDR:%-4s MHz (%s MT/s data rate) " + "(Asynchronous), ", + strmhz(buf1, sysinfo.freqDDRBus/2), + strmhz(buf2, sysinfo.freqDDRBus)); + } +#else switch (ddr_ratio) { case 0x0: printf(" DDR:%-4s MHz (%s MT/s data rate), ", @@ -118,22 +140,26 @@ int checkcpu (void) strmhz(buf2, sysinfo.freqDDRBus)); break; case 0x7: - printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ", + printf(" DDR:%-4s MHz (%s MT/s data rate) " + "(Synchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; default: - printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ", + printf(" DDR:%-4s MHz (%s MT/s data rate) " + "(Asynchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; } +#endif - if (sysinfo.freqLocalBus > LCRR_CLKDIV) + if (sysinfo.freqLocalBus > LCRR_CLKDIV) { printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); - else + } else { printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freqLocalBus); + } #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); @@ -143,6 +169,17 @@ int checkcpu (void) printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); #endif +#ifdef CONFIG_SYS_DPAA_FMAN + for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { + printf(" FMAN%d: %s MHz\n", i, + strmhz(buf1, sysinfo.freqFMan[i])); + } +#endif + +#ifdef CONFIG_SYS_DPAA_PME + printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); +#endif + puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); return 0; diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 2fdcefb219c..0244b5c1b7e 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -1,5 +1,6 @@ /* * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc. + * * (C) Copyright 2003 Motorola Inc. * Xianghua Xiao, (X.Xiao@motorola.com) * @@ -37,6 +38,90 @@ DECLARE_GLOBAL_DATA_PTR; void get_sys_info (sys_info_t * sysInfo) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#ifdef CONFIG_FSL_CORENET + volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); + + const u8 core_cplx_PLL[16] = { + [ 0] = 0, /* CC1 PPL / 1 */ + [ 1] = 0, /* CC1 PPL / 2 */ + [ 2] = 0, /* CC1 PPL / 4 */ + [ 4] = 1, /* CC2 PPL / 1 */ + [ 5] = 1, /* CC2 PPL / 2 */ + [ 6] = 1, /* CC2 PPL / 4 */ + [ 8] = 2, /* CC3 PPL / 1 */ + [ 9] = 2, /* CC3 PPL / 2 */ + [10] = 2, /* CC3 PPL / 4 */ + [12] = 3, /* CC4 PPL / 1 */ + [13] = 3, /* CC4 PPL / 2 */ + [14] = 3, /* CC4 PPL / 4 */ + }; + + const u8 core_cplx_PLL_div[16] = { + [ 0] = 1, /* CC1 PPL / 1 */ + [ 1] = 2, /* CC1 PPL / 2 */ + [ 2] = 4, /* CC1 PPL / 4 */ + [ 4] = 1, /* CC2 PPL / 1 */ + [ 5] = 2, /* CC2 PPL / 2 */ + [ 6] = 4, /* CC2 PPL / 4 */ + [ 8] = 1, /* CC3 PPL / 1 */ + [ 9] = 2, /* CC3 PPL / 2 */ + [10] = 4, /* CC3 PPL / 4 */ + [12] = 1, /* CC4 PPL / 1 */ + [13] = 2, /* CC4 PPL / 2 */ + [14] = 4, /* CC4 PPL / 4 */ + }; + uint lcrr_div, i, freqCC_PLL[4], rcw_tmp; + unsigned long sysclk = CONFIG_SYS_CLK_FREQ; + + sysInfo->freqSystemBus = sysclk; + sysInfo->freqDDRBus = sysclk; + freqCC_PLL[0] = sysclk; + freqCC_PLL[1] = sysclk; + freqCC_PLL[2] = sysclk; + freqCC_PLL[3] = sysclk; + + sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0xf; + sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0xf); + freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f; + freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f; + freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f; + freqCC_PLL[3] *= (in_be32(&clk->pllc4gsr) >> 1) & 0x3f; + + rcw_tmp = in_be32(&gur->rcwsr[3]); + for (i = 0; i < cpu_numcores(); i++) { + u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf; + u32 cplx_pll = core_cplx_PLL[c_pll_sel]; + + sysInfo->freqProcessor[i] = + freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel]; + } + +#define PME_CLK_SEL 0x80000000 +#define FM1_CLK_SEL 0x40000000 +#define FM2_CLK_SEL 0x20000000 + rcw_tmp = in_be32(&gur->rcwsr[7]); + +#ifdef CONFIG_SYS_DPAA_PME + if (rcw_tmp & PME_CLK_SEL) + sysInfo->freqPME = freqCC_PLL[2] / 2; + else + sysInfo->freqPME = sysInfo->freqSystemBus / 2; +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN + if (rcw_tmp & FM1_CLK_SEL) + sysInfo->freqFMan[0] = freqCC_PLL[2] / 2; + else + sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; +#if (CONFIG_SYS_NUM_FMAN) == 2 + if (rcw_tmp & FM2_CLK_SEL) + sysInfo->freqFMan[1] = freqCC_PLL[2] / 2; + else + sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; +#endif +#endif + +#else uint plat_ratio,e500_ratio,half_freqSystemBus; uint lcrr_div; int i; @@ -67,6 +152,7 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ; } #endif +#endif #ifdef CONFIG_QE qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) diff --git a/include/e500.h b/include/e500.h index f8c82661a2d..e1708b9dc95 100644 --- a/include/e500.h +++ b/include/e500.h @@ -15,6 +15,12 @@ typedef struct unsigned long freqDDRBus; unsigned long freqLocalBus; unsigned long freqQE; +#ifdef CONFIG_SYS_DPAA_FMAN + unsigned long freqFMan[CONFIG_SYS_NUM_FMAN]; +#endif +#ifdef CONFIG_SYS_DPAA_PME + unsigned long freqPME; +#endif } MPC85xx_SYS_INFO; #endif /* _ASMLANGUAGE */ From 054197ba8ee5ef1e41694df58531b6e53ec43f2d Mon Sep 17 00:00:00 2001 From: Martha M Stan Date: Mon, 21 Sep 2009 14:07:14 -0400 Subject: [PATCH 177/208] mpc512x: Streamlined fixed_sdram() init sequence. Signed-off-by: Martha M Stan Minor cleanup: Re-ordered default_mddrc_config[] to have matching indices. This allows to use the same index "N" for source and target fields; before, we had code like this out_be32(&im->mddrc.ddr_time_config2, mddrc_config[3]); which always looked like a copy & paste error because 2 != 3. Also, use NULL when meaning a null pointer. Signed-off-by: Wolfgang Denk --- board/davedenx/aria/aria.c | 2 +- board/esd/mecp5123/mecp5123.c | 2 +- board/freescale/mpc5121ads/mpc5121ads.c | 2 +- cpu/mpc512x/fixed_sdram.c | 104 ++++++++++++++++-------- include/asm-ppc/immap_512x.h | 4 + include/asm-ppc/mpc512x.h | 2 +- include/configs/aria.h | 22 ++--- include/configs/mecp5123.h | 21 ++--- include/configs/mpc5121ads.h | 28 +++---- 9 files changed, 107 insertions(+), 80 deletions(-) diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c index 2064aa2c6c1..cc69c9d38e0 100644 --- a/board/davedenx/aria/aria.c +++ b/board/davedenx/aria/aria.c @@ -101,7 +101,7 @@ int board_early_init_f(void) phys_size_t initdram (int board_type) { - return fixed_sdram(); + return fixed_sdram(NULL, NULL, 0); } int misc_init_r(void) diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c index f591e326210..51393584438 100644 --- a/board/esd/mecp5123/mecp5123.c +++ b/board/esd/mecp5123/mecp5123.c @@ -135,7 +135,7 @@ int board_early_init_f(void) phys_size_t initdram(int board_type) { - return get_ram_size(0, fixed_sdram()); + return get_ram_size(0, fixed_sdram(NULL, NULL, 0)); } int misc_init_r(void) diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c index a0d7a82e4bb..8defb001a38 100644 --- a/board/freescale/mpc5121ads/mpc5121ads.c +++ b/board/freescale/mpc5121ads/mpc5121ads.c @@ -137,7 +137,7 @@ phys_size_t initdram(int board_type) { u32 msize = 0; - msize = fixed_sdram(); + msize = fixed_sdram(NULL, NULL, 0); return msize; } diff --git a/cpu/mpc512x/fixed_sdram.c b/cpu/mpc512x/fixed_sdram.c index d906903d28d..673d61ee100 100644 --- a/cpu/mpc512x/fixed_sdram.c +++ b/cpu/mpc512x/fixed_sdram.c @@ -25,18 +25,70 @@ #include #include +/* + * MDDRC Config Runtime Settings in order of the 4 MDDRC cfg registers + */ +u32 default_mddrc_config[4] = { + CONFIG_SYS_MDDRC_TIME_CFG0, /* time_config0 */ + CONFIG_SYS_MDDRC_TIME_CFG1, /* time_config1 */ + CONFIG_SYS_MDDRC_TIME_CFG2, /* time_config2 */ + CONFIG_SYS_MDDRC_SYS_CFG, /* sys_config */ +}; + +u32 default_init_seq[] = { + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_PCHG_ALL, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_RFSH, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_RFSH, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_MICRON_INIT_DEV_OP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_EM2, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_PCHG_ALL, + CONFIG_SYS_DDRCMD_EM2, + CONFIG_SYS_DDRCMD_EM3, + CONFIG_SYS_DDRCMD_EN_DLL, + CONFIG_SYS_MICRON_INIT_DEV_OP, + CONFIG_SYS_DDRCMD_PCHG_ALL, + CONFIG_SYS_DDRCMD_RFSH, + CONFIG_SYS_MICRON_INIT_DEV_OP, + CONFIG_SYS_DDRCMD_OCD_DEFAULT, + CONFIG_SYS_DDRCMD_PCHG_ALL, + CONFIG_SYS_DDRCMD_NOP +}; + /* * fixed sdram init: * The board doesn't use memory modules that have serial presence * detect or similar mechanism for discovery of the DRAM settings */ -long int fixed_sdram(void) +long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize); u32 i; + /* take default settings and init sequence if necessary */ + if (mddrc_config == NULL) + mddrc_config = default_mddrc_config; + if (dram_init_seq == NULL) { + dram_init_seq = default_init_seq; + seq_sz = sizeof(default_init_seq)/sizeof(u32); + } + /* Initialize IO Control */ out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR); @@ -45,8 +97,8 @@ long int fixed_sdram(void) out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1); sync_law(&im->sysconf.ddrlaw.ar); - /* Enable DDR */ - out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN); + /* DDR Enable */ + out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_EN); /* Initialize DDR Priority Manager */ out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1); @@ -73,41 +125,23 @@ long int fixed_sdram(void) out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU); out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL); - /* Initialize MDDRC */ - out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG); - out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0); - out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1); - out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2); + /* + * Initialize MDDRC + * put MDDRC in CMD mode and + * set the max time between refreshes to 0 during init process + */ + out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3] | MDDRC_SYS_CFG_CMD_MASK); + out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0] & MDDRC_REFRESH_ZERO_MASK); + out_be32(&im->mddrc.ddr_time_config1, mddrc_config[1]); + out_be32(&im->mddrc.ddr_time_config2, mddrc_config[2]); - /* Initialize DDR */ - for (i = 0; i < 10; i++) - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); + /* Initialize DDR with either default or supplied init sequence */ + for (i = 0; i < seq_sz; i++) + out_be32(&im->mddrc.ddr_command, dram_init_seq[i]); /* Start MDDRC */ - out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN); - out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN); + out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0]); + out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3]); return msize; } diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h index 24e6c6934ee..79cdd80298f 100644 --- a/include/asm-ppc/immap_512x.h +++ b/include/asm-ppc/immap_512x.h @@ -341,6 +341,10 @@ typedef struct ddr512x { u32 res2[0x3AD]; } ddr512x_t; +/* MDDRC SYS CFG and Timing CFG0 Registers */ +#define MDDRC_SYS_CFG_EN 0xF0000000 +#define MDDRC_SYS_CFG_CMD_MASK 0x10000000 +#define MDDRC_REFRESH_ZERO_MASK 0x0000FFFF /* * DMA/Messaging Unit diff --git a/include/asm-ppc/mpc512x.h b/include/asm-ppc/mpc512x.h index 20456f52f7d..8ef0d9ca6dd 100644 --- a/include/asm-ppc/mpc512x.h +++ b/include/asm-ppc/mpc512x.h @@ -50,7 +50,7 @@ static inline void sync_law(volatile void *addr) /* * Prototypes */ -extern long int fixed_sdram(void); +extern long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz); extern int mpc5121_diu_init(void); extern void ide_set_reset(int idereset); diff --git a/include/configs/aria.h b/include/configs/aria.h index 4211113d9e1..2938eac396d 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -126,7 +126,7 @@ #define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | /* RST_B */ \ (1 << 30) | /* CKE */ \ (1 << 29) | /* CLK_ON */ \ - (1 << 28) | /* CMD_MODE */ \ + (0 << 28) | /* CMD_MODE */ \ (4 << 25) | /* DRAM_ROW_SELECT */ \ (3 << 21) | /* DRAM_BANK_SELECT */ \ (0 << 18) | /* SELF_REF_EN */ \ @@ -143,16 +143,12 @@ (0 << 0) /* FIFO_UV_EN */ \ ) -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN (CONFIG_SYS_MDDRC_SYS_CFG & ~(1 << 28)) +#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E #define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189 #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863 -#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E -#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x030C3D2E - -#define CONFIG_SYS_MICRON_NOP 0x01380000 -#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 +#define CONFIG_SYS_DDRCMD_NOP 0x01380000 +#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 #define CONFIG_SYS_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \ (0 << 22) | /* DRAM_CS */ \ (0 << 21) | /* DRAM_RAS */ \ @@ -172,7 +168,7 @@ ) #define CONFIG_SYS_MICRON_EMR2 0x01020000 #define CONFIG_SYS_MICRON_EMR3 0x01030000 -#define CONFIG_SYS_MICRON_RFSH 0x01080000 +#define CONFIG_SYS_DDRCMD_RFSH 0x01080000 #define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 #define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | /* CMD_REQ */ \ (0 << 22) | /* DRAM_CS */ \ @@ -196,10 +192,10 @@ * Backward compatible definitions, * so we do not have to change cpu/mpc512x/fixed_sdram.c */ -#define CONFIG_SYS_MICRON_EM2 (CONFIG_SYS_MICRON_EMR2) -#define CONFIG_SYS_MICRON_EM3 (CONFIG_SYS_MICRON_EMR3) -#define CONFIG_SYS_MICRON_EN_DLL (CONFIG_SYS_MICRON_EMR) -#define CONFIG_SYS_MICRON_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD) +#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2) +#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3) +#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR) +#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD) /* DDR Priority Manager Configuration */ #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h index 1ecae005ce2..e194c8f7bbe 100644 --- a/include/configs/mecp5123.h +++ b/include/configs/mecp5123.h @@ -111,22 +111,19 @@ * [09:05] DRAM tRP: * [04:00] DRAM tRPA */ -#define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00 +#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00 +#define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E #define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 -#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E -#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E -#define CONFIG_SYS_MICRON_NOP 0x01380000 -#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 -#define CONFIG_SYS_MICRON_EM2 0x01020000 -#define CONFIG_SYS_MICRON_EM3 0x01030000 -#define CONFIG_SYS_MICRON_EN_DLL 0x01010000 -#define CONFIG_SYS_MICRON_RFSH 0x01080000 +#define CONFIG_SYS_DDRCMD_NOP 0x01380000 +#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 +#define CONFIG_SYS_DDRCMD_EM2 0x01020000 +#define CONFIG_SYS_DDRCMD_EM3 0x01030000 +#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000 +#define CONFIG_SYS_DDRCMD_RFSH 0x01080000 #define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780 +#define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x01010780 /* DDR Priority Manager Configuration */ #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index 76f174db3fa..0c871c91951 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -131,28 +131,24 @@ * [04:00] DRAM tRPA */ #ifdef CONFIG_MPC5121ADS_REV2 -#define CONFIG_SYS_MDDRC_SYS_CFG 0xF8604A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xE8604A00 +#define CONFIG_SYS_MDDRC_SYS_CFG 0xE8604A00 #define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168 #define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864 #else -#define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00 -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 +#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00 +#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 +#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 #endif -#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E -#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E +#define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E -#define CONFIG_SYS_MICRON_NOP 0x01380000 -#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 -#define CONFIG_SYS_MICRON_EM2 0x01020000 -#define CONFIG_SYS_MICRON_EM3 0x01030000 -#define CONFIG_SYS_MICRON_EN_DLL 0x01010000 -#define CONFIG_SYS_MICRON_RFSH 0x01080000 +#define CONFIG_SYS_DDRCMD_NOP 0x01380000 +#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 +#define CONFIG_SYS_DDRCMD_EM2 0x01020000 +#define CONFIG_SYS_DDRCMD_EM3 0x01030000 +#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000 +#define CONFIG_SYS_DDRCMD_RFSH 0x01080000 #define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780 +#define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x01010780 /* DDR Priority Manager Configuration */ #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 From a5aa3998ab6408a6ac738a3ce8005e647b9465f8 Mon Sep 17 00:00:00 2001 From: Martha M Stan Date: Mon, 21 Sep 2009 14:08:00 -0400 Subject: [PATCH 178/208] Add Elpida Memory Configuration to mpc5121ads Boards Signed-off-by: Martha M Stan Minor coding style cleanup. Signed-off-by: Wolfgang Denk --- board/freescale/mpc5121ads/mpc5121ads.c | 97 ++++++++++++++++++++++++- include/configs/mpc5121ads.h | 35 ++++++++- 2 files changed, 129 insertions(+), 3 deletions(-) diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c index 8defb001a38..3323d66a3c3 100644 --- a/board/freescale/mpc5121ads/mpc5121ads.c +++ b/board/freescale/mpc5121ads/mpc5121ads.c @@ -31,6 +31,7 @@ #ifdef CONFIG_MISC_INIT_R #include #endif +#include #include #include @@ -133,11 +134,105 @@ int board_early_init_f(void) return 0; } +int is_micron(void){ + + ushort brd_rev = *(vu_short *)(CONFIG_SYS_CPLD_BASE + 0x00); + uchar macaddr[6]; + u32 brddate, macchk, ismicron; + + /* + * MAC address has serial number with date of manufacture + * Boards made before Nov-08 #1180 use Micron memory; + * 001e59 is the STx vendor # + * Default is Elpida since it works for both but is slightly slower + */ + ismicron = 0; + if (brd_rev >= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr)) { + brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5]; + macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2]; + debug("brddate = %d\n\t", brddate); + + if (macchk == 0x001e59 && brddate <= 8111180) + ismicron = 1; + } else if (brd_rev < 0x400) { + ismicron = 1; + } + debug("Using %s Memory settings\n\t", + ismicron ? "Micron" : "Elpida"); + return(ismicron); +} + phys_size_t initdram(int board_type) { u32 msize = 0; + /* + * Elpida MDDRC and initialization settings are an alternative + * to the Default Micron ones for all but the earliest Rev 4 boards + */ + u32 elpida_mddrc_config[4] = { + CONFIG_SYS_MDDRC_TIME_CFG0, + CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA, + CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA + CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA, + }; - msize = fixed_sdram(NULL, NULL, 0); + u32 elpida_init_sequence[] = { + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_PCHG_ALL, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_RFSH, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_RFSH, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_EM2, + CONFIG_SYS_DDRCMD_EM3, + CONFIG_SYS_DDRCMD_EN_DLL, + CONFIG_SYS_ELPIDA_RES_DLL, + CONFIG_SYS_DDRCMD_PCHG_ALL, + CONFIG_SYS_DDRCMD_RFSH, + CONFIG_SYS_DDRCMD_RFSH, + CONFIG_SYS_DDRCMD_RFSH, + CONFIG_SYS_ELPIDA_INIT_DEV_OP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_OCD_DEFAULT, + CONFIG_SYS_ELPIDA_OCD_EXIT, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP + }; + + if (is_micron()) { + msize = fixed_sdram(NULL, NULL, 0); + } else { + msize = fixed_sdram(elpida_mddrc_config, + elpida_init_sequence, + sizeof(elpida_init_sequence)/sizeof(u32)); + } return msize; } diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index 0c871c91951..ebc518c03c1 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -141,14 +141,45 @@ #endif #define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E +#define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA 0xEA802B00 +#define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA 0x690e1189 +#define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA 0x35310864 + #define CONFIG_SYS_DDRCMD_NOP 0x01380000 #define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 #define CONFIG_SYS_DDRCMD_EM2 0x01020000 #define CONFIG_SYS_DDRCMD_EM3 0x01030000 #define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000 #define CONFIG_SYS_DDRCMD_RFSH 0x01080000 -#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x01010780 + +#define DDRCMD_EMR_OCD(pr, ohm) ( \ + (1 << 24) | /* MDDRC Command Request */ \ + (1 << 16) | /* MODE Reg BA[2:0] */ \ + (0 << 12) | /* Outputs 0=Enabled */ \ + (0 << 11) | /* RDQS */ \ + (1 << 10) | /* DQS# */ \ + (pr << 7) | /* OCD prog 7=deflt,0=exit */ \ + /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \ + ((ohm & 0x2) << 5)| /* Rtt1 */ \ + (0 << 3) | /* additive posted CAS# */ \ + ((ohm & 0x1) << 2)| /* Rtt0 */ \ + (0 << 0) | /* Output Drive Strength */ \ + (0 << 0)) /* DLL Enable 0=Normal */ + +#define CONFIG_SYS_DDRCMD_OCD_DEFAULT DDRCMD_EMR_OCD(7, 0) +#define CONFIG_SYS_ELPIDA_OCD_EXIT DDRCMD_EMR_OCD(0, 0) + +#define DDRCMD_MODE_REG(cas, wr) ( \ + (1 << 24) | /* MDDRC Command Request */ \ + (0 << 16) | /* MODE Reg BA[2:0] */ \ + ((wr-1) << 9)| /* Write Recovery */ \ + (cas << 4) | /* CAS */ \ + (0 << 3) | /* Burst Type:0=Sequential,1=Interleaved */ \ + (2 << 0)) /* 4 or 8 Burst Length:0x2=4 0x3=8 */ + +#define CONFIG_SYS_MICRON_INIT_DEV_OP DDRCMD_MODE_REG(3, 3) +#define CONFIG_SYS_ELPIDA_INIT_DEV_OP DDRCMD_MODE_REG(4, 4) +#define CONFIG_SYS_ELPIDA_RES_DLL (DDRCMD_MODE_REG(4, 4) | (1 << 8)) /* DDR Priority Manager Configuration */ #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 From 9d142ea8f787882ab732fa531a34db091bfa363d Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 25 Sep 2009 00:57:49 +0200 Subject: [PATCH 179/208] Fix "ppc/85xx: Clean up use of LAWAR defines" breakage Commit 002741ae86 modified include/asm-ppc/mmu.h such that the LAWAR_ defines were only enabled for the 83xx platform, but they are also needed on MPC512x system. Enabling these for E300 systems seems thus more appropriate. Signed-off-by: Wolfgang Denk --- include/asm-ppc/mmu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index d516d91403d..ec22a5058e1 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -504,7 +504,7 @@ extern int num_tlb_entries; #endif #endif -#ifdef CONFIG_MPC83xx +#ifdef CONFIG_E300 #define LAWAR_EN 0x80000000 #define LAWAR_SIZE 0x0000003F From 7f625fc6d3ba8f890e843ac01717804c2462ed53 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 23 Sep 2009 07:56:04 +0200 Subject: [PATCH 180/208] mpc5200, mucmc52, uc101: config cleanup - As these boards are similiar, collect common config options in manroland/common.h and manroland/mpc52xx-common.h for mpc5200 specific common options for this manufacturer. - add OF support - update default environment Signed-off-by: Heiko Schocher Minor edit of commit message. Signed-off-by: Wolfgang Denk --- board/mucmc52/mucmc52.c | 7 + board/uc101/uc101.c | 7 + include/configs/manroland/common.h | 141 +++++++++++ include/configs/manroland/mpc5200-common.h | 229 ++++++++++++++++++ include/configs/mucmc52.h | 257 +------------------- include/configs/uc101.h | 267 +-------------------- 6 files changed, 404 insertions(+), 504 deletions(-) create mode 100644 include/configs/manroland/common.h create mode 100644 include/configs/manroland/mpc5200-common.h diff --git a/board/mucmc52/mucmc52.c b/board/mucmc52/mucmc52.c index 7181bd8a423..bac49befffe 100644 --- a/board/mucmc52/mucmc52.c +++ b/board/mucmc52/mucmc52.c @@ -398,3 +398,10 @@ void pci_init_board (void) pci_mpc5xxx_init (&hose); } #endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/uc101/uc101.c b/board/uc101/uc101.c index 7df349f3e54..4030b9d0d83 100644 --- a/board/uc101/uc101.c +++ b/board/uc101/uc101.c @@ -371,3 +371,10 @@ void hw_watchdog_reset(void) *(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_0; } #endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/include/configs/manroland/common.h b/include/configs/manroland/common.h new file mode 100644 index 00000000000..c0122b7a695 --- /dev/null +++ b/include/configs/manroland/common.h @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2009 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MANROLAND_COMMON_H +#define __MANROLAND_COMMON_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_BOARD_EARLY_INIT_R + +/* Partitions */ +#define CONFIG_DOS_PARTITION + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DISPLAY +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_DTT +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_NFS +#define CONFIG_CMD_MII +#define CONFIG_CMD_SNTP + +#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define xstr(s) str(s) +#define str(s) #s + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addwdt=setenv bootargs ${bootargs} wdt=off\0" \ + "logval=4\0" \ + "addlog=setenv bootargs ${bootargs} loglevel=${logval}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "kernel_addr=ff810000\0" \ + "fdt_addr="xstr(CONFIG_SYS_FLASH_BASE)"\0" \ + "flash_nfs=run nfsargs addip addcon addwdt addlog;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ + "kernel_addr_r=300000\0" \ + "fdt_addr_r=200000\0" \ + "fdt_file=" xstr(CONFIG_HOSTNAME) "/" \ + xstr(CONFIG_HOSTNAME) ".dtb\0" \ + "kernel_file=" xstr(CONFIG_HOSTNAME) "/uImage \0" \ + "load_fdt=tftp ${fdt_addr_r} ${fdt_file};\0" \ + "load_kernel=tftp ${kernel_addr_r} ${kernel_file};\0" \ + "addcon=setenv bootargs ${bootargs} console=ttyPSC0,${baudrate}\0"\ + "net_nfs=run load_fdt load_kernel; " \ + "run nfsargs addip addcon addwdt addlog;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin \0" \ + "u-boot_addr_r=200000\0" \ + "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ + "update=protect off " xstr(TEXT_BASE) " +${filesize};" \ + "erase " xstr(TEXT_BASE) " +${filesize};" \ + "cp.b ${u-boot_addr_r} " xstr(TEXT_BASE) \ + " ${filesize};" \ + "protect on " xstr(TEXT_BASE) " +${filesize}\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run net_nfs" + +#define CONFIG_MISC_INIT_R 1 + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* Enable an alternate, more extensive memory test */ +#define CONFIG_SYS_ALT_MEMTEST + +/* + * Enable loopw command. + */ +#define CONFIG_LOOPW + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#endif /* __MANROLAND_COMMON_H */ diff --git a/include/configs/manroland/mpc5200-common.h b/include/configs/manroland/mpc5200-common.h new file mode 100644 index 00000000000..2f092b18072 --- /dev/null +++ b/include/configs/manroland/mpc5200-common.h @@ -0,0 +1,229 @@ +/* + * (C) Copyright 2009 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MANROLAND_MPC52XX__COMMON_H +#define __MANROLAND_MPC52XX__COMMON_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ + +#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200,\ + 230400 } + +#if (TEXT_BASE == 0xFFF00000) /* Boot low */ +# define CONFIG_SYS_LOWBOOT 1 +#endif + +/* + * IPB Bus clocking configuration. + */ +#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ + +#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ +#define CONFIG_SYS_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* + * RTC configuration + */ +#define CONFIG_RTC_PCF8563 +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 + +/* I2C SYSMON (LM75) */ +#define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CONFIG_SYS_DTT_MAX_TEMP 70 +#define CONFIG_SYS_DTT_LOW_TEMP -30 +#define CONFIG_SYS_DTT_HYSTERESIS 3 + +/* + * Flash configuration + */ +#define CONFIG_SYS_FLASH_BASE 0xFF800000 + +#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ + +#define CONFIG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks + (= chip selects) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout [ms]*/ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout [ms]*/ + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_CFI_AMD_RESET + +/* + * Environment settings + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SIZE 0x4000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +/* + * Memory map + */ +#define CONFIG_SYS_MBAR 0xF0000000 +#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 + +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END -\ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SRAM_BASE 0x80100000 /* CS 1 */ +#define CONFIG_SYS_DISPLAY_BASE 0x80600000 /* CS 3 */ + +/* Settings for XLB = 132 MHz */ +#define SDRAM_DDR 1 +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + +/* Use ON-Chip SRAM until RAM will be available */ +#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM +#ifdef CONFIG_POST +/* preserve space for the post_word at end of on-chip SRAM */ +#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE +#else +#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE +#endif + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +# define CONFIG_SYS_RAMBOOT 1 +#endif + +#define CONFIG_SYS_MONITOR_LEN (192 << 10) +#define CONFIG_SYS_MALLOC_LEN (512 << 10) +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 +#define CONFIG_PHY_ADDR 0x00 +#define CONFIG_MII 1 + +/*use Hardware WDT */ +#define CONFIG_HW_WATCHDOG + +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ +#endif + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI +#define CONFIG_SYS_HID0_FINAL HID0_ICE +#else +#define CONFIG_SYS_HID0_INIT 0 +#define CONFIG_SYS_HID0_FINAL 0 +#endif + +#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE +#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE + +/* 8Mbit SRAM @0x80100000 */ +#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE + +#define CONFIG_SYS_CS_BURST 0x00000000 +#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 + +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ + +#define CONFIG_IDE_PREINIT 1 + +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 + +#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA + +/* Offset for data I/O */ +#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) + +/* Offset for normal register accesses */ +#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) + +/* Interval between registers */ +#define CONFIG_SYS_ATA_STRIDE 4 + +#define CONFIG_ATAPI 1 + +#define OF_CPU "PowerPC,5200@0" +#define OF_SOC "soc5200@f0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" + +#endif /* __MANROLAND_MPC52XX__COMMON_H */ diff --git a/include/configs/mucmc52.h b/include/configs/mucmc52.h index ae60cd2215f..07ed0461994 100644 --- a/include/configs/mucmc52.h +++ b/include/configs/mucmc52.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2008 + * (C) Copyright 2008-2009 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * * (C) Copyright 2003-2005 @@ -32,260 +32,51 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_MUCMC52 1 /* MUCMC52 board */ +#define CONFIG_MUCMC52 1 /* MUCMC52 board */ +#define CONFIG_HOSTNAME mucmc52 -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CONFIG_SYS_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CONFIG_BOARD_EARLY_INIT_R +#include "manroland/common.h" +#include "manroland/mpc5200-common.h" #define CONFIG_LAST_STAGE_INIT - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* * Serial console configuration */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ #define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -/* Partitions */ -#define CONFIG_DOS_PARTITION - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DISPLAY -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DTT -#define CONFIG_CMD_IDE -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SNTP - -#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ - -#if (TEXT_BASE == 0xFFF00000) /* Boot low */ -# define CONFIG_SYS_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#define CONFIG_MISC_INIT_R 1 - -/* - * IPB Bus clocking configuration. - */ -#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/* I2C SYSMON (LM75) */ -#define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 /* * Flash configuration */ -#define CONFIG_SYS_FLASH_BASE 0xFF800000 - -#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */ - -#define CONFIG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_CFI_AMD_RESET +#define CONFIG_SYS_MAX_FLASH_SECT 67 /* * Environment settings */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x4000 #define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) /* * Memory map */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 -#define CONFIG_SYS_DISPLAY_BASE 0x80600000 #define CONFIG_SYS_STATUS1_BASE 0x80600200 #define CONFIG_SYS_STATUS2_BASE 0x80600300 #define CONFIG_SYS_PMI_UNI_BASE 0x80800000 #define CONFIG_SYS_PMI_BROAD_BASE 0x80810000 -/* Settings for XLB = 132 MHz */ -#define SDRAM_DDR 1 -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE -#else -#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE -#endif - -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_MII 1 /* MII PHY management */ - /* * GPIO configuration */ #define CONFIG_SYS_GPS_PORT_CONFIG 0x8D550644 -/*use Hardware WDT */ -#define CONFIG_HW_WATCHDOG +#define CONFIG_SYS_MEMTEST_START 0x00100000 +#define CONFIG_SYS_MEMTEST_END 0x00f00000 -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CONFIG_SYS_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_LOAD_ADDR 0x100000 -/* Enable an alternate, more extensive memory test */ -#define CONFIG_SYS_ALT_MEMTEST - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Enable loopw commando. This has only affect, if CONFIG_SYS_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) - */ -#define CONFIG_LOOPW - -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE #define CONFIG_SYS_BOOTCS_CFG 0x0004FB00 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE /* 8Mbit SRAM @0x80100000 */ -#define CONFIG_SYS_CS1_START 0x80100000 #define CONFIG_SYS_CS1_SIZE 0x00100000 #define CONFIG_SYS_CS1_CFG 0x00019B00 @@ -309,42 +100,12 @@ #define CONFIG_SYS_CS7_SIZE 0x00008000 #define CONFIG_SYS_CS7_CFG 0xFF00F930 -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - /*----------------------------------------------------------------------- * IDE/ATA stuff Supports IDE harddisk *----------------------------------------------------------------------- */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */ -#define CONFIG_IDE_PREINIT 1 - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#define CONFIG_ATAPI 1 - /* * PCI Mapping: * 0x40000000 - 0x4fffffff - PCI Memory diff --git a/include/configs/uc101.h b/include/configs/uc101.h index 87cb4e508b1..fc0b103fbb4 100644 --- a/include/configs/uc101.h +++ b/include/configs/uc101.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2003-2006 + * (C) Copyright 2003-2009 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * * See file CREDITS for list of people who contributed to this @@ -29,29 +29,16 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_UC101 1 /* UC101 board */ +#define CONFIG_UC101 1 /* UC101 board */ +#define CONFIG_HOSTNAME uc101 -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_BOARD_EARLY_INIT_R - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ +#include "manroland/common.h" +#include "manroland/mpc5200-common.h" /* * Serial console configuration */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* Partitions */ -#define CONFIG_DOS_PARTITION - /* * BOOTP options @@ -61,243 +48,40 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DISPLAY -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DTT -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_NFS -#define CONFIG_CMD_MII -#define CONFIG_CMD_SNTP - - -#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ - -#if (TEXT_BASE == 0xFFF00000) /* Boot low */ -# define CONFIG_SYS_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addwdt=setenv bootargs ${bootargs} wdt=off" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 300000 ${bootfile};run nfsargs addip addwdt;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#define CONFIG_MISC_INIT_R 1 - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/* I2C SYSMON (LM75) */ -#define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 - /* * Flash configuration */ -#define CONFIG_SYS_FLASH_BASE 0xFF800000 - -#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CONFIG_SYS_MAX_FLASH_SECT 140 /* max num of sects on one chip */ - -#define CONFIG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_CFI_AMD_RESET +#define CONFIG_SYS_MAX_FLASH_SECT 140 /* * Environment settings */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x4000 #define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) /* * Memory map */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SRAM_BASE 0x80100000 /* CS 1 */ -#define CONFIG_SYS_DISPLAY_BASE 0x80600000 /* CS 3 */ #define CONFIG_SYS_IB_MASTER 0xc0510000 /* CS 6 */ #define CONFIG_SYS_IB_EPLD 0xc0500000 /* CS 7 */ -/* Settings for XLB = 132 MHz */ -#define SDRAM_DDR 1 -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 - /* SRAM */ -#define SRAM_BASE CONFIG_SYS_SRAM_BASE /* SRAM base address */ +#define SRAM_BASE CONFIG_SYS_SRAM_BASE #define SRAM_LEN 0x1fffff #define SRAM_END (SRAM_BASE + SRAM_LEN) -/* Use ON-Chip SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE -#else -#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE -#endif - - -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_MII 1 - /* * GPIO configuration */ #define CONFIG_SYS_GPS_PORT_CONFIG 0x4d558044 -/*use Hardware WDT */ -#define CONFIG_HW_WATCHDOG +#define CONFIG_SYS_MEMTEST_START 0x00300000 +#define CONFIG_SYS_MEMTEST_END 0x00f00000 -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_LOAD_ADDR 0x300000 -/* Enable an alternate, more extensive memory test */ -#define CONFIG_SYS_ALT_MEMTEST - -#define CONFIG_SYS_MEMTEST_START 0x00300000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 3 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x300000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Enable loopw command. - */ -#define CONFIG_LOOPW - -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE #define CONFIG_SYS_BOOTCS_CFG 0x00045D00 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE /* 8Mbit SRAM @0x80100000 */ -#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE #define CONFIG_SYS_CS1_SIZE 0x00200000 #define CONFIG_SYS_CS1_CFG 0x21D00 @@ -316,41 +100,12 @@ #define CONFIG_SYS_CS7_SIZE 0x00010000 #define CONFIG_SYS_CS7_CFG 0x00081800 -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - /*----------------------------------------------------------------------- * IDE/ATA stuff Supports IDE harddisk *----------------------------------------------------------------------- */ -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ - -#define CONFIG_IDE_PREINIT 1 - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#define CONFIG_ATAPI 1 +#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus*/ /*---------------------------------------------------------------------*/ /* Display addresses */ From 3887c3fbdbbe6bbb4df60ed415c8e1ab9fe56b5e Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 23 Sep 2009 07:56:08 +0200 Subject: [PATCH 181/208] mucmc52, uc101: delete ata@3a00 node, if no CF card is detected U-Boot can detect if an IDE device is present or not. If not, and this new config option is activated, U-Boot removes the ATA node from the DTS before booting Linux, so the Linux IDE driver does not probe the device and crash. This is needed for buggy hardware (uc101) where no pull down resistor is connected to the signal IDE5V_DD7. Signed-off-by: Heiko Schocher --- README | 9 +++++++++ common/cmd_ide.c | 8 ++++++++ cpu/mpc5xxx/cpu.c | 20 ++++++++++++++++++++ include/configs/manroland/mpc5200-common.h | 1 + include/ide.h | 3 +++ 5 files changed, 41 insertions(+) diff --git a/README b/README index ce86e74baf3..dee0e674a18 100644 --- a/README +++ b/README @@ -388,6 +388,15 @@ The following options need to be configured: This define fills in the correct boot CPU in the boot param header, the default value is zero if undefined. + CONFIG_OF_IDE_FIXUP + + U-Boot can detect if an IDE device is present or not. + If not, and this new config option is activated, U-Boot + removes the ATA node from the DTS before booting Linux, + so the Linux IDE driver does not probe the device and + crash. This is needed for buggy hardware (uc101) where + no pull down resistor is connected to the signal IDE5V_DD7. + - vxWorks boot parameters: bootvx constructs a valid bootline using the following diff --git a/common/cmd_ide.c b/common/cmd_ide.c index 4d7a0ac9e46..ec9a1df38e7 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -1624,6 +1624,14 @@ static void ide_led (uchar led, uchar status) #endif /* CONFIG_IDE_LED */ +#if defined(CONFIG_OF_IDE_FIXUP) +int ide_device_present(int dev) +{ + if (dev >= CONFIG_SYS_IDE_MAXBUS) + return 0; + return (ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN ? 0 : 1); +} +#endif /* ------------------------------------------------------------------------- */ #ifdef CONFIG_ATAPI diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c index f6258c7be60..efa64c74815 100644 --- a/cpu/mpc5xxx/cpu.c +++ b/cpu/mpc5xxx/cpu.c @@ -40,6 +40,10 @@ #include #endif +#if defined(CONFIG_OF_IDE_FIXUP) +#include +#endif + DECLARE_GLOBAL_DATA_PTR; int checkcpu (void) @@ -137,6 +141,22 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_path(blob, eth_path, "mac-address", enetaddr, 6, 0); do_fixup_by_path(blob, eth_path, "local-mac-address", enetaddr, 6, 0); #endif +#if defined(CONFIG_OF_IDE_FIXUP) + if (!ide_device_present(0)) { + /* NO CF card detected -> delete ata node in DTS */ + int nodeoffset = 0; + char nodename[] = "/soc5200@f0000000/ata@3a00"; + + nodeoffset = fdt_path_offset(blob, nodename); + if (nodeoffset >= 0) { + fdt_del_node(blob, nodeoffset); + } else { + printf("%s: cannot find %s node err:%s\n", + __func__, nodename, fdt_strerror(nodeoffset)); + } + } + +#endif } #endif diff --git a/include/configs/manroland/mpc5200-common.h b/include/configs/manroland/mpc5200-common.h index 2f092b18072..b29ef9b6559 100644 --- a/include/configs/manroland/mpc5200-common.h +++ b/include/configs/manroland/mpc5200-common.h @@ -225,5 +225,6 @@ #define OF_SOC "soc5200@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" +#define CONFIG_OF_IDE_FIXUP #endif /* __MANROLAND_MPC52XX__COMMON_H */ diff --git a/include/ide.h b/include/ide.h index ddb9579f8fa..6a1b7ae844f 100644 --- a/include/ide.h +++ b/include/ide.h @@ -54,4 +54,7 @@ void ide_init(void); ulong ide_read(int device, lbaint_t blknr, ulong blkcnt, void *buffer); ulong ide_write(int device, lbaint_t blknr, ulong blkcnt, void *buffer); +#if defined(CONFIG_OF_IDE_FIXUP) +int ide_device_present(int dev); +#endif #endif /* _IDE_H */ From 6e748ea004473cce99fbde6382dd580c10ffdb60 Mon Sep 17 00:00:00 2001 From: Ken MacLeod Date: Fri, 11 Sep 2009 15:16:18 -0500 Subject: [PATCH 182/208] cmd_fdt.c: fix parse of byte streams and strings Commit 4abd844d8e extended the fdt command parser to handle property strings which are split across multiple arguments but it was broken for byte streams and strings. Byte stream parsing: * Fixes where it would terminate early or go into an endless loop. * Fixes a 0x00 being inserted into the data if there is a space after '[' or a separate argument. * Fixes dereferencing the argument pointer after the last argument. * Checks for bad characters. String parsing: * Treat multiple arguments as a string list. This fixes an issue where only the last argument was stored. Signed-off-by: Ken MacLeod --- common/cmd_fdt.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c index 86837723b55..919a0bf6e78 100644 --- a/common/cmd_fdt.c +++ b/common/cmd_fdt.c @@ -574,14 +574,18 @@ static int fdt_parse_prop(char **newval, int count, char *data, int *len) * Byte stream. Convert the values. */ newp++; - while ((*newp != ']') && (stridx < count)) { + while ((stridx < count) && (*newp != ']')) { + while (*newp == ' ') + newp++; + if (*newp == '\0') { + newp = newval[++stridx]; + continue; + } + if (!isxdigit(*newp)) + break; tmp = simple_strtoul(newp, &newp, 16); *data++ = tmp & 0xFF; *len = *len + 1; - while (*newp == ' ') - newp++; - if (*newp != '\0') - newp = newval[++stridx]; } if (*newp != ']') { printf("Unexpected character '%c'\n", *newp); @@ -589,12 +593,15 @@ static int fdt_parse_prop(char **newval, int count, char *data, int *len) } } else { /* - * Assume it is a string. Copy it into our data area for - * convenience (including the terminating '\0'). + * Assume it is one or more strings. Copy it into our + * data area for convenience (including the + * terminating '\0's). */ while (stridx < count) { - *len = strlen(newp) + 1; + size_t length = strlen(newp) + 1; strcpy(data, newp); + data += length; + *len += length; newp = newval[++stridx]; } } From 984f10baac8ef6032df52f135943d6b0bc96f724 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 25 Sep 2009 14:16:00 +0200 Subject: [PATCH 183/208] mpc5121ads: fix breakage introduced when reordering elpida_mddrc_config[] Signed-off-by: Wolfgang Denk --- board/freescale/mpc5121ads/mpc5121ads.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c index 3323d66a3c3..13bd73c81e9 100644 --- a/board/freescale/mpc5121ads/mpc5121ads.c +++ b/board/freescale/mpc5121ads/mpc5121ads.c @@ -172,7 +172,7 @@ phys_size_t initdram(int board_type) u32 elpida_mddrc_config[4] = { CONFIG_SYS_MDDRC_TIME_CFG0, CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA, - CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA + CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA, CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA, }; From 6185f80c311cc3bdef2f8d5096c61e40ca6f48b2 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Wed, 16 Sep 2009 23:21:53 +0400 Subject: [PATCH 184/208] net: uec_phy: Implement TXID and RXID RGMII modes for Marvell PHYs This will be needed for MPC8360E-MDS boards with rev. 2.1 CPUs. Signed-off-by: Anton Vorontsov Signed-off-by: Kim Phillips --- drivers/qe/uec.h | 1 + drivers/qe/uec_phy.c | 15 +++++++++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h index 1568310090b..df6f7c98781 100644 --- a/drivers/qe/uec.h +++ b/drivers/qe/uec.h @@ -670,6 +670,7 @@ typedef enum enet_interface { ENET_1000_RGMII, ENET_1000_RGMII_ID, ENET_1000_RGMII_RXID, + ENET_1000_RGMII_TXID, ENET_1000_TBI, ENET_1000_RTBI, ENET_1000_SGMII diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index aa4eb5e3893..97151839428 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -429,12 +429,23 @@ static int marvell_init(struct uec_mii_info *mii_info) { struct eth_device *edev = mii_info->dev; uec_private_t *uec = edev->priv; + enum enet_interface iface = uec->uec_info->enet_interface; - if (uec->uec_info->enet_interface == ENET_1000_RGMII_ID) { + if (iface == ENET_1000_RGMII_ID || + iface == ENET_1000_RGMII_RXID || + iface == ENET_1000_RGMII_TXID) { int temp; temp = phy_read(mii_info, MII_M1111_PHY_EXT_CR); - temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY); + if (iface == ENET_1000_RGMII_ID) { + temp |= MII_M1111_RX_DELAY | MII_M1111_TX_DELAY; + } else if (iface == ENET_1000_RGMII_RXID) { + temp &= ~MII_M1111_TX_DELAY; + temp |= MII_M1111_RX_DELAY; + } else if (iface == ENET_1000_RGMII_TXID) { + temp &= ~MII_M1111_RX_DELAY; + temp |= MII_M1111_TX_DELAY; + } phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp); temp = phy_read(mii_info, MII_M1111_PHY_EXT_SR); From d77c779bc23596aa3693d1c5c4d5b6e1072f93f2 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Wed, 16 Sep 2009 23:21:55 +0400 Subject: [PATCH 185/208] net: uec: Fix uccf.h and uec.h headers to include headers they depend on Headers should include headers containing prototypes and defines they depend on, don't assume that they're included by somebody else. Signed-off-by: Anton Vorontsov Signed-off-by: Kim Phillips --- drivers/qe/uccf.h | 1 + drivers/qe/uec.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/qe/uccf.h b/drivers/qe/uccf.h index 1ff9e1daf59..2404c6a8f0e 100644 --- a/drivers/qe/uccf.h +++ b/drivers/qe/uccf.h @@ -25,6 +25,7 @@ #include "common.h" #include "qe.h" +#include "asm/immap_qe.h" /* Fast or Giga ethernet */ diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h index df6f7c98781..febfbcef532 100644 --- a/drivers/qe/uec.h +++ b/drivers/qe/uec.h @@ -23,6 +23,9 @@ #ifndef __UEC_H__ #define __UEC_H__ +#include "qe.h" +#include "uccf.h" + #define MAX_TX_THREADS 8 #define MAX_RX_THREADS 8 #define MAX_TX_QUEUES 8 From 034477bb31948d698d18b84bc0834c3e25a14d04 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Wed, 16 Sep 2009 23:21:57 +0400 Subject: [PATCH 186/208] mpc83xx: mpc8360emds: Don't use LBC SDRAM when DDR is available Since commit 5c2ff323a94e27e481f70c44838d43fcd844dd46 ("mpc8360emds: rework LBC SDRAM setup"), LBC SDRAM is available for use in Linux. Though, it appears that QE Ethernet in Gigabit mode can't transmit large packets when it tries to work with a data in LBC SDRAM (memtest didn't discover any issues, is LBC SDRAM just too slow?). With this patch we can still use the board without DDR memory, but if DDR is available, we don't use LBC SDRAM. Signed-off-by: Anton Vorontsov Signed-off-by: Kim Phillips --- board/freescale/mpc8360emds/mpc8360emds.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index dc4dbd3c3a5..769eb2f11f4 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -126,6 +126,7 @@ phys_size_t initdram(int board_type) { volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 msize = 0; + u32 lbc_sdram_size; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) return -1; @@ -147,7 +148,9 @@ phys_size_t initdram(int board_type) /* * Initialize SDRAM if it is on local bus. */ - msize += sdram_init(msize * 1024 * 1024); + lbc_sdram_size = sdram_init(msize * 1024 * 1024); + if (!msize) + msize = lbc_sdram_size; /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); From 89da44ce3fe1638312d71cb3add8c6a6d2c7c1f3 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Wed, 16 Sep 2009 23:21:59 +0400 Subject: [PATCH 187/208] mpc83xx: mpc8360emds: Use RGMII-ID mode, add workarounds for rev. 2.1 CPUs This patch fixes various ethernet issues with gigabit links handling in U-Boot. The workarounds originally implemented by Kim Phillips for Linux kernel. Signed-off-by: Anton Vorontsov Signed-off-by: Kim Phillips --- board/freescale/mpc8360emds/mpc8360emds.c | 56 ++++++++++++++++++++--- include/configs/MPC8360EMDS.h | 4 +- 2 files changed, 52 insertions(+), 8 deletions(-) diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 769eb2f11f4..54f2989990a 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -21,12 +21,14 @@ #endif #include #include +#include #if defined(CONFIG_OF_LIBFDT) #include #endif #if defined(CONFIG_PQ_MDS_PIB) #include "../common/pq-mds-pib.h" #endif +#include "../../../drivers/qe/uec.h" const qe_iop_conf_t qe_iop_conf_tab[] = { /* GETH1 */ @@ -89,11 +91,19 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ }; +/* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */ +static int board_handle_erratum2(void) +{ + const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + + return REVID_MAJOR(immr->sysconf.spridr) == 2 && + REVID_MINOR(immr->sysconf.spridr) == 1; +} + int board_early_init_f(void) { - - u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; /* Enable flash write */ bcsr[0xa] &= ~0x04; @@ -105,6 +115,21 @@ int board_early_init_f(void) /* Enable second UART */ bcsr[0x9] &= ~0x01; + if (board_handle_erratum2()) { + void *immap = (immap_t *)(CONFIG_SYS_IMMR + 0x14a8); + + /* + * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) + * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) + */ + setbits_be32(immap, 0x0c003000); + + /* + * IMMR + 0x14AC[20:27] = 10101010 + * (data delay for both UCC's) + */ + clrsetbits_be32(immap + 4, 0xff0, 0xaa0); + } return 0; } @@ -116,6 +141,28 @@ int board_early_init_r(void) return 0; } +#ifdef CONFIG_UEC_ETH +static uec_info_t uec_info[] = { +#ifdef CONFIG_UEC_ETH1 + STD_UEC_INFO(1), +#endif +#ifdef CONFIG_UEC_ETH2 + STD_UEC_INFO(2), +#endif +}; + +int board_eth_init(bd_t *bd) +{ + if (board_handle_erratum2()) { + int i; + + for (i = 0; i < ARRAY_SIZE(uec_info); i++) + uec_info[i].enet_interface = ENET_1000_RGMII_RXID; + } + return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info)); +} +#endif /* CONFIG_UEC_ETH */ + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif @@ -312,8 +359,6 @@ static int sdram_init(unsigned int base) { return 0; } #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { - const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); @@ -323,8 +368,7 @@ void ft_board_setup(void *blob, bd_t *bd) * if on mpc8360ea rev. 2.1, * change both ucc phy-connection-types from rgmii-id to rgmii-rxid */ - if ((REVID_MAJOR(immr->sysconf.spridr) == 2) && - (REVID_MINOR(immr->sysconf.spridr) == 1)) { + if (board_handle_erratum2()) { int nodeoffset; const char *prop; int path; diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index b072e84473b..fec7cc58551 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -397,7 +397,7 @@ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_GMII +#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID #endif #define CONFIG_UEC_ETH2 /* GETH2 */ @@ -408,7 +408,7 @@ #define CONFIG_SYS_UEC2_TX_CLK QE_CLK4 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 1 -#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_GMII +#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID #endif /* From da6eea0f48c24a318e6de69d6bca0bb5ab70572b Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Wed, 16 Sep 2009 23:22:08 +0400 Subject: [PATCH 188/208] mpc83xx: mpc8360emds: Add QE USB device tree fixups With this patch we can change QE USB mode without need to hand-edit the device tree. Signed-off-by: Anton Vorontsov Signed-off-by: Kim Phillips --- board/freescale/mpc8360emds/mpc8360emds.c | 12 ++++++++++++ include/configs/MPC8360EMDS.h | 2 ++ 2 files changed, 14 insertions(+) diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 54f2989990a..d4ba043b283 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -25,6 +25,8 @@ #if defined(CONFIG_OF_LIBFDT) #include #endif +#include +#include #if defined(CONFIG_PQ_MDS_PIB) #include "../common/pq-mds-pib.h" #endif @@ -357,12 +359,22 @@ static int sdram_init(unsigned int base) { return 0; } #endif #if defined(CONFIG_OF_BOARD_SETUP) +static void ft_board_fixup_qe_usb(void *blob, bd_t *bd) +{ + if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) + return; + + do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode", + "peripheral", sizeof("peripheral"), 1); +} + void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + ft_board_fixup_qe_usb(blob, bd); /* * mpc8360ea pb mds errata 2: RGMII timing * if on mpc8360ea rev. 2.1, diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index fec7cc58551..62cf13be6d1 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -382,6 +382,8 @@ #define CONFIG_NET_MULTI 1 #endif +#define CONFIG_HWCONFIG 1 + /* * QE UEC ethernet configuration */ From 00ec0ff549b8cb6fb6d40e275aeb5a460642a3bd Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Mon, 21 Sep 2009 17:44:51 -0400 Subject: [PATCH 189/208] sbc8349: tidy up Makefile to use new configuration script. Commit 804d83a5 allows us to move all the configuration variation tweaks out of the top level Makefile and down into the board config header. This takes advantage of that for the sbc8349 board. Signed-off-by: Paul Gortmaker Signed-off-by: Kim Phillips --- Makefile | 15 +-------------- include/configs/sbc8349.h | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/Makefile b/Makefile index 9c5b2a5c9a3..8ab864d0cb2 100644 --- a/Makefile +++ b/Makefile @@ -2403,20 +2403,7 @@ MVBLM7_config: unconfig sbc8349_config \ sbc8349_PCI_33_config \ sbc8349_PCI_66_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _PCI_,$@)" ] ; then \ - $(XECHO) -n "... PCI HOST at " ; \ - echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \ - fi ; \ - if [ "$(findstring _33_,$@)" ] ; then \ - $(XECHO) -n "33MHz... " ; \ - echo "#define PCI_33M" >>$(obj)include/config.h ; \ - fi ; \ - if [ "$(findstring _66_,$@)" ] ; then \ - $(XECHO) -n "66MHz... " ; \ - echo "#define PCI_66M" >>$(obj)include/config.h ; \ - fi ; - @$(MKCONFIG) -a sbc8349 ppc mpc83xx sbc8349 + @$(MKCONFIG) -t $(@:_config=) sbc8349 ppc mpc83xx sbc8349 SIMPC8313_LP_config \ SIMPC8313_SP_config: unconfig diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index e961bb3929f..6f574ca6bf4 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -31,6 +31,21 @@ #ifndef __CONFIG_H #define __CONFIG_H +/* + * Top level Makefile configuration choices + */ +#ifdef CONFIG_MK_PCI +#define CONFIG_PCI +#endif + +#ifdef CONFIG_MK_66 +#define PCI_66M +#endif + +#ifdef CONFIG_MK_33 +#define PCI_33M +#endif + /* * High Level Configuration Options */ From c7190f028fa950d4d36b6d0b4bb3fc72602ec54c Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Fri, 25 Sep 2009 18:19:44 -0500 Subject: [PATCH 190/208] mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS__ assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips --- cpu/mpc83xx/cpu_init.c | 277 ++++++++++++++++++++-------------- include/configs/MPC8313ERDB.h | 3 +- include/configs/MPC8315ERDB.h | 3 +- include/configs/MPC8323ERDB.h | 3 +- include/configs/MPC832XEMDS.h | 3 +- include/configs/MPC8349EMDS.h | 3 +- include/configs/MPC8349ITX.h | 3 +- include/configs/MPC8360EMDS.h | 3 +- include/configs/MPC8360ERDK.h | 3 +- include/configs/MPC837XEMDS.h | 3 +- include/configs/MPC837XERDB.h | 3 +- include/configs/MVBLM7.h | 3 +- include/configs/SIMPC8313.h | 4 +- include/configs/TQM834x.h | 3 +- include/configs/kmeter1.h | 4 +- include/configs/sbc8349.h | 3 +- include/configs/vme8349.h | 3 +- 17 files changed, 196 insertions(+), 131 deletions(-) diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 5c930d38880..031e8d5744f 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -23,8 +23,8 @@ #include #include #include -#ifdef CONFIG_USB_EHCI_FSL #include +#ifdef CONFIG_USB_EHCI_FSL #include #endif @@ -63,6 +63,115 @@ static void config_qe_ioports(void) */ void cpu_init_f (volatile immap_t * im) { + __be32 acr_mask = +#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */ + (ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) | +#endif +#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */ + (ACR_RPTCNT << ACR_RPTCNT_SHIFT) | +#endif + 0; + __be32 acr_val = +#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */ + (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) | +#endif +#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */ + (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) | +#endif + 0; + __be32 spcr_mask = +#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */ + (SPCR_OPT << SPCR_OPT_SHIFT) | +#endif +#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */ + (SPCR_TSECEP << SPCR_TSECEP_SHIFT) | +#endif +#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */ + (SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) | +#endif +#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */ + (SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) | +#endif + 0; + __be32 spcr_val = +#ifdef CONFIG_SYS_SPCR_OPT + (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) | +#endif +#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */ + (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) | +#endif +#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */ + (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) | +#endif +#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */ + (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) | +#endif + 0; + __be32 sccr_mask = +#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */ + (SCCR_ENCCM << SCCR_ENCCM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */ + (SCCR_PCICM << SCCR_PCICM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ + (SCCR_TSECCM << SCCR_TSECCM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ + (SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ + (SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */ + (SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */ + (SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ + (SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */ + (SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ + (SCCR_SATACM << SCCR_SATACM_SHIFT) | +#endif + 0; + __be32 sccr_val = +#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */ + (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */ + (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ + (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ + (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ + (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */ + (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */ + (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ + (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */ + (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ + (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) | +#endif + 0; + /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); @@ -70,142 +179,47 @@ void cpu_init_f (volatile immap_t * im) memset ((void *) gd, 0, sizeof (gd_t)); /* system performance tweaking */ + clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val); -#ifdef CONFIG_SYS_ACR_PIPE_DEP - /* Arbiter pipeline depth */ - im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | - (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); -#endif + clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val); -#ifdef CONFIG_SYS_ACR_RPTCNT - /* Arbiter repeat count */ - im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) | - (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT); -#endif - -#ifdef CONFIG_SYS_SPCR_OPT - /* Optimize transactions between CSB and other devices */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) | - (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT); -#endif - -#ifdef CONFIG_SYS_SPCR_TSECEP - /* all eTSEC's Emergency priority */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) | - (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT); -#endif - -#ifdef CONFIG_SYS_SPCR_TSEC1EP - /* TSEC1 Emergency priority */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | - (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT); -#endif - -#ifdef CONFIG_SYS_SPCR_TSEC2EP - /* TSEC2 Emergency priority */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | - (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT); -#endif - -#ifdef CONFIG_SYS_SCCR_ENCCM - /* Encryption clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) | - (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT); -#endif - -#ifdef CONFIG_SYS_SCCR_PCICM - /* PCI & DMA clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) | - (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT); -#endif - -#ifdef CONFIG_SYS_SCCR_TSECCM - /* all TSEC's clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSECCM) | - (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT); -#endif - -#ifdef CONFIG_SYS_SCCR_TSEC1CM - /* TSEC1 clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | - (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT); -#endif - -#ifdef CONFIG_SYS_SCCR_TSEC2CM - /* TSEC2 clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | - (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT); -#endif - -#ifdef CONFIG_SYS_SCCR_TSEC1ON - /* TSEC1 clock switch */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) | - (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT); -#endif - -#ifdef CONFIG_SYS_SCCR_TSEC2ON - /* TSEC2 clock switch */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) | - (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT); -#endif - -#ifdef CONFIG_SYS_SCCR_USBMPHCM - /* USB MPH clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) | - (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT); -#endif - -#ifdef CONFIG_SYS_SCCR_USBDRCM - /* USB DR clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) | - (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT); -#endif - -#ifdef CONFIG_SYS_SCCR_SATACM - /* SATA controller clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_SATACM) | - (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT); -#endif + clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val); /* RSR - Reset Status Register - clear all status (4.6.1.3) */ - gd->reset_status = im->reset.rsr; - im->reset.rsr = ~(RSR_RES); + gd->reset_status = __raw_readl(&im->reset.rsr); + __raw_writel(~(RSR_RES), &im->reset.rsr); /* AER - Arbiter Event Register - store status */ - gd->arbiter_event_attributes = im->arbiter.aeatr; - gd->arbiter_event_address = im->arbiter.aeadr; + gd->arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr); + gd->arbiter_event_address = __raw_readl(&im->arbiter.aeadr); /* * RMR - Reset Mode Register * contains checkstop reset enable (4.6.1.4) */ - im->reset.rmr = (RMR_CSRE & (1<reset.rmr); - /* LCRR - Clock Ratio Register (10.3.1.16) */ - im->lbus.lcrr = CONFIG_SYS_LCRR; - - /* Enable Time Base & Decrimenter ( so we will have udelay() )*/ - im->sysconf.spcr |= SPCR_TBEN; + /* Enable Time Base & Decrementer ( so we will have udelay() )*/ + setbits_be32(&im->sysconf.spcr, SPCR_TBEN); /* System General Purpose Register */ #ifdef CONFIG_SYS_SICRH #if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313) /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */ - im->sysconf.sicrh = (im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH; + __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH, + &im->sysconf.sicrh); #else - im->sysconf.sicrh = CONFIG_SYS_SICRH; + __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh); #endif #endif #ifdef CONFIG_SYS_SICRL - im->sysconf.sicrl = CONFIG_SYS_SICRL; + __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl); #endif - /* DDR control driver register */ -#ifdef CONFIG_SYS_DDRCDR - im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR; +#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */ + __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr); #endif - /* Output buffer impedance register */ -#ifdef CONFIG_SYS_OBIR - im->sysconf.obir = CONFIG_SYS_OBIR; +#ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */ + __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir); #endif #ifdef CONFIG_QE @@ -308,7 +322,7 @@ void cpu_init_f (volatile immap_t * im) /* Wait for clock to stabilize */ do { - temp = in_be32(&ehci->control); + temp = __raw_readl(&ehci->control); udelay(1000); } while (!(temp & PHY_CLK_VALID)); #endif @@ -317,8 +331,41 @@ void cpu_init_f (volatile immap_t * im) int cpu_init_r (void) { + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; #ifdef CONFIG_QE uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */ +#endif + __be32 lcrr_mask = +#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */ + LCRR_DBYP | +#endif +#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */ + LCRR_EADC | +#endif +#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */ + LCRR_CLKDIV | +#endif + 0; + __be32 lcrr_val = +#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */ + CONFIG_SYS_LCRR_DBYP | +#endif +#ifdef CONFIG_SYS_LCRR_EADC + CONFIG_SYS_LCRR_EADC | +#endif +#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */ + CONFIG_SYS_LCRR_CLKDIV | +#endif + 0; + + /* LCRR - Clock Ratio Register (10.3.1.16) + * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description + */ + clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val); + __raw_readl(&im->lbus.lcrr); + isync(); + +#ifdef CONFIG_QE qe_init(qe_base); qe_reset(); #endif diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 76b78942ba9..5927e763974 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -216,7 +216,8 @@ /* * Local Bus LCRR and LBCR regs */ -#define CONFIG_SYS_LCRR LCRR_EADC_1 | LCRR_CLKDIV_4 +#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR ( 0x00040000 /* TODO */ \ | (0xFF << LBCR_BMT_SHIFT) \ | 0xF ) /* 0x0004ff0f */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 84cc9fa41ea..8eaff5d06f4 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -182,7 +182,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index c40d3d3f4a3..356586c4280 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -170,7 +170,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index f16616c0db0..f17f9c7c376 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -159,7 +159,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 9b2d25a0118..6361c459500 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -206,7 +206,8 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 3b4e3449b0e..eaa59fde41b 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -317,7 +317,8 @@ boards, we say we have two, but don't display a message if we find only one. */ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 62cf13be6d1..852015512c0 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -185,7 +185,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index cb0535c151d..6cee78aa260 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -177,7 +177,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index a190a50ed8a..abeb6a2c60a 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -220,7 +220,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 89fafe7d23d..7ef92f7be1f 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -243,7 +243,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 9835567838f..f8b016feed3 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -137,7 +137,8 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB sdram refresh timer, about 6us */ diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index 866ff179e63..f68d834170a 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -111,7 +111,9 @@ /* * Local Bus LCRR and LBCR regs */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ | (0xFF << LBCR_BMT_SHIFT) \ | 0xF ) /* 0x0004ff0f */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index da08b7c2134..4c909e61ad0 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -52,7 +52,8 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 /* board pre init: do not call, nothing to do */ #undef CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 79d8638fe28..bec08dab1ff 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -170,7 +170,9 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_2 | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2 +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 /* * Init Local Bus Memory Controller: diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 6f574ca6bf4..bf7cf82d8eb 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -197,7 +197,8 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 5304ec94aef..d0690feb173 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -178,7 +178,8 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ From 21f4cbb77299788e2b06c9b0f48cf20a5ab00d4a Mon Sep 17 00:00:00 2001 From: Joakim Tjernlund Date: Thu, 17 Sep 2009 11:07:15 +0200 Subject: [PATCH 191/208] fsl_i2c: Wait for STOP condition to propagate After issuing a STOP one must wait until the STOP has completed on the bus before doing something new to the controller. Also add an extra read of SR as the manual mentions doing that is a good idea. Remove surplus write of CR just before a write, isn't required and could potentially disturb the I2C bus. Signed-off-by: Joakim Tjernlund --- drivers/i2c/fsl_i2c.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 47bbf792c40..56f9680063a 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -223,7 +223,7 @@ i2c_init(int speed, int slaveadd) #endif } -static __inline__ int +static int i2c_wait4bus(void) { unsigned long long timeval = get_ticks(); @@ -248,6 +248,8 @@ i2c_wait(int write) csr = readb(&i2c_dev[i2c_bus_num]->sr); if (!(csr & I2C_SR_MIF)) continue; + /* Read again to allow register to stabilise */ + csr = readb(&i2c_dev[i2c_bus_num]->sr); writeb(0x0, &i2c_dev[i2c_bus_num]->sr); @@ -293,9 +295,6 @@ __i2c_write(u8 *data, int length) { int i; - writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, - &i2c_dev[i2c_bus_num]->cr); - for (i = 0; i < length; i++) { writeb(data[i], &i2c_dev[i2c_bus_num]->dr); @@ -351,6 +350,9 @@ i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0) i = __i2c_read(data, length); + if (length && i2c_wait4bus()) /* Wait until STOP */ + debug("i2c_read: wait4bus timed out\n"); + writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); if (i == length) @@ -372,6 +374,8 @@ i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) } writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); + if (i2c_wait4bus()) /* Wait until STOP */ + debug("i2c_write: wait4bus timed out\n"); if (i == length) return 0; From d01ee4db9302cfccaa5c548a1c4e873b415681a0 Mon Sep 17 00:00:00 2001 From: Joakim Tjernlund Date: Thu, 17 Sep 2009 11:07:16 +0200 Subject: [PATCH 192/208] fsl_i2c: Add CONFIG_FSL_I2C_CUSTOM_{DFSR/FDR} Some boards need a higher DFSR value than the spec currently recommends so give these boards the means to define there own. For completeness, add CONFIG_FSL_I2C_CUSTOM_FDR too. Signed-off-by: Joakim Tjernlund --- drivers/i2c/fsl_i2c.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 56f9680063a..0c5f6be23f7 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -172,14 +172,22 @@ static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev, u8 fdr; #ifdef __PPC__ u8 dfsr; +#ifdef CONFIG_FSL_I2C_CUSTOM_DFSR + dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR; +#else dfsr = fsl_i2c_speed_map[i].dfsr; #endif - fdr = fsl_i2c_speed_map[i].fdr; - speed = i2c_clk / fsl_i2c_speed_map[i].divider; - writeb(fdr, &dev->fdr); /* set bus speed */ -#ifdef __PPC__ writeb(dfsr, &dev->dfsrr); /* set default filter */ #endif +#ifdef CONFIG_FSL_I2C_CUSTOM_FDR + fdr = CONFIG_FSL_I2C_CUSTOM_FDR; + speed = i2c_clk / divider; /* Fake something */ +#else + fdr = fsl_i2c_speed_map[i].fdr; + speed = i2c_clk / fsl_i2c_speed_map[i].divider; +#endif + writeb(fdr, &dev->fdr); /* set bus speed */ + break; } From 99404202127346b9e91503bbd69deafa18c980c4 Mon Sep 17 00:00:00 2001 From: Joakim Tjernlund Date: Thu, 17 Sep 2009 11:07:17 +0200 Subject: [PATCH 193/208] fsl_i2c: Impl. AN2919, rev 5 to calculate FDR/DFSR The latest AN2919 has changed the way FDR/DFSR should be calculated. Update the driver according to spec. However, Condition 2 is not accounted for as it is not clear how to do so. Signed-off-by: Joakim Tjernlund Acked-by: Wolfgang Grandegger --- drivers/i2c/fsl_i2c.c | 94 ++++++++++++++++++++++++++----------------- 1 file changed, 57 insertions(+), 37 deletions(-) diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 0c5f6be23f7..4d5552bcd53 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -100,29 +100,9 @@ static const struct fsl_i2c *i2c_dev[2] = { */ static const struct { unsigned short divider; -#ifdef __PPC__ - u8 dfsr; -#endif u8 fdr; } fsl_i2c_speed_map[] = { -#ifdef __PPC__ - {160, 1, 32}, {192, 1, 33}, {224, 1, 34}, {256, 1, 35}, - {288, 1, 0}, {320, 1, 1}, {352, 6, 1}, {384, 1, 2}, {416, 6, 2}, - {448, 1, 38}, {480, 1, 3}, {512, 1, 39}, {544, 11, 3}, {576, 1, 4}, - {608, 22, 3}, {640, 1, 5}, {672, 32, 3}, {704, 11, 5}, {736, 43, 3}, - {768, 1, 6}, {800, 54, 3}, {832, 11, 6}, {896, 1, 42}, {960, 1, 7}, - {1024, 1, 43}, {1088, 22, 7}, {1152, 1, 8}, {1216, 43, 7}, {1280, 1, 9}, - {1408, 22, 9}, {1536, 1, 10}, {1664, 22, 10}, {1792, 1, 46}, - {1920, 1, 11}, {2048, 1, 47}, {2176, 43, 11}, {2304, 1, 12}, - {2560, 1, 13}, {2816, 43, 13}, {3072, 1, 14}, {3328, 43, 14}, - {3584, 1, 50}, {3840, 1, 15}, {4096, 1, 51}, {4608, 1, 16}, - {5120, 1, 17}, {6144, 1, 18}, {7168, 1, 54}, {7680, 1, 19}, - {8192, 1, 55}, {9216, 1, 20}, {10240, 1, 21}, {12288, 1, 22}, - {14336, 1, 58}, {15360, 1, 23}, {16384, 1, 59}, {18432, 1, 24}, - {20480, 1, 25}, {24576, 1, 26}, {28672, 1, 62}, {30720, 1, 27}, - {32768, 1, 63}, {36864, 1, 28}, {40960, 1, 29}, {49152, 1, 30}, - {61440, 1, 31}, {-1, 1, 31} -#elif defined(__M68K__) +#ifdef __M68K__ {20, 32}, {22, 33}, {24, 34}, {26, 35}, {28, 0}, {28, 36}, {30, 1}, {32, 37}, {34, 2}, {36, 38}, {40, 3}, {40, 39}, @@ -158,7 +138,6 @@ static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev, unsigned int i2c_clk, unsigned int speed) { unsigned short divider = min(i2c_clk / speed, (unsigned short) -1); - unsigned int i; /* * We want to choose an FDR/DFSR that generates an I2C bus speed that @@ -166,31 +145,72 @@ static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev, * want the first divider that is equal to or greater than the * calculated divider. */ +#ifdef __PPC__ + u8 dfsr, fdr = 0x31; /* Default if no FDR found */ + /* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */ + unsigned short a, b, ga, gb; + unsigned long c_div, est_div; + +#ifdef CONFIG_FSL_I2C_CUSTOM_DFSR + dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR; +#else + /* Condition 1: dfsr <= 50/T */ + dfsr = (5 * (i2c_clk / 1000)) / 100000; +#endif +#ifdef CONFIG_FSL_I2C_CUSTOM_FDR + fdr = CONFIG_FSL_I2C_CUSTOM_FDR; + speed = i2c_clk / divider; /* Fake something */ +#else + debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk); + if (!dfsr) + dfsr = 1; + + est_div = ~0; + for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) { + for (gb = 0; gb < 8; gb++) { + b = 16 << gb; + c_div = b * (a + ((3*dfsr)/b)*2); + if ((c_div > divider) && (c_div < est_div)) { + unsigned short bin_gb, bin_ga; + + est_div = c_div; + bin_gb = gb << 2; + bin_ga = (ga & 0x3) | ((ga & 0x4) << 3); + fdr = bin_gb | bin_ga; + speed = i2c_clk / est_div; + debug("FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x, " + "a:%d, b:%d, speed:%d\n", + fdr, est_div, ga, gb, a, b, speed); + /* Condition 2 not accounted for */ + debug("Tr <= %d ns\n", + (b - 3 * dfsr) * 1000000 / + (i2c_clk / 1000)); + } + } + if (a == 20) + a += 2; + if (a == 24) + a += 4; + } + debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr); + debug("FDR:0x%.2x, speed:%d\n", fdr, speed); +#endif + writeb(dfsr, &dev->dfsrr); /* set default filter */ + writeb(fdr, &dev->fdr); /* set bus speed */ +#else + unsigned int i; for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++) if (fsl_i2c_speed_map[i].divider >= divider) { u8 fdr; -#ifdef __PPC__ - u8 dfsr; -#ifdef CONFIG_FSL_I2C_CUSTOM_DFSR - dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR; -#else - dfsr = fsl_i2c_speed_map[i].dfsr; -#endif - writeb(dfsr, &dev->dfsrr); /* set default filter */ -#endif -#ifdef CONFIG_FSL_I2C_CUSTOM_FDR - fdr = CONFIG_FSL_I2C_CUSTOM_FDR; - speed = i2c_clk / divider; /* Fake something */ -#else + fdr = fsl_i2c_speed_map[i].fdr; speed = i2c_clk / fsl_i2c_speed_map[i].divider; -#endif writeb(fdr, &dev->fdr); /* set bus speed */ break; } - +#endif return speed; } From d1c9e5b37901b53ffc1ce3f08ec8ed61bfd557b6 Mon Sep 17 00:00:00 2001 From: Joakim Tjernlund Date: Tue, 22 Sep 2009 13:40:44 +0200 Subject: [PATCH 194/208] fsl_i2c: Do not generate STOP after read. __i2c_read always ends with a STOP condition thereby releasing the bus. It is cleaner to do the STOP magic in i2c_read(), like i2c_write() does. This may also help future multimaster systems which wants to hold on to the bus until all transactions are finished. Signed-off-by: Joakim Tjernlund --- drivers/i2c/fsl_i2c.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 4d5552bcd53..2241990f94f 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -353,9 +353,10 @@ __i2c_read(u8 *data, int length) writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr); - /* Generate stop on last byte */ + /* Do not generate stop on last byte */ if (i == length - 1) - writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr); + writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, + &i2c_dev[i2c_bus_num]->cr); data[i] = readb(&i2c_dev[i2c_bus_num]->dr); } @@ -378,11 +379,11 @@ i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0) i = __i2c_read(data, length); - if (length && i2c_wait4bus()) /* Wait until STOP */ - debug("i2c_read: wait4bus timed out\n"); - writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); + if (i2c_wait4bus()) /* Wait until STOP */ + debug("i2c_read: wait4bus timed out\n"); + if (i == length) return 0; From 952e7760bfc5b0e3b142b9ce34e7fbb7d008c900 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 24 Sep 2009 09:55:50 +0200 Subject: [PATCH 195/208] ppc4xx: Convert PPC4xx UIC defines from lower case to upper case The latest PPC4xx register cleanup patch missed the UIC defines. This patch now changes lower case UIC defines to upper case. Signed-off-by: Stefan Roese --- board/amcc/acadia/acadia.c | 12 ++-- board/amcc/bamboo/bamboo.c | 28 ++++---- board/amcc/bubinga/bubinga.c | 12 ++-- board/amcc/canyonlands/canyonlands.c | 56 +++++++-------- board/amcc/ebony/ebony.c | 28 ++++---- board/amcc/katmai/katmai.c | 64 ++++++++--------- board/amcc/kilauea/kilauea.c | 48 ++++++------- board/amcc/luan/luan.c | 32 ++++----- board/amcc/makalu/makalu.c | 48 ++++++------- board/amcc/ocotea/ocotea.c | 54 +++++++-------- board/amcc/redwood/redwood.c | 56 +++++++-------- board/amcc/sequoia/sequoia.c | 42 ++++++------ board/amcc/taihu/taihu.c | 14 ++-- board/amcc/taishan/taishan.c | 54 +++++++-------- board/amcc/walnut/walnut.c | 14 ++-- board/amcc/yosemite/yosemite.c | 28 ++++---- board/amcc/yucca/yucca.c | 64 ++++++++--------- board/cray/L1/L1.c | 14 ++-- board/csb272/csb272.c | 14 ++-- board/csb472/csb472.c | 14 ++-- board/dave/PPChameleonEVB/PPChameleonEVB.c | 14 ++-- board/eric/eric.c | 14 ++-- board/esd/apc405/apc405.c | 14 ++-- board/esd/ar405/ar405.c | 14 ++-- board/esd/ash405/ash405.c | 14 ++-- board/esd/canbt/canbt.c | 14 ++-- board/esd/cms700/cms700.c | 14 ++-- board/esd/cpci2dp/cpci2dp.c | 14 ++-- board/esd/cpci405/cpci405.c | 18 ++--- board/esd/cpciiser4/cpciiser4.c | 16 ++--- board/esd/dp405/dp405.c | 14 ++-- board/esd/du405/du405.c | 14 ++-- board/esd/du440/du440.c | 42 ++++++------ board/esd/hh405/hh405.c | 14 ++-- board/esd/hub405/hub405.c | 14 ++-- board/esd/ocrtc/ocrtc.c | 14 ++-- board/esd/pci405/pci405.c | 16 ++--- board/esd/plu405/plu405.c | 14 ++-- board/esd/pmc405/pmc405.c | 14 ++-- board/esd/pmc405de/pmc405de.c | 14 ++-- board/esd/pmc440/pmc440.c | 42 ++++++------ board/esd/voh405/voh405.c | 14 ++-- board/esd/vom405/vom405.c | 14 ++-- board/esd/wuh405/wuh405.c | 14 ++-- board/exbitgen/exbitgen.c | 14 ++-- board/g2000/g2000.c | 26 +++---- board/gdsys/dlvision/dlvision.c | 14 ++-- board/gdsys/gdppc440etx/gdppc440etx.c | 28 ++++---- board/gdsys/intip/intip.c | 56 +++++++-------- board/gdsys/neo/neo.c | 14 ++-- board/jse/jse.c | 12 ++-- board/korat/korat.c | 42 ++++++------ board/lwmon5/lwmon5.c | 42 ++++++------ board/mpl/mip405/mip405.c | 14 ++-- board/mpl/pip405/pip405.c | 14 ++-- board/netstal/hcu4/hcu4.c | 12 ++-- board/netstal/hcu5/hcu5.c | 42 ++++++------ board/netstal/mcu25/mcu25.c | 12 ++-- board/pcs440ep/pcs440ep.c | 28 ++++---- board/prodrive/alpr/alpr.c | 54 +++++++-------- board/prodrive/p3p440/p3p440.c | 28 ++++---- board/quad100hd/quad100hd.c | 14 ++-- board/sandburst/karef/karef.c | 54 +++++++-------- board/sandburst/metrobox/metrobox.c | 54 +++++++-------- board/sbc405/sbc405.c | 14 ++-- board/sc3/sc3.c | 18 ++--- board/w7o/w7o.c | 28 ++++---- board/xes/xpedite1000/xpedite1000.c | 54 +++++++-------- board/zeus/zeus.c | 14 ++-- common/cmd_reginfo.c | 36 +++++----- cpu/ppc4xx/uic.c | 28 ++++---- include/asm-ppc/ppc4xx-uic.h | 80 +++++++++------------- 72 files changed, 965 insertions(+), 977 deletions(-) diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c index 0db619952eb..482561122ae 100644 --- a/board/amcc/acadia/acadia.c +++ b/board/amcc/acadia/acadia.c @@ -78,12 +78,12 @@ int board_early_init_f(void) mfsdr(SDR0_ULTRA1, reg); mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE); - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000010); - mtdcr(uicpr, 0xFE7FFFF0); /* set int polarities */ - mtdcr(uictr, 0x00000010); /* set int trigger levels */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000010); + mtdcr(UIC0PR, 0xFE7FFFF0); /* set int polarities */ + mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ return 0; } diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 2ffd720d5c4..38186a5d378 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -392,21 +392,21 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ + mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ /*-------------------------------------------------------------------- * Setup the GPIO pins diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c index d0aebec2cd4..49eadb9212e 100644 --- a/board/amcc/bubinga/bubinga.c +++ b/board/amcc/bubinga/bubinga.c @@ -29,12 +29,12 @@ long int spd_sdram(void); int board_early_init_f(void) { - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000010); - mtdcr(uicpr, 0xFFFF7FF0); /* set int polarities */ - mtdcr(uictr, 0x00000010); /* set int trigger levels */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000010); + mtdcr(UIC0PR, 0xFFFF7FF0); /* set int polarities */ + mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * Configure CPC0_PCI to enable PerWE as output diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 3a03f307310..f359d2377af 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -116,37 +116,37 @@ int board_early_init_f(void) /* * Setup the interrupt controller polarities, triggers, etc. */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ - mtdcr(uic2er, 0x00000000); /* disable all */ - mtdcr(uic2cr, 0x00000000); /* all non-critical */ - mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtdcr(uic3sr, 0xffffffff); /* clear all */ - mtdcr(uic3er, 0x00000000); /* disable all */ - mtdcr(uic3cr, 0x00000000); /* all non-critical */ - mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic3tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic3sr, 0xffffffff); /* clear all */ + mtdcr(UIC3SR, 0xffffffff); /* clear all */ + mtdcr(UIC3ER, 0x00000000); /* disable all */ + mtdcr(UIC3CR, 0x00000000); /* all non-critical */ + mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC3SR, 0xffffffff); /* clear all */ #if !defined(CONFIG_ARCHES) /* SDR Setting - enable NDFC */ diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c index 2439b03a9f7..0543bad138a 100644 --- a/board/amcc/ebony/ebony.c +++ b/board/amcc/ebony/ebony.c @@ -71,21 +71,21 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000009); /* SMI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ + mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ return 0; } diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index 1a45056daa0..bcef707403d 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -183,42 +183,42 @@ int board_early_init_f (void) * Set critical interrupt values. Set interrupt polarities. Set interrupt * trigger levels. Make bit 0 High priority. Clear all interrupts again. *------------------------------------------------------------------------*/ - mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic3er, 0x00000000); /* disable all interrupts */ - mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical interrupts: */ - mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities*/ - mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */ - mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (uic3sr, 0x00000000); /* clear all interrupts*/ - mtdcr (uic3sr, 0xffffffff); /* clear all interrupts*/ + mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical interrupts: */ + mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities*/ + mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ + mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC3SR, 0x00000000); /* clear all interrupts*/ + mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts*/ - mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic2er, 0x00000000); /* disable all interrupts*/ - mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts*/ - mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities*/ - mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */ - mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (uic2sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC2ER, 0x00000000); /* disable all interrupts*/ + mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts*/ + mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities*/ + mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ + mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ - mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts*/ - mtdcr (uic1er, 0x00000000); /* disable all interrupts*/ - mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts*/ - mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels*/ - mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (uic1sr, 0x00000000); /* clear all interrupts*/ - mtdcr (uic1sr, 0xffffffff); /* clear all interrupts*/ + mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts*/ + mtdcr (UIC1ER, 0x00000000); /* disable all interrupts*/ + mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts*/ + mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels*/ + mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC1SR, 0x00000000); /* clear all interrupts*/ + mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts*/ - mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted cascade to be checked */ - mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical interrupts*/ - mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities*/ - mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */ - mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (uic0sr, 0x00000000); /* clear all interrupts*/ - mtdcr (uic0sr, 0xffffffff); /* clear all interrupts*/ + mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted cascade to be checked */ + mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical interrupts*/ + mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities*/ + mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */ + mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC0SR, 0x00000000); /* clear all interrupts*/ + mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts*/ mfsdr(SDR0_MFR, mfr); mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c index 7e84a61a96d..5ebe69272c4 100644 --- a/board/amcc/kilauea/kilauea.c +++ b/board/amcc/kilauea/kilauea.c @@ -158,33 +158,33 @@ int board_early_init_f (void) | interrupts again. +-------------------------------------------------------------------*/ - mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic2er, 0x00000000); /* disable all interrupts */ - mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */ - mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */ - mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (uic2sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */ + mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */ + mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ - mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic1er, 0x00000000); /* disable all interrupts */ - mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */ - mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */ - mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (uic1sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */ + mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */ + mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */ - mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */ + mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */ /* Except cascade UIC0 and UIC1 */ - mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */ - mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */ - mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (uic0sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */ + mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */ + mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */ /* * Note: Some cores are still in reset when the chip starts, so diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 71ad89fa6c3..5f76672fb52 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -49,23 +49,23 @@ int board_early_init_f(void) mtebc( PB2AP, 0x03800000 ); mtebc( PB2CR, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */ - mtdcr( uic1sr, 0xffffffff ); /* Clear all interrupts */ - mtdcr( uic1er, 0x00000000 ); /* disable all interrupts */ - mtdcr( uic1cr, 0x00000000 ); /* Set Critical / Non Critical interrupts */ - mtdcr( uic1pr, 0x7fff83ff ); /* Set Interrupt Polarities */ - mtdcr( uic1tr, 0x001f8000 ); /* Set Interrupt Trigger Levels */ - mtdcr( uic1vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ - mtdcr( uic1sr, 0x00000000 ); /* clear all interrupts */ - mtdcr( uic1sr, 0xffffffff ); + mtdcr( UIC1SR, 0xffffffff ); /* Clear all interrupts */ + mtdcr( UIC1ER, 0x00000000 ); /* disable all interrupts */ + mtdcr( UIC1CR, 0x00000000 ); /* Set Critical / Non Critical interrupts */ + mtdcr( UIC1PR, 0x7fff83ff ); /* Set Interrupt Polarities */ + mtdcr( UIC1TR, 0x001f8000 ); /* Set Interrupt Trigger Levels */ + mtdcr( UIC1VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ + mtdcr( UIC1SR, 0x00000000 ); /* clear all interrupts */ + mtdcr( UIC1SR, 0xffffffff ); - mtdcr( uic0sr, 0xffffffff ); /* Clear all interrupts */ - mtdcr( uic0er, 0x00000000 ); /* disable all interrupts excepted cascade */ - mtdcr( uic0cr, 0x00000001 ); /* Set Critical / Non Critical interrupts */ - mtdcr( uic0pr, 0xffffffff ); /* Set Interrupt Polarities */ - mtdcr( uic0tr, 0x01000004 ); /* Set Interrupt Trigger Levels */ - mtdcr( uic0vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ - mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */ - mtdcr( uic0sr, 0xffffffff ); + mtdcr( UIC0SR, 0xffffffff ); /* Clear all interrupts */ + mtdcr( UIC0ER, 0x00000000 ); /* disable all interrupts excepted cascade */ + mtdcr( UIC0CR, 0x00000001 ); /* Set Critical / Non Critical interrupts */ + mtdcr( UIC0PR, 0xffffffff ); /* Set Interrupt Polarities */ + mtdcr( UIC0TR, 0x01000004 ); /* Set Interrupt Trigger Levels */ + mtdcr( UIC0VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ + mtdcr( UIC0SR, 0x00000000 ); /* clear all interrupts */ + mtdcr( UIC0SR, 0xffffffff ); mfsdr(SDR0_MFR, mfr); mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c index 9fc0ec6667e..fb0e7b75eb9 100644 --- a/board/amcc/makalu/makalu.c +++ b/board/amcc/makalu/makalu.c @@ -159,33 +159,33 @@ int board_early_init_f (void) | interrupts again. +-------------------------------------------------------------------*/ - mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic2er, 0x00000000); /* disable all interrupts */ - mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */ - mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */ - mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (uic2sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */ + mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */ + mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ - mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic1er, 0x00000000); /* disable all interrupts */ - mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */ - mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */ - mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (uic1sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */ + mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */ + mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */ - mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */ + mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */ /* Except cascade UIC0 and UIC1 */ - mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */ - mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */ - mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (uic0sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */ + mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */ + mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */ /* * Note: Some cores are still in reset when the chip starts, so diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index 5e32e8a7844..8513f43a8f1 100644 --- a/board/amcc/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -159,36 +159,36 @@ int board_early_init_f (void) * UIC2 UIC1 * UIC3 UIC2 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ - mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr (uic1pr, 0xfffffe13); /* per ref-board manual */ - mtdcr (uic1tr, 0x01c00008); /* per ref-board manual */ - mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ + mtdcr (UIC1SR, 0xffffffff); /* clear all */ + mtdcr (UIC1ER, 0x00000000); /* disable all */ + mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */ + mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */ + mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */ + mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC1SR, 0xffffffff); /* clear all */ - mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uic2er, 0x00000000); /* disable all */ - mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */ - mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic2sr, 0xffffffff); /* clear all */ + mtdcr (UIC2SR, 0xffffffff); /* clear all */ + mtdcr (UIC2ER, 0x00000000); /* disable all */ + mtdcr (UIC2CR, 0x00000000); /* all non-critical */ + mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */ + mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */ + mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC2SR, 0xffffffff); /* clear all */ - mtdcr (uic3sr, 0xffffffff); /* clear all */ - mtdcr (uic3er, 0x00000000); /* disable all */ - mtdcr (uic3cr, 0x00000000); /* all non-critical */ - mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */ - mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */ - mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic3sr, 0xffffffff); /* clear all */ + mtdcr (UIC3SR, 0xffffffff); /* clear all */ + mtdcr (UIC3ER, 0x00000000); /* disable all */ + mtdcr (UIC3CR, 0x00000000); /* all non-critical */ + mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */ + mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC3SR, 0xffffffff); /* clear all */ - mtdcr (uic0sr, 0xfc000000); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000000); /* all non-critical */ - mtdcr (uic0pr, 0xfc000000); /* */ - mtdcr (uic0tr, 0x00000000); /* */ - mtdcr (uic0vr, 0x00000001); /* */ + mtdcr (UIC0SR, 0xfc000000); /* clear all */ + mtdcr (UIC0ER, 0x00000000); /* disable all */ + mtdcr (UIC0CR, 0x00000000); /* all non-critical */ + mtdcr (UIC0PR, 0xfc000000); /* */ + mtdcr (UIC0TR, 0x00000000); /* */ + mtdcr (UIC0VR, 0x00000001); /* */ mfsdr (SDR0_MFR, mfr); mfr &= ~SDR0_MFR_ECS_MASK; /* mtsdr(SDR0_MFR, mfr); */ diff --git a/board/amcc/redwood/redwood.c b/board/amcc/redwood/redwood.c index 49078ebee2f..bc8cb0c443a 100644 --- a/board/amcc/redwood/redwood.c +++ b/board/amcc/redwood/redwood.c @@ -416,41 +416,41 @@ static void early_init_UIC(void) * interrupt trigger levels. Make bit 0 High priority. Clear all * interrupts again. */ - mtdcr(uic3sr, 0xffffffff); /* Clear all interrupts */ - mtdcr(uic3er, 0x00000000); /* disable all interrupts */ - mtdcr(uic3cr, 0x00000000); /* Set Critical / Non Critical + mtdcr(UIC3SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC3ER, 0x00000000); /* disable all interrupts */ + mtdcr(UIC3CR, 0x00000000); /* Set Critical / Non Critical * interrupts */ - mtdcr(uic3pr, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr(uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */ - mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic3sr, 0xffffffff); /* clear all interrupts */ + mtdcr(UIC3PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr(UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ + mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC3SR, 0xffffffff); /* clear all interrupts */ - mtdcr(uic2sr, 0xffffffff); /* Clear all interrupts */ - mtdcr(uic2er, 0x00000000); /* disable all interrupts */ - mtdcr(uic2cr, 0x00000000); /* Set Critical / Non Critical + mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */ + mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical * interrupts */ - mtdcr(uic2pr, 0xebebebff); /* Set Interrupt Polarities */ - mtdcr(uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */ - mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic2sr, 0xffffffff); /* clear all interrupts */ + mtdcr(UIC2PR, 0xebebebff); /* Set Interrupt Polarities */ + mtdcr(UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */ - mtdcr(uic1sr, 0xffffffff); /* Clear all interrupts */ - mtdcr(uic1er, 0x00000000); /* disable all interrupts */ - mtdcr(uic1cr, 0x00000000); /* Set Critical / Non Critical + mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */ + mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical * interrupts */ - mtdcr(uic1pr, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr(uic1tr, 0x001fc0ff); /* Set Interrupt Trigger Levels */ - mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all interrupts */ + mtdcr(UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr(UIC1TR, 0x001fc0ff); /* Set Interrupt Trigger Levels */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */ - mtdcr(uic0sr, 0xffffffff); /* Clear all interrupts */ - mtdcr(uic0er, 0x00000000); /* disable all interrupts excepted + mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC0ER, 0x00000000); /* disable all interrupts excepted * cascade to be checked */ - mtdcr(uic0cr, 0x00104001); /* Set Critical / Non Critical + mtdcr(UIC0CR, 0x00104001); /* Set Critical / Non Critical * interrupts */ - mtdcr(uic0pr, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr(uic0tr, 0x000f003c); /* Set Interrupt Trigger Levels */ - mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all interrupts */ + mtdcr(UIC0PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr(UIC0TR, 0x000f003c); /* Set Interrupt Trigger Levels */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */ } diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 5913455ba15..17f831c3f41 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -52,29 +52,29 @@ int board_early_init_f(void) /* * Setup the interrupt controller polarities, triggers, etc. */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ - mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */ + mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ - mtdcr(uic2er, 0x00000000); /* disable all */ - mtdcr(uic2cr, 0x00000000); /* all non-critical */ - mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ /* 50MHz tmrclk */ out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00); diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c index 4e5796ee828..be381d60ac2 100644 --- a/board/amcc/taihu/taihu.c +++ b/board/amcc/taihu/taihu.c @@ -40,13 +40,13 @@ int board_early_init_f(void) { lcd_init(); - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); - mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */ - mtdcr(uictr, 0x00000000); /* set int trigger levels */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); + mtdcr(UIC0PR, 0xFFFF7F00); /* set int polarities */ + mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */ mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR); diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c index 086778a6523..4a0573eb380 100644 --- a/board/amcc/taishan/taishan.c +++ b/board/amcc/taishan/taishan.c @@ -132,36 +132,36 @@ int board_early_init_f (void) * UIC2 UIC1 * UIC3 UIC2 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ - mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr (uic1pr, 0xfffffe13); /* per ref-board manual */ - mtdcr (uic1tr, 0x01c00008); /* per ref-board manual */ - mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ + mtdcr (UIC1SR, 0xffffffff); /* clear all */ + mtdcr (UIC1ER, 0x00000000); /* disable all */ + mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */ + mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */ + mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */ + mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC1SR, 0xffffffff); /* clear all */ - mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uic2er, 0x00000000); /* disable all */ - mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */ - mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic2sr, 0xffffffff); /* clear all */ + mtdcr (UIC2SR, 0xffffffff); /* clear all */ + mtdcr (UIC2ER, 0x00000000); /* disable all */ + mtdcr (UIC2CR, 0x00000000); /* all non-critical */ + mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */ + mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */ + mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC2SR, 0xffffffff); /* clear all */ - mtdcr (uic3sr, 0xffffffff); /* clear all */ - mtdcr (uic3er, 0x00000000); /* disable all */ - mtdcr (uic3cr, 0x00000000); /* all non-critical */ - mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */ - mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */ - mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic3sr, 0xffffffff); /* clear all */ + mtdcr (UIC3SR, 0xffffffff); /* clear all */ + mtdcr (UIC3ER, 0x00000000); /* disable all */ + mtdcr (UIC3CR, 0x00000000); /* all non-critical */ + mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */ + mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC3SR, 0xffffffff); /* clear all */ - mtdcr (uic0sr, 0xfc000000); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000000); /* all non-critical */ - mtdcr (uic0pr, 0xfc000000); /* */ - mtdcr (uic0tr, 0x00000000); /* */ - mtdcr (uic0vr, 0x00000001); /* */ + mtdcr (UIC0SR, 0xfc000000); /* clear all */ + mtdcr (UIC0ER, 0x00000000); /* disable all */ + mtdcr (UIC0CR, 0x00000000); /* all non-critical */ + mtdcr (UIC0PR, 0xfc000000); /* */ + mtdcr (UIC0TR, 0x00000000); /* */ + mtdcr (UIC0VR, 0x00000001); /* */ /* Enable two GPIO 10~11 and TraceA signal */ mfsdr(SDR0_PFC0,reg); diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c index 28dcb66ebc4..4f299324cd7 100644 --- a/board/amcc/walnut/walnut.c +++ b/board/amcc/walnut/walnut.c @@ -47,13 +47,13 @@ int board_early_init_f(void) | +-------------------------------------------------------------------------*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */ - mtdcr(uicpr, 0xFFFFFFE0); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */ + mtdcr(UIC0PR, 0xFFFFFFE0); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* set UART1 control to select CTS/RTS */ #define FPGA_BRDC 0xF0300004 diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 2a654fa895b..731d441526f 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -82,21 +82,21 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ + mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ /*-------------------------------------------------------------------- * Setup other serial configuration diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 245004cee87..033bdd20fa7 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -485,50 +485,50 @@ int board_early_init_f (void) | interrupt trigger levels. Make bit 0 High priority. Clear all | interrupts again. +-------------------------------------------------------------------*/ - mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic3er, 0x00000000); /* disable all interrupts */ - mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical + mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical * interrupts */ - mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */ - mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest + mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ + mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest * priority */ - mtdcr (uic3sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic3sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC3SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts */ - mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic2er, 0x00000000); /* disable all interrupts */ - mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical + mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical * interrupts */ - mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities */ - mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */ - mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest + mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities */ + mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ + mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest * priority */ - mtdcr (uic2sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ - mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic1er, 0x00000000); /* disable all interrupts */ - mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical + mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical * interrupts */ - mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels */ - mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest + mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels */ + mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest * priority */ - mtdcr (uic1sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */ - mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted + mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted * cascade to be checked */ - mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical + mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical * interrupts */ - mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */ - mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest + mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */ + mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest * priority */ - mtdcr (uic0sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */ mfsdr(SDR0_MFR, mfr); mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c index 5d1c4170dd1..79130711d46 100644 --- a/board/cray/L1/L1.c +++ b/board/cray/L1/L1.c @@ -113,13 +113,13 @@ int board_early_init_f (void) { /* Running from ROM: global data is still READONLY */ init_sdram (); - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */ - mtdcr (uicpr, 0xFFFFFFE0); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFFE0); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ return 0; } diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c index cb24cd4ffeb..740e3ac6f5e 100644 --- a/board/csb272/csb272.c +++ b/board/csb272/csb272.c @@ -87,13 +87,13 @@ int board_early_init_f(void) | +-------------------------------------------------------------------------*/ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF83); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF83); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */ diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c index fa0fa193e82..0c7760a02f8 100644 --- a/board/csb472/csb472.c +++ b/board/csb472/csb472.c @@ -55,13 +55,13 @@ int board_early_init_f(void) | +-------------------------------------------------------------------------*/ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF83); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF83); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */ diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c index 56751e15995..06de6e0b1d7 100644 --- a/board/dave/PPChameleonEVB/PPChameleonEVB.c +++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c @@ -53,13 +53,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) * IRQ 31 (EXT IRQ 6) */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us diff --git a/board/eric/eric.c b/board/eric/eric.c index bc2a907f6b9..cfcfa525a9d 100644 --- a/board/eric/eric.c +++ b/board/eric/eric.c @@ -62,13 +62,13 @@ int board_early_init_f (void) | +-------------------------------------------------------------------------*/ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all SMI to be non-critical */ - mtdcr (uicpr, 0xFFFFFF88); /* set int polarities; IRQ3 to 1 */ - mtdcr (uictr, 0x10000000); /* set int trigger levels, UART0 is EDGE */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all SMI to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF88); /* set int polarities; IRQ3 to 1 */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels, UART0 is EDGE */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtdcr (CPC0_CR0, 0x00002000); /* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */ diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c index 46622a29fd4..409a0540bf7 100644 --- a/board/esd/apc405/apc405.c +++ b/board/esd/apc405/apc405.c @@ -155,13 +155,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0 */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0 */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks diff --git a/board/esd/ar405/ar405.c b/board/esd/ar405/ar405.c index 9d1b6d26442..a632cb42d61 100644 --- a/board/esd/ar405/ar405.c +++ b/board/esd/ar405/ar405.c @@ -130,13 +130,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF81); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ out_be16((void *)0xf03000ec, 0x0fff); /* enable interrupts in fpga */ diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c index 8da08facffc..5f0e67cbb4c 100644 --- a/board/esd/ash405/ash405.c +++ b/board/esd/ash405/ash405.c @@ -66,13 +66,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF9F); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us diff --git a/board/esd/canbt/canbt.c b/board/esd/canbt/canbt.c index 418d3e237ed..5a3f61de3c1 100644 --- a/board/esd/canbt/canbt.c +++ b/board/esd/canbt/canbt.c @@ -134,13 +134,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF81); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ return 0; } diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c index 7a92401893d..391fbf4c1bd 100644 --- a/board/esd/cms700/cms700.c +++ b/board/esd/cms700/cms700.c @@ -45,13 +45,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c index 00c7024a852..6d9814f163f 100644 --- a/board/esd/cpci2dp/cpci2dp.c +++ b/board/esd/cpci2dp/cpci2dp.c @@ -58,14 +58,14 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive * IRQ 31 (EXT IRQ 6) unused */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ return 0; } diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index 4c9ed2fa585..c29c876d617 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -179,22 +179,22 @@ int board_early_init_f(void) * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ #if defined(CONFIG_CPCI405_6U) if (cpci405_version() == 3) { - mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */ + mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */ } else { - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ + mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ } #else - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ + mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ #endif - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0, + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, * INT0 highest priority */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ return 0; } diff --git a/board/esd/cpciiser4/cpciiser4.c b/board/esd/cpciiser4/cpciiser4.c index 6e97392c4b6..ee90e2c28a5 100644 --- a/board/esd/cpciiser4/cpciiser4.c +++ b/board/esd/cpciiser4/cpciiser4.c @@ -129,14 +129,14 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - /* mtdcr(uicpr, 0xFFFFFF81); / set int polarities */ - mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + /* mtdcr(UIC0PR, 0xFFFFFF81); / set int polarities */ + mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ return 0; } diff --git a/board/esd/dp405/dp405.c b/board/esd/dp405/dp405.c index fc0d091bca9..228a57057a9 100644 --- a/board/esd/dp405/dp405.c +++ b/board/esd/dp405/dp405.c @@ -43,13 +43,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c index 28a50c7b0e7..f475d11072d 100644 --- a/board/esd/du405/du405.c +++ b/board/esd/du405/du405.c @@ -124,13 +124,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) unused; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFFB1); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFFB1); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 100 us diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c index 376de983548..056f455d687 100644 --- a/board/esd/du440/du440.c +++ b/board/esd/du440/du440.c @@ -87,37 +87,37 @@ int board_early_init_f(void) /* * Setup the interrupt controller polarities, triggers, etc. */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ - mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */ + mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ /* * UIC1: * bit30: ext. Irq 1: PLD : int 32+30 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xfffffffd); - mtdcr(uic1tr, 0x00000000); - mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xfffffffd); + mtdcr(UIC1TR, 0x00000000); + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ /* * UIC2 * bit3: ext. Irq 2: DCF77 : int 64+3 */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ - mtdcr(uic2er, 0x00000000); /* disable all */ - mtdcr(uic2cr, 0x00000000); /* all non-critical */ - mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ /* select Ethernet pins */ mfsdr(SDR0_PFC1, sdr0_pfc1); diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c index b72b716ddf2..132531b39c5 100644 --- a/board/esd/hh405/hh405.c +++ b/board/esd/hh405/hh405.c @@ -363,13 +363,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c index acb23dad1f5..2a2c4343c0d 100644 --- a/board/esd/hub405/hub405.c +++ b/board/esd/hub405/hub405.c @@ -86,13 +86,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF9F); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us diff --git a/board/esd/ocrtc/ocrtc.c b/board/esd/ocrtc/ocrtc.c index 709bcdd9802..ab909e50304 100644 --- a/board/esd/ocrtc/ocrtc.c +++ b/board/esd/ocrtc/ocrtc.c @@ -45,13 +45,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF81); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: clear EBTC -> high-Z ebc signals between diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c index 04bc569ead1..34a16324011 100644 --- a/board/esd/pci405/pci405.c +++ b/board/esd/pci405/pci405.c @@ -155,13 +155,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * Setup GPIO pins (IRQ4/GPIO21 as GPIO) @@ -271,7 +271,7 @@ int misc_init_r (void) pci_write_config_dword(PCIDEVID_405GP, i, *ptr++); } } - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ *magic = 0; /* clear pci reconfig magic again */ } diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index a3c1cec6ef4..f14ef7a20f8 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -78,13 +78,13 @@ int board_early_init_f(void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c index 5ff87e7a250..e7415e44cb0 100644 --- a/board/esd/pmc405/pmc405.c +++ b/board/esd/pmc405/pmc405.c @@ -48,13 +48,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0, INT0 highest priority */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: diff --git a/board/esd/pmc405de/pmc405de.c b/board/esd/pmc405de/pmc405de.c index 419311aec83..3725ece3946 100644 --- a/board/esd/pmc405de/pmc405de.c +++ b/board/esd/pmc405de/pmc405de.c @@ -114,13 +114,13 @@ int board_early_init_f(void) * IRQ 30 (EXT IRQ 5) ETH1-PHY-IRQ#; active low; level sensitive * IRQ 31 (EXT IRQ 6) PLD-IRQ#; active low; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0, INT0 highest prio */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest prio */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index 119cbf26273..f0f9bff3eb2 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -148,29 +148,29 @@ int board_early_init_f(void) /* * Setup the interrupt controller polarities, triggers, etc. */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffff7ef); - mtdcr(uic0tr, 0x00000000); - mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xfffff7ef); + mtdcr(UIC0TR, 0x00000000); + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffc7f5); - mtdcr(uic1tr, 0x00000000); - mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffc7f5); + mtdcr(UIC1TR, 0x00000000); + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ - mtdcr(uic2er, 0x00000000); /* disable all */ - mtdcr(uic2cr, 0x00000000); /* all non-critical */ - mtdcr(uic2pr, 0x27ffffff); - mtdcr(uic2tr, 0x00000000); - mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0x27ffffff); + mtdcr(UIC2TR, 0x00000000); + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ /* select Ethernet pins */ mfsdr(SDR0_PFC1, sdr0_pfc1); diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c index 7477f56b2b1..3f81665eb20 100644 --- a/board/esd/voh405/voh405.c +++ b/board/esd/voh405/voh405.c @@ -88,13 +88,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFFB5); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFFB5); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c index de9c7b974cf..fb480226599 100644 --- a/board/esd/vom405/vom405.c +++ b/board/esd/vom405/vom405.c @@ -45,13 +45,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c index e86f1d0abc6..f2591d57f4f 100644 --- a/board/esd/wuh405/wuh405.c +++ b/board/esd/wuh405/wuh405.c @@ -64,13 +64,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF9F); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us diff --git a/board/exbitgen/exbitgen.c b/board/exbitgen/exbitgen.c index 0f8412776b6..ce6469d29e1 100644 --- a/board/exbitgen/exbitgen.c +++ b/board/exbitgen/exbitgen.c @@ -37,13 +37,13 @@ int board_early_init_f (void) | +-------------------------------------------------------------------------*/ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */ - mtdcr (uicpr, 0xFFFFFF90); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF90); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* Perform reset of PHY connected to PPC via register in CPLD */ out8 (PHY_CTRL_ADDR, 0x2e); /* activate nRESET,FDX,F100,ANEN, enable output */ diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c index ae258e1f263..8afffdc7372 100644 --- a/board/g2000/g2000.c +++ b/board/g2000/g2000.c @@ -38,20 +38,20 @@ int board_early_init_f (void) { #if 0 /* test-only */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000010); - mtdcr (uicpr, 0xFFFF7FF0); /* set int polarities */ - mtdcr (uictr, 0x00000010); /* set int trigger levels */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000010); + mtdcr (UIC0PR, 0xFFFF7FF0); /* set int polarities */ + mtdcr (UIC0TR, 0x00000010); /* set int trigger levels */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ #else - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFFF0); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFFF0); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ #endif #if 1 /* test-only */ diff --git a/board/gdsys/dlvision/dlvision.c b/board/gdsys/dlvision/dlvision.c index 5246bc8c4fb..ff5f1832359 100644 --- a/board/gdsys/dlvision/dlvision.c +++ b/board/gdsys/dlvision/dlvision.c @@ -36,13 +36,13 @@ enum { int board_early_init_f(void) { - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c index 27c159bec62..7cc1bf26783 100644 --- a/board/gdsys/gdppc440etx/gdppc440etx.c +++ b/board/gdsys/gdppc440etx/gdppc440etx.c @@ -83,21 +83,21 @@ int board_early_init_f(void) /* * Setup the interrupt controller polarities, triggers, etc. */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ + mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ /* * Setup other serial configuration diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c index 0de1be85792..2cd2e6d4503 100644 --- a/board/gdsys/intip/intip.c +++ b/board/gdsys/intip/intip.c @@ -44,37 +44,37 @@ int board_early_init_f(void) /* * Setup the interrupt controller polarities, triggers, etc. */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ - mtdcr(uic2er, 0x00000000); /* disable all */ - mtdcr(uic2cr, 0x00000000); /* all non-critical */ - mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtdcr(uic3sr, 0xffffffff); /* clear all */ - mtdcr(uic3er, 0x00000000); /* disable all */ - mtdcr(uic3cr, 0x00000000); /* all non-critical */ - mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic3tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic3sr, 0xffffffff); /* clear all */ + mtdcr(UIC3SR, 0xffffffff); /* clear all */ + mtdcr(UIC3ER, 0x00000000); /* disable all */ + mtdcr(UIC3CR, 0x00000000); /* all non-critical */ + mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC3SR, 0xffffffff); /* clear all */ /* * Configure PFC (Pin Function Control) registers diff --git a/board/gdsys/neo/neo.c b/board/gdsys/neo/neo.c index 628ce3dc90b..a56c2cc9879 100644 --- a/board/gdsys/neo/neo.c +++ b/board/gdsys/neo/neo.c @@ -31,13 +31,13 @@ int board_early_init_f(void) { - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks diff --git a/board/jse/jse.c b/board/jse/jse.c index 6dc9a01af8f..1849ca47d77 100644 --- a/board/jse/jse.c +++ b/board/jse/jse.c @@ -48,12 +48,12 @@ int board_early_init_f (void) | IRQ 30 (EXT IRQ 5) SystemACE BRdy (unused) | IRQ 31 (EXT IRQ 6) (unused) +-------------------------------------------------------------------------*/ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF87); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF87); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* Configure the interface to the SystemACE MCU port. The SystemACE is fast, but there is no reason to have diff --git a/board/korat/korat.c b/board/korat/korat.c index 3d4d149f6c6..40a097cef59 100644 --- a/board/korat/korat.c +++ b/board/korat/korat.c @@ -87,29 +87,29 @@ int board_early_init_f(void) /* * Setup the interrupt controller polarities, triggers, etc. */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ - mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */ + mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ - mtdcr(uic2er, 0x00000000); /* disable all */ - mtdcr(uic2cr, 0x00000000); /* all non-critical */ - mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ /* * Take sim card reader and CF controller out of reset. Also enable PHY diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index a9c2a6f441a..f4090f40dd3 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -44,29 +44,29 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ - mtdcr(uic0sr, 0xffffffff); /* clear all. if write with 1 then the status is cleared */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000000); /* we have not critical interrupts at the moment */ - mtdcr(uic0pr, 0xFFBFF1EF); /* Adjustment of the polarity */ - mtdcr(uic0tr, 0x00000900); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all. if write with 1 then the status is cleared */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000000); /* we have not critical interrupts at the moment */ + mtdcr(UIC0PR, 0xFFBFF1EF); /* Adjustment of the polarity */ + mtdcr(UIC0TR, 0x00000900); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xFFFFC6A5); /* Adjustment of the polarity */ - mtdcr(uic1tr, 0x60000040); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xFFFFC6A5); /* Adjustment of the polarity */ + mtdcr(UIC1TR, 0x60000040); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ - mtdcr(uic2er, 0x00000000); /* disable all */ - mtdcr(uic2cr, 0x00000000); /* all non-critical */ - mtdcr(uic2pr, 0x27C00000); /* Adjustment of the polarity */ - mtdcr(uic2tr, 0x3C000000); /* per ref-board manual */ - mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0x27C00000); /* Adjustment of the polarity */ + mtdcr(UIC2TR, 0x3C000000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ /* Trace Pins are disabled. SDR0_PFC0 Register */ mtsdr(SDR0_PFC0, 0x0); diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c index d8279e81c98..b87df01fec2 100644 --- a/board/mpl/mip405/mip405.c +++ b/board/mpl/mip405/mip405.c @@ -489,13 +489,13 @@ int board_early_init_f (void) | caused the interrupt. | +-------------------------------------------------------------------------*/ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */ - mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */ + mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ return 0; } diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c index e00d1d08f5c..c2d6c6fbcfa 100644 --- a/board/mpl/pip405/pip405.c +++ b/board/mpl/pip405/pip405.c @@ -552,13 +552,13 @@ int board_early_init_f (void) | caused the interrupt. | +-------------------------------------------------------------------------*/ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */ - mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */ + mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ return 0; } diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c index 40bec8edcc5..ba3e9c3cff1 100644 --- a/board/netstal/hcu4/hcu4.c +++ b/board/netstal/hcu4/hcu4.c @@ -58,12 +58,12 @@ int board_early_init_f (void) * IRQ 17-24 RESERVED/UNUSED * IRQ 31 (EXT IRQ 6) (unused) */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr(uicpr, 0xFFFFE000); /* set int polarities */ - mtdcr(uictr, 0x00000000); /* set int trigger levels */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr(UIC0PR, 0xFFFFE000); /* set int polarities */ + mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtdcr(CPC0_CR1, CPC0_CR1_VALUE); mtdcr(CPC0_ECR, 0x60606000); diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index 836c0346da3..4522612daef 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -129,29 +129,29 @@ int board_early_init_f(void) /* * Setup the interrupt controller polarities, triggers, etc. */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ - mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */ + mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ - mtdcr(uic2er, 0x00000000); /* disable all */ - mtdcr(uic2cr, 0x00000000); /* all non-critical */ - mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ mtsdr(SDR0_PFC0, 0x00003E00); /* Pin function: */ mtsdr(SDR0_PFC1, 0x00848000); /* Pin function: UART0 has 4 pins */ diff --git a/board/netstal/mcu25/mcu25.c b/board/netstal/mcu25/mcu25.c index 9054282c94d..945d79aa200 100644 --- a/board/netstal/mcu25/mcu25.c +++ b/board/netstal/mcu25/mcu25.c @@ -64,12 +64,12 @@ int board_early_init_f (void) * IRQ 17-24 RESERVED/UNUSED * IRQ 31 (EXT IRQ 6) (unused) */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr(uicpr, 0xFFFFE000); /* set int polarities */ - mtdcr(uictr, 0x00000000); /* set int trigger levels */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr(UIC0PR, 0xFFFFE000); /* set int polarities */ + mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtdcr(CPC0_CR1, CPC0_CR1_VALUE); mtdcr(CPC0_ECR, 0x60606000); diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index f966d02f107..ac059a903b1 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -155,21 +155,21 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000001); /* UIC1 crit is critical */ - mtdcr(uic0pr, 0xfffffe1f); /* per ref-board manual */ - mtdcr(uic0tr, 0x01c00000); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000001); /* UIC1 crit is critical */ + mtdcr(UIC0PR, 0xfffffe1f); /* per ref-board manual */ + mtdcr(UIC0TR, 0x01c00000); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ /*-------------------------------------------------------------------- * Setup other serial configuration diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c index be79b42bd04..cdb91ac36b4 100644 --- a/board/prodrive/alpr/alpr.c +++ b/board/prodrive/alpr/alpr.c @@ -60,36 +60,36 @@ int board_early_init_f (void) * UIC2 UIC1 * UIC3 UIC2 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ - mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr (uic1pr, 0xfffffe03); /* per manual */ - mtdcr (uic1tr, 0x01c00000); /* per manual */ - mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ + mtdcr (UIC1SR, 0xffffffff); /* clear all */ + mtdcr (UIC1ER, 0x00000000); /* disable all */ + mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */ + mtdcr (UIC1PR, 0xfffffe03); /* per manual */ + mtdcr (UIC1TR, 0x01c00000); /* per manual */ + mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC1SR, 0xffffffff); /* clear all */ - mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uic2er, 0x00000000); /* disable all */ - mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */ - mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic2sr, 0xffffffff); /* clear all */ + mtdcr (UIC2SR, 0xffffffff); /* clear all */ + mtdcr (UIC2ER, 0x00000000); /* disable all */ + mtdcr (UIC2CR, 0x00000000); /* all non-critical */ + mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */ + mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */ + mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC2SR, 0xffffffff); /* clear all */ - mtdcr (uic3sr, 0xffffffff); /* clear all */ - mtdcr (uic3er, 0x00000000); /* disable all */ - mtdcr (uic3cr, 0x00000000); /* all non-critical */ - mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */ - mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */ - mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic3sr, 0xffffffff); /* clear all */ + mtdcr (UIC3SR, 0xffffffff); /* clear all */ + mtdcr (UIC3ER, 0x00000000); /* disable all */ + mtdcr (UIC3CR, 0x00000000); /* all non-critical */ + mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */ + mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC3SR, 0xffffffff); /* clear all */ - mtdcr (uic0sr, 0xfc000000); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000000); /* all non-critical */ - mtdcr (uic0pr, 0xfc000000); /* */ - mtdcr (uic0tr, 0x00000000); /* */ - mtdcr (uic0vr, 0x00000001); /* */ + mtdcr (UIC0SR, 0xfc000000); /* clear all */ + mtdcr (UIC0ER, 0x00000000); /* disable all */ + mtdcr (UIC0CR, 0x00000000); /* all non-critical */ + mtdcr (UIC0PR, 0xfc000000); /* */ + mtdcr (UIC0TR, 0x00000000); /* */ + mtdcr (UIC0VR, 0x00000001); /* */ /* Setup shutdown/SSD empty interrupt as inputs */ out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY)); diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c index 18054e45b6e..20fd4dc2769 100644 --- a/board/prodrive/p3p440/p3p440.c +++ b/board/prodrive/p3p440/p3p440.c @@ -101,21 +101,21 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000001); /* UIC1 crit is critical */ - mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000001); /* UIC1 crit is critical */ + mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ + mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ return 0; } diff --git a/board/quad100hd/quad100hd.c b/board/quad100hd/quad100hd.c index ffc47de25dc..f878c49bfad 100644 --- a/board/quad100hd/quad100hd.c +++ b/board/quad100hd/quad100hd.c @@ -40,13 +40,13 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { /* taken from PPCBoot */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); - mtdcr(uicpr, 0xFFFF7FFE); /* set int polarities */ - mtdcr(uictr, 0x00000000); /* set int trigger levels */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); + mtdcr(UIC0PR, 0xFFFF7FFE); /* set int polarities */ + mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ mtdcr(CPC0_SRR, 0x00040000); /* Hold PCI bridge in reset */ diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c index b80c2069400..92b15aa50fb 100644 --- a/board/sandburst/karef/karef.c +++ b/board/sandburst/karef/karef.c @@ -212,36 +212,36 @@ int board_early_init_f (void) * UIC2 UIC1 * UIC3 UIC2 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ - mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000000); /* all non- critical */ - mtdcr (uic1pr, 0xfffffe03); /* polarity */ - mtdcr (uic1tr, 0x01c00000); /* trigger edge vs level */ - mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ + mtdcr (UIC1SR, 0xffffffff); /* clear all */ + mtdcr (UIC1ER, 0x00000000); /* disable all */ + mtdcr (UIC1CR, 0x00000000); /* all non- critical */ + mtdcr (UIC1PR, 0xfffffe03); /* polarity */ + mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */ + mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC1SR, 0xffffffff); /* clear all */ - mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uic2er, 0x00000000); /* disable all */ - mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffffc8ff); /* polarity */ - mtdcr (uic2tr, 0x00ff0000); /* trigger edge vs level */ - mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic2sr, 0xffffffff); /* clear all */ + mtdcr (UIC2SR, 0xffffffff); /* clear all */ + mtdcr (UIC2ER, 0x00000000); /* disable all */ + mtdcr (UIC2CR, 0x00000000); /* all non-critical */ + mtdcr (UIC2PR, 0xffffc8ff); /* polarity */ + mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */ + mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC2SR, 0xffffffff); /* clear all */ - mtdcr (uic3sr, 0xffffffff); /* clear all */ - mtdcr (uic3er, 0x00000000); /* disable all */ - mtdcr (uic3cr, 0x00000000); /* all non-critical */ - mtdcr (uic3pr, 0xffff83ff); /* polarity */ - mtdcr (uic3tr, 0x00ff8c0f); /* trigger edge vs level */ - mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic3sr, 0xffffffff); /* clear all */ + mtdcr (UIC3SR, 0xffffffff); /* clear all */ + mtdcr (UIC3ER, 0x00000000); /* disable all */ + mtdcr (UIC3CR, 0x00000000); /* all non-critical */ + mtdcr (UIC3PR, 0xffff83ff); /* polarity */ + mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */ + mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC3SR, 0xffffffff); /* clear all */ - mtdcr (uic0sr, 0xfc000000); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000000); /* all non-critical */ - mtdcr (uic0pr, 0xfc000000); - mtdcr (uic0tr, 0x00000000); - mtdcr (uic0vr, 0x00000001); + mtdcr (UIC0SR, 0xfc000000); /* clear all */ + mtdcr (UIC0ER, 0x00000000); /* disable all */ + mtdcr (UIC0CR, 0x00000000); /* all non-critical */ + mtdcr (UIC0PR, 0xfc000000); + mtdcr (UIC0TR, 0x00000000); + mtdcr (UIC0VR, 0x00000001); fpga_init(); diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c index ad3f9bc28e1..0c8e6dfb1ec 100644 --- a/board/sandburst/metrobox/metrobox.c +++ b/board/sandburst/metrobox/metrobox.c @@ -202,36 +202,36 @@ int board_early_init_f (void) * UIC2 UIC1 * UIC3 UIC2 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ - mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000000); /* all non- critical */ - mtdcr (uic1pr, 0xfffffe03); /* polarity */ - mtdcr (uic1tr, 0x01c00000); /* trigger edge vs level */ - mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ + mtdcr (UIC1SR, 0xffffffff); /* clear all */ + mtdcr (UIC1ER, 0x00000000); /* disable all */ + mtdcr (UIC1CR, 0x00000000); /* all non- critical */ + mtdcr (UIC1PR, 0xfffffe03); /* polarity */ + mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */ + mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC1SR, 0xffffffff); /* clear all */ - mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uic2er, 0x00000000); /* disable all */ - mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffffc8ff); /* polarity */ - mtdcr (uic2tr, 0x00ff0000); /* trigger edge vs level */ - mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic2sr, 0xffffffff); /* clear all */ + mtdcr (UIC2SR, 0xffffffff); /* clear all */ + mtdcr (UIC2ER, 0x00000000); /* disable all */ + mtdcr (UIC2CR, 0x00000000); /* all non-critical */ + mtdcr (UIC2PR, 0xffffc8ff); /* polarity */ + mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */ + mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC2SR, 0xffffffff); /* clear all */ - mtdcr (uic3sr, 0xffffffff); /* clear all */ - mtdcr (uic3er, 0x00000000); /* disable all */ - mtdcr (uic3cr, 0x00000000); /* all non-critical */ - mtdcr (uic3pr, 0xffff83ff); /* polarity */ - mtdcr (uic3tr, 0x00ff8c0f); /* trigger edge vs level */ - mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic3sr, 0xffffffff); /* clear all */ + mtdcr (UIC3SR, 0xffffffff); /* clear all */ + mtdcr (UIC3ER, 0x00000000); /* disable all */ + mtdcr (UIC3CR, 0x00000000); /* all non-critical */ + mtdcr (UIC3PR, 0xffff83ff); /* polarity */ + mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */ + mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC3SR, 0xffffffff); /* clear all */ - mtdcr (uic0sr, 0xfc000000); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000000); /* all non-critical */ - mtdcr (uic0pr, 0xfc000000); - mtdcr (uic0tr, 0x00000000); - mtdcr (uic0vr, 0x00000001); + mtdcr (UIC0SR, 0xfc000000); /* clear all */ + mtdcr (UIC0ER, 0x00000000); /* disable all */ + mtdcr (UIC0CR, 0x00000000); /* all non-critical */ + mtdcr (UIC0PR, 0xfc000000); + mtdcr (UIC0TR, 0x00000000); + mtdcr (UIC0VR, 0x00000001); fpga_init(); diff --git a/board/sbc405/sbc405.c b/board/sbc405/sbc405.c index 66842eaf4da..74e6204db9e 100644 --- a/board/sbc405/sbc405.c +++ b/board/sbc405/sbc405.c @@ -41,13 +41,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c index 5ae7b1244a7..e7772c5ff6d 100644 --- a/board/sc3/sc3.c +++ b/board/sc3/sc3.c @@ -294,22 +294,22 @@ int board_early_init_f (void) writeb (cpldConfig_1, CPLD_CONTROL_1); /* disable everything in CPLD */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ if (IS_CAMERON) { sc3_cameron_init(); mtdcr (0x0B6, 0x18000000); - mtdcr (uicpr, 0xFFFFFFF0); - mtdcr (uictr, 0x10001030); + mtdcr (UIC0PR, 0xFFFFFFF0); + mtdcr (UIC0TR, 0x10001030); } else { mtdcr (0x0B6, 0x0000000); - mtdcr (uicpr, 0xFFFFFFE0); - mtdcr (uictr, 0x10000020); + mtdcr (UIC0PR, 0xFFFFFFE0); + mtdcr (UIC0TR, 0x10000020); } - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* setup other implementation specific details */ mtdcr (CPC0_ECR, 0x60606000); diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c index 6479beeb13b..00a9f98b44c 100644 --- a/board/w7o/w7o.c +++ b/board/w7o/w7o.c @@ -64,16 +64,16 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0, + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ #elif defined(CONFIG_W7OLMC) /* @@ -95,16 +95,16 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0, + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ #else /* Unknown */ # error "Unknown W7O board configuration" diff --git a/board/xes/xpedite1000/xpedite1000.c b/board/xes/xpedite1000/xpedite1000.c index 58041fcd349..011fb94bb63 100644 --- a/board/xes/xpedite1000/xpedite1000.c +++ b/board/xes/xpedite1000/xpedite1000.c @@ -74,36 +74,36 @@ int board_early_init_f(void) * UIC2 UIC1 * UIC3 UIC2 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000003); /* SMI & UIC1 crit are critical */ - mtdcr(uic1pr, 0xfffffe00); /* per ref-board manual */ - mtdcr(uic1tr, 0x01c00000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000003); /* SMI & UIC1 crit are critical */ + mtdcr(UIC1PR, 0xfffffe00); /* per ref-board manual */ + mtdcr(UIC1TR, 0x01c00000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ - mtdcr(uic2er, 0x00000000); /* disable all */ - mtdcr(uic2cr, 0x00000000); /* all non-critical */ - mtdcr(uic2pr, 0xffffc0ff); /* per ref-board manual */ - mtdcr(uic2tr, 0x00ff8000); /* per ref-board manual */ - mtdcr(uic2vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0xffffc0ff); /* per ref-board manual */ + mtdcr(UIC2TR, 0x00ff8000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtdcr(uic3sr, 0xffffffff); /* clear all */ - mtdcr(uic3er, 0x00000000); /* disable all */ - mtdcr(uic3cr, 0x00000000); /* all non-critical */ - mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic3tr, 0x00ff8c0f); /* per ref-board manual */ - mtdcr(uic3vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic3sr, 0xffffffff); /* clear all */ + mtdcr(UIC3SR, 0xffffffff); /* clear all */ + mtdcr(UIC3ER, 0x00000000); /* disable all */ + mtdcr(UIC3CR, 0x00000000); /* all non-critical */ + mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC3TR, 0x00ff8c0f); /* per ref-board manual */ + mtdcr(UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC3SR, 0xffffffff); /* clear all */ - mtdcr(uic0sr, 0xfc000000); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000000); /* all non-critical */ - mtdcr(uic0pr, 0xfc000000); /* */ - mtdcr(uic0tr, 0x00000000); /* */ - mtdcr(uic0vr, 0x00000001); /* */ + mtdcr(UIC0SR, 0xfc000000); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000000); /* all non-critical */ + mtdcr(UIC0PR, 0xfc000000); /* */ + mtdcr(UIC0TR, 0x00000000); /* */ + mtdcr(UIC0VR, 0x00000001); /* */ LED0_ON(); diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c index fc9dfa02c01..01273a1f7db 100644 --- a/board/zeus/zeus.c +++ b/board/zeus/zeus.c @@ -50,13 +50,13 @@ static u32 start_time; int board_early_init_f(void) { - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); - mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */ - mtdcr(uictr, 0x00000000); /* set int trigger levels */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); + mtdcr(UIC0PR, 0xFFFF7F00); /* set int polarities */ + mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ /* * Configure CPC0_PCI to enable PerWE as output diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c index 3ed15092ae9..5e29ff3bcd7 100644 --- a/common/cmd_reginfo.c +++ b/common/cmd_reginfo.c @@ -93,17 +93,17 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #elif defined (CONFIG_405GP) printf ("\n405GP registers; MSR=%08x\n",mfmsr()); printf ("\nUniversal Interrupt Controller Regs\n" - "uicsr uicer uiccr uicpr uictr uicmsr uicvr uicvcr" + "UIC0SR UIC0ER UIC0CR UIC0PR UIC0TR UIC0MSR UIC0VR UIC0VCR" "\n" "%08x %08x %08x %08x %08x %08x %08x %08x\n", - mfdcr(uicsr), - mfdcr(uicer), - mfdcr(uiccr), - mfdcr(uicpr), - mfdcr(uictr), - mfdcr(uicmsr), - mfdcr(uicvr), - mfdcr(uicvcr)); + mfdcr(UIC0SR), + mfdcr(UIC0ER), + mfdcr(UIC0CR), + mfdcr(UIC0PR), + mfdcr(UIC0TR), + mfdcr(UIC0MSR), + mfdcr(UIC0VR), + mfdcr(UIC0VCR)); puts ("\nMemory (SDRAM) Configuration\n" "besra besrsa besrb besrsb bear mcopt1 rtr pmit\n"); @@ -180,17 +180,17 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #elif defined(CONFIG_405EP) printf ("\n405EP registers; MSR=%08x\n",mfmsr()); printf ("\nUniversal Interrupt Controller Regs\n" - "uicsr uicer uiccr uicpr uictr uicmsr uicvr uicvcr" + "UIC0SR UIC0ER UIC0CR UIC0PR UIC0TR UIC0MSR UIC0VR UIC0VCR" "\n" "%08x %08x %08x %08x %08x %08x %08x %08x\n", - mfdcr(uicsr), - mfdcr(uicer), - mfdcr(uiccr), - mfdcr(uicpr), - mfdcr(uictr), - mfdcr(uicmsr), - mfdcr(uicvr), - mfdcr(uicvcr)); + mfdcr(UIC0SR), + mfdcr(UIC0ER), + mfdcr(UIC0CR), + mfdcr(UIC0PR), + mfdcr(UIC0TR), + mfdcr(UIC0MSR), + mfdcr(UIC0VR), + mfdcr(UIC0VCR)); puts ("\nMemory (SDRAM) Configuration\n" "mcopt1 rtr pmit mb0cf mb1cf sdtr1\n"); diff --git a/cpu/ppc4xx/uic.c b/cpu/ppc4xx/uic.c index d298b312cee..8b1b259fafe 100644 --- a/cpu/ppc4xx/uic.c +++ b/cpu/ppc4xx/uic.c @@ -109,7 +109,7 @@ void external_interrupt(struct pt_regs *regs) /* * Read masked interrupt status register to determine interrupt source */ - uic_msr = mfdcr(uic0msr); + uic_msr = mfdcr(UIC0MSR); #if (UIC_MAX > 1) if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) || @@ -129,7 +129,7 @@ void external_interrupt(struct pt_regs *regs) uic_interrupt(UIC3_DCR_BASE, 96); #endif - mtdcr(uic0sr, (uic_msr & UICB0_ALL)); + mtdcr(UIC0SR, (uic_msr & UICB0_ALL)); if (uic_msr & ~(UICB0_ALL)) uic_interrupt(UIC0_DCR_BASE, 0); @@ -140,13 +140,13 @@ void external_interrupt(struct pt_regs *regs) void pic_irq_ack(unsigned int vec) { if ((vec >= 0) && (vec < 32)) - mtdcr(uicsr, UIC_MASK(vec)); + mtdcr(UIC0SR, UIC_MASK(vec)); else if ((vec >= 32) && (vec < 64)) - mtdcr(uic1sr, UIC_MASK(vec)); + mtdcr(UIC1SR, UIC_MASK(vec)); else if ((vec >= 64) && (vec < 96)) - mtdcr(uic2sr, UIC_MASK(vec)); + mtdcr(UIC2SR, UIC_MASK(vec)); else if (vec >= 96) - mtdcr(uic3sr, UIC_MASK(vec)); + mtdcr(UIC3SR, UIC_MASK(vec)); } /* @@ -156,13 +156,13 @@ void pic_irq_enable(unsigned int vec) { if ((vec >= 0) && (vec < 32)) - mtdcr(uicer, mfdcr(uicer) | UIC_MASK(vec)); + mtdcr(UIC0ER, mfdcr(UIC0ER) | UIC_MASK(vec)); else if ((vec >= 32) && (vec < 64)) - mtdcr(uic1er, mfdcr(uic1er) | UIC_MASK(vec)); + mtdcr(UIC1ER, mfdcr(UIC1ER) | UIC_MASK(vec)); else if ((vec >= 64) && (vec < 96)) - mtdcr(uic2er, mfdcr(uic2er) | UIC_MASK(vec)); + mtdcr(UIC2ER, mfdcr(UIC2ER) | UIC_MASK(vec)); else if (vec >= 96) - mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec)); + mtdcr(UIC3ER, mfdcr(UIC3ER) | UIC_MASK(vec)); debug("Install interrupt vector %d\n", vec); } @@ -170,11 +170,11 @@ void pic_irq_enable(unsigned int vec) void pic_irq_disable(unsigned int vec) { if ((vec >= 0) && (vec < 32)) - mtdcr(uicer, mfdcr(uicer) & ~UIC_MASK(vec)); + mtdcr(UIC0ER, mfdcr(UIC0ER) & ~UIC_MASK(vec)); else if ((vec >= 32) && (vec < 64)) - mtdcr(uic1er, mfdcr(uic1er) & ~UIC_MASK(vec)); + mtdcr(UIC1ER, mfdcr(UIC1ER) & ~UIC_MASK(vec)); else if ((vec >= 64) && (vec < 96)) - mtdcr(uic2er, mfdcr(uic2er) & ~UIC_MASK(vec)); + mtdcr(UIC2ER, mfdcr(UIC2ER) & ~UIC_MASK(vec)); else if (vec >= 96) - mtdcr(uic3er, mfdcr(uic3er) & ~UIC_MASK(vec)); + mtdcr(UIC3ER, mfdcr(UIC3ER) & ~UIC_MASK(vec)); } diff --git a/include/asm-ppc/ppc4xx-uic.h b/include/asm-ppc/ppc4xx-uic.h index c908d424525..782d0454b7e 100644 --- a/include/asm-ppc/ppc4xx-uic.h +++ b/include/asm-ppc/ppc4xx-uic.h @@ -1,7 +1,7 @@ /* * Copyright (C) 2002 Scott McNutt * - * (C) Copyright 2008 + * (C) Copyright 2008-2009 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this @@ -43,7 +43,7 @@ #define UIC_MAX 1 #endif -#define IRQ_MAX UIC_MAX * 32 +#define IRQ_MAX (UIC_MAX * 32) /* * UIC register @@ -74,53 +74,41 @@ #define UIC3_DCR_BASE 0xf0 #endif -#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ -#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ -#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */ -#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ -#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ -#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ -#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */ -#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ +#define UIC0SR (UIC0_DCR_BASE+0x0) /* UIC0 status */ +#define UIC0ER (UIC0_DCR_BASE+0x2) /* UIC0 enable */ +#define UIC0CR (UIC0_DCR_BASE+0x3) /* UIC0 critical */ +#define UIC0PR (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ +#define UIC0TR (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ +#define UIC0MSR (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ +#define UIC0VR (UIC0_DCR_BASE+0x7) /* UIC0 vector */ +#define UIC0VCR (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ -#define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */ -#define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */ -#define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */ -#define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */ -#define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */ -#define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */ -#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */ -#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */ +#define UIC1SR (UIC1_DCR_BASE+0x0) /* UIC1 status */ +#define UIC1ER (UIC1_DCR_BASE+0x2) /* UIC1 enable */ +#define UIC1CR (UIC1_DCR_BASE+0x3) /* UIC1 critical */ +#define UIC1PR (UIC1_DCR_BASE+0x4) /* UIC1 polarity */ +#define UIC1TR (UIC1_DCR_BASE+0x5) /* UIC1 triggering */ +#define UIC1MSR (UIC1_DCR_BASE+0x6) /* UIC1 masked status */ +#define UIC1VR (UIC1_DCR_BASE+0x7) /* UIC1 vector */ +#define UIC1VCR (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */ -#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */ -#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */ -#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */ -#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */ -#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */ -#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */ -#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */ -#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */ -#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */ +#define UIC2SR (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */ +#define UIC2ER (UIC2_DCR_BASE+0x2) /* UIC2 enable */ +#define UIC2CR (UIC2_DCR_BASE+0x3) /* UIC2 critical */ +#define UIC2PR (UIC2_DCR_BASE+0x4) /* UIC2 polarity */ +#define UIC2TR (UIC2_DCR_BASE+0x5) /* UIC2 triggering */ +#define UIC2MSR (UIC2_DCR_BASE+0x6) /* UIC2 masked status */ +#define UIC2VR (UIC2_DCR_BASE+0x7) /* UIC2 vector */ +#define UIC2VCR (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */ -#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */ -#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */ -#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */ -#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */ -#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */ -#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */ -#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */ -#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */ -#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */ - -/* The following is for compatibility with 405 code */ -#define uicsr uic0sr -#define uicer uic0er -#define uiccr uic0cr -#define uicpr uic0pr -#define uictr uic0tr -#define uicmsr uic0msr -#define uicvr uic0vr -#define uicvcr uic0vcr +#define UIC3SR (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */ +#define UIC3ER (UIC3_DCR_BASE+0x2) /* UIC3 enable */ +#define UIC3CR (UIC3_DCR_BASE+0x3) /* UIC3 critical */ +#define UIC3PR (UIC3_DCR_BASE+0x4) /* UIC3 polarity */ +#define UIC3TR (UIC3_DCR_BASE+0x5) /* UIC3 triggering */ +#define UIC3MSR (UIC3_DCR_BASE+0x6) /* UIC3 masked status */ +#define UIC3VR (UIC3_DCR_BASE+0x7) /* UIC3 vector */ +#define UIC3VCR (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */ /* * Now the interrupt vector definitions. They are different for most of From 95b602bab5fec2fffab07a01ea3947c70d1bacc1 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 24 Sep 2009 13:59:57 +0200 Subject: [PATCH 196/208] ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper case The latest PPC4xx register cleanup patch missed some SDRAM defines. This patch now changes lower case UIC defines to upper case. Also some names are changed to match the naming in the IBM/AMCC users manuals (e.g. mem_mcopt1 -> SDRAM0_CFG). Signed-off-by: Stefan Roese --- board/amcc/ebony/ebony.c | 24 ++++----- board/amcc/ocotea/ocotea.c | 24 ++++----- board/amcc/yosemite/yosemite.c | 32 +++++------ board/cray/L1/L1.c | 18 +++---- board/csb272/csb272.c | 8 +-- board/csb272/init.S | 18 +++---- board/csb472/csb472.c | 8 +-- board/csb472/init.S | 18 +++---- board/eric/init.S | 14 ++--- board/exbitgen/exbitgen.c | 8 +-- board/exbitgen/init.S | 14 ++--- board/g2000/g2000.c | 14 ++--- board/jse/sdram.c | 36 ++++++------- board/mpl/mip405/mip405.c | 38 ++++++------- board/mpl/pip405/pip405.c | 36 ++++++------- board/netstal/common/fixed_sdram.c | 40 +++++++------- board/sandburst/common/sb_common.c | 24 ++++----- board/sc3/sc3.c | 22 ++++---- board/w7o/init.S | 10 ++-- board/w7o/w7o.c | 8 +-- common/cmd_reginfo.c | 42 +++++++-------- cpu/ppc4xx/40x_spd_sdram.c | 26 ++++----- cpu/ppc4xx/44x_spd_ddr.c | 44 +++++++-------- cpu/ppc4xx/sdram.c | 60 ++++++++++----------- include/asm-ppc/ppc4xx-sdram.h | 86 ++++++++++++------------------ nand_spl/board/amcc/bamboo/sdram.c | 26 ++++----- 26 files changed, 341 insertions(+), 357 deletions(-) diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c index 0543bad138a..e61b5de2d84 100644 --- a/board/amcc/ebony/ebony.c +++ b/board/amcc/ebony/ebony.c @@ -131,11 +131,11 @@ long int fixed_sdram(void) /*-------------------------------------------------------------------- * Setup some default *------------------------------------------------------------------*/ - mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ - mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ + mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ + mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ + mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ + mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ + mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ /*-------------------------------------------------------------------- * Setup for board-specific specific mem @@ -143,20 +143,20 @@ long int fixed_sdram(void) /* * Following for CAS Latency = 2.5 @ 133 MHz PLB */ - mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ - mtsdram(mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ + mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ + mtsdram(SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ /* RA=10 RD=3 */ - mtsdram(mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram(mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ + mtsdram(SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ + mtsdram(SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ + mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */ udelay(400); /* Delay 200 usecs (min) */ /*-------------------------------------------------------------------- * Enable the controller, then wait for DCEN to complete *------------------------------------------------------------------*/ - mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ + mtsdram(SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ for (;;) { - mfsdram(mem_mcsts, reg); + mfsdram(SDRAM0_MCSTS, reg); if (reg & 0x80000000) break; } diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index 8513f43a8f1..d776edabcda 100644 --- a/board/amcc/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -241,11 +241,11 @@ long int fixed_sdram (void) /*-------------------------------------------------------------------- * Setup some default *------------------------------------------------------------------*/ - mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */ - mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ + mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ + mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ + mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ + mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ + mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ /*-------------------------------------------------------------------- * Setup for board-specific specific mem @@ -253,20 +253,20 @@ long int fixed_sdram (void) /* * Following for CAS Latency = 2.5 @ 133 MHz PLB */ - mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ - mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ + mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ + mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ /* RA=10 RD=3 */ - mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ + mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ + mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ + mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */ udelay (400); /* Delay 200 usecs (min) */ /*-------------------------------------------------------------------- * Enable the controller, then wait for DCEN to complete *------------------------------------------------------------------*/ - mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ + mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ for (;;) { - mfsdram (mem_mcsts, reg); + mfsdram (SDRAM0_MCSTS, reg); if (reg & 0x80000000) break; } diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 731d441526f..1ec13eb6b56 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -237,7 +237,7 @@ void sdram_tr1_set(int ram_address, int* tr1_value) /* go through all possible SDRAM0_TR1[RDCT] values */ for (i=0; i<=0x1ff; i++) { /* set the current value for TR1 */ - mtsdram(mem_tr1, (0x80800800 | i)); + mtsdram(SDRAM0_TR1, (0x80800800 | i)); /* write values */ for (j=0; j> 28) & 0x3); */ /* write SDRAM timing for 100MHz. */ - mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); mtdcr (SDRAM0_CFGDATA, 0x0086400D); /* write SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); mtdcr (SDRAM0_CFGDATA, 0x05F00000); udelay (200); /* sdram controller.*/ - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); mtdcr (SDRAM0_CFGDATA, 0x90800000); udelay (200); /* initially, disable ECC on all banks */ udelay (200); - mtdcr (SDRAM0_CFGADDR, mem_ecccf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); tmp = mfdcr (SDRAM0_CFGDATA); tmp &= 0xff0fffff; - mtdcr (SDRAM0_CFGADDR, mem_ecccf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); mtdcr (SDRAM0_CFGDATA, tmp); return; @@ -282,15 +282,15 @@ int testdram (void) } printf ("Enable ECC.."); - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000; - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); mtdcr (SDRAM0_CFGDATA, tmp); udelay (600); for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L) ; udelay (400); - mtdcr (SDRAM0_CFGADDR, mem_ecccf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); tmp = mfdcr (SDRAM0_CFGDATA); tmp |= 0x00800000; mtdcr (SDRAM0_CFGDATA, tmp); diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c index 740e3ac6f5e..d6d65cf45cf 100644 --- a/board/csb272/csb272.c +++ b/board/csb272/csb272.c @@ -135,28 +135,28 @@ phys_size_t initdram (int board_type) tot_size = 0; - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); diff --git a/board/csb272/init.S b/board/csb272/init.S index 15b26f8bf86..a6b0d4045a7 100644 --- a/board/csb272/init.S +++ b/board/csb272/init.S @@ -175,26 +175,26 @@ sdram_init: * Disable memory controller to allow * values to be changed. */ - WDCR_SDRAM(mem_mcopt1, 0x00000000) + WDCR_SDRAM(SDRAM0_CFG, 0x00000000) /* * Configure Memory Banks */ - WDCR_SDRAM(mem_mb0cf, 0x00084001) - WDCR_SDRAM(mem_mb1cf, 0x00000000) - WDCR_SDRAM(mem_mb2cf, 0x00000000) - WDCR_SDRAM(mem_mb3cf, 0x00000000) + WDCR_SDRAM(SDRAM0_B0CR, 0x00084001) + WDCR_SDRAM(SDRAM0_B1CR, 0x00000000) + WDCR_SDRAM(SDRAM0_B2CR, 0x00000000) + WDCR_SDRAM(SDRAM0_B3CR, 0x00000000) /* * Set up SDTR1 (SDRAM Timing Register) */ - WDCR_SDRAM(mem_sdtr1, 0x00854009) + WDCR_SDRAM(SDRAM0_TR, 0x00854009) /* * Set RTR (Refresh Timing Register) */ - WDCR_SDRAM(mem_rtr, 0x10000000) - /* WDCR_SDRAM(mem_rtr, 0x05f00000) */ + WDCR_SDRAM(SDRAM0_RTR, 0x10000000) + /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */ /******************************************************************** * Delay to ensure 200usec have elapsed since reset. Assume worst @@ -210,7 +210,7 @@ sdram_init: /******************************************************************** * Set memory controller options reg, MCOPT1. *******************************************************************/ - WDCR_SDRAM(mem_mcopt1,0x80800000) + WDCR_SDRAM(SDRAM0_CFG,0x80800000) ..sdri_done: blr /* Return to calling function */ diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c index 0c7760a02f8..20d34adfdd6 100644 --- a/board/csb472/csb472.c +++ b/board/csb472/csb472.c @@ -103,28 +103,28 @@ phys_size_t initdram (int board_type) tot_size = 0; - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); diff --git a/board/csb472/init.S b/board/csb472/init.S index 105cb71bec0..b31bd045504 100644 --- a/board/csb472/init.S +++ b/board/csb472/init.S @@ -171,26 +171,26 @@ sdram_init: * Disable memory controller to allow * values to be changed. */ - WDCR_SDRAM(mem_mcopt1, 0x00000000) + WDCR_SDRAM(SDRAM0_CFG, 0x00000000) /* * Configure Memory Banks */ - WDCR_SDRAM(mem_mb0cf, 0x00062001) - WDCR_SDRAM(mem_mb1cf, 0x00000000) - WDCR_SDRAM(mem_mb2cf, 0x00000000) - WDCR_SDRAM(mem_mb3cf, 0x00000000) + WDCR_SDRAM(SDRAM0_B0CR, 0x00062001) + WDCR_SDRAM(SDRAM0_B1CR, 0x00000000) + WDCR_SDRAM(SDRAM0_B2CR, 0x00000000) + WDCR_SDRAM(SDRAM0_B3CR, 0x00000000) /* * Set up SDTR1 (SDRAM Timing Register) */ - WDCR_SDRAM(mem_sdtr1, 0x00854009) + WDCR_SDRAM(SDRAM0_TR, 0x00854009) /* * Set RTR (Refresh Timing Register) */ - WDCR_SDRAM(mem_rtr, 0x10000000) - /* WDCR_SDRAM(mem_rtr, 0x05f00000) */ + WDCR_SDRAM(SDRAM0_RTR, 0x10000000) + /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */ /******************************************************************** * Delay to ensure 200usec have elapsed since reset. Assume worst @@ -206,7 +206,7 @@ sdram_init: /******************************************************************** * Set memory controller options reg, MCOPT1. *******************************************************************/ - WDCR_SDRAM(mem_mcopt1,0x80800000) + WDCR_SDRAM(SDRAM0_CFG,0x80800000) ..sdri_done: blr /* Return to calling function */ diff --git a/board/eric/init.S b/board/eric/init.S index 16ab11eae25..c18663a75dc 100644 --- a/board/eric/init.S +++ b/board/eric/init.S @@ -228,7 +228,7 @@ sdram_init: /* Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2) */ /*------------------------------------------------------------------- */ - addi r4,0,mem_mb0cf + addi r4,0,SDRAM0_B0CR mtdcr SDRAM0_CFGADDR,r4 addis r4,0,MB0CF@h ori r4,r4,MB0CF@l @@ -238,7 +238,7 @@ sdram_init: /* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) */ /*------------------------------------------------------------------- */ - addi r4,0,mem_mb1cf + addi r4,0,SDRAM0_B1CR mtdcr SDRAM0_CFGADDR,r4 addis r4,0,MB1CF@h ori r4,r4,MB1CF@l @@ -248,7 +248,7 @@ sdram_init: /* Set MB2CF for bank 2. off */ /*------------------------------------------------------------------- */ - addi r4,0,mem_mb2cf + addi r4,0,SDRAM0_B2CR mtdcr SDRAM0_CFGADDR,r4 addis r4,0,MB2CF@h ori r4,r4,MB2CF@l @@ -258,7 +258,7 @@ sdram_init: /* Set MB3CF for bank 3. off */ /*------------------------------------------------------------------- */ - addi r4,0,mem_mb3cf + addi r4,0,SDRAM0_B3CR mtdcr SDRAM0_CFGADDR,r4 addis r4,0,MB3CF@h ori r4,r4,MB3CF@l @@ -305,14 +305,14 @@ sdram_init: /*------------------------------------------------------------------- */ /* Set SDTR1 */ /*------------------------------------------------------------------- */ - addi r4,0,mem_sdtr1 + addi r4,0,SDRAM0_TR mtdcr SDRAM0_CFGADDR,r4 mtdcr SDRAM0_CFGDATA,r6 /*------------------------------------------------------------------- */ /* Set RTR */ /*------------------------------------------------------------------- */ - addi r4,0,mem_rtr + addi r4,0,SDRAM0_RTR mtdcr SDRAM0_CFGADDR,r4 mtdcr SDRAM0_CFGDATA,r7 @@ -332,7 +332,7 @@ sdram_init: /* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */ /* read/prefetch. */ /*------------------------------------------------------------------- */ - addi r4,0,mem_mcopt1 + addi r4,0,SDRAM0_CFG mtdcr SDRAM0_CFGADDR,r4 addis r4,0,0x8080 /* set DC_EN=1 */ ori r4,r4,0x0000 diff --git a/board/exbitgen/exbitgen.c b/board/exbitgen/exbitgen.c index ce6469d29e1..50d9748c71a 100644 --- a/board/exbitgen/exbitgen.c +++ b/board/exbitgen/exbitgen.c @@ -94,28 +94,28 @@ phys_size_t initdram (int board_type) tot_size = 0; - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); diff --git a/board/exbitgen/init.S b/board/exbitgen/init.S index c2dae560f5f..7a9726fe78e 100644 --- a/board/exbitgen/init.S +++ b/board/exbitgen/init.S @@ -382,7 +382,7 @@ sdram_init: /*----------------------------------------------------------- */ /* Set SDTR1 */ /*----------------------------------------------------------- */ - addi r5,0,mem_sdtr1 + addi r5,0,SDRAM0_TR mtdcr SDRAM0_CFGADDR,r5 mtdcr SDRAM0_CFGDATA,r4 @@ -413,7 +413,7 @@ sdram_init: /* Set SDRAM bank 0 register and adjust r6 for next bank */ /*------------------------------------------------------ */ - addi r7,0,mem_mb0cf + addi r7,0,SDRAM0_B0CR mtdcr SDRAM0_CFGADDR,r7 mtdcr SDRAM0_CFGDATA,r6 @@ -424,7 +424,7 @@ sdram_init: cmpi 0, r12, 2 bne b1skip - addi r7,0,mem_mb1cf + addi r7,0,SDRAM0_B1CR mtdcr SDRAM0_CFGADDR,r7 mtdcr SDRAM0_CFGDATA,r6 @@ -432,7 +432,7 @@ sdram_init: /* Set SDRAM bank 2 register and adjust r6 for next bank */ /*------------------------------------------------------ */ -b1skip: addi r7,0,mem_mb2cf +b1skip: addi r7,0,SDRAM0_B2CR mtdcr SDRAM0_CFGADDR,r7 mtdcr SDRAM0_CFGDATA,r6 @@ -443,7 +443,7 @@ b1skip: addi r7,0,mem_mb2cf cmpi 0, r12, 2 bne b3skip - addi r7,0,mem_mb3cf + addi r7,0,SDRAM0_B3CR mtdcr SDRAM0_CFGADDR,r7 mtdcr SDRAM0_CFGDATA,r6 b3skip: @@ -456,7 +456,7 @@ b3skip: addis r7, 0, 0x05F0 /* RTR value for 100Mhz */ bl rtr_2 rtr_1: addis r7, 0, 0x03F8 -rtr_2: addi r4,0,mem_rtr +rtr_2: addi r4,0,SDRAM0_RTR mtdcr SDRAM0_CFGADDR,r4 mtdcr SDRAM0_CFGDATA,r7 @@ -476,7 +476,7 @@ rtr_2: addi r4,0,mem_rtr /* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */ /* read/prefetch. */ /*----------------------------------------------------------- */ - addi r4,0,mem_mcopt1 + addi r4,0,SDRAM0_CFG mtdcr SDRAM0_CFGADDR,r4 addis r4,0,0x80C0 /* set DC_EN=1 */ ori r4,r4,0x0000 diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c index 8afffdc7372..092a3d8a19a 100644 --- a/board/g2000/g2000.c +++ b/board/g2000/g2000.c @@ -116,16 +116,16 @@ long int init_sdram_static_settings(void) { #define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data) /* disable memcontroller so updates work */ - mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL ); - mtsdram0( mem_rtr , MEM_RTR_INIT_VAL ); - mtsdram0( mem_pmit , MEM_PMIT_INIT_VAL ); - mtsdram0( mem_mb0cf , MEM_MB0CF_INIT_VAL ); - mtsdram0( mem_mb1cf , MEM_MB1CF_INIT_VAL ); - mtsdram0( mem_sdtr1 , MEM_SDTR1_INIT_VAL ); + mtsdram0( SDRAM0_CFG, MEM_MCOPT1_INIT_VAL ); + mtsdram0( SDRAM0_RTR , MEM_RTR_INIT_VAL ); + mtsdram0( SDRAM0_PMIT , MEM_PMIT_INIT_VAL ); + mtsdram0( SDRAM0_B0CR , MEM_MB0CF_INIT_VAL ); + mtsdram0( SDRAM0_B1CR , MEM_MB1CF_INIT_VAL ); + mtsdram0( SDRAM0_TR , MEM_SDTR1_INIT_VAL ); /* SDRAM have a power on delay, 500 micro should do */ udelay(500); - mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE ); + mtsdram0( SDRAM0_CFG, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE ); return (CONFIG_SYS_SDRAM_SIZE); /* CONFIG_SYS_SDRAM_SIZE is in G2000.h */ } diff --git a/board/jse/sdram.c b/board/jse/sdram.c index bb6f85eee51..88fdd84130f 100644 --- a/board/jse/sdram.c +++ b/board/jse/sdram.c @@ -35,59 +35,59 @@ phys_size_t initdram (int board_type) /* Configure the SDRAMS */ /* disable memory controller */ - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); mtdcr (SDRAM0_CFGDATA, 0x00000000); udelay (500); /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */ - mtdcr (SDRAM0_CFGADDR, mem_besra); + mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR0); mtdcr (SDRAM0_CFGDATA, 0xffffffff); /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */ - mtdcr (SDRAM0_CFGADDR, mem_besrb); + mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR1); mtdcr (SDRAM0_CFGDATA, 0xffffffff); /* Clear SDRAM0_ECCCFG (disable ECC) */ - mtdcr (SDRAM0_CFGADDR, mem_ecccf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); mtdcr (SDRAM0_CFGDATA, 0x00000000); /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */ - mtdcr (SDRAM0_CFGADDR, mem_eccerr); + mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCESR); mtdcr (SDRAM0_CFGDATA, 0xffffffff); /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */ - mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); mtdcr (SDRAM0_CFGDATA, 0x010a4016); /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */ - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); mtdcr (SDRAM0_CFGDATA, 0x00084001); /* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */ - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); mtdcr (SDRAM0_CFGDATA, 0x04084001); /* Memory Bank 2 Config == BE=0 */ - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); mtdcr (SDRAM0_CFGDATA, 0x00000000); /* Memory Bank 3 Config == BE=0 */ - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); mtdcr (SDRAM0_CFGDATA, 0x00000000); /* refresh timer = 0x400 */ - mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); mtdcr (SDRAM0_CFGDATA, 0x04000000); /* Power management idle timer set to the default. */ - mtdcr (SDRAM0_CFGADDR, mem_pmit); + mtdcr (SDRAM0_CFGADDR, SDRAM0_PMIT); mtdcr (SDRAM0_CFGDATA, 0x07c00000); udelay (500); /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */ - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); mtdcr (SDRAM0_CFGDATA, 0x80e00000); return SDRAM_LEN; @@ -108,7 +108,7 @@ int testdram (void) #ifdef DEBUG printf ("SDRAM Controller Registers --\n"); - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_CFG : 0x%08x\n", val); @@ -116,19 +116,19 @@ int testdram (void) val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_STATUS: 0x%08x\n", val); - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_B0CR : 0x%08x\n", val); - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_B1CR : 0x%08x\n", val); - mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_TR : 0x%08x\n", val); - mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_RTR : 0x%08x\n", val); #endif diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c index b87df01fec2..ae8eade64ad 100644 --- a/board/mpl/mip405/mip405.c +++ b/board/mpl/mip405/mip405.c @@ -348,7 +348,7 @@ int init_sdram (void) /* trc_clocks is sum of trp_clocks + tras_clocks */ trc_clocks = trp_clocks + tras_clocks; /* get SDRAM timing register */ - mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F; /* insert CASL value */ sdram_tim |= ((unsigned long) (cal_val)) << 23; @@ -369,7 +369,7 @@ int init_sdram (void) /* insert SZ value; */ tmp |= ((unsigned long) sdram_table[i].sz << 17); /* get SDRAM bank 0 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; sdram_bank |= (baseaddr | tmp | 0x01); @@ -380,7 +380,7 @@ int init_sdram (void) #endif /* write SDRAM timing register */ - mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); mtdcr (SDRAM0_CFGDATA, sdram_tim); #ifdef SDRAM_DEBUG @@ -390,22 +390,22 @@ int init_sdram (void) #endif /* write SDRAM bank 0 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); mtdcr (SDRAM0_CFGDATA, sdram_bank); if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */ /* get SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; tmp |= 0x07F00000; } else { /* get SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; tmp |= 0x05F00000; } /* write SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); mtdcr (SDRAM0_CFGDATA, tmp); /* enable ECC if used */ #if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI) @@ -415,18 +415,18 @@ int init_sdram (void) #ifdef SDRAM_DEBUG serial_puts ("disable ECC.. "); #endif - mtdcr (SDRAM0_CFGADDR, mem_ecccf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); tmp = mfdcr (SDRAM0_CFGDATA); tmp &= 0xff0fffff; /* disable all banks */ - mtdcr (SDRAM0_CFGADDR, mem_ecccf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); /* set up SDRAM Controller with ECC enabled */ #ifdef SDRAM_DEBUG serial_puts ("setup SDRAM Controller.. "); #endif mtdcr (SDRAM0_CFGDATA, tmp); - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000; - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); mtdcr (SDRAM0_CFGDATA, tmp); udelay (600); #ifdef SDRAM_DEBUG @@ -447,7 +447,7 @@ int init_sdram (void) serial_puts ("enable ECC\n"); #endif udelay (400); - mtdcr (SDRAM0_CFGADDR, mem_ecccf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); tmp = mfdcr (SDRAM0_CFGDATA); tmp |= 0x00800000; /* enable bank 0 */ mtdcr (SDRAM0_CFGDATA, tmp); @@ -456,9 +456,9 @@ int init_sdram (void) #endif { /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000; - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); mtdcr (SDRAM0_CFGDATA, tmp); udelay (400); } @@ -631,13 +631,13 @@ phys_size_t initdram (int board_type) ds = 0; /* since the DRAM controller is allready set up, calculate the size with the bank registers */ - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); bank_reg[0] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); bank_reg[1] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); bank_reg[2] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); bank_reg[3] = mfdcr (SDRAM0_CFGDATA); TotalSize = 0; for (i = 0; i < 4; i++) { @@ -648,7 +648,7 @@ phys_size_t initdram (int board_type) } else ds = 1; } - mtdcr (SDRAM0_CFGADDR, mem_ecccf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); tmp = mfdcr (SDRAM0_CFGDATA); if (!tmp) diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c index c2d6c6fbcfa..792eccc1545 100644 --- a/board/mpl/pip405/pip405.c +++ b/board/mpl/pip405/pip405.c @@ -361,7 +361,7 @@ int board_early_init_f (void) SDRAM_err ("unsupported SDRAM"); /* get SDRAM timing register */ - mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F; /* insert CASL value */ /* tmp |= ((unsigned long)cal_val) << 23; */ @@ -385,7 +385,7 @@ int board_early_init_f (void) #endif /* write SDRAM timing register */ - mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); mtdcr (SDRAM0_CFGDATA, tmp); baseaddr = CONFIG_SYS_SDRAM_BASE; bank_size = (((unsigned long) density) << 22) / 2; @@ -418,7 +418,7 @@ int board_early_init_f (void) SDRAM_err ("unsupported SDRAM"); } /* endswitch */ /* get SDRAM bank 0 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; bank |= (baseaddr | tmp | 0x01); #ifdef SDRAM_DEBUG @@ -434,11 +434,11 @@ int board_early_init_f (void) sdram_size += bank_size; /* write SDRAM bank 0 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); mtdcr (SDRAM0_CFGDATA, bank); /* get SDRAM bank 1 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; sdram_size = 0; @@ -459,11 +459,11 @@ int board_early_init_f (void) serial_puts ("\n"); #endif /* write SDRAM bank 1 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); mtdcr (SDRAM0_CFGDATA, bank); /* get SDRAM bank 2 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; bank |= (baseaddr | tmp | 0x01); @@ -482,11 +482,11 @@ int board_early_init_f (void) sdram_size += bank_size; /* write SDRAM bank 2 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); mtdcr (SDRAM0_CFGDATA, bank); /* get SDRAM bank 3 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; #ifdef SDRAM_DEBUG @@ -509,12 +509,12 @@ int board_early_init_f (void) #endif /* write SDRAM bank 3 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); mtdcr (SDRAM0_CFGDATA, bank); /* get SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; if (tmemclk < NSto10PS (16)) @@ -523,13 +523,13 @@ int board_early_init_f (void) tmp |= 0x03F80000; /* write SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); mtdcr (SDRAM0_CFGDATA, tmp); /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000; - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); mtdcr (SDRAM0_CFGDATA, tmp); @@ -619,13 +619,13 @@ phys_size_t initdram (int board_type) /* since the DRAM controller is allready set up, * calculate the size with the bank registers */ - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); bank_reg[0] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); bank_reg[1] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); bank_reg[2] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); bank_reg[3] = mfdcr (SDRAM0_CFGDATA); TotalSize = 0; for (i = 0; i < 4; i++) { diff --git a/board/netstal/common/fixed_sdram.c b/board/netstal/common/fixed_sdram.c index f7baed6e910..2f21fbb4e38 100644 --- a/board/netstal/common/fixed_sdram.c +++ b/board/netstal/common/fixed_sdram.c @@ -29,17 +29,17 @@ void show_sdram_registers(void) u32 value; printf("SDRAM Controller Registers --\n"); - mfsdram(mem_mcopt1, value); + mfsdram(SDRAM0_CFG, value); printf(" SDRAM0_CFG : 0x%08x\n", value); - mfsdram(mem_status, value); + mfsdram(SDRAM0_STATUS, value); printf(" SDRAM0_STATUS: 0x%08x\n", value); - mfsdram(mem_mb0cf, value); + mfsdram(SDRAM0_B0CR, value); printf(" SDRAM0_B0CR : 0x%08x\n", value); - mfsdram(mem_mb1cf, value); + mfsdram(SDRAM0_B1CR, value); printf(" SDRAM0_B1CR : 0x%08x\n", value); - mfsdram(mem_sdtr1, value); + mfsdram(SDRAM0_TR, value); printf(" SDRAM0_TR : 0x%08x\n", value); - mfsdram(mem_rtr, value); + mfsdram(SDRAM0_RTR, value); printf(" SDRAM0_RTR : 0x%08x\n", value); } #endif @@ -50,53 +50,53 @@ long int init_ppc405_sdram(unsigned int dram_size) printf(__FUNCTION__); #endif /* disable memory controller */ - mtsdram(mem_mcopt1, 0x00000000); + mtsdram(SDRAM0_CFG, 0x00000000); udelay (500); /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */ - mtsdram(mem_besra, 0xffffffff); + mtsdram(SDRAM0_BESR0, 0xffffffff); /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */ - mtsdram(mem_besrb, 0xffffffff); + mtsdram(SDRAM0_BESR1, 0xffffffff); /* Clear SDRAM0_ECCCFG (disable ECC) */ - mtsdram(mem_ecccf, 0x00000000); + mtsdram(SDRAM0_ECCCFG, 0x00000000); /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */ - mtsdram(mem_eccerr, 0xffffffff); + mtsdram(SDRAM0_ECCESR, 0xffffffff); /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */ - mtsdram(mem_sdtr1, 0x008a4015); + mtsdram(SDRAM0_TR, 0x008a4015); /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 * and refresh timer */ switch (dram_size >> 20) { case 32: - mtsdram(mem_mb0cf, 0x00062001); - mtsdram(mem_rtr, 0x07F00000); + mtsdram(SDRAM0_B0CR, 0x00062001); + mtsdram(SDRAM0_RTR, 0x07F00000); break; case 64: - mtsdram(mem_mb0cf, 0x00084001); - mtsdram(mem_rtr, 0x04100000); + mtsdram(SDRAM0_B0CR, 0x00084001); + mtsdram(SDRAM0_RTR, 0x04100000); break; case 128: - mtsdram(mem_mb0cf, 0x000A4001); - mtsdram(mem_rtr, 0x04100000); + mtsdram(SDRAM0_B0CR, 0x000A4001); + mtsdram(SDRAM0_RTR, 0x04100000); break; default: printf("Invalid memory size of %d MB given\n", dram_size >> 20); } /* Power management idle timer set to the default. */ - mtsdram(mem_pmit, 0x07c00000); + mtsdram(SDRAM0_PMIT, 0x07c00000); udelay (500); /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */ - mtsdram(mem_mcopt1, 0x90800000); + mtsdram(SDRAM0_CFG, 0x90800000); #ifdef DEBUG printf("%s: done\n", __FUNCTION__); diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c index d8b0564b3be..e1c61463dd2 100644 --- a/board/sandburst/common/sb_common.c +++ b/board/sandburst/common/sb_common.c @@ -266,11 +266,11 @@ long int fixed_sdram (void) /*-------------------------------------------------------------------- * Setup some default *------------------------------------------------------------------*/ - mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */ - mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ + mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ + mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ + mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ + mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ + mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ /*-------------------------------------------------------------------- * Setup for board-specific specific mem @@ -278,20 +278,20 @@ long int fixed_sdram (void) /* * Following for CAS Latency = 2.5 @ 133 MHz PLB */ - mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ - mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ + mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ + mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ /* RA=10 RD=3 */ - mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ + mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ + mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ + mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */ udelay (400); /* Delay 200 usecs (min) */ /*-------------------------------------------------------------------- * Enable the controller, then wait for DCEN to complete *------------------------------------------------------------------*/ - mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ + mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ for (;;) { - mfsdram (mem_mcsts, reg); + mfsdram (SDRAM0_MCSTS, reg); if (reg & 0x80000000) break; } diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c index e7772c5ff6d..63927f72984 100644 --- a/board/sc3/sc3.c +++ b/board/sc3/sc3.c @@ -577,7 +577,7 @@ static int printSDRAMConfig(char reg, unsigned long cr) } #ifdef SC3_DEBUGOUT -static unsigned int mbcf[] = {mem_mb0cf, mem_mb1cf, mem_mb2cf, mem_mb3cf}; +static unsigned int mbcf[] = {SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2CR, SDRAM0_B3CR}; #endif phys_size_t initdram (int board_type) @@ -591,7 +591,7 @@ phys_size_t initdram (int board_type) puts("\nSDRAM configuration:\n"); - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); ul1 = mfdcr(SDRAM0_CFGDATA); if (!(ul1 & 0x80000000)) { @@ -604,7 +604,7 @@ phys_size_t initdram (int board_type) mems += printSDRAMConfig (i, ul1); } - mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); ul1 = mfdcr(SDRAM0_CFGDATA); printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1); @@ -614,14 +614,14 @@ phys_size_t initdram (int board_type) printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4); printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1)); puts ("Misc:\n"); - mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); ul1 = mfdcr(SDRAM0_CFGDATA); printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7); - mtdcr(SDRAM0_CFGADDR,mem_pmit); + mtdcr(SDRAM0_CFGADDR,SDRAM0_PMIT); ul2=mfdcr(SDRAM0_CFGDATA); - mtdcr(SDRAM0_CFGADDR,mem_mcopt1); + mtdcr(SDRAM0_CFGADDR,SDRAM0_CFG); ul1=mfdcr(SDRAM0_CFGDATA); if (ul1 & 0x20000000) @@ -658,7 +658,7 @@ phys_size_t initdram (int board_type) else puts(" -Memory lines only at write cycles active outputs\n"); - mtdcr (SDRAM0_CFGADDR, mem_status); + mtdcr (SDRAM0_CFGADDR, SDRAM0_STATUS); ul1 = mfdcr (SDRAM0_CFGDATA); if (ul1 & 0x80000000) puts(" -SDRAM Controller ready\n"); @@ -670,19 +670,19 @@ phys_size_t initdram (int board_type) return (mems * 1024 * 1024); #else - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); ul1 = mfdcr (SDRAM0_CFGDATA); mems = printSDRAMConfig (0, ul1); - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); ul1 = mfdcr (SDRAM0_CFGDATA); mems += printSDRAMConfig (1, ul1); - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); ul1 = mfdcr(SDRAM0_CFGDATA); mems += printSDRAMConfig (2, ul1); - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); ul1 = mfdcr(SDRAM0_CFGDATA); mems += printSDRAMConfig (3, ul1); diff --git a/board/w7o/init.S b/board/w7o/init.S index 090b07a1e62..5477f986b98 100644 --- a/board/w7o/init.S +++ b/board/w7o/init.S @@ -182,7 +182,7 @@ sdram_init: * Disable memory controller to allow * values to be changed. */ - addi r3, 0, mem_mcopt1 + addi r3, 0, SDRAM0_CFG mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x0 ori r4, r4, 0x0 @@ -192,7 +192,7 @@ sdram_init: * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2 * All other banks are disabled. */ - addi r3, 0, mem_mb0cf + addi r3, 0, SDRAM0_B0CR mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */ ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */ @@ -222,7 +222,7 @@ sdram_init: /* * Set up SDTR1 */ - addi r3, 0, mem_sdtr1 + addi r3, 0, SDRAM0_TR mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */ ori r4, r4, 0x400D @@ -231,7 +231,7 @@ sdram_init: /* * Set RTR */ - addi r3, 0, mem_rtr + addi r3, 0, SDRAM0_RTR mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms@100Mhz */ mtdcr SDRAM0_CFGDATA, r4 @@ -250,7 +250,7 @@ sdram_init: /******************************************************************** * Set memory controller options reg, MCOPT1. *******************************************************************/ - addi r3, 0, mem_mcopt1 + addi r3, 0, SDRAM0_CFG mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */ ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */ diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c index 00a9f98b44c..a818808ba08 100644 --- a/board/w7o/w7o.c +++ b/board/w7o/w7o.c @@ -170,16 +170,16 @@ unsigned long get_dram_size (void) int size = 0; /* Get bank Size registers */ - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); /* get bank 0 config reg */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); /* get bank 0 config reg */ regs[0] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); /* get bank 1 config reg */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); /* get bank 1 config reg */ regs[1] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); /* get bank 2 config reg */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); /* get bank 2 config reg */ regs[2] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); /* get bank 3 config reg */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); /* get bank 3 config reg */ regs[3] = mfdcr (SDRAM0_CFGDATA); /* compute the size, add each bank if enabled */ diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c index 5e29ff3bcd7..d0ebd0fd603 100644 --- a/common/cmd_reginfo.c +++ b/common/cmd_reginfo.c @@ -108,24 +108,24 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) puts ("\nMemory (SDRAM) Configuration\n" "besra besrsa besrb besrsb bear mcopt1 rtr pmit\n"); - mtdcr(SDRAM0_CFGADDR,mem_besra); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,mem_besrsa); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,mem_besrb); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,mem_besrsb); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,mem_bear); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,mem_mcopt1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,mem_rtr); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,mem_pmit); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,SDRAM0_BESR0); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,SDRAM0_BESRS0); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,SDRAM0_BESR1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,SDRAM0_BESRS1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,SDRAM0_BEAR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,SDRAM0_CFG); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,SDRAM0_RTR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,SDRAM0_PMIT); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); puts ("\n" "mb0cf mb1cf mb2cf mb3cf sdtr1 ecccf eccerr\n"); - mtdcr(SDRAM0_CFGADDR,mem_mb0cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,mem_mb1cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,mem_mb2cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,mem_mb3cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,mem_sdtr1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,mem_ecccf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,mem_eccerr); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,SDRAM0_B0CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,SDRAM0_B1CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,SDRAM0_B2CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,SDRAM0_B3CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,SDRAM0_TR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,SDRAM0_ECCCFG); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,SDRAM0_ECCESR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); printf ("\n\n" "DMA Channels\n" @@ -195,12 +195,12 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) puts ("\nMemory (SDRAM) Configuration\n" "mcopt1 rtr pmit mb0cf mb1cf sdtr1\n"); - mtdcr(SDRAM0_CFGADDR,mem_mcopt1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,mem_rtr); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,mem_pmit); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,mem_mb0cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,mem_mb1cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,mem_sdtr1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,SDRAM0_CFG); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,SDRAM0_RTR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,SDRAM0_PMIT); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,SDRAM0_B0CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,SDRAM0_B1CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,SDRAM0_TR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); printf ("\n\n" "DMA Channels\n" diff --git a/cpu/ppc4xx/40x_spd_sdram.c b/cpu/ppc4xx/40x_spd_sdram.c index 83fa709da2d..c50f6730809 100644 --- a/cpu/ppc4xx/40x_spd_sdram.c +++ b/cpu/ppc4xx/40x_spd_sdram.c @@ -424,30 +424,30 @@ long int spd_sdram(int(read_spd)(uint addr)) #define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data) /* disable memcontroller so updates work */ - mtsdram0( mem_mcopt1, 0 ); + mtsdram0( SDRAM0_CFG, 0 ); #ifndef CONFIG_405EP /* not on PPC405EP */ - mtsdram0( mem_besra , sdram0_besr0 ); - mtsdram0( mem_besrb , sdram0_besr1 ); - mtsdram0( mem_ecccf , sdram0_ecccfg ); - mtsdram0( mem_eccerr, sdram0_eccesr ); + mtsdram0( SDRAM0_BESR0 , sdram0_besr0 ); + mtsdram0( SDRAM0_BESR1 , sdram0_besr1 ); + mtsdram0( SDRAM0_ECCCFG , sdram0_ecccfg ); + mtsdram0( SDRAM0_ECCESR, sdram0_eccesr ); #endif - mtsdram0( mem_rtr , sdram0_rtr ); - mtsdram0( mem_pmit , sdram0_pmit ); - mtsdram0( mem_mb0cf , sdram0_b0cr ); - mtsdram0( mem_mb1cf , sdram0_b1cr ); + mtsdram0( SDRAM0_RTR , sdram0_rtr ); + mtsdram0( SDRAM0_PMIT , sdram0_pmit ); + mtsdram0( SDRAM0_B0CR , sdram0_b0cr ); + mtsdram0( SDRAM0_B1CR , sdram0_b1cr ); #ifndef CONFIG_405EP /* not on PPC405EP */ - mtsdram0( mem_mb2cf , sdram0_b2cr ); - mtsdram0( mem_mb3cf , sdram0_b3cr ); + mtsdram0( SDRAM0_B2CR , sdram0_b2cr ); + mtsdram0( SDRAM0_B3CR , sdram0_b3cr ); #endif - mtsdram0( mem_sdtr1 , sdram0_tr ); + mtsdram0( SDRAM0_TR , sdram0_tr ); /* SDRAM have a power on delay, 500 micro should do */ udelay(500); sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR; if (ecc_on) sdram0_cfg |= SDRAM0_CFG_MEMCHK; - mtsdram0(mem_mcopt1, sdram0_cfg); + mtsdram0(SDRAM0_CFG, sdram0_cfg); return (total_size); } diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index c93f23a679f..6176eabfbfd 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -230,7 +230,7 @@ long int spd_sdram(void) { /* * program SDRAM Clock Timing Register (SDRAM0_CLKTR) */ - mtsdram(mem_clktr, 0x40000000); + mtsdram(SDRAM0_CLKTR, 0x40000000); /* * delay to ensure 200 usec has elapsed @@ -240,14 +240,14 @@ long int spd_sdram(void) { /* * enable the memory controller */ - mfsdram(mem_cfg0, cfg0); - mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN); + mfsdram(SDRAM0_CFG0, cfg0); + mtsdram(SDRAM0_CFG0, cfg0 | SDRAM_CFG0_DCEN); /* * wait for SDRAM_CFG0_DC_EN to complete */ while (1) { - mfsdram(mem_mcsts, mcsts); + mfsdram(SDRAM0_MCSTS, mcsts); if ((mcsts & SDRAM_MCSTS_MRSC) != 0) break; } @@ -386,7 +386,7 @@ static void program_cfg0(unsigned long *dimm_populated, /* * get Memory Controller Options 0 data */ - mfsdram(mem_cfg0, cfg0); + mfsdram(SDRAM0_CFG0, cfg0); /* * clear bits @@ -457,7 +457,7 @@ static void program_cfg0(unsigned long *dimm_populated, * Note: DCEN must be enabled after all DDR SDRAM controller * configuration registers get initialized. */ - mtsdram(mem_cfg0, cfg0); + mtsdram(SDRAM0_CFG0, cfg0); } static void program_cfg1(unsigned long *dimm_populated, @@ -465,7 +465,7 @@ static void program_cfg1(unsigned long *dimm_populated, unsigned long num_dimm_banks) { unsigned long cfg1; - mfsdram(mem_cfg1, cfg1); + mfsdram(SDRAM0_CFG1, cfg1); /* * Self-refresh exit, disable PM @@ -475,7 +475,7 @@ static void program_cfg1(unsigned long *dimm_populated, /* * program Memory Controller Options 1 */ - mtsdram(mem_cfg1, cfg1); + mtsdram(SDRAM0_CFG1, cfg1); } static void program_rtr(unsigned long *dimm_populated, @@ -535,7 +535,7 @@ static void program_rtr(unsigned long *dimm_populated, /* * program Refresh Timer Register (SDRAM0_RTR) */ - mtsdram(mem_rtr, sdram_rtr); + mtsdram(SDRAM0_RTR, sdram_rtr); } static void program_tr0(unsigned long *dimm_populated, @@ -576,7 +576,7 @@ static void program_tr0(unsigned long *dimm_populated, /* * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits */ - mfsdram(mem_tr0, tr0); + mfsdram(SDRAM0_TR0, tr0); tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK | SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK | SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK | @@ -821,7 +821,7 @@ static void program_tr0(unsigned long *dimm_populated, } debug("tr0: %x\n", tr0); - mtsdram(mem_tr0, tr0); + mtsdram(SDRAM0_TR0, tr0); } static int short_mem_test(void) @@ -848,7 +848,7 @@ static int short_mem_test(void) 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}}; for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) { - mtdcr(SDRAM0_CFGADDR, mem_b0cr + (bxcr_num << 2)); + mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bxcr_num << 2)); if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) { /* Bank is enabled */ membase = (unsigned long*) @@ -918,11 +918,11 @@ static void program_tr1(void) /* * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits */ - mfsdram(mem_tr1, tr1); + mfsdram(SDRAM0_TR1, tr1); tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK | SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK); - mfsdram(mem_tr0, tr0); + mfsdram(SDRAM0_TR0, tr0); if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) && (sys_info.freqPLB > 100000000)) { tr1 |= SDRAM_TR1_RDSS_TR2; @@ -937,14 +937,14 @@ static void program_tr1(void) /* * save CFG0 ECC setting to a temporary variable and turn ECC off */ - mfsdram(mem_cfg0, cfg0); + mfsdram(SDRAM0_CFG0, cfg0); ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK; - mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON); + mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON); /* * get the delay line calibration register value */ - mfsdram(mem_dlycal, dlycal); + mfsdram(SDRAM0_DLYCAL, dlycal); dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2; max_pass_length = 0; @@ -964,7 +964,7 @@ static void program_tr1(void) /* * Set the timing reg for the test. */ - mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt))); + mtsdram(SDRAM0_TR1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt))); if (short_mem_test()) { if (fail_found == TRUE) { @@ -1018,7 +1018,7 @@ static void program_tr1(void) /* * restore the orignal ECC setting */ - mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp); + mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp); /* * set the SDRAM TR1 RDCD value @@ -1056,7 +1056,7 @@ static void program_tr1(void) /* * program SDRAM Timing Register 1 TR1 */ - mtsdram(mem_tr1, tr1); + mtsdram(SDRAM0_TR1, tr1); } static unsigned long program_bxcr(unsigned long *dimm_populated, @@ -1086,7 +1086,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated, * Set the BxCR regs. First, wipe out the bank config registers. */ for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) { - mtdcr(SDRAM0_CFGADDR, mem_b0cr + (bx_cr_num << 2)); + mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bx_cr_num << 2)); mtdcr(SDRAM0_CFGDATA, 0x00000000); bank_parms[bx_cr_num].bank_size_bytes = 0; } @@ -1232,7 +1232,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated, /* Set the SDRAM0_BxCR regs thanks to sort tables */ for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) { if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) { - mtdcr(SDRAM0_CFGADDR, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2)); + mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (sorted_bank_num[bx_cr_num] << 2)); temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK | SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE); temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) | diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index 5a3336e3c8a..30c6e0e38e7 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -188,14 +188,14 @@ phys_size_t initdram(int board_type) /* * Disable memory controller. */ - mtsdram(mem_mcopt1, 0x00000000); + mtsdram(SDRAM0_CFG, 0x00000000); /* * Set MB0CF for bank 0. */ - mtsdram(mem_mb0cf, mb0cf[i].reg); - mtsdram(mem_sdtr1, sdtr1); - mtsdram(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64)); + mtsdram(SDRAM0_B0CR, mb0cf[i].reg); + mtsdram(SDRAM0_TR, sdtr1); + mtsdram(SDRAM0_RTR, compute_rtr(speed, mb0cf[i].rows, 64)); udelay(200); @@ -204,7 +204,7 @@ phys_size_t initdram(int board_type) * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst * read/prefetch. */ - mtsdram(mem_mcopt1, 0x80800000); + mtsdram(SDRAM0_CFG, 0x80800000); udelay(10000); @@ -216,9 +216,9 @@ phys_size_t initdram(int board_type) * defined (assumes same type as bank 0) */ #ifdef CONFIG_SDRAM_BANK1 - mtsdram(mem_mcopt1, 0x00000000); - mtsdram(mem_mb1cf, mb0cf[i].size | mb0cf[i].reg); - mtsdram(mem_mcopt1, 0x80800000); + mtsdram(SDRAM0_CFG, 0x00000000); + mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg); + mtsdram(SDRAM0_CFG, 0x80800000); udelay(10000); /* @@ -228,8 +228,8 @@ phys_size_t initdram(int board_type) */ if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) != mb0cf[i].size) { - mtsdram(mem_mb1cf, 0); - mtsdram(mem_mcopt1, 0); + mtsdram(SDRAM0_B1CR, 0); + mtsdram(SDRAM0_CFG, 0); } else { /* * We have two identical banks, so the size @@ -315,7 +315,7 @@ static void sdram_tr1_set(int ram_address, int* tr1_value) /* go through all possible SDRAM0_TR1[RDCT] values */ for (i=0; i<=0x1ff; i++) { /* set the current value for TR1 */ - mtsdram(mem_tr1, (0x80800800 | i)); + mtsdram(SDRAM0_TR1, (0x80800800 | i)); /* write values */ for (j=0; j Date: Thu, 24 Sep 2009 14:10:30 +0200 Subject: [PATCH 197/208] ppc4xx: Remove mtsdram0() marcos and use common mtsdram() instead Additionally some whitespace coding style fixes. Signed-off-by: Stefan Roese --- board/g2000/g2000.c | 15 +++++++-------- cpu/ppc4xx/40x_spd_sdram.c | 27 +++++++++++++-------------- 2 files changed, 20 insertions(+), 22 deletions(-) diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c index 092a3d8a19a..03cd6b8847d 100644 --- a/board/g2000/g2000.c +++ b/board/g2000/g2000.c @@ -114,18 +114,17 @@ int checkboard (void) long int init_sdram_static_settings(void) { -#define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data) /* disable memcontroller so updates work */ - mtsdram0( SDRAM0_CFG, MEM_MCOPT1_INIT_VAL ); - mtsdram0( SDRAM0_RTR , MEM_RTR_INIT_VAL ); - mtsdram0( SDRAM0_PMIT , MEM_PMIT_INIT_VAL ); - mtsdram0( SDRAM0_B0CR , MEM_MB0CF_INIT_VAL ); - mtsdram0( SDRAM0_B1CR , MEM_MB1CF_INIT_VAL ); - mtsdram0( SDRAM0_TR , MEM_SDTR1_INIT_VAL ); + mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL); + mtsdram(SDRAM0_RTR, MEM_RTR_INIT_VAL); + mtsdram(SDRAM0_PMIT, MEM_PMIT_INIT_VAL); + mtsdram(SDRAM0_B0CR, MEM_MB0CF_INIT_VAL); + mtsdram(SDRAM0_B1CR, MEM_MB1CF_INIT_VAL); + mtsdram(SDRAM0_TR, MEM_SDTR1_INIT_VAL); /* SDRAM have a power on delay, 500 micro should do */ udelay(500); - mtsdram0( SDRAM0_CFG, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE ); + mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE); return (CONFIG_SYS_SDRAM_SIZE); /* CONFIG_SYS_SDRAM_SIZE is in G2000.h */ } diff --git a/cpu/ppc4xx/40x_spd_sdram.c b/cpu/ppc4xx/40x_spd_sdram.c index c50f6730809..5e6dbe3331d 100644 --- a/cpu/ppc4xx/40x_spd_sdram.c +++ b/cpu/ppc4xx/40x_spd_sdram.c @@ -422,32 +422,31 @@ long int spd_sdram(int(read_spd)(uint addr)) * program all the registers. * -------------------------------------------------------------------*/ -#define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data) /* disable memcontroller so updates work */ - mtsdram0( SDRAM0_CFG, 0 ); + mtsdram(SDRAM0_CFG, 0); #ifndef CONFIG_405EP /* not on PPC405EP */ - mtsdram0( SDRAM0_BESR0 , sdram0_besr0 ); - mtsdram0( SDRAM0_BESR1 , sdram0_besr1 ); - mtsdram0( SDRAM0_ECCCFG , sdram0_ecccfg ); - mtsdram0( SDRAM0_ECCESR, sdram0_eccesr ); + mtsdram(SDRAM0_BESR0, sdram0_besr0); + mtsdram(SDRAM0_BESR1, sdram0_besr1); + mtsdram(SDRAM0_ECCCFG, sdram0_ecccfg); + mtsdram(SDRAM0_ECCESR, sdram0_eccesr); #endif - mtsdram0( SDRAM0_RTR , sdram0_rtr ); - mtsdram0( SDRAM0_PMIT , sdram0_pmit ); - mtsdram0( SDRAM0_B0CR , sdram0_b0cr ); - mtsdram0( SDRAM0_B1CR , sdram0_b1cr ); + mtsdram(SDRAM0_RTR, sdram0_rtr); + mtsdram(SDRAM0_PMIT, sdram0_pmit); + mtsdram(SDRAM0_B0CR, sdram0_b0cr); + mtsdram(SDRAM0_B1CR, sdram0_b1cr); #ifndef CONFIG_405EP /* not on PPC405EP */ - mtsdram0( SDRAM0_B2CR , sdram0_b2cr ); - mtsdram0( SDRAM0_B3CR , sdram0_b3cr ); + mtsdram(SDRAM0_B2CR, sdram0_b2cr); + mtsdram(SDRAM0_B3CR, sdram0_b3cr); #endif - mtsdram0( SDRAM0_TR , sdram0_tr ); + mtsdram(SDRAM0_TR, sdram0_tr); /* SDRAM have a power on delay, 500 micro should do */ udelay(500); sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR; if (ecc_on) sdram0_cfg |= SDRAM0_CFG_MEMCHK; - mtsdram0(SDRAM0_CFG, sdram0_cfg); + mtsdram(SDRAM0_CFG, sdram0_cfg); return (total_size); } From ef37c6835eac66206a9c7c11f0c7186f5d64bf91 Mon Sep 17 00:00:00 2001 From: Simon Kagstrom Date: Fri, 25 Sep 2009 14:05:57 +0200 Subject: [PATCH 198/208] ubifs: Correct dereferencing of files-after-symlinks Files in directories which are symlinked to were not dereferenced correctly in last commit. E.g., with a symlink /boot/lnk -> /boot/real_dir loading /boot/lnk/uImage will fail. This patch fixes that by simply seeing to it that the target base directory has a slash after it. Signed-off-by: Simon Kagstrom Signed-off-by: Stefan Roese --- fs/ubifs/ubifs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c index b03ed0bb8e9..286739c3687 100644 --- a/fs/ubifs/ubifs.c +++ b/fs/ubifs/ubifs.c @@ -439,7 +439,7 @@ static unsigned long ubifs_findfile(struct super_block *sb, char *filename) continue; } /* Relative to cur dir */ - sprintf(buf, "%s%s", + sprintf(buf, "%s/%s", link_name, next == NULL ? "" : next); memcpy(symlinkpath, buf, sizeof(buf)); next = name = symlinkpath; From a05e3f9a084fc8951d87745b3a91df246432df7d Mon Sep 17 00:00:00 2001 From: Shinya Kuribayashi Date: Sat, 12 Sep 2009 18:01:40 +0900 Subject: [PATCH 199/208] MIPS: VCT: Remove read_spareram reference The commit ecad289fc6bd9d89ef4d5093cc7b6fd712fd0d29 (OneNAND: Remove unused read_spareram and add unlock_all as kernel does) forgot to remove a local reference to read_spareram in board/micronas/vct/ebi_onenand.c, which causes the following build failure when configured with OneNAND: ebi_onenand.c: In function 'onenand_board_init': ebi_onenand.c:196: error: 'struct onenand_chip' has no member named 'read_spareram' make[1]: *** [ebi_onenand.o] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [board/micronas/vct/libvct.a] Error 2 Signed-off-by: Shinya Kuribayashi Acked-by: Stefan Roese Cc: Kyungmin Park Signed-off-by: Scott Wood --- board/micronas/vct/ebi_onenand.c | 1 - 1 file changed, 1 deletion(-) diff --git a/board/micronas/vct/ebi_onenand.c b/board/micronas/vct/ebi_onenand.c index 522b88f8ea1..1e8afa6f57d 100644 --- a/board/micronas/vct/ebi_onenand.c +++ b/board/micronas/vct/ebi_onenand.c @@ -193,6 +193,5 @@ void onenand_board_init(struct mtd_info *mtd) chip->write_word = ebi_nand_write_word; chip->read_bufferram = ebi_read_bufferram; - chip->read_spareram = ebi_read_bufferram; chip->write_bufferram = ebi_write_bufferram; } From ca6189db484882798f2a35a476c07e618e21f6d3 Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Tue, 22 Sep 2009 09:05:00 +0900 Subject: [PATCH 200/208] Refactor OneNAND IPL code Refactoring the OneNAND IPL code and some minor fixed: - Remove unnecessary header file - Fix wrong access at read interrupt - The recent OneNAND has 4KiB pagesize Also Board can override OneNAND IPL image Signed-off-by: Kyungmin Park --- Makefile | 9 ++++---- onenand_ipl/onenand_boot.c | 1 - onenand_ipl/onenand_ipl.h | 5 +++-- onenand_ipl/onenand_read.c | 46 ++++++++++++++++++++++++++++---------- 4 files changed, 41 insertions(+), 20 deletions(-) diff --git a/Makefile b/Makefile index 9c5b2a5c9a3..30a35f3fc9a 100644 --- a/Makefile +++ b/Makefile @@ -285,6 +285,7 @@ endif ifeq ($(CONFIG_ONENAND_U_BOOT),y) ONENAND_IPL = onenand_ipl U_BOOT_ONENAND = $(obj)u-boot-onenand.bin +ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin endif __OBJS := $(subst $(obj),,$(OBJS)) @@ -378,8 +379,7 @@ $(ONENAND_IPL): $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk $(MAKE) -C onenand_ipl/board/$(BOARDDIR) all $(U_BOOT_ONENAND): $(ONENAND_IPL) $(obj)u-boot.bin - cat $(obj)onenand_ipl/onenand-ipl-2k.bin $(obj)u-boot.bin > $(obj)u-boot-onenand.bin - cat $(obj)onenand_ipl/onenand-ipl-4k.bin $(obj)u-boot.bin > $(obj)u-boot-flexonenand.bin + cat $(ONENAND_BIN) $(obj)u-boot.bin > $(obj)u-boot-onenand.bin $(VERSION_FILE): @( printf '#define U_BOOT_VERSION "U-Boot %s%s"\n' "$(U_BOOT_VERSION)" \ @@ -3223,8 +3223,6 @@ zylonite_config : ######################################################################### apollon_config : unconfig - @mkdir -p $(obj)include - @mkdir -p $(obj)onenand_ipl/board/apollon @echo "#define CONFIG_ONENAND_U_BOOT" > $(obj)include/config.h @$(MKCONFIG) $(@:_config=) arm arm1136 apollon NULL omap24xx @echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk @@ -3706,7 +3704,8 @@ clean: $(obj)cpu/blackfin/bootrom-asm-offsets.[chs] @rm -f $(obj)include/bmp_logo.h @rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map} - @rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl-2k.bin,ipl-4k.bin,ipl.map} + @rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map} + @rm -f $(ONENAND_BIN) @rm -f $(obj)onenand_ipl/u-boot.lds @rm -f $(TIMESTAMP_FILE) $(VERSION_FILE) @find $(OBJTREE) -type f \ diff --git a/onenand_ipl/onenand_boot.c b/onenand_ipl/onenand_boot.c index 63995ce504e..22baebb314c 100644 --- a/onenand_ipl/onenand_boot.c +++ b/onenand_ipl/onenand_boot.c @@ -24,7 +24,6 @@ */ #include -#include #include "onenand_ipl.h" diff --git a/onenand_ipl/onenand_ipl.h b/onenand_ipl/onenand_ipl.h index 412572a08dc..7ebb3e32ddb 100644 --- a/onenand_ipl/onenand_ipl.h +++ b/onenand_ipl/onenand_ipl.h @@ -28,8 +28,9 @@ #define THIS_ONENAND(a) (CONFIG_SYS_ONENAND_BASE + (a)) -#define READ_INTERRUPT() \ - onenand_readw(THIS_ONENAND(ONENAND_REG_INTERRUPT)) +#define READ_INTERRUPT() onenand_readw(ONENAND_REG_INTERRUPT) +extern int (*onenand_read_page)(ulong block, ulong page, + u_char *buf, int pagesize); extern int onenand_read_block(unsigned char *buf); #endif diff --git a/onenand_ipl/onenand_read.c b/onenand_ipl/onenand_read.c index d1a842dd67d..8d0df81af63 100644 --- a/onenand_ipl/onenand_read.c +++ b/onenand_ipl/onenand_read.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2005-2008 Samsung Electronis + * (C) Copyright 2005-2009 Samsung Electronics * Kyungmin Park * * See file CREDITS for list of people who contributed to this @@ -37,8 +37,10 @@ extern void *memcpy32(void *dest, void *src, int size); #endif +int (*onenand_read_page)(ulong block, ulong page, u_char *buf, int pagesize); + /* read a page with ECC */ -static inline int onenand_read_page(ulong block, ulong page, +static int generic_onenand_read_page(ulong block, ulong page, u_char * buf, int pagesize) { unsigned long *base; @@ -89,9 +91,25 @@ static inline int onenand_read_page(ulong block, ulong page, return 0; } -#define ONENAND_START_PAGE 1 +#ifndef CONFIG_ONENAND_START_PAGE +#define CONFIG_ONENAND_START_PAGE 1 +#endif #define ONENAND_PAGES_PER_BLOCK 64 +static void onenand_generic_init(int *page_is_4KiB, int *page) +{ + int dev_id, density; + + if (onenand_readw(ONENAND_REG_TECHNOLOGY)) + *page_is_4KiB = 1; + dev_id = onenand_readw(ONENAND_REG_DEVICE_ID); + density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT; + density &= ONENAND_DEVICE_DENSITY_MASK; + if (density >= ONENAND_DEVICE_DENSITY_4Gb && + !(dev_id & ONENAND_DEVICE_IS_DDP)) + *page_is_4KiB = 1; +} + /** * onenand_read_block - Read CONFIG_SYS_MONITOR_LEN from begining * of OneNAND, skipping bad blocks @@ -99,24 +117,28 @@ static inline int onenand_read_page(ulong block, ulong page, */ int onenand_read_block(unsigned char *buf) { - int block; - int page = ONENAND_START_PAGE, offset = 0; - int pagesize = 0, erase_shift = 0; - int erasesize = 0, nblocks = 0; + int block, nblocks; + int page = CONFIG_ONENAND_START_PAGE, offset = 0; + int pagesize, erasesize, erase_shift; + int page_is_4KiB = 0; - if (onenand_readw(ONENAND_REG_TECHNOLOGY)) { - pagesize = 4096; /* MLC OneNAND has 4KiB pagesize */ + onenand_read_page = generic_onenand_read_page; + + onenand_generic_init(&page_is_4KiB, &page); + + if (page_is_4KiB) { + pagesize = 4096; /* OneNAND has 4KiB pagesize */ erase_shift = 18; } else { - pagesize = 2048; + pagesize = 2048; /* OneNAND has 2KiB pagesize */ erase_shift = 17; } - erasesize = ONENAND_PAGES_PER_BLOCK * pagesize; + erasesize = (1 << erase_shift); nblocks = (CONFIG_SYS_MONITOR_LEN + erasesize - 1) >> erase_shift; /* NOTE: you must read page from page 1 of block 0 */ - /* read the block page by page*/ + /* read the block page by page */ for (block = 0; block < nblocks; block++) { for (; page < ONENAND_PAGES_PER_BLOCK; page++) { if (onenand_read_page(block, page, buf + offset, From d44e9c1736283f0abc5d3c5d28cfea8480c93a79 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Mon, 28 Sep 2009 16:33:18 -0500 Subject: [PATCH 201/208] NAND: davinci: Fix warnings when 4-bit ECC not used I accidentally left v2 of "NAND: DaVinci:Adding 4 BIT ECC support" applied when I pushed the tree last merge window, and missed these fixes which were in v3 of that patch. Signed-off-by: Sandeep Paulraj Signed-off-by: Scott Wood --- drivers/mtd/nand/davinci_nand.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index 37d8b7312cf..eabaf3e773f 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -202,7 +202,6 @@ static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = { }, #endif }; -#endif static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode) { @@ -289,7 +288,6 @@ static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd, static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc) { - struct nand_chip *this = mtd->priv; unsigned short ecc_10bit[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; int i; unsigned int hw_4ecc[4] = { 0, 0, 0, 0 }, iserror = 0; @@ -441,6 +439,7 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat, return numerrors; } +#endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */ static int nand_davinci_dev_ready(struct mtd_info *mtd) { From 8280912e0657e96a7b7d8da7003656d62b0fd109 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 28 Sep 2009 21:38:00 -0500 Subject: [PATCH 202/208] ppc/85xx: Clean up immap_85xx.h * Converted all white space to tabs * Converted all types to u8/u16/u32 * Reduce lines to fit in 80 columns * Renamed MPC85xx_{Q,B}MAN -> FSL_CORENET_{Q,B}MAN Signed-off-by: Kumar Gala --- include/asm-ppc/immap_85xx.h | 3175 +++++++++++++++++----------------- 1 file changed, 1586 insertions(+), 1589 deletions(-) diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 100dfe10692..41942954b80 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -17,197 +17,191 @@ #include typedef struct ccsr_local { - u32 ccsrbarh; /* 0x0 - Control Configuration Status Registers Base Address Register High */ - u32 ccsrbarl; /* 0x4 - Control Configuration Status Registers Base Address Register Low */ - u32 ccsrar; /* 0x8 - Configuration, Control, and Status Attribute Register */ + u32 ccsrbarh; /* CCSR Base Addr High */ + u32 ccsrbarl; /* CCSR Base Addr Low */ + u32 ccsrar; /* CCSR Attr */ #define CCSRAR_C 0x80000000 /* Commit */ u8 res1[4]; - u32 altcbarh; /* 0x10 - Alternate Configuration Base Address Register High */ - u32 altcbarl; /* 0x14 - Alternate Configuration Base Address Register Low */ - u32 altcar; /* 0x18 - Alternate Configuration Attribute Register */ + u32 altcbarh; /* Alternate Configuration Base Addr High */ + u32 altcbarl; /* Alternate Configuration Base Addr Low */ + u32 altcar; /* Alternate Configuration Attr */ u8 res2[4]; - u32 bstrh; /* 0x20 - Boot space translation register high */ - u32 bstrl; /* 0x24 - Boot space translation register Low */ - u32 bstrar; /* 0x28 - Boot space translation attributes register */ + u32 bstrh; /* Boot space translation high */ + u32 bstrl; /* Boot space translation Low */ + u32 bstrar; /* Boot space translation attributes */ u8 res3[0xbd4]; struct { - u32 lawbarh; /* 0xc00 + n * 0x10 - LAW0 base address register high */ - u32 lawbarl; /* 0xc04 + n * 0x10 - LAW0 base address register low */ - u32 lawar; /* 0xc08 + n * 0x10 - LAW0 attributes register */ + u32 lawbarh; /* LAWn base addr high */ + u32 lawbarl; /* LAWn base addr low */ + u32 lawar; /* LAWn attributes */ u8 res4[4]; } law[32]; u8 res35[0x204]; } ccsr_local_t; -/* - * Local-Access Registers and ECM Registers(0x0000-0x2000) - */ +/* Local-Access Registers & ECM Registers */ typedef struct ccsr_local_ecm { - uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */ - char res1[4]; - uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */ - char res2[4]; - uint altcar; /* 0x10 - Alternate Configuration Attribute Register */ - char res3[12]; - uint bptr; /* 0x20 - Boot Page Translation Register */ - char res4[3044]; - uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */ - char res5[4]; - uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */ - char res6[20]; - uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */ - char res7[4]; - uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */ - char res8[20]; - uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */ - char res9[4]; - uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */ - char res10[20]; - uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */ - char res11[4]; - uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */ - char res12[20]; - uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */ - char res13[4]; - uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */ - char res14[20]; - uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */ - char res15[4]; - uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */ - char res16[20]; - uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */ - char res17[4]; - uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */ - char res18[20]; - uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */ - char res19[4]; - uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */ - char res19_8a[20]; - uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */ - char res19_8b[4]; - uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */ - char res19_9a[20]; - uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */ - char res19_9b[4]; - uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */ - char res19_10a[20]; - uint lawbar10; /* 0xd48 - Local Access Window 10 Base Address Register */ - char res19_10b[4]; - uint lawar10; /* 0xd50 - Local Access Window 10 Attributes Register */ - char res19_11a[20]; - uint lawbar11; /* 0xd68 - Local Access Window 11 Base Address Register */ - char res19_11b[4]; - uint lawar11; /* 0xd70 - Local Access Window 11 Attributes Register */ - char res20[652]; - uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */ - char res21[12]; - uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */ - char res22[3564]; - uint eedr; /* 0x1e00 - ECM Error Detect Register */ - char res23[4]; - uint eeer; /* 0x1e08 - ECM Error Enable Register */ - uint eeatr; /* 0x1e0c - ECM Error Attributes Capture Register */ - uint eeadr; /* 0x1e10 - ECM Error Address Capture Register */ - char res24[492]; + u32 ccsrbar; /* CCSR Base Addr */ + u8 res1[4]; + u32 altcbar; /* Alternate Configuration Base Addr */ + u8 res2[4]; + u32 altcar; /* Alternate Configuration Attr */ + u8 res3[12]; + u32 bptr; /* Boot Page Translation */ + u8 res4[3044]; + u32 lawbar0; /* Local Access Window 0 Base Addr */ + u8 res5[4]; + u32 lawar0; /* Local Access Window 0 Attrs */ + u8 res6[20]; + u32 lawbar1; /* Local Access Window 1 Base Addr */ + u8 res7[4]; + u32 lawar1; /* Local Access Window 1 Attrs */ + u8 res8[20]; + u32 lawbar2; /* Local Access Window 2 Base Addr */ + u8 res9[4]; + u32 lawar2; /* Local Access Window 2 Attrs */ + u8 res10[20]; + u32 lawbar3; /* Local Access Window 3 Base Addr */ + u8 res11[4]; + u32 lawar3; /* Local Access Window 3 Attrs */ + u8 res12[20]; + u32 lawbar4; /* Local Access Window 4 Base Addr */ + u8 res13[4]; + u32 lawar4; /* Local Access Window 4 Attrs */ + u8 res14[20]; + u32 lawbar5; /* Local Access Window 5 Base Addr */ + u8 res15[4]; + u32 lawar5; /* Local Access Window 5 Attrs */ + u8 res16[20]; + u32 lawbar6; /* Local Access Window 6 Base Addr */ + u8 res17[4]; + u32 lawar6; /* Local Access Window 6 Attrs */ + u8 res18[20]; + u32 lawbar7; /* Local Access Window 7 Base Addr */ + u8 res19[4]; + u32 lawar7; /* Local Access Window 7 Attrs */ + u8 res19_8a[20]; + u32 lawbar8; /* Local Access Window 8 Base Addr */ + u8 res19_8b[4]; + u32 lawar8; /* Local Access Window 8 Attrs */ + u8 res19_9a[20]; + u32 lawbar9; /* Local Access Window 9 Base Addr */ + u8 res19_9b[4]; + u32 lawar9; /* Local Access Window 9 Attrs */ + u8 res19_10a[20]; + u32 lawbar10; /* Local Access Window 10 Base Addr */ + u8 res19_10b[4]; + u32 lawar10; /* Local Access Window 10 Attrs */ + u8 res19_11a[20]; + u32 lawbar11; /* Local Access Window 11 Base Addr */ + u8 res19_11b[4]; + u32 lawar11; /* Local Access Window 11 Attrs */ + u8 res20[652]; + u32 eebacr; /* ECM CCB Addr Configuration */ + u8 res21[12]; + u32 eebpcr; /* ECM CCB Port Configuration */ + u8 res22[3564]; + u32 eedr; /* ECM Error Detect */ + u8 res23[4]; + u32 eeer; /* ECM Error Enable */ + u32 eeatr; /* ECM Error Attrs Capture */ + u32 eeadr; /* ECM Error Addr Capture */ + u8 res24[492]; } ccsr_local_ecm_t; -/* - * DDR memory controller registers(0x2000-0x3000) - */ +/* DDR memory controller registers */ typedef struct ccsr_ddr { - uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */ - char res1[4]; - uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */ - char res2[4]; - uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */ - char res3[4]; - uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */ - char res4[100]; - uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */ - uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */ - uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */ - uint cs3_config; /* 0x208c - DDR Chip Select Configuration */ - char res4a[48]; - uint cs0_config_2; /* 0x20c0 - DDR Chip Select Configuration 2 */ - uint cs1_config_2; /* 0x20c4 - DDR Chip Select Configuration 2 */ - uint cs2_config_2; /* 0x20c8 - DDR Chip Select Configuration 2 */ - uint cs3_config_2; /* 0x20cc - DDR Chip Select Configuration 2 */ - char res5[48]; - uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */ - uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ - uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ - uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ - uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration */ - uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */ - uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration */ - uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2*/ - uint sdram_md_cntl; /* 0x2120 - DDR SDRAM Mode Control */ - uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */ - uint sdram_data_init; /* 0x2128 - DDR SDRAM Data initialization */ - char res6[4]; - uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ - char res7[20]; - uint init_addr; /* 0x2148 - DDR training initialization address */ - uint init_ext_addr; /* 0x214C - DDR training initialization extended address */ - char res8_1[16]; - uint timing_cfg_4; /* 0x2160 - DDR SDRAM Timing Configuration Register 4 */ - uint timing_cfg_5; /* 0x2164 - DDR SDRAM Timing Configuration Register 5 */ - char reg8_1a[8]; - uint ddr_zq_cntl; /* 0x2170 - DDR ZQ calibration control*/ - uint ddr_wrlvl_cntl; /* 0x2174 - DDR write leveling control*/ - char reg8_1aa[4]; - uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */ - uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */ - uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */ - char res8_1b[2456]; - uint ddr_dsr1; /* 0x2B20 - DDR Debug Status Register 1 */ - uint ddr_dsr2; /* 0x2B24 - DDR Debug Status Register 2 */ - uint ddr_cdr1; /* 0x2B28 - DDR Control Driver Register 1 */ - uint ddr_cdr2; /* 0x2B2C - DDR Control Driver Register 2 */ - char res8_1c[200]; - uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ - uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ - char res8_2[512]; - uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */ - uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */ - uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */ - char res9[20]; - uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */ - uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */ - uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */ - char res10[20]; - uint err_detect; /* 0x2e40 - DDR Memory Error Detect */ - uint err_disable; /* 0x2e44 - DDR Memory Error Disable */ - uint err_int_en; /* 0x2e48 - DDR */ - uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */ - uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */ - uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */ - uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */ - char res11[164]; - uint debug_1; /* 0x2f00 */ - uint debug_2; - uint debug_3; - uint debug_4; - uint debug_5; - uint debug_6; - uint debug_7; - uint debug_8; - uint debug_9; - uint debug_10; - uint debug_11; - uint debug_12; - uint debug_13; /* +0xF30 */ - uint debug_14; - uint debug_15; - uint debug_16; - uint debug_17; - uint debug_18; /* +0xF44 */ - char res12[184]; + u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ + u8 res1[4]; + u32 cs1_bnds; /* Chip Select 1 Memory Bounds */ + u8 res2[4]; + u32 cs2_bnds; /* Chip Select 2 Memory Bounds */ + u8 res3[4]; + u32 cs3_bnds; /* Chip Select 3 Memory Bounds */ + u8 res4[100]; + u32 cs0_config; /* Chip Select Configuration */ + u32 cs1_config; /* Chip Select Configuration */ + u32 cs2_config; /* Chip Select Configuration */ + u32 cs3_config; /* Chip Select Configuration */ + u8 res4a[48]; + u32 cs0_config_2; /* Chip Select Configuration 2 */ + u32 cs1_config_2; /* Chip Select Configuration 2 */ + u32 cs2_config_2; /* Chip Select Configuration 2 */ + u32 cs3_config_2; /* Chip Select Configuration 2 */ + u8 res5[48]; + u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ + u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ + u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ + u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ + u32 sdram_cfg; /* SDRAM Control Configuration */ + u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ + u32 sdram_mode; /* SDRAM Mode Configuration */ + u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */ + u32 sdram_md_cntl; /* SDRAM Mode Control */ + u32 sdram_interval; /* SDRAM Interval Configuration */ + u32 sdram_data_init; /* SDRAM Data initialization */ + u8 res6[4]; + u32 sdram_clk_cntl; /* SDRAM Clock Control */ + u8 res7[20]; + u32 init_addr; /* training init addr */ + u32 init_ext_addr; /* training init extended addr */ + u8 res8_1[16]; + u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ + u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ + u8 reg8_1a[8]; + u32 ddr_zq_cntl; /* ZQ calibration control*/ + u32 ddr_wrlvl_cntl; /* write leveling control*/ + u8 reg8_1aa[4]; + u32 ddr_sr_cntr; /* self refresh counter */ + u32 ddr_sdram_rcw_1; /* Control Words 1 */ + u32 ddr_sdram_rcw_2; /* Control Words 2 */ + u8 res8_1b[2456]; + u32 ddr_dsr1; /* Debug Status 1 */ + u32 ddr_dsr2; /* Debug Status 2 */ + u32 ddr_cdr1; /* Control Driver 1 */ + u32 ddr_cdr2; /* Control Driver 2 */ + u8 res8_1c[200]; + u32 ip_rev1; /* IP Block Revision 1 */ + u32 ip_rev2; /* IP Block Revision 2 */ + u8 res8_2[512]; + u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ + u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ + u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ + u8 res9[20]; + u32 capture_data_hi; /* Data Path Read Capture High */ + u32 capture_data_lo; /* Data Path Read Capture Low */ + u32 capture_ecc; /* Data Path Read Capture ECC */ + u8 res10[20]; + u32 err_detect; /* Error Detect */ + u32 err_disable; /* Error Disable */ + u32 err_int_en; + u32 capture_attributes; /* Error Attrs Capture */ + u32 capture_address; /* Error Addr Capture */ + u32 capture_ext_address; /* Error Extended Addr Capture */ + u32 err_sbe; /* Single-Bit ECC Error Management */ + u8 res11[164]; + u32 debug_1; + u32 debug_2; + u32 debug_3; + u32 debug_4; + u32 debug_5; + u32 debug_6; + u32 debug_7; + u32 debug_8; + u32 debug_9; + u32 debug_10; + u32 debug_11; + u32 debug_12; + u32 debug_13; + u32 debug_14; + u32 debug_15; + u32 debug_16; + u32 debug_17; + u32 debug_18; + u8 res12[184]; } ccsr_ddr_t; -/* - * I2C Registers(0x3000-0x4000) - */ +/* I2C Registers */ typedef struct ccsr_i2c { struct fsl_i2c i2c[1]; u8 res[4096 - 1 * sizeof(struct fsl_i2c)]; @@ -217,176 +211,167 @@ typedef struct ccsr_i2c { || defined(CONFIG_MPC8541) \ || defined(CONFIG_MPC8548) \ || defined(CONFIG_MPC8555) -/* DUART Registers(0x4000-0x5000) */ +/* DUART Registers */ typedef struct ccsr_duart { - char res1[1280]; - u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */ - u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */ - u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */ - u_char ulcr1; /* 0x4503 - UART1 Line Control Register */ - u_char umcr1; /* 0x4504 - UART1 Modem Control Register */ - u_char ulsr1; /* 0x4505 - UART1 Line Status Register */ - u_char umsr1; /* 0x4506 - UART1 Modem Status Register */ - u_char uscr1; /* 0x4507 - UART1 Scratch Register */ - char res2[8]; - u_char udsr1; /* 0x4510 - UART1 DMA Status Register */ - char res3[239]; - u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */ - u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */ - u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */ - u_char ulcr2; /* 0x4603 - UART2 Line Control Register */ - u_char umcr2; /* 0x4604 - UART2 Modem Control Register */ - u_char ulsr2; /* 0x4605 - UART2 Line Status Register */ - u_char umsr2; /* 0x4606 - UART2 Modem Status Register */ - u_char uscr2; /* 0x4607 - UART2 Scratch Register */ - char res4[8]; - u_char udsr2; /* 0x4610 - UART2 DMA Status Register */ - char res5[2543]; + u8 res1[1280]; +/* URBR1, UTHR1, UDLB1 with the same addr */ + u8 urbr1_uthr1_udlb1; +/* UIER1, UDMB1 with the same addr01 */ + u8 uier1_udmb1; +/* UIIR1, UFCR1, UAFR1 with the same addr */ + u8 uiir1_ufcr1_uafr1; + u8 ulcr1; /* UART1 Line Control */ + u8 umcr1; /* UART1 Modem Control */ + u8 ulsr1; /* UART1 Line Status */ + u8 umsr1; /* UART1 Modem Status */ + u8 uscr1; /* UART1 Scratch */ + u8 res2[8]; + u8 udsr1; /* UART1 DMA Status */ + u8 res3[239]; +/* URBR2, UTHR2, UDLB2 with the same addr */ + u8 urbr2_uthr2_udlb2; +/* UIER2, UDMB2 with the same addr */ + u8 uier2_udmb2; +/* UIIR2, UFCR2, UAFR2 with the same addr */ + u8 uiir2_ufcr2_uafr2; + u8 ulcr2; /* UART2 Line Control */ + u8 umcr2; /* UART2 Modem Control */ + u8 ulsr2; /* UART2 Line Status */ + u8 umsr2; /* UART2 Modem Status */ + u8 uscr2; /* UART2 Scratch */ + u8 res4[8]; + u8 udsr2; /* UART2 DMA Status */ + u8 res5[2543]; } ccsr_duart_t; #else /* MPC8560 uses UART on its CPM */ typedef struct ccsr_duart { - char res[4096]; + u8 res[4096]; } ccsr_duart_t; #endif -/* Local Bus Controller Registers(0x5000-0x6000) */ -/* Omitting OCeaN(0x6000) and Reserved(0x7000) block */ - +/* Local Bus Controller Registers */ typedef struct ccsr_lbc { - uint br0; /* 0x5000 - LBC Base Register 0 */ - uint or0; /* 0x5004 - LBC Options Register 0 */ - uint br1; /* 0x5008 - LBC Base Register 1 */ - uint or1; /* 0x500c - LBC Options Register 1 */ - uint br2; /* 0x5010 - LBC Base Register 2 */ - uint or2; /* 0x5014 - LBC Options Register 2 */ - uint br3; /* 0x5018 - LBC Base Register 3 */ - uint or3; /* 0x501c - LBC Options Register 3 */ - uint br4; /* 0x5020 - LBC Base Register 4 */ - uint or4; /* 0x5024 - LBC Options Register 4 */ - uint br5; /* 0x5028 - LBC Base Register 5 */ - uint or5; /* 0x502c - LBC Options Register 5 */ - uint br6; /* 0x5030 - LBC Base Register 6 */ - uint or6; /* 0x5034 - LBC Options Register 6 */ - uint br7; /* 0x5038 - LBC Base Register 7 */ - uint or7; /* 0x503c - LBC Options Register 7 */ - char res1[40]; - uint mar; /* 0x5068 - LBC UPM Address Register */ - char res2[4]; - uint mamr; /* 0x5070 - LBC UPMA Mode Register */ - uint mbmr; /* 0x5074 - LBC UPMB Mode Register */ - uint mcmr; /* 0x5078 - LBC UPMC Mode Register */ - char res3[8]; - uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */ - uint mdr; /* 0x5088 - LBC UPM Data Register */ - char res4[8]; - uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */ - char res5[8]; - uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */ - uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */ - char res6[8]; - uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */ - uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */ - uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */ - uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */ - uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */ - char res7[12]; - uint lbcr; /* 0x50d0 - LBC Configuration Register */ - uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */ - char res8[3880]; + u32 br0; /* LBC Base 0 */ + u32 or0; /* LBC Options 0 */ + u32 br1; /* LBC Base 1 */ + u32 or1; /* LBC Options 1 */ + u32 br2; /* LBC Base 2 */ + u32 or2; /* LBC Options 2 */ + u32 br3; /* LBC Base 3 */ + u32 or3; /* LBC Options 3 */ + u32 br4; /* LBC Base 4 */ + u32 or4; /* LBC Options 4 */ + u32 br5; /* LBC Base 5 */ + u32 or5; /* LBC Options 5 */ + u32 br6; /* LBC Base 6 */ + u32 or6; /* LBC Options 6 */ + u32 br7; /* LBC Base 7 */ + u32 or7; /* LBC Options 7 */ + u8 res1[40]; + u32 mar; /* LBC UPM Addr */ + u8 res2[4]; + u32 mamr; /* LBC UPMA Mode */ + u32 mbmr; /* LBC UPMB Mode */ + u32 mcmr; /* LBC UPMC Mode */ + u8 res3[8]; + u32 mrtpr; /* LBC Memory Refresh Timer Prescaler */ + u32 mdr; /* LBC UPM Data */ + u8 res4[8]; + u32 lsdmr; /* LBC SDRAM Mode */ + u8 res5[8]; + u32 lurt; /* LBC UPM Refresh Timer */ + u32 lsrt; /* LBC SDRAM Refresh Timer */ + u8 res6[8]; + u32 ltesr; /* LBC Transfer Error Status */ + u32 ltedr; /* LBC Transfer Error Disable */ + u32 lteir; /* LBC Transfer Error IRQ */ + u32 lteatr; /* LBC Transfer Error Attrs */ + u32 ltear; /* LBC Transfer Error Addr */ + u8 res7[12]; + u32 lbcr; /* LBC Configuration */ + u32 lcrr; /* LBC Clock Ratio */ + u8 res8[3880]; } ccsr_lbc_t; -/* - * eSPI Registers(0x7000-0x8000) - */ +/* eSPI Registers */ typedef struct ccsr_espi { - uint mode; /* 0x00 - eSPI mode register */ - uint event; /* 0x04 - eSPI event register */ - uint mask; /* 0x08 - eSPI mask register */ - uint com; /* 0x0c - eSPI command register */ - uint tx; /* 0x10 - eSPI transmit FIFO access register */ - uint rx; /* 0x14 - eSPI receive FIFO access register */ - char res1[8]; /* reserved */ - uint csmode[4]; /* 0x20 - 0x2c: sSPI CS0/1/2/3 mode register */ - char res2[4048]; /* fill up to 0x1000 */ + u32 mode; /* eSPI mode */ + u32 event; /* eSPI event */ + u32 mask; /* eSPI mask */ + u32 com; /* eSPI command */ + u32 tx; /* eSPI transmit FIFO access */ + u32 rx; /* eSPI receive FIFO access */ + u8 res1[8]; /* reserved */ + u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */ + u8 res2[4048]; /* fill up to 0x1000 */ } ccsr_espi_t; -/* - * PCI Registers(0x8000-0x9000) - */ +/* PCI Registers */ typedef struct ccsr_pcix { - uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */ - uint cfg_data; /* 0x8004 - PCIX Configuration Data Register */ - uint int_ack; /* 0x8008 - PCIX Interrupt Acknowledge Register */ - char res1[3060]; - uint potar0; /* 0x8c00 - PCIX Outbound Transaction Address Register 0 */ - uint potear0; /* 0x8c04 - PCIX Outbound Translation Extended Address Register 0 */ - uint powbar0; /* 0x8c08 - PCIX Outbound Window Base Address Register 0 */ - uint powbear0; /* 0x8c0c - PCIX Outbound Window Base Extended Address Register 0 */ - uint powar0; /* 0x8c10 - PCIX Outbound Window Attributes Register 0 */ - char res2[12]; - uint potar1; /* 0x8c20 - PCIX Outbound Transaction Address Register 1 */ - uint potear1; /* 0x8c24 - PCIX Outbound Translation Extended Address Register 1 */ - uint powbar1; /* 0x8c28 - PCIX Outbound Window Base Address Register 1 */ - uint powbear1; /* 0x8c2c - PCIX Outbound Window Base Extended Address Register 1 */ - uint powar1; /* 0x8c30 - PCIX Outbound Window Attributes Register 1 */ - char res3[12]; - uint potar2; /* 0x8c40 - PCIX Outbound Transaction Address Register 2 */ - uint potear2; /* 0x8c44 - PCIX Outbound Translation Extended Address Register 2 */ - uint powbar2; /* 0x8c48 - PCIX Outbound Window Base Address Register 2 */ - uint powbear2; /* 0x8c4c - PCIX Outbound Window Base Extended Address Register 2 */ - uint powar2; /* 0x8c50 - PCIX Outbound Window Attributes Register 2 */ - char res4[12]; - uint potar3; /* 0x8c60 - PCIX Outbound Transaction Address Register 3 */ - uint potear3; /* 0x8c64 - PCIX Outbound Translation Extended Address Register 3 */ - uint powbar3; /* 0x8c68 - PCIX Outbound Window Base Address Register 3 */ - uint powbear3; /* 0x8c6c - PCIX Outbound Window Base Extended Address Register 3 */ - uint powar3; /* 0x8c70 - PCIX Outbound Window Attributes Register 3 */ - char res5[12]; - uint potar4; /* 0x8c80 - PCIX Outbound Transaction Address Register 4 */ - uint potear4; /* 0x8c84 - PCIX Outbound Translation Extended Address Register 4 */ - uint powbar4; /* 0x8c88 - PCIX Outbound Window Base Address Register 4 */ - uint powbear4; /* 0x8c8c - PCIX Outbound Window Base Extended Address Register 4 */ - uint powar4; /* 0x8c90 - PCIX Outbound Window Attributes Register 4 */ - char res6[268]; - uint pitar3; /* 0x8da0 - PCIX Inbound Translation Address Register 3 */ - uint pitear3; /* 0x8da4 - PCIX Inbound Translation Extended Address Register 3 */ - uint piwbar3; /* 0x8da8 - PCIX Inbound Window Base Address Register 3 */ - uint piwbear3; /* 0x8dac - PCIX Inbound Window Base Extended Address Register 3 */ - uint piwar3; /* 0x8db0 - PCIX Inbound Window Attributes Register 3 */ - char res7[12]; - uint pitar2; /* 0x8dc0 - PCIX Inbound Translation Address Register 2 */ - uint pitear2; /* 0x8dc4 - PCIX Inbound Translation Extended Address Register 2 */ - uint piwbar2; /* 0x8dc8 - PCIX Inbound Window Base Address Register 2 */ - uint piwbear2; /* 0x8dcc - PCIX Inbound Window Base Extended Address Register 2 */ - uint piwar2; /* 0x8dd0 - PCIX Inbound Window Attributes Register 2 */ - char res8[12]; - uint pitar1; /* 0x8de0 - PCIX Inbound Translation Address Register 1 */ - uint pitear1; /* 0x8de4 - PCIX Inbound Translation Extended Address Register 1 */ - uint piwbar1; /* 0x8de8 - PCIX Inbound Window Base Address Register 1 */ - char res9[4]; - uint piwar1; /* 0x8df0 - PCIX Inbound Window Attributes Register 1 */ - char res10[12]; - uint pedr; /* 0x8e00 - PCIX Error Detect Register */ - uint pecdr; /* 0x8e04 - PCIX Error Capture Disable Register */ - uint peer; /* 0x8e08 - PCIX Error Enable Register */ - uint peattrcr; /* 0x8e0c - PCIX Error Attributes Capture Register */ - uint peaddrcr; /* 0x8e10 - PCIX Error Address Capture Register */ - uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */ - uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */ - uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */ - uint gas_timr; /* 0x8e20 - PCIX Gasket Timer Register */ - char res11[476]; + u32 cfg_addr; /* PCIX Configuration Addr */ + u32 cfg_data; /* PCIX Configuration Data */ + u32 int_ack; /* PCIX IRQ Acknowledge */ + u8 res1[3060]; + u32 potar0; /* PCIX Outbound Transaction Addr 0 */ + u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */ + u32 powbar0; /* PCIX Outbound Window Base Addr 0 */ + u32 powbear0; /* PCIX Outbound Window Base Extended Addr 0 */ + u32 powar0; /* PCIX Outbound Window Attrs 0 */ + u8 res2[12]; + u32 potar1; /* PCIX Outbound Transaction Addr 1 */ + u32 potear1; /* PCIX Outbound Translation Extended Addr 1 */ + u32 powbar1; /* PCIX Outbound Window Base Addr 1 */ + u32 powbear1; /* PCIX Outbound Window Base Extended Addr 1 */ + u32 powar1; /* PCIX Outbound Window Attrs 1 */ + u8 res3[12]; + u32 potar2; /* PCIX Outbound Transaction Addr 2 */ + u32 potear2; /* PCIX Outbound Translation Extended Addr 2 */ + u32 powbar2; /* PCIX Outbound Window Base Addr 2 */ + u32 powbear2; /* PCIX Outbound Window Base Extended Addr 2 */ + u32 powar2; /* PCIX Outbound Window Attrs 2 */ + u8 res4[12]; + u32 potar3; /* PCIX Outbound Transaction Addr 3 */ + u32 potear3; /* PCIX Outbound Translation Extended Addr 3 */ + u32 powbar3; /* PCIX Outbound Window Base Addr 3 */ + u32 powbear3; /* PCIX Outbound Window Base Extended Addr 3 */ + u32 powar3; /* PCIX Outbound Window Attrs 3 */ + u8 res5[12]; + u32 potar4; /* PCIX Outbound Transaction Addr 4 */ + u32 potear4; /* PCIX Outbound Translation Extended Addr 4 */ + u32 powbar4; /* PCIX Outbound Window Base Addr 4 */ + u32 powbear4; /* PCIX Outbound Window Base Extended Addr 4 */ + u32 powar4; /* PCIX Outbound Window Attrs 4 */ + u8 res6[268]; + u32 pitar3; /* PCIX Inbound Translation Addr 3 */ + u32 pitear3; /* PCIX Inbound Translation Extended Addr 3 */ + u32 piwbar3; /* PCIX Inbound Window Base Addr 3 */ + u32 piwbear3; /* PCIX Inbound Window Base Extended Addr 3 */ + u32 piwar3; /* PCIX Inbound Window Attrs 3 */ + u8 res7[12]; + u32 pitar2; /* PCIX Inbound Translation Addr 2 */ + u32 pitear2; /* PCIX Inbound Translation Extended Addr 2 */ + u32 piwbar2; /* PCIX Inbound Window Base Addr 2 */ + u32 piwbear2; /* PCIX Inbound Window Base Extended Addr 2 */ + u32 piwar2; /* PCIX Inbound Window Attrs 2 */ + u8 res8[12]; + u32 pitar1; /* PCIX Inbound Translation Addr 1 */ + u32 pitear1; /* PCIX Inbound Translation Extended Addr 1 */ + u32 piwbar1; /* PCIX Inbound Window Base Addr 1 */ + u8 res9[4]; + u32 piwar1; /* PCIX Inbound Window Attrs 1 */ + u8 res10[12]; + u32 pedr; /* PCIX Error Detect */ + u32 pecdr; /* PCIX Error Capture Disable */ + u32 peer; /* PCIX Error Enable */ + u32 peattrcr; /* PCIX Error Attrs Capture */ + u32 peaddrcr; /* PCIX Error Addr Capture */ + u32 peextaddrcr; /* PCIX Error Extended Addr Capture */ + u32 pedlcr; /* PCIX Error Data Low Capture */ + u32 pedhcr; /* PCIX Error Error Data High Capture */ + u32 gas_timr; /* PCIX Gasket Timer */ + u8 res11[476]; } ccsr_pcix_t; -typedef struct ccsr_gpio { - uint gpdir; - uint gpodr; - uint gpdat; - uint gpier; - uint gpimr; - uint gpicr; -} ccsr_gpio_t; - #define PCIX_COMMAND 0x62 #define POWAR_EN 0x80000000 #define POWAR_IO_READ 0x00080000 @@ -403,49 +388,55 @@ typedef struct ccsr_gpio { #define PIWAR_WRITE_SNOOP 0x00005000 #define PIWAR_MEM_2G 0x0000001e +typedef struct ccsr_gpio { + u32 gpdir; + u32 gpodr; + u32 gpdat; + u32 gpier; + u32 gpimr; + u32 gpicr; +} ccsr_gpio_t; -/* - * L2 Cache Registers(0x2_0000-0x2_1000) - */ +/* L2 Cache Registers */ typedef struct ccsr_l2cache { - uint l2ctl; /* 0x20000 - L2 configuration register 0 */ - char res1[12]; - uint l2cewar0; /* 0x20010 - L2 cache external write address register 0 */ - char res2[4]; - uint l2cewcr0; /* 0x20018 - L2 cache external write control register 0 */ - char res3[4]; - uint l2cewar1; /* 0x20020 - L2 cache external write address register 1 */ - char res4[4]; - uint l2cewcr1; /* 0x20028 - L2 cache external write control register 1 */ - char res5[4]; - uint l2cewar2; /* 0x20030 - L2 cache external write address register 2 */ - char res6[4]; - uint l2cewcr2; /* 0x20038 - L2 cache external write control register 2 */ - char res7[4]; - uint l2cewar3; /* 0x20040 - L2 cache external write address register 3 */ - char res8[4]; - uint l2cewcr3; /* 0x20048 - L2 cache external write control register 3 */ - char res9[180]; - uint l2srbar0; /* 0x20100 - L2 memory-mapped SRAM base address register 0 */ - char res10[4]; - uint l2srbar1; /* 0x20108 - L2 memory-mapped SRAM base address register 1 */ - char res11[3316]; - uint l2errinjhi; /* 0x20e00 - L2 error injection mask high register */ - uint l2errinjlo; /* 0x20e04 - L2 error injection mask low register */ - uint l2errinjctl; /* 0x20e08 - L2 error injection tag/ECC control register */ - char res12[20]; - uint l2captdatahi; /* 0x20e20 - L2 error data high capture register */ - uint l2captdatalo; /* 0x20e24 - L2 error data low capture register */ - uint l2captecc; /* 0x20e28 - L2 error ECC capture register */ - char res13[20]; - uint l2errdet; /* 0x20e40 - L2 error detect register */ - uint l2errdis; /* 0x20e44 - L2 error disable register */ - uint l2errinten; /* 0x20e48 - L2 error interrupt enable register */ - uint l2errattr; /* 0x20e4c - L2 error attributes capture register */ - uint l2erraddr; /* 0x20e50 - L2 error address capture register */ - char res14[4]; - uint l2errctl; /* 0x20e58 - L2 error control register */ - char res15[420]; + u32 l2ctl; /* L2 configuration 0 */ + u8 res1[12]; + u32 l2cewar0; /* L2 cache external write addr 0 */ + u8 res2[4]; + u32 l2cewcr0; /* L2 cache external write control 0 */ + u8 res3[4]; + u32 l2cewar1; /* L2 cache external write addr 1 */ + u8 res4[4]; + u32 l2cewcr1; /* L2 cache external write control 1 */ + u8 res5[4]; + u32 l2cewar2; /* L2 cache external write addr 2 */ + u8 res6[4]; + u32 l2cewcr2; /* L2 cache external write control 2 */ + u8 res7[4]; + u32 l2cewar3; /* L2 cache external write addr 3 */ + u8 res8[4]; + u32 l2cewcr3; /* L2 cache external write control 3 */ + u8 res9[180]; + u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */ + u8 res10[4]; + u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */ + u8 res11[3316]; + u32 l2errinjhi; /* L2 error injection mask high */ + u32 l2errinjlo; /* L2 error injection mask low */ + u32 l2errinjctl; /* L2 error injection tag/ECC control */ + u8 res12[20]; + u32 l2captdatahi; /* L2 error data high capture */ + u32 l2captdatalo; /* L2 error data low capture */ + u32 l2captecc; /* L2 error ECC capture */ + u8 res13[20]; + u32 l2errdet; /* L2 error detect */ + u32 l2errdis; /* L2 error disable */ + u32 l2errinten; /* L2 error interrupt enable */ + u32 l2errattr; /* L2 error attributes capture */ + u32 l2erraddr; /* L2 error addr capture */ + u8 res14[4]; + u32 l2errctl; /* L2 error control */ + u8 res15[420]; } ccsr_l2cache_t; #define MPC85xx_L2CTL_L2E 0x80000000 @@ -453,919 +444,910 @@ typedef struct ccsr_l2cache { #define MPC85xx_L2ERRDIS_MBECC 0x00000008 #define MPC85xx_L2ERRDIS_SBECC 0x00000004 -/* - * DMA Registers(0x2_1000-0x2_2000) - */ +/* DMA Registers */ typedef struct ccsr_dma { - char res1[256]; + u8 res1[256]; struct fsl_dma dma[4]; - uint dgsr; /* 0x21300 - DMA General Status Register */ - char res2[11516]; + u32 dgsr; /* DMA General Status */ + u8 res2[11516]; } ccsr_dma_t; -/* - * tsec1 tsec2: 24000-26000 - */ +/* tsec */ typedef struct ccsr_tsec { - char res1[16]; - uint ievent; /* 0x24010 - Interrupt Event Register */ - uint imask; /* 0x24014 - Interrupt Mask Register */ - uint edis; /* 0x24018 - Error Disabled Register */ - char res2[4]; - uint ecntrl; /* 0x24020 - Ethernet Control Register */ - uint minflr; /* 0x24024 - Minimum Frame Length Register */ - uint ptv; /* 0x24028 - Pause Time Value Register */ - uint dmactrl; /* 0x2402c - DMA Control Register */ - uint tbipa; /* 0x24030 - TBI PHY Address Register */ - char res3[88]; - uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */ - char res4[8]; - uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */ - uint fifo_tx_starve_shutoff; /* 0x2409c - FIFO transmit starve shutoff register */ - char res5[96]; - uint tctrl; /* 0x24100 - Transmit Control Register */ - uint tstat; /* 0x24104 - Transmit Status Register */ - char res6[4]; - uint tbdlen; /* 0x2410c - Transmit Buffer Descriptor Data Length Register */ - char res7[16]; - uint ctbptrh; /* 0x24120 - Current Transmit Buffer Descriptor Pointer High Register */ - uint ctbptr; /* 0x24124 - Current Transmit Buffer Descriptor Pointer Register */ - char res8[88]; - uint tbptrh; /* 0x24180 - Transmit Buffer Descriptor Pointer High Register */ - uint tbptr; /* 0x24184 - Transmit Buffer Descriptor Pointer Low Register */ - char res9[120]; - uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */ - uint tbase; /* 0x24204 - Transmit Descriptor Base Address Register */ - char res10[168]; - uint ostbd; /* 0x242b0 - Out-of-Sequence Transmit Buffer Descriptor Register */ - uint ostbdp; /* 0x242b4 - Out-of-Sequence Transmit Data Buffer Pointer Register */ - uint os32tbdp; /* 0x242b8 - Out-of-Sequence 32 Bytes Transmit Data Buffer Pointer Low Register */ - uint os32iptrh; /* 0x242bc - Out-of-Sequence 32 Bytes Transmit Insert Pointer High Register */ - uint os32iptrl; /* 0x242c0 - Out-of-Sequence 32 Bytes Transmit Insert Pointer Low Register */ - uint os32tbdr; /* 0x242c4 - Out-of-Sequence 32 Bytes Transmit Reserved Register */ - uint os32iil; /* 0x242c8 - Out-of-Sequence 32 Bytes Transmit Insert Index/Length Register */ - char res11[52]; - uint rctrl; /* 0x24300 - Receive Control Register */ - uint rstat; /* 0x24304 - Receive Status Register */ - char res12[4]; - uint rbdlen; /* 0x2430c - RxBD Data Length Register */ - char res13[16]; - uint crbptrh; /* 0x24320 - Current Receive Buffer Descriptor Pointer High */ - uint crbptr; /* 0x24324 - Current Receive Buffer Descriptor Pointer */ - char res14[24]; - uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */ - uint mrblr2r3; /* 0x24344 - Maximum Receive Buffer Length R2R3 Register */ - char res15[56]; - uint rbptrh; /* 0x24380 - Receive Buffer Descriptor Pointer High 0 */ - uint rbptr; /* 0x24384 - Receive Buffer Descriptor Pointer */ - uint rbptrh1; /* 0x24388 - Receive Buffer Descriptor Pointer High 1 */ - uint rbptrl1; /* 0x2438c - Receive Buffer Descriptor Pointer Low 1 */ - uint rbptrh2; /* 0x24390 - Receive Buffer Descriptor Pointer High 2 */ - uint rbptrl2; /* 0x24394 - Receive Buffer Descriptor Pointer Low 2 */ - uint rbptrh3; /* 0x24398 - Receive Buffer Descriptor Pointer High 3 */ - uint rbptrl3; /* 0x2439c - Receive Buffer Descriptor Pointer Low 3 */ - char res16[96]; - uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */ - uint rbase; /* 0x24404 - Receive Descriptor Base Address */ - uint rbaseh1; /* 0x24408 - Receive Descriptor Base Address High 1 */ - uint rbasel1; /* 0x2440c - Receive Descriptor Base Address Low 1 */ - uint rbaseh2; /* 0x24410 - Receive Descriptor Base Address High 2 */ - uint rbasel2; /* 0x24414 - Receive Descriptor Base Address Low 2 */ - uint rbaseh3; /* 0x24418 - Receive Descriptor Base Address High 3 */ - uint rbasel3; /* 0x2441c - Receive Descriptor Base Address Low 3 */ - char res17[224]; - uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */ - uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */ - uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */ - uint hafdup; /* 0x2450c - Half Duplex Register */ - uint maxfrm; /* 0x24510 - Maximum Frame Length Register */ - char res18[12]; - uint miimcfg; /* 0x24520 - MII Management Configuration Register */ - uint miimcom; /* 0x24524 - MII Management Command Register */ - uint miimadd; /* 0x24528 - MII Management Address Register */ - uint miimcon; /* 0x2452c - MII Management Control Register */ - uint miimstat; /* 0x24530 - MII Management Status Register */ - uint miimind; /* 0x24534 - MII Management Indicator Register */ - char res19[4]; - uint ifstat; /* 0x2453c - Interface Status Register */ - uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */ - uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */ - char res20[312]; - uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */ - uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */ - uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */ - uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */ - uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */ - uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */ - uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */ - uint rbyt; /* 0x2469c - Receive Byte Counter */ - uint rpkt; /* 0x246a0 - Receive Packet Counter */ - uint rfcs; /* 0x246a4 - Receive FCS Error Counter */ - uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */ - uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */ - uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */ - uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */ - uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */ - uint raln; /* 0x246bc - Receive Alignment Error Counter */ - uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */ - uint rcde; /* 0x246c4 - Receive Code Error Counter */ - uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */ - uint rund; /* 0x246cc - Receive Undersize Packet Counter */ - uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */ - uint rfrg; /* 0x246d4 - Receive Fragments Counter */ - uint rjbr; /* 0x246d8 - Receive Jabber Counter */ - uint rdrp; /* 0x246dc - Receive Drop Counter */ - uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */ - uint tpkt; /* 0x246e4 - Transmit Packet Counter */ - uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */ - uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */ - uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */ - uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */ - uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */ - uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */ - uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */ - uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */ - uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */ - uint tncl; /* 0x2470c - Transmit Total Collision Counter */ - char res21[4]; - uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */ - uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */ - uint tfcs; /* 0x2471c - Transmit FCS Error Counter */ - uint txcf; /* 0x24720 - Transmit Control Frame Counter */ - uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */ - uint tund; /* 0x24728 - Transmit Undersize Frame Counter */ - uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */ - uint car1; /* 0x24730 - Carry Register One */ - uint car2; /* 0x24734 - Carry Register Two */ - uint cam1; /* 0x24738 - Carry Mask Register One */ - uint cam2; /* 0x2473c - Carry Mask Register Two */ - char res22[192]; - uint iaddr0; /* 0x24800 - Indivdual address register 0 */ - uint iaddr1; /* 0x24804 - Indivdual address register 1 */ - uint iaddr2; /* 0x24808 - Indivdual address register 2 */ - uint iaddr3; /* 0x2480c - Indivdual address register 3 */ - uint iaddr4; /* 0x24810 - Indivdual address register 4 */ - uint iaddr5; /* 0x24814 - Indivdual address register 5 */ - uint iaddr6; /* 0x24818 - Indivdual address register 6 */ - uint iaddr7; /* 0x2481c - Indivdual address register 7 */ - char res23[96]; - uint gaddr0; /* 0x24880 - Global address register 0 */ - uint gaddr1; /* 0x24884 - Global address register 1 */ - uint gaddr2; /* 0x24888 - Global address register 2 */ - uint gaddr3; /* 0x2488c - Global address register 3 */ - uint gaddr4; /* 0x24890 - Global address register 4 */ - uint gaddr5; /* 0x24894 - Global address register 5 */ - uint gaddr6; /* 0x24898 - Global address register 6 */ - uint gaddr7; /* 0x2489c - Global address register 7 */ - char res24[96]; - uint pmd0; /* 0x24900 - Pattern Match Data Register */ - char res25[4]; - uint pmask0; /* 0x24908 - Pattern Mask Register */ - char res26[4]; - uint pcntrl0; /* 0x24910 - Pattern Match Control Register */ - char res27[4]; - uint pattrb0; /* 0x24918 - Pattern Match Attributes Register */ - uint pattrbeli0; /* 0x2491c - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd1; /* 0x24920 - Pattern Match Data Register */ - char res28[4]; - uint pmask1; /* 0x24928 - Pattern Mask Register */ - char res29[4]; - uint pcntrl1; /* 0x24930 - Pattern Match Control Register */ - char res30[4]; - uint pattrb1; /* 0x24938 - Pattern Match Attributes Register */ - uint pattrbeli1; /* 0x2493c - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd2; /* 0x24940 - Pattern Match Data Register */ - char res31[4]; - uint pmask2; /* 0x24948 - Pattern Mask Register */ - char res32[4]; - uint pcntrl2; /* 0x24950 - Pattern Match Control Register */ - char res33[4]; - uint pattrb2; /* 0x24958 - Pattern Match Attributes Register */ - uint pattrbeli2; /* 0x2495c - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd3; /* 0x24960 - Pattern Match Data Register */ - char res34[4]; - uint pmask3; /* 0x24968 - Pattern Mask Register */ - char res35[4]; - uint pcntrl3; /* 0x24970 - Pattern Match Control Register */ - char res36[4]; - uint pattrb3; /* 0x24978 - Pattern Match Attributes Register */ - uint pattrbeli3; /* 0x2497c - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd4; /* 0x24980 - Pattern Match Data Register */ - char res37[4]; - uint pmask4; /* 0x24988 - Pattern Mask Register */ - char res38[4]; - uint pcntrl4; /* 0x24990 - Pattern Match Control Register */ - char res39[4]; - uint pattrb4; /* 0x24998 - Pattern Match Attributes Register */ - uint pattrbeli4; /* 0x2499c - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd5; /* 0x249a0 - Pattern Match Data Register */ - char res40[4]; - uint pmask5; /* 0x249a8 - Pattern Mask Register */ - char res41[4]; - uint pcntrl5; /* 0x249b0 - Pattern Match Control Register */ - char res42[4]; - uint pattrb5; /* 0x249b8 - Pattern Match Attributes Register */ - uint pattrbeli5; /* 0x249bc - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd6; /* 0x249c0 - Pattern Match Data Register */ - char res43[4]; - uint pmask6; /* 0x249c8 - Pattern Mask Register */ - char res44[4]; - uint pcntrl6; /* 0x249d0 - Pattern Match Control Register */ - char res45[4]; - uint pattrb6; /* 0x249d8 - Pattern Match Attributes Register */ - uint pattrbeli6; /* 0x249dc - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd7; /* 0x249e0 - Pattern Match Data Register */ - char res46[4]; - uint pmask7; /* 0x249e8 - Pattern Mask Register */ - char res47[4]; - uint pcntrl7; /* 0x249f0 - Pattern Match Control Register */ - char res48[4]; - uint pattrb7; /* 0x249f8 - Pattern Match Attributes Register */ - uint pattrbeli7; /* 0x249fc - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd8; /* 0x24a00 - Pattern Match Data Register */ - char res49[4]; - uint pmask8; /* 0x24a08 - Pattern Mask Register */ - char res50[4]; - uint pcntrl8; /* 0x24a10 - Pattern Match Control Register */ - char res51[4]; - uint pattrb8; /* 0x24a18 - Pattern Match Attributes Register */ - uint pattrbeli8; /* 0x24a1c - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd9; /* 0x24a20 - Pattern Match Data Register */ - char res52[4]; - uint pmask9; /* 0x24a28 - Pattern Mask Register */ - char res53[4]; - uint pcntrl9; /* 0x24a30 - Pattern Match Control Register */ - char res54[4]; - uint pattrb9; /* 0x24a38 - Pattern Match Attributes Register */ - uint pattrbeli9; /* 0x24a3c - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd10; /* 0x24a40 - Pattern Match Data Register */ - char res55[4]; - uint pmask10; /* 0x24a48 - Pattern Mask Register */ - char res56[4]; - uint pcntrl10; /* 0x24a50 - Pattern Match Control Register */ - char res57[4]; - uint pattrb10; /* 0x24a58 - Pattern Match Attributes Register */ - uint pattrbeli10; /* 0x24a5c - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd11; /* 0x24a60 - Pattern Match Data Register */ - char res58[4]; - uint pmask11; /* 0x24a68 - Pattern Mask Register */ - char res59[4]; - uint pcntrl11; /* 0x24a70 - Pattern Match Control Register */ - char res60[4]; - uint pattrb11; /* 0x24a78 - Pattern Match Attributes Register */ - uint pattrbeli11; /* 0x24a7c - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd12; /* 0x24a80 - Pattern Match Data Register */ - char res61[4]; - uint pmask12; /* 0x24a88 - Pattern Mask Register */ - char res62[4]; - uint pcntrl12; /* 0x24a90 - Pattern Match Control Register */ - char res63[4]; - uint pattrb12; /* 0x24a98 - Pattern Match Attributes Register */ - uint pattrbeli12; /* 0x24a9c - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd13; /* 0x24aa0 - Pattern Match Data Register */ - char res64[4]; - uint pmask13; /* 0x24aa8 - Pattern Mask Register */ - char res65[4]; - uint pcntrl13; /* 0x24ab0 - Pattern Match Control Register */ - char res66[4]; - uint pattrb13; /* 0x24ab8 - Pattern Match Attributes Register */ - uint pattrbeli13; /* 0x24abc - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd14; /* 0x24ac0 - Pattern Match Data Register */ - char res67[4]; - uint pmask14; /* 0x24ac8 - Pattern Mask Register */ - char res68[4]; - uint pcntrl14; /* 0x24ad0 - Pattern Match Control Register */ - char res69[4]; - uint pattrb14; /* 0x24ad8 - Pattern Match Attributes Register */ - uint pattrbeli14; /* 0x24adc - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd15; /* 0x24ae0 - Pattern Match Data Register */ - char res70[4]; - uint pmask15; /* 0x24ae8 - Pattern Mask Register */ - char res71[4]; - uint pcntrl15; /* 0x24af0 - Pattern Match Control Register */ - char res72[4]; - uint pattrb15; /* 0x24af8 - Pattern Match Attributes Register */ - uint pattrbeli15; /* 0x24afc - Pattern Match Attributes Extract Length and Extract Index Register */ - char res73[248]; - uint attr; /* 0x24bf8 - Attributes Register */ - uint attreli; /* 0x24bfc - Attributes Extract Length and Extract Index Register */ - char res74[1024]; + u8 res1[16]; + u32 ievent; /* IRQ Event */ + u32 imask; /* IRQ Mask */ + u32 edis; /* Error Disabled */ + u8 res2[4]; + u32 ecntrl; /* Ethernet Control */ + u32 minflr; /* Minimum Frame Len */ + u32 ptv; /* Pause Time Value */ + u32 dmactrl; /* DMA Control */ + u32 tbipa; /* TBI PHY Addr */ + u8 res3[88]; + u32 fifo_tx_thr; /* FIFO transmit threshold */ + u8 res4[8]; + u32 fifo_tx_starve; /* FIFO transmit starve */ + u32 fifo_tx_starve_shutoff; /* FIFO transmit starve shutoff */ + u8 res5[96]; + u32 tctrl; /* TX Control */ + u32 tstat; /* TX Status */ + u8 res6[4]; + u32 tbdlen; /* TX Buffer Desc Data Len */ + u8 res7[16]; + u32 ctbptrh; /* Current TX Buffer Desc Ptr High */ + u32 ctbptr; /* Current TX Buffer Desc Ptr */ + u8 res8[88]; + u32 tbptrh; /* TX Buffer Desc Ptr High */ + u32 tbptr; /* TX Buffer Desc Ptr Low */ + u8 res9[120]; + u32 tbaseh; /* TX Desc Base Addr High */ + u32 tbase; /* TX Desc Base Addr */ + u8 res10[168]; + u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */ + u32 ostbdp; /* OOS TX Data Buffer Ptr */ + u32 os32tbdp; /* OOS 32 Bytes TX Data Buffer Ptr Low */ + u32 os32iptrh; /* OOS 32 Bytes TX Insert Ptr High */ + u32 os32iptrl; /* OOS 32 Bytes TX Insert Ptr Low */ + u32 os32tbdr; /* OOS 32 Bytes TX Reserved */ + u32 os32iil; /* OOS 32 Bytes TX Insert Idx/Len */ + u8 res11[52]; + u32 rctrl; /* RX Control */ + u32 rstat; /* RX Status */ + u8 res12[4]; + u32 rbdlen; /* RxBD Data Len */ + u8 res13[16]; + u32 crbptrh; /* Current RX Buffer Desc Ptr High */ + u32 crbptr; /* Current RX Buffer Desc Ptr */ + u8 res14[24]; + u32 mrblr; /* Maximum RX Buffer Len */ + u32 mrblr2r3; /* Maximum RX Buffer Len R2R3 */ + u8 res15[56]; + u32 rbptrh; /* RX Buffer Desc Ptr High 0 */ + u32 rbptr; /* RX Buffer Desc Ptr */ + u32 rbptrh1; /* RX Buffer Desc Ptr High 1 */ + u32 rbptrl1; /* RX Buffer Desc Ptr Low 1 */ + u32 rbptrh2; /* RX Buffer Desc Ptr High 2 */ + u32 rbptrl2; /* RX Buffer Desc Ptr Low 2 */ + u32 rbptrh3; /* RX Buffer Desc Ptr High 3 */ + u32 rbptrl3; /* RX Buffer Desc Ptr Low 3 */ + u8 res16[96]; + u32 rbaseh; /* RX Desc Base Addr High 0 */ + u32 rbase; /* RX Desc Base Addr */ + u32 rbaseh1; /* RX Desc Base Addr High 1 */ + u32 rbasel1; /* RX Desc Base Addr Low 1 */ + u32 rbaseh2; /* RX Desc Base Addr High 2 */ + u32 rbasel2; /* RX Desc Base Addr Low 2 */ + u32 rbaseh3; /* RX Desc Base Addr High 3 */ + u32 rbasel3; /* RX Desc Base Addr Low 3 */ + u8 res17[224]; + u32 maccfg1; /* MAC Configuration 1 */ + u32 maccfg2; /* MAC Configuration 2 */ + u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */ + u32 hafdup; /* Half Duplex */ + u32 maxfrm; /* Maximum Frame Len */ + u8 res18[12]; + u32 miimcfg; /* MII Management Configuration */ + u32 miimcom; /* MII Management Cmd */ + u32 miimadd; /* MII Management Addr */ + u32 miimcon; /* MII Management Control */ + u32 miimstat; /* MII Management Status */ + u32 miimind; /* MII Management Indicator */ + u8 res19[4]; + u32 ifstat; /* Interface Status */ + u32 macstnaddr1; /* Station Addr Part 1 */ + u32 macstnaddr2; /* Station Addr Part 2 */ + u8 res20[312]; + u32 tr64; /* TX & RX 64-byte Frame Counter */ + u32 tr127; /* TX & RX 65-127 byte Frame Counter */ + u32 tr255; /* TX & RX 128-255 byte Frame Counter */ + u32 tr511; /* TX & RX 256-511 byte Frame Counter */ + u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */ + u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */ + u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */ + u32 rbyt; /* RX Byte Counter */ + u32 rpkt; /* RX Packet Counter */ + u32 rfcs; /* RX FCS Error Counter */ + u32 rmca; /* RX Multicast Packet Counter */ + u32 rbca; /* RX Broadcast Packet Counter */ + u32 rxcf; /* RX Control Frame Packet Counter */ + u32 rxpf; /* RX Pause Frame Packet Counter */ + u32 rxuo; /* RX Unknown OP Code Counter */ + u32 raln; /* RX Alignment Error Counter */ + u32 rflr; /* RX Frame Len Error Counter */ + u32 rcde; /* RX Code Error Counter */ + u32 rcse; /* RX Carrier Sense Error Counter */ + u32 rund; /* RX Undersize Packet Counter */ + u32 rovr; /* RX Oversize Packet Counter */ + u32 rfrg; /* RX Fragments Counter */ + u32 rjbr; /* RX Jabber Counter */ + u32 rdrp; /* RX Drop Counter */ + u32 tbyt; /* TX Byte Counter Counter */ + u32 tpkt; /* TX Packet Counter */ + u32 tmca; /* TX Multicast Packet Counter */ + u32 tbca; /* TX Broadcast Packet Counter */ + u32 txpf; /* TX Pause Control Frame Counter */ + u32 tdfr; /* TX Deferral Packet Counter */ + u32 tedf; /* TX Excessive Deferral Packet Counter */ + u32 tscl; /* TX Single Collision Packet Counter */ + u32 tmcl; /* TX Multiple Collision Packet Counter */ + u32 tlcl; /* TX Late Collision Packet Counter */ + u32 txcl; /* TX Excessive Collision Packet Counter */ + u32 tncl; /* TX Total Collision Counter */ + u8 res21[4]; + u32 tdrp; /* TX Drop Frame Counter */ + u32 tjbr; /* TX Jabber Frame Counter */ + u32 tfcs; /* TX FCS Error Counter */ + u32 txcf; /* TX Control Frame Counter */ + u32 tovr; /* TX Oversize Frame Counter */ + u32 tund; /* TX Undersize Frame Counter */ + u32 tfrg; /* TX Fragments Frame Counter */ + u32 car1; /* Carry One */ + u32 car2; /* Carry Two */ + u32 cam1; /* Carry Mask One */ + u32 cam2; /* Carry Mask Two */ + u8 res22[192]; + u32 iaddr0; /* Indivdual addr 0 */ + u32 iaddr1; /* Indivdual addr 1 */ + u32 iaddr2; /* Indivdual addr 2 */ + u32 iaddr3; /* Indivdual addr 3 */ + u32 iaddr4; /* Indivdual addr 4 */ + u32 iaddr5; /* Indivdual addr 5 */ + u32 iaddr6; /* Indivdual addr 6 */ + u32 iaddr7; /* Indivdual addr 7 */ + u8 res23[96]; + u32 gaddr0; /* Global addr 0 */ + u32 gaddr1; /* Global addr 1 */ + u32 gaddr2; /* Global addr 2 */ + u32 gaddr3; /* Global addr 3 */ + u32 gaddr4; /* Global addr 4 */ + u32 gaddr5; /* Global addr 5 */ + u32 gaddr6; /* Global addr 6 */ + u32 gaddr7; /* Global addr 7 */ + u8 res24[96]; + u32 pmd0; /* Pattern Match Data */ + u8 res25[4]; + u32 pmask0; /* Pattern Mask */ + u8 res26[4]; + u32 pcntrl0; /* Pattern Match Control */ + u8 res27[4]; + u32 pattrb0; /* Pattern Match Attrs */ + u32 pattrbeli0; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd1; /* Pattern Match Data */ + u8 res28[4]; + u32 pmask1; /* Pattern Mask */ + u8 res29[4]; + u32 pcntrl1; /* Pattern Match Control */ + u8 res30[4]; + u32 pattrb1; /* Pattern Match Attrs */ + u32 pattrbeli1; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd2; /* Pattern Match Data */ + u8 res31[4]; + u32 pmask2; /* Pattern Mask */ + u8 res32[4]; + u32 pcntrl2; /* Pattern Match Control */ + u8 res33[4]; + u32 pattrb2; /* Pattern Match Attrs */ + u32 pattrbeli2; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd3; /* Pattern Match Data */ + u8 res34[4]; + u32 pmask3; /* Pattern Mask */ + u8 res35[4]; + u32 pcntrl3; /* Pattern Match Control */ + u8 res36[4]; + u32 pattrb3; /* Pattern Match Attrs */ + u32 pattrbeli3; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd4; /* Pattern Match Data */ + u8 res37[4]; + u32 pmask4; /* Pattern Mask */ + u8 res38[4]; + u32 pcntrl4; /* Pattern Match Control */ + u8 res39[4]; + u32 pattrb4; /* Pattern Match Attrs */ + u32 pattrbeli4; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd5; /* Pattern Match Data */ + u8 res40[4]; + u32 pmask5; /* Pattern Mask */ + u8 res41[4]; + u32 pcntrl5; /* Pattern Match Control */ + u8 res42[4]; + u32 pattrb5; /* Pattern Match Attrs */ + u32 pattrbeli5; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd6; /* Pattern Match Data */ + u8 res43[4]; + u32 pmask6; /* Pattern Mask */ + u8 res44[4]; + u32 pcntrl6; /* Pattern Match Control */ + u8 res45[4]; + u32 pattrb6; /* Pattern Match Attrs */ + u32 pattrbeli6; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd7; /* Pattern Match Data */ + u8 res46[4]; + u32 pmask7; /* Pattern Mask */ + u8 res47[4]; + u32 pcntrl7; /* Pattern Match Control */ + u8 res48[4]; + u32 pattrb7; /* Pattern Match Attrs */ + u32 pattrbeli7; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd8; /* Pattern Match Data */ + u8 res49[4]; + u32 pmask8; /* Pattern Mask */ + u8 res50[4]; + u32 pcntrl8; /* Pattern Match Control */ + u8 res51[4]; + u32 pattrb8; /* Pattern Match Attrs */ + u32 pattrbeli8; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd9; /* Pattern Match Data */ + u8 res52[4]; + u32 pmask9; /* Pattern Mask */ + u8 res53[4]; + u32 pcntrl9; /* Pattern Match Control */ + u8 res54[4]; + u32 pattrb9; /* Pattern Match Attrs */ + u32 pattrbeli9; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd10; /* Pattern Match Data */ + u8 res55[4]; + u32 pmask10; /* Pattern Mask */ + u8 res56[4]; + u32 pcntrl10; /* Pattern Match Control */ + u8 res57[4]; + u32 pattrb10; /* Pattern Match Attrs */ + u32 pattrbeli10; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd11; /* Pattern Match Data */ + u8 res58[4]; + u32 pmask11; /* Pattern Mask */ + u8 res59[4]; + u32 pcntrl11; /* Pattern Match Control */ + u8 res60[4]; + u32 pattrb11; /* Pattern Match Attrs */ + u32 pattrbeli11; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd12; /* Pattern Match Data */ + u8 res61[4]; + u32 pmask12; /* Pattern Mask */ + u8 res62[4]; + u32 pcntrl12; /* Pattern Match Control */ + u8 res63[4]; + u32 pattrb12; /* Pattern Match Attrs */ + u32 pattrbeli12; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd13; /* Pattern Match Data */ + u8 res64[4]; + u32 pmask13; /* Pattern Mask */ + u8 res65[4]; + u32 pcntrl13; /* Pattern Match Control */ + u8 res66[4]; + u32 pattrb13; /* Pattern Match Attrs */ + u32 pattrbeli13; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd14; /* Pattern Match Data */ + u8 res67[4]; + u32 pmask14; /* Pattern Mask */ + u8 res68[4]; + u32 pcntrl14; /* Pattern Match Control */ + u8 res69[4]; + u32 pattrb14; /* Pattern Match Attrs */ + u32 pattrbeli14; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd15; /* Pattern Match Data */ + u8 res70[4]; + u32 pmask15; /* Pattern Mask */ + u8 res71[4]; + u32 pcntrl15; /* Pattern Match Control */ + u8 res72[4]; + u32 pattrb15; /* Pattern Match Attrs */ + u32 pattrbeli15; /* Pattern Match Attrs Extract Len & Idx */ + u8 res73[248]; + u32 attr; /* Attrs */ + u32 attreli; /* Attrs Extract Len & Idx */ + u8 res74[1024]; } ccsr_tsec_t; -/* - * PIC Registers(0x4_0000-0x8_0000) - */ +/* PIC Registers */ typedef struct ccsr_pic { - char res1[64]; /* 0x40000 */ - uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */ - char res2[12]; - uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */ - char res3[12]; - uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */ - char res4[12]; - uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */ - char res5[12]; - uint ctpr; /* 0x40080 - Current Task Priority Register */ - char res6[12]; - uint whoami; /* 0x40090 - Who Am I Register */ - char res7[12]; - uint iack; /* 0x400a0 - Interrupt Acknowledge Register */ - char res8[12]; - uint eoi; /* 0x400b0 - End Of Interrupt Register */ - char res9[3916]; - uint frr; /* 0x41000 - Feature Reporting Register */ - char res10[28]; - uint gcr; /* 0x41020 - Global Configuration Register */ -#define MPC85xx_PICGCR_RST 0x80000000 -#define MPC85xx_PICGCR_M 0x20000000 - char res11[92]; - uint vir; /* 0x41080 - Vendor Identification Register */ - char res12[12]; - uint pir; /* 0x41090 - Processor Initialization Register */ - char res13[12]; - uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */ - char res14[12]; - uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */ - char res15[12]; - uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */ - char res16[12]; - uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */ - char res17[12]; - uint svr; /* 0x410e0 - Spurious Vector Register */ - char res18[12]; - uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */ - char res19[12]; - uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */ - char res20[12]; - uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */ - char res21[12]; - uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */ - char res22[12]; - uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */ - char res23[12]; - uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */ - char res24[12]; - uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */ - char res25[12]; - uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */ - char res26[12]; - uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */ - char res27[12]; - uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */ - char res28[12]; - uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */ - char res29[12]; - uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */ - char res30[12]; - uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */ - char res31[12]; - uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */ - char res32[12]; - uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */ - char res33[12]; - uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */ - char res34[12]; - uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */ - char res35[268]; - uint tcr; /* 0x41300 - Timer Control Register */ - char res36[12]; - uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */ - char res37[12]; - uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */ - char res38[12]; - uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */ - char res39[12]; - uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */ - char res40[188]; - uint msgr0; /* 0x41400 - Message Register 0 */ - char res41[12]; - uint msgr1; /* 0x41410 - Message Register 1 */ - char res42[12]; - uint msgr2; /* 0x41420 - Message Register 2 */ - char res43[12]; - uint msgr3; /* 0x41430 - Message Register 3 */ - char res44[204]; - uint mer; /* 0x41500 - Message Enable Register */ - char res45[12]; - uint msr; /* 0x41510 - Message Status Register */ - char res46[60140]; - uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */ - char res47[12]; - uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */ - char res48[12]; - uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */ - char res49[12]; - uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */ - char res50[12]; - uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */ - char res51[12]; - uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */ - char res52[12]; - uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */ - char res53[12]; - uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */ - char res54[12]; - uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */ - char res55[12]; - uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */ - char res56[12]; - uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */ - char res57[12]; - uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */ - char res58[12]; - uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */ - char res59[12]; - uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */ - char res60[12]; - uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */ - char res61[12]; - uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */ - char res62[12]; - uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */ - char res63[12]; - uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */ - char res64[12]; - uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */ - char res65[12]; - uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */ - char res66[12]; - uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */ - char res67[12]; - uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */ - char res68[12]; - uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */ - char res69[12]; - uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */ - char res70[140]; - uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */ - char res71[12]; - uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */ - char res72[12]; - uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */ - char res73[12]; - uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */ - char res74[12]; - uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */ - char res75[12]; - uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */ - char res76[12]; - uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */ - char res77[12]; - uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */ - char res78[12]; - uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */ - char res79[12]; - uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */ - char res80[12]; - uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */ - char res81[12]; - uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */ - char res82[12]; - uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */ - char res83[12]; - uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */ - char res84[12]; - uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */ - char res85[12]; - uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */ - char res86[12]; - uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */ - char res87[12]; - uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */ - char res88[12]; - uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */ - char res89[12]; - uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */ - char res90[12]; - uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */ - char res91[12]; - uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */ - char res92[12]; - uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */ - char res93[12]; - uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */ - char res94[12]; - uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */ - char res95[12]; - uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */ - char res96[12]; - uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */ - char res97[12]; - uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */ - char res98[12]; - uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */ - char res99[12]; - uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */ - char res100[12]; - uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */ - char res101[12]; - uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */ - char res102[12]; - uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */ - char res103[12]; - uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */ - char res104[12]; - uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */ - char res105[12]; - uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */ - char res106[12]; - uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */ - char res107[12]; - uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */ - char res108[12]; - uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */ - char res109[12]; - uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */ - char res110[12]; - uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */ - char res111[12]; - uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */ - char res112[12]; - uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */ - char res113[12]; - uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */ - char res114[12]; - uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */ - char res115[12]; - uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */ - char res116[12]; - uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */ - char res117[12]; - uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */ - char res118[12]; - uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */ - char res119[12]; - uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */ - char res120[12]; - uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */ - char res121[12]; - uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */ - char res122[12]; - uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */ - char res123[12]; - uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */ - char res124[12]; - uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */ - char res125[12]; - uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */ - char res126[12]; - uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */ - char res127[12]; - uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */ - char res128[12]; - uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */ - char res129[12]; - uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */ - char res130[12]; - uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */ - char res131[12]; - uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */ - char res132[12]; - uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */ - char res133[12]; - uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */ - char res134[4108]; - uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */ - char res135[12]; - uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */ - char res136[12]; - uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */ - char res137[12]; - uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */ - char res138[12]; - uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */ - char res139[12]; - uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */ - char res140[12]; - uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */ - char res141[12]; - uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */ - char res142[59852]; - uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */ - char res143[12]; - uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */ - char res144[12]; - uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */ - char res145[12]; - uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */ - char res146[12]; - uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */ - char res147[12]; - uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */ - char res148[12]; - uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */ - char res149[12]; - uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */ - char res150[130892]; + u8 res1[64]; + u32 ipidr0; /* Interprocessor IRQ Dispatch 0 */ + u8 res2[12]; + u32 ipidr1; /* Interprocessor IRQ Dispatch 1 */ + u8 res3[12]; + u32 ipidr2; /* Interprocessor IRQ Dispatch 2 */ + u8 res4[12]; + u32 ipidr3; /* Interprocessor IRQ Dispatch 3 */ + u8 res5[12]; + u32 ctpr; /* Current Task Priority */ + u8 res6[12]; + u32 whoami; /* Who Am I */ + u8 res7[12]; + u32 iack; /* IRQ Acknowledge */ + u8 res8[12]; + u32 eoi; /* End Of IRQ */ + u8 res9[3916]; + u32 frr; /* Feature Reporting */ + u8 res10[28]; + u32 gcr; /* Global Configuration */ +#define MPC85xx_PICGCR_RST 0x80000000 +#define MPC85xx_PICGCR_M 0x20000000 + u8 res11[92]; + u32 vir; /* Vendor Identification */ + u8 res12[12]; + u32 pir; /* Processor Initialization */ + u8 res13[12]; + u32 ipivpr0; /* IPI Vector/Priority 0 */ + u8 res14[12]; + u32 ipivpr1; /* IPI Vector/Priority 1 */ + u8 res15[12]; + u32 ipivpr2; /* IPI Vector/Priority 2 */ + u8 res16[12]; + u32 ipivpr3; /* IPI Vector/Priority 3 */ + u8 res17[12]; + u32 svr; /* Spurious Vector */ + u8 res18[12]; + u32 tfrr; /* Timer Frequency Reporting */ + u8 res19[12]; + u32 gtccr0; /* Global Timer Current Count 0 */ + u8 res20[12]; + u32 gtbcr0; /* Global Timer Base Count 0 */ + u8 res21[12]; + u32 gtvpr0; /* Global Timer Vector/Priority 0 */ + u8 res22[12]; + u32 gtdr0; /* Global Timer Destination 0 */ + u8 res23[12]; + u32 gtccr1; /* Global Timer Current Count 1 */ + u8 res24[12]; + u32 gtbcr1; /* Global Timer Base Count 1 */ + u8 res25[12]; + u32 gtvpr1; /* Global Timer Vector/Priority 1 */ + u8 res26[12]; + u32 gtdr1; /* Global Timer Destination 1 */ + u8 res27[12]; + u32 gtccr2; /* Global Timer Current Count 2 */ + u8 res28[12]; + u32 gtbcr2; /* Global Timer Base Count 2 */ + u8 res29[12]; + u32 gtvpr2; /* Global Timer Vector/Priority 2 */ + u8 res30[12]; + u32 gtdr2; /* Global Timer Destination 2 */ + u8 res31[12]; + u32 gtccr3; /* Global Timer Current Count 3 */ + u8 res32[12]; + u32 gtbcr3; /* Global Timer Base Count 3 */ + u8 res33[12]; + u32 gtvpr3; /* Global Timer Vector/Priority 3 */ + u8 res34[12]; + u32 gtdr3; /* Global Timer Destination 3 */ + u8 res35[268]; + u32 tcr; /* Timer Control */ + u8 res36[12]; + u32 irqsr0; /* IRQ_OUT Summary 0 */ + u8 res37[12]; + u32 irqsr1; /* IRQ_OUT Summary 1 */ + u8 res38[12]; + u32 cisr0; /* Critical IRQ Summary 0 */ + u8 res39[12]; + u32 cisr1; /* Critical IRQ Summary 1 */ + u8 res40[188]; + u32 msgr0; /* Message 0 */ + u8 res41[12]; + u32 msgr1; /* Message 1 */ + u8 res42[12]; + u32 msgr2; /* Message 2 */ + u8 res43[12]; + u32 msgr3; /* Message 3 */ + u8 res44[204]; + u32 mer; /* Message Enable */ + u8 res45[12]; + u32 msr; /* Message Status */ + u8 res46[60140]; + u32 eivpr0; /* External IRQ Vector/Priority 0 */ + u8 res47[12]; + u32 eidr0; /* External IRQ Destination 0 */ + u8 res48[12]; + u32 eivpr1; /* External IRQ Vector/Priority 1 */ + u8 res49[12]; + u32 eidr1; /* External IRQ Destination 1 */ + u8 res50[12]; + u32 eivpr2; /* External IRQ Vector/Priority 2 */ + u8 res51[12]; + u32 eidr2; /* External IRQ Destination 2 */ + u8 res52[12]; + u32 eivpr3; /* External IRQ Vector/Priority 3 */ + u8 res53[12]; + u32 eidr3; /* External IRQ Destination 3 */ + u8 res54[12]; + u32 eivpr4; /* External IRQ Vector/Priority 4 */ + u8 res55[12]; + u32 eidr4; /* External IRQ Destination 4 */ + u8 res56[12]; + u32 eivpr5; /* External IRQ Vector/Priority 5 */ + u8 res57[12]; + u32 eidr5; /* External IRQ Destination 5 */ + u8 res58[12]; + u32 eivpr6; /* External IRQ Vector/Priority 6 */ + u8 res59[12]; + u32 eidr6; /* External IRQ Destination 6 */ + u8 res60[12]; + u32 eivpr7; /* External IRQ Vector/Priority 7 */ + u8 res61[12]; + u32 eidr7; /* External IRQ Destination 7 */ + u8 res62[12]; + u32 eivpr8; /* External IRQ Vector/Priority 8 */ + u8 res63[12]; + u32 eidr8; /* External IRQ Destination 8 */ + u8 res64[12]; + u32 eivpr9; /* External IRQ Vector/Priority 9 */ + u8 res65[12]; + u32 eidr9; /* External IRQ Destination 9 */ + u8 res66[12]; + u32 eivpr10; /* External IRQ Vector/Priority 10 */ + u8 res67[12]; + u32 eidr10; /* External IRQ Destination 10 */ + u8 res68[12]; + u32 eivpr11; /* External IRQ Vector/Priority 11 */ + u8 res69[12]; + u32 eidr11; /* External IRQ Destination 11 */ + u8 res70[140]; + u32 iivpr0; /* Internal IRQ Vector/Priority 0 */ + u8 res71[12]; + u32 iidr0; /* Internal IRQ Destination 0 */ + u8 res72[12]; + u32 iivpr1; /* Internal IRQ Vector/Priority 1 */ + u8 res73[12]; + u32 iidr1; /* Internal IRQ Destination 1 */ + u8 res74[12]; + u32 iivpr2; /* Internal IRQ Vector/Priority 2 */ + u8 res75[12]; + u32 iidr2; /* Internal IRQ Destination 2 */ + u8 res76[12]; + u32 iivpr3; /* Internal IRQ Vector/Priority 3 */ + u8 res77[12]; + u32 iidr3; /* Internal IRQ Destination 3 */ + u8 res78[12]; + u32 iivpr4; /* Internal IRQ Vector/Priority 4 */ + u8 res79[12]; + u32 iidr4; /* Internal IRQ Destination 4 */ + u8 res80[12]; + u32 iivpr5; /* Internal IRQ Vector/Priority 5 */ + u8 res81[12]; + u32 iidr5; /* Internal IRQ Destination 5 */ + u8 res82[12]; + u32 iivpr6; /* Internal IRQ Vector/Priority 6 */ + u8 res83[12]; + u32 iidr6; /* Internal IRQ Destination 6 */ + u8 res84[12]; + u32 iivpr7; /* Internal IRQ Vector/Priority 7 */ + u8 res85[12]; + u32 iidr7; /* Internal IRQ Destination 7 */ + u8 res86[12]; + u32 iivpr8; /* Internal IRQ Vector/Priority 8 */ + u8 res87[12]; + u32 iidr8; /* Internal IRQ Destination 8 */ + u8 res88[12]; + u32 iivpr9; /* Internal IRQ Vector/Priority 9 */ + u8 res89[12]; + u32 iidr9; /* Internal IRQ Destination 9 */ + u8 res90[12]; + u32 iivpr10; /* Internal IRQ Vector/Priority 10 */ + u8 res91[12]; + u32 iidr10; /* Internal IRQ Destination 10 */ + u8 res92[12]; + u32 iivpr11; /* Internal IRQ Vector/Priority 11 */ + u8 res93[12]; + u32 iidr11; /* Internal IRQ Destination 11 */ + u8 res94[12]; + u32 iivpr12; /* Internal IRQ Vector/Priority 12 */ + u8 res95[12]; + u32 iidr12; /* Internal IRQ Destination 12 */ + u8 res96[12]; + u32 iivpr13; /* Internal IRQ Vector/Priority 13 */ + u8 res97[12]; + u32 iidr13; /* Internal IRQ Destination 13 */ + u8 res98[12]; + u32 iivpr14; /* Internal IRQ Vector/Priority 14 */ + u8 res99[12]; + u32 iidr14; /* Internal IRQ Destination 14 */ + u8 res100[12]; + u32 iivpr15; /* Internal IRQ Vector/Priority 15 */ + u8 res101[12]; + u32 iidr15; /* Internal IRQ Destination 15 */ + u8 res102[12]; + u32 iivpr16; /* Internal IRQ Vector/Priority 16 */ + u8 res103[12]; + u32 iidr16; /* Internal IRQ Destination 16 */ + u8 res104[12]; + u32 iivpr17; /* Internal IRQ Vector/Priority 17 */ + u8 res105[12]; + u32 iidr17; /* Internal IRQ Destination 17 */ + u8 res106[12]; + u32 iivpr18; /* Internal IRQ Vector/Priority 18 */ + u8 res107[12]; + u32 iidr18; /* Internal IRQ Destination 18 */ + u8 res108[12]; + u32 iivpr19; /* Internal IRQ Vector/Priority 19 */ + u8 res109[12]; + u32 iidr19; /* Internal IRQ Destination 19 */ + u8 res110[12]; + u32 iivpr20; /* Internal IRQ Vector/Priority 20 */ + u8 res111[12]; + u32 iidr20; /* Internal IRQ Destination 20 */ + u8 res112[12]; + u32 iivpr21; /* Internal IRQ Vector/Priority 21 */ + u8 res113[12]; + u32 iidr21; /* Internal IRQ Destination 21 */ + u8 res114[12]; + u32 iivpr22; /* Internal IRQ Vector/Priority 22 */ + u8 res115[12]; + u32 iidr22; /* Internal IRQ Destination 22 */ + u8 res116[12]; + u32 iivpr23; /* Internal IRQ Vector/Priority 23 */ + u8 res117[12]; + u32 iidr23; /* Internal IRQ Destination 23 */ + u8 res118[12]; + u32 iivpr24; /* Internal IRQ Vector/Priority 24 */ + u8 res119[12]; + u32 iidr24; /* Internal IRQ Destination 24 */ + u8 res120[12]; + u32 iivpr25; /* Internal IRQ Vector/Priority 25 */ + u8 res121[12]; + u32 iidr25; /* Internal IRQ Destination 25 */ + u8 res122[12]; + u32 iivpr26; /* Internal IRQ Vector/Priority 26 */ + u8 res123[12]; + u32 iidr26; /* Internal IRQ Destination 26 */ + u8 res124[12]; + u32 iivpr27; /* Internal IRQ Vector/Priority 27 */ + u8 res125[12]; + u32 iidr27; /* Internal IRQ Destination 27 */ + u8 res126[12]; + u32 iivpr28; /* Internal IRQ Vector/Priority 28 */ + u8 res127[12]; + u32 iidr28; /* Internal IRQ Destination 28 */ + u8 res128[12]; + u32 iivpr29; /* Internal IRQ Vector/Priority 29 */ + u8 res129[12]; + u32 iidr29; /* Internal IRQ Destination 29 */ + u8 res130[12]; + u32 iivpr30; /* Internal IRQ Vector/Priority 30 */ + u8 res131[12]; + u32 iidr30; /* Internal IRQ Destination 30 */ + u8 res132[12]; + u32 iivpr31; /* Internal IRQ Vector/Priority 31 */ + u8 res133[12]; + u32 iidr31; /* Internal IRQ Destination 31 */ + u8 res134[4108]; + u32 mivpr0; /* Messaging IRQ Vector/Priority 0 */ + u8 res135[12]; + u32 midr0; /* Messaging IRQ Destination 0 */ + u8 res136[12]; + u32 mivpr1; /* Messaging IRQ Vector/Priority 1 */ + u8 res137[12]; + u32 midr1; /* Messaging IRQ Destination 1 */ + u8 res138[12]; + u32 mivpr2; /* Messaging IRQ Vector/Priority 2 */ + u8 res139[12]; + u32 midr2; /* Messaging IRQ Destination 2 */ + u8 res140[12]; + u32 mivpr3; /* Messaging IRQ Vector/Priority 3 */ + u8 res141[12]; + u32 midr3; /* Messaging IRQ Destination 3 */ + u8 res142[59852]; + u32 ipi0dr0; /* Processor 0 Interprocessor IRQ Dispatch 0 */ + u8 res143[12]; + u32 ipi0dr1; /* Processor 0 Interprocessor IRQ Dispatch 1 */ + u8 res144[12]; + u32 ipi0dr2; /* Processor 0 Interprocessor IRQ Dispatch 2 */ + u8 res145[12]; + u32 ipi0dr3; /* Processor 0 Interprocessor IRQ Dispatch 3 */ + u8 res146[12]; + u32 ctpr0; /* Current Task Priority for Processor 0 */ + u8 res147[12]; + u32 whoami0; /* Who Am I for Processor 0 */ + u8 res148[12]; + u32 iack0; /* IRQ Acknowledge for Processor 0 */ + u8 res149[12]; + u32 eoi0; /* End Of IRQ for Processor 0 */ + u8 res150[130892]; } ccsr_pic_t; -/* - * CPM Block(0x8_0000-0xc_0000) - */ +/* CPM Block */ #ifndef CONFIG_CPM2 typedef struct ccsr_cpm { - char res[262144]; + u8 res[262144]; } ccsr_cpm_t; #else /* - * 0x8000-0x8ffff:DPARM - * 0x9000-0x90bff: General SIU + * DPARM + * General SIU */ typedef struct ccsr_cpm_siu { - char res1[80]; - uint smaer; - uint smser; - uint smevr; - char res2[4]; - uint lmaer; - uint lmser; - uint lmevr; - char res3[2964]; + u8 res1[80]; + u32 smaer; + u32 smser; + u32 smevr; + u8 res2[4]; + u32 lmaer; + u32 lmser; + u32 lmevr; + u8 res3[2964]; } ccsr_cpm_siu_t; -/* 0x90c00-0x90cff: Interrupt Controller */ +/* IRQ Controller */ typedef struct ccsr_cpm_intctl { - ushort sicr; - char res1[2]; - uint sivec; - uint sipnrh; - uint sipnrl; - uint siprr; - uint scprrh; - uint scprrl; - uint simrh; - uint simrl; - uint siexr; - char res2[88]; - uint sccr; - char res3[124]; + u16 sicr; + u8 res1[2]; + u32 sivec; + u32 sipnrh; + u32 sipnrl; + u32 siprr; + u32 scprrh; + u32 scprrl; + u32 simrh; + u32 simrl; + u32 siexr; + u8 res2[88]; + u32 sccr; + u8 res3[124]; } ccsr_cpm_intctl_t; -/* 0x90d00-0x90d7f: input/output port */ +/* input/output port */ typedef struct ccsr_cpm_iop { - uint pdira; - uint ppara; - uint psora; - uint podra; - uint pdata; - char res1[12]; - uint pdirb; - uint pparb; - uint psorb; - uint podrb; - uint pdatb; - char res2[12]; - uint pdirc; - uint pparc; - uint psorc; - uint podrc; - uint pdatc; - char res3[12]; - uint pdird; - uint ppard; - uint psord; - uint podrd; - uint pdatd; - char res4[12]; + u32 pdira; + u32 ppara; + u32 psora; + u32 podra; + u32 pdata; + u8 res1[12]; + u32 pdirb; + u32 pparb; + u32 psorb; + u32 podrb; + u32 pdatb; + u8 res2[12]; + u32 pdirc; + u32 pparc; + u32 psorc; + u32 podrc; + u32 pdatc; + u8 res3[12]; + u32 pdird; + u32 ppard; + u32 psord; + u32 podrd; + u32 pdatd; + u8 res4[12]; } ccsr_cpm_iop_t; -/* 0x90d80-0x91017: CPM timers */ +/* CPM timers */ typedef struct ccsr_cpm_timer { - u_char tgcr1; - char res1[3]; - u_char tgcr2; - char res2[11]; - ushort tmr1; - ushort tmr2; - ushort trr1; - ushort trr2; - ushort tcr1; - ushort tcr2; - ushort tcn1; - ushort tcn2; - ushort tmr3; - ushort tmr4; - ushort trr3; - ushort trr4; - ushort tcr3; - ushort tcr4; - ushort tcn3; - ushort tcn4; - ushort ter1; - ushort ter2; - ushort ter3; - ushort ter4; - char res3[608]; + u8 tgcr1; + u8 res1[3]; + u8 tgcr2; + u8 res2[11]; + u16 tmr1; + u16 tmr2; + u16 trr1; + u16 trr2; + u16 tcr1; + u16 tcr2; + u16 tcn1; + u16 tcn2; + u16 tmr3; + u16 tmr4; + u16 trr3; + u16 trr4; + u16 tcr3; + u16 tcr4; + u16 tcn3; + u16 tcn4; + u16 ter1; + u16 ter2; + u16 ter3; + u16 ter4; + u8 res3[608]; } ccsr_cpm_timer_t; -/* 0x91018-0x912ff: SDMA */ +/* SDMA */ typedef struct ccsr_cpm_sdma { - uchar sdsr; - char res1[3]; - uchar sdmr; - char res2[739]; + u8 sdsr; + u8 res1[3]; + u8 sdmr; + u8 res2[739]; } ccsr_cpm_sdma_t; -/* 0x91300-0x9131f: FCC1 */ +/* FCC1 */ typedef struct ccsr_cpm_fcc1 { - uint gfmr; - uint fpsmr; - ushort ftodr; - char res1[2]; - ushort fdsr; - char res2[2]; - ushort fcce; - char res3[2]; - ushort fccm; - char res4[2]; - u_char fccs; - char res5[3]; - u_char ftirr_phy[4]; + u32 gfmr; + u32 fpsmr; + u16 ftodr; + u8 res1[2]; + u16 fdsr; + u8 res2[2]; + u16 fcce; + u8 res3[2]; + u16 fccm; + u8 res4[2]; + u8 fccs; + u8 res5[3]; + u8 ftirr_phy[4]; } ccsr_cpm_fcc1_t; -/* 0x91320-0x9133f: FCC2 */ +/* FCC2 */ typedef struct ccsr_cpm_fcc2 { - uint gfmr; - uint fpsmr; - ushort ftodr; - char res1[2]; - ushort fdsr; - char res2[2]; - ushort fcce; - char res3[2]; - ushort fccm; - char res4[2]; - u_char fccs; - char res5[3]; - u_char ftirr_phy[4]; + u32 gfmr; + u32 fpsmr; + u16 ftodr; + u8 res1[2]; + u16 fdsr; + u8 res2[2]; + u16 fcce; + u8 res3[2]; + u16 fccm; + u8 res4[2]; + u8 fccs; + u8 res5[3]; + u8 ftirr_phy[4]; } ccsr_cpm_fcc2_t; -/* 0x91340-0x9137f: FCC3 */ +/* FCC3 */ typedef struct ccsr_cpm_fcc3 { - uint gfmr; - uint fpsmr; - ushort ftodr; - char res1[2]; - ushort fdsr; - char res2[2]; - ushort fcce; - char res3[2]; - ushort fccm; - char res4[2]; - u_char fccs; - char res5[3]; - char res[36]; + u32 gfmr; + u32 fpsmr; + u16 ftodr; + u8 res1[2]; + u16 fdsr; + u8 res2[2]; + u16 fcce; + u8 res3[2]; + u16 fccm; + u8 res4[2]; + u8 fccs; + u8 res5[3]; + u8 res[36]; } ccsr_cpm_fcc3_t; -/* 0x91380-0x9139f: FCC1 extended */ +/* FCC1 extended */ typedef struct ccsr_cpm_fcc1_ext { - uint firper; - uint firer; - uint firsr_h; - uint firsr_l; - u_char gfemr; - char res[15]; + u32 firper; + u32 firer; + u32 firsr_h; + u32 firsr_l; + u8 gfemr; + u8 res[15]; } ccsr_cpm_fcc1_ext_t; -/* 0x913a0-0x913cf: FCC2 extended */ +/* FCC2 extended */ typedef struct ccsr_cpm_fcc2_ext { - uint firper; - uint firer; - uint firsr_h; - uint firsr_l; - u_char gfemr; - char res[31]; + u32 firper; + u32 firer; + u32 firsr_h; + u32 firsr_l; + u8 gfemr; + u8 res[31]; } ccsr_cpm_fcc2_ext_t; -/* 0x913d0-0x913ff: FCC3 extended */ +/* FCC3 extended */ typedef struct ccsr_cpm_fcc3_ext { - u_char gfemr; - char res[47]; + u8 gfemr; + u8 res[47]; } ccsr_cpm_fcc3_ext_t; -/* 0x91400-0x915ef: TC layers */ +/* TC layers */ typedef struct ccsr_cpm_tmp1 { - char res[496]; + u8 res[496]; } ccsr_cpm_tmp1_t; -/* 0x915f0-0x9185f: BRGs:5,6,7,8 */ +/* BRGs:5,6,7,8 */ typedef struct ccsr_cpm_brg2 { - uint brgc5; - uint brgc6; - uint brgc7; - uint brgc8; - char res[608]; + u32 brgc5; + u32 brgc6; + u32 brgc7; + u32 brgc8; + u8 res[608]; } ccsr_cpm_brg2_t; -/* 0x91860-0x919bf: I2C */ +/* I2C */ typedef struct ccsr_cpm_i2c { - u_char i2mod; - char res1[3]; - u_char i2add; - char res2[3]; - u_char i2brg; - char res3[3]; - u_char i2com; - char res4[3]; - u_char i2cer; - char res5[3]; - u_char i2cmr; - char res6[331]; + u8 i2mod; + u8 res1[3]; + u8 i2add; + u8 res2[3]; + u8 i2brg; + u8 res3[3]; + u8 i2com; + u8 res4[3]; + u8 i2cer; + u8 res5[3]; + u8 i2cmr; + u8 res6[331]; } ccsr_cpm_i2c_t; -/* 0x919c0-0x919ef: CPM core */ +/* CPM core */ typedef struct ccsr_cpm_cp { - uint cpcr; - uint rccr; - char res1[14]; - ushort rter; - char res2[2]; - ushort rtmr; - ushort rtscr; - char res3[2]; - uint rtsr; - char res4[12]; + u32 cpcr; + u32 rccr; + u8 res1[14]; + u16 rter; + u8 res2[2]; + u16 rtmr; + u16 rtscr; + u8 res3[2]; + u32 rtsr; + u8 res4[12]; } ccsr_cpm_cp_t; -/* 0x919f0-0x919ff: BRGs:1,2,3,4 */ +/* BRGs:1,2,3,4 */ typedef struct ccsr_cpm_brg1 { - uint brgc1; - uint brgc2; - uint brgc3; - uint brgc4; + u32 brgc1; + u32 brgc2; + u32 brgc3; + u32 brgc4; } ccsr_cpm_brg1_t; -/* 0x91a00-0x91a9f: SCC1-SCC4 */ +/* SCC1-SCC4 */ typedef struct ccsr_cpm_scc { - uint gsmrl; - uint gsmrh; - ushort psmr; - char res1[2]; - ushort todr; - ushort dsr; - ushort scce; - char res2[2]; - ushort sccm; - char res3; - u_char sccs; - char res4[8]; + u32 gsmrl; + u32 gsmrh; + u16 psmr; + u8 res1[2]; + u16 todr; + u16 dsr; + u16 scce; + u8 res2[2]; + u16 sccm; + u8 res3; + u8 sccs; + u8 res4[8]; } ccsr_cpm_scc_t; -/* 0x91a80-0x91a9f */ typedef struct ccsr_cpm_tmp2 { - char res[32]; + u8 res[32]; } ccsr_cpm_tmp2_t; -/* 0x91aa0-0x91aff: SPI */ +/* SPI */ typedef struct ccsr_cpm_spi { - ushort spmode; - char res1[4]; - u_char spie; - char res2[3]; - u_char spim; - char res3[2]; - u_char spcom; - char res4[82]; + u16 spmode; + u8 res1[4]; + u8 spie; + u8 res2[3]; + u8 spim; + u8 res3[2]; + u8 spcom; + u8 res4[82]; } ccsr_cpm_spi_t; -/* 0x91b00-0x91b1f: CPM MUX */ +/* CPM MUX */ typedef struct ccsr_cpm_mux { - u_char cmxsi1cr; - char res1; - u_char cmxsi2cr; - char res2; - uint cmxfcr; - uint cmxscr; - char res3[2]; - ushort cmxuar; - char res4[16]; + u8 cmxsi1cr; + u8 res1; + u8 cmxsi2cr; + u8 res2; + u32 cmxfcr; + u32 cmxscr; + u8 res3[2]; + u16 cmxuar; + u8 res4[16]; } ccsr_cpm_mux_t; -/* 0x91b20-0xbffff: SI,MCC,etc */ +/* SI,MCC,etc */ typedef struct ccsr_cpm_tmp3 { - char res[58592]; + u8 res[58592]; } ccsr_cpm_tmp3_t; typedef struct ccsr_cpm_iram { - unsigned long iram[8192]; - char res[98304]; + u32 iram[8192]; + u8 res[98304]; } ccsr_cpm_iram_t; typedef struct ccsr_cpm { - /* Some references are into the unique and known dpram spaces, + /* Some references are into the unique & known dpram spaces, * others are from the generic base. */ #define im_dprambase im_dpram1 - u_char im_dpram1[16*1024]; - char res1[16*1024]; - u_char im_dpram2[16*1024]; - char res2[16*1024]; - ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */ - ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */ - ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */ - ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */ - ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */ + u8 im_dpram1[16*1024]; + u8 res1[16*1024]; + u8 im_dpram2[16*1024]; + u8 res2[16*1024]; + ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */ + ccsr_cpm_intctl_t im_cpm_intctl; /* IRQ Controller */ + ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */ + ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */ + ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */ ccsr_cpm_fcc1_t im_cpm_fcc1; ccsr_cpm_fcc2_t im_cpm_fcc2; ccsr_cpm_fcc3_t im_cpm_fcc3; @@ -1386,203 +1368,199 @@ typedef struct ccsr_cpm { } ccsr_cpm_t; #endif -/* - * RapidIO Registers(0xc_0000-0xe_0000) - */ +/* RapidIO Registers */ typedef struct ccsr_rio { - uint didcar; /* 0xc0000 - Device Identity Capability Register */ - uint dicar; /* 0xc0004 - Device Information Capability Register */ - uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */ - uint aicar; /* 0xc000c - Assembly Information Capability Register */ - uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */ - uint spicar; /* 0xc0014 - Switch Port Information Capability Register */ - uint socar; /* 0xc0018 - Source Operations Capability Register */ - uint docar; /* 0xc001c - Destination Operations Capability Register */ - char res1[32]; - uint msr; /* 0xc0040 - Mailbox Command And Status Register */ - uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */ - char res2[4]; - uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */ - char res3[12]; - uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */ - uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */ - char res4[4]; - uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */ - uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */ - char res5[144]; - uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */ - char res6[28]; - uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */ - uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */ - char res7[20]; - uint pgccsr; /* 0xc013c - Port General Command and Status Register */ - uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */ - uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */ - uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */ - char res8[12]; - uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */ - uint pccsr; /* 0xc015c - Port Control Command and Status Register */ - char res9[65184]; - uint cr; /* 0xd0000 - Port Control Command and Status Register */ - char res10[12]; - uint pcr; /* 0xd0010 - Port Configuration Register */ - uint peir; /* 0xd0014 - Port Error Injection Register */ - char res11[3048]; - uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */ - char res12[12]; - uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */ - char res13[12]; - uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */ - char res14[4]; - uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */ - char res15[4]; - uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */ - char res16[12]; - uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */ - char res17[4]; - uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */ - char res18[4]; - uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */ - char res19[12]; - uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */ - char res20[4]; - uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */ - char res21[4]; - uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */ - char res22[12]; - uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */ - char res23[4]; - uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */ - char res24[4]; - uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */ - char res25[12]; - uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */ - char res26[4]; - uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */ - char res27[4]; - uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */ - char res28[12]; - uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */ - char res29[4]; - uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */ - char res30[4]; - uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */ - char res31[12]; - uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */ - char res32[4]; - uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */ - char res33[4]; - uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */ - char res34[12]; - uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */ - char res35[4]; - uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */ - char res36[4]; - uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */ - char res37[76]; - uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */ - char res38[4]; - uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */ - char res39[4]; - uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */ - char res40[12]; - uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */ - char res41[4]; - uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */ - char res42[4]; - uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */ - char res43[12]; - uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */ - char res44[4]; - uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */ - char res45[4]; - uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */ - char res46[12]; - uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */ - char res47[4]; - uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */ - char res48[4]; - uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */ - char res49[12]; - uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */ - char res50[12]; - uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */ - char res51[12]; - uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */ - uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */ - uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */ - uint pecr; /* 0xd0e0c - Port Error Control Register */ - uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */ - uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */ - uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */ - char res52[4]; - uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */ - char res53[4]; - uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */ - uint prtr; /* 0xd0e2c - Port Retry Threshold Register */ - char res54[464]; - uint omr; /* 0xd1000 - Outbound Mode Register */ - uint osr; /* 0xd1004 - Outbound Status Register */ - uint eodqtpar; /* 0xd1008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */ - uint odqtpar; /* 0xd100c - Outbound Descriptor Queue Tail Pointer Address Register */ - uint eosar; /* 0xd1010 - Extended Outbound Unit Source Address Register */ - uint osar; /* 0xd1014 - Outbound Unit Source Address Register */ - uint odpr; /* 0xd1018 - Outbound Destination Port Register */ - uint odatr; /* 0xd101c - Outbound Destination Attributes Register */ - uint odcr; /* 0xd1020 - Outbound Doubleword Count Register */ - uint eodqhpar; /* 0xd1024 - Extended Outbound Descriptor Queue Head Pointer Address Register */ - uint odqhpar; /* 0xd1028 - Outbound Descriptor Queue Head Pointer Address Register */ - char res55[52]; - uint imr; /* 0xd1060 - Outbound Mode Register */ - uint isr; /* 0xd1064 - Inbound Status Register */ - uint eidqtpar; /* 0xd1068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */ - uint idqtpar; /* 0xd106c - Inbound Descriptor Queue Tail Pointer Address Register */ - uint eifqhpar; /* 0xd1070 - Extended Inbound Frame Queue Head Pointer Address Register */ - uint ifqhpar; /* 0xd1074 - Inbound Frame Queue Head Pointer Address Register */ - char res56[1000]; - uint dmr; /* 0xd1460 - Doorbell Mode Register */ - uint dsr; /* 0xd1464 - Doorbell Status Register */ - uint edqtpar; /* 0xd1468 - Extended Doorbell Queue Tail Pointer Address Register */ - uint dqtpar; /* 0xd146c - Doorbell Queue Tail Pointer Address Register */ - uint edqhpar; /* 0xd1470 - Extended Doorbell Queue Head Pointer Address Register */ - uint dqhpar; /* 0xd1474 - Doorbell Queue Head Pointer Address Register */ - char res57[104]; - uint pwmr; /* 0xd14e0 - Port-Write Mode Register */ - uint pwsr; /* 0xd14e4 - Port-Write Status Register */ - uint epwqbar; /* 0xd14e8 - Extended Port-Write Queue Base Address Register */ - uint pwqbar; /* 0xd14ec - Port-Write Queue Base Address Register */ - char res58[60176]; + u32 didcar; /* Device Identity Capability */ + u32 dicar; /* Device Information Capability */ + u32 aidcar; /* Assembly Identity Capability */ + u32 aicar; /* Assembly Information Capability */ + u32 pefcar; /* Processing Element Features Capability */ + u32 spicar; /* Switch Port Information Capability */ + u32 socar; /* Source Operations Capability */ + u32 docar; /* Destination Operations Capability */ + u8 res1[32]; + u32 msr; /* Mailbox Cmd And Status */ + u32 pwdcsr; /* Port-Write & Doorbell Cmd And Status */ + u8 res2[4]; + u32 pellccsr; /* Processing Element Logic Layer CCSR */ + u8 res3[12]; + u32 lcsbacsr; /* Local Cfg Space Base Addr Cmd & Status */ + u32 bdidcsr; /* Base Device ID Cmd & Status */ + u8 res4[4]; + u32 hbdidlcsr; /* Host Base Device ID Lock Cmd & Status */ + u32 ctcsr; /* Component Tag Cmd & Status */ + u8 res5[144]; + u32 pmbh0csr; /* Port Maint. Block Hdr 0 Cmd & Status */ + u8 res6[28]; + u32 pltoccsr; /* Port Link Time-out Ctrl Cmd & Status */ + u32 prtoccsr; /* Port Response Time-out Ctrl Cmd & Status */ + u8 res7[20]; + u32 pgccsr; /* Port General Cmd & Status */ + u32 plmreqcsr; /* Port Link Maint. Request Cmd & Status */ + u32 plmrespcsr; /* Port Link Maint. Response Cmd & Status */ + u32 plascsr; /* Port Local Ackid Status Cmd & Status */ + u8 res8[12]; + u32 pescsr; /* Port Error & Status Cmd & Status */ + u32 pccsr; /* Port Control Cmd & Status */ + u8 res9[65184]; + u32 cr; /* Port Control Cmd & Status */ + u8 res10[12]; + u32 pcr; /* Port Configuration */ + u32 peir; /* Port Error Injection */ + u8 res11[3048]; + u32 rowtar0; /* RIO Outbound Window Translation Addr 0 */ + u8 res12[12]; + u32 rowar0; /* RIO Outbound Attrs 0 */ + u8 res13[12]; + u32 rowtar1; /* RIO Outbound Window Translation Addr 1 */ + u8 res14[4]; + u32 rowbar1; /* RIO Outbound Window Base Addr 1 */ + u8 res15[4]; + u32 rowar1; /* RIO Outbound Attrs 1 */ + u8 res16[12]; + u32 rowtar2; /* RIO Outbound Window Translation Addr 2 */ + u8 res17[4]; + u32 rowbar2; /* RIO Outbound Window Base Addr 2 */ + u8 res18[4]; + u32 rowar2; /* RIO Outbound Attrs 2 */ + u8 res19[12]; + u32 rowtar3; /* RIO Outbound Window Translation Addr 3 */ + u8 res20[4]; + u32 rowbar3; /* RIO Outbound Window Base Addr 3 */ + u8 res21[4]; + u32 rowar3; /* RIO Outbound Attrs 3 */ + u8 res22[12]; + u32 rowtar4; /* RIO Outbound Window Translation Addr 4 */ + u8 res23[4]; + u32 rowbar4; /* RIO Outbound Window Base Addr 4 */ + u8 res24[4]; + u32 rowar4; /* RIO Outbound Attrs 4 */ + u8 res25[12]; + u32 rowtar5; /* RIO Outbound Window Translation Addr 5 */ + u8 res26[4]; + u32 rowbar5; /* RIO Outbound Window Base Addr 5 */ + u8 res27[4]; + u32 rowar5; /* RIO Outbound Attrs 5 */ + u8 res28[12]; + u32 rowtar6; /* RIO Outbound Window Translation Addr 6 */ + u8 res29[4]; + u32 rowbar6; /* RIO Outbound Window Base Addr 6 */ + u8 res30[4]; + u32 rowar6; /* RIO Outbound Attrs 6 */ + u8 res31[12]; + u32 rowtar7; /* RIO Outbound Window Translation Addr 7 */ + u8 res32[4]; + u32 rowbar7; /* RIO Outbound Window Base Addr 7 */ + u8 res33[4]; + u32 rowar7; /* RIO Outbound Attrs 7 */ + u8 res34[12]; + u32 rowtar8; /* RIO Outbound Window Translation Addr 8 */ + u8 res35[4]; + u32 rowbar8; /* RIO Outbound Window Base Addr 8 */ + u8 res36[4]; + u32 rowar8; /* RIO Outbound Attrs 8 */ + u8 res37[76]; + u32 riwtar4; /* RIO Inbound Window Translation Addr 4 */ + u8 res38[4]; + u32 riwbar4; /* RIO Inbound Window Base Addr 4 */ + u8 res39[4]; + u32 riwar4; /* RIO Inbound Attrs 4 */ + u8 res40[12]; + u32 riwtar3; /* RIO Inbound Window Translation Addr 3 */ + u8 res41[4]; + u32 riwbar3; /* RIO Inbound Window Base Addr 3 */ + u8 res42[4]; + u32 riwar3; /* RIO Inbound Attrs 3 */ + u8 res43[12]; + u32 riwtar2; /* RIO Inbound Window Translation Addr 2 */ + u8 res44[4]; + u32 riwbar2; /* RIO Inbound Window Base Addr 2 */ + u8 res45[4]; + u32 riwar2; /* RIO Inbound Attrs 2 */ + u8 res46[12]; + u32 riwtar1; /* RIO Inbound Window Translation Addr 1 */ + u8 res47[4]; + u32 riwbar1; /* RIO Inbound Window Base Addr 1 */ + u8 res48[4]; + u32 riwar1; /* RIO Inbound Attrs 1 */ + u8 res49[12]; + u32 riwtar0; /* RIO Inbound Window Translation Addr 0 */ + u8 res50[12]; + u32 riwar0; /* RIO Inbound Attrs 0 */ + u8 res51[12]; + u32 pnfedr; /* Port Notification/Fatal Error Detect */ + u32 pnfedir; /* Port Notification/Fatal Error Detect */ + u32 pnfeier; /* Port Notification/Fatal Error IRQ Enable */ + u32 pecr; /* Port Error Control */ + u32 pepcsr0; /* Port Error Packet/Control Symbol 0 */ + u32 pepr1; /* Port Error Packet 1 */ + u32 pepr2; /* Port Error Packet 2 */ + u8 res52[4]; + u32 predr; /* Port Recoverable Error Detect */ + u8 res53[4]; + u32 pertr; /* Port Error Recovery Threshold */ + u32 prtr; /* Port Retry Threshold */ + u8 res54[464]; + u32 omr; /* Outbound Mode */ + u32 osr; /* Outbound Status */ + u32 eodqtpar; /* Extended Outbound Desc Queue Tail Ptr Addr */ + u32 odqtpar; /* Outbound Desc Queue Tail Ptr Addr */ + u32 eosar; /* Extended Outbound Unit Source Addr */ + u32 osar; /* Outbound Unit Source Addr */ + u32 odpr; /* Outbound Destination Port */ + u32 odatr; /* Outbound Destination Attrs */ + u32 odcr; /* Outbound Doubleword Count */ + u32 eodqhpar; /* Extended Outbound Desc Queue Head Ptr Addr */ + u32 odqhpar; /* Outbound Desc Queue Head Ptr Addr */ + u8 res55[52]; + u32 imr; /* Outbound Mode */ + u32 isr; /* Inbound Status */ + u32 eidqtpar; /* Extended Inbound Desc Queue Tail Ptr Addr */ + u32 idqtpar; /* Inbound Desc Queue Tail Ptr Addr */ + u32 eifqhpar; /* Extended Inbound Frame Queue Head Ptr Addr */ + u32 ifqhpar; /* Inbound Frame Queue Head Ptr Addr */ + u8 res56[1000]; + u32 dmr; /* Doorbell Mode */ + u32 dsr; /* Doorbell Status */ + u32 edqtpar; /* Extended Doorbell Queue Tail Ptr Addr */ + u32 dqtpar; /* Doorbell Queue Tail Ptr Addr */ + u32 edqhpar; /* Extended Doorbell Queue Head Ptr Addr */ + u32 dqhpar; /* Doorbell Queue Head Ptr Addr */ + u8 res57[104]; + u32 pwmr; /* Port-Write Mode */ + u32 pwsr; /* Port-Write Status */ + u32 epwqbar; /* Extended Port-Write Queue Base Addr */ + u32 pwqbar; /* Port-Write Queue Base Addr */ + u8 res58[60176]; } ccsr_rio_t; -/* Quick Engine Block Pin Muxing Registers (0xe_0100 - 0xe_01bf) */ +/* Quick Engine Block Pin Muxing Registers */ typedef struct par_io { - uint cpodr; /* 0x100 */ - uint cpdat; /* 0x104 */ - uint cpdir1; /* 0x108 */ - uint cpdir2; /* 0x10c */ - uint cppar1; /* 0x110 */ - uint cppar2; /* 0x114 */ - char res[8]; -}par_io_t; + u32 cpodr; + u32 cpdat; + u32 cpdir1; + u32 cpdir2; + u32 cppar1; + u32 cppar2; + u8 res[8]; +} par_io_t; -/* - * Global Utilities Register Block(0xe_0000-0xf_ffff) - */ +/* Global Utilities Block */ #ifdef CONFIG_FSL_CORENET typedef struct ccsr_gur { - u32 porsr1; /* 0xe0000 - POR status register */ - u8 res1[28]; /* 0xe0004 - 0xe001c Reserved: PORSRn */ - u32 gpporcr1; /* 0xe0020 - General-purpose POR configuration register */ + u32 porsr1; /* POR status */ + u8 res1[28]; + u32 gpporcr1; /* General-purpose POR configuration */ u8 res2[12]; - u32 gpiocr; /* 0xe0030 - GPIO control register */ + u32 gpiocr; /* GPIO control */ u8 res3[12]; - u32 gpoutdr; /* 0xe0040 - General-purpose output data register */ + u32 gpoutdr; /* General-purpose output data */ u8 res4[12]; - u32 gpindr; /* 0xe0050 - General-purpose input data register */ + u32 gpindr; /* General-purpose input data */ u8 res5[12]; - u32 pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ + u32 pmuxcr; /* Alt function signal multiplex control */ u8 res6[12]; - u32 devdisr; /* 0xe0070 - Device disable control */ + u32 devdisr; /* Device disable control */ #define FSL_CORENET_DEVDISR_PCIE1 0x80000000 #define FSL_CORENET_DEVDISR_PCIE2 0x40000000 #define FSL_CORENET_DEVDISR_PCIE3 0x20000000 @@ -1606,157 +1584,157 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR_DUART1 0x00000002 #define FSL_CORENET_DEVDISR_DUART2 0x00000001 u8 res7[12]; - u32 powmgtcsr; /* 0xe0080 - Power management status and control register */ + u32 powmgtcsr; /* Power management status & control */ u8 res8[12]; - u32 coredisru; /* 0xe0090 - uppper portion for support of 64 cores */ - u32 coredisrl; /* 0xe0094 - lower portion for support of 64 cores */ + u32 coredisru; /* uppper portion for support of 64 cores */ + u32 coredisrl; /* lower portion for support of 64 cores */ u8 res9[8]; - u32 pvr; /* 0xe00a0 - Processor version register */ - u32 svr; /* 0xe00a4 - System version register */ + u32 pvr; /* Processor version */ + u32 svr; /* System version */ u8 res10[8]; - u32 rstcr; /* 0xe00b0 - Reset control register */ - u32 rstrqpblsr; /* 0xe00b4 - Reset request preboot loader status register */ + u32 rstcr; /* Reset control */ + u32 rstrqpblsr; /* Reset request preboot loader status */ u8 res11[8]; - u32 rstrqmr1; /* 0xe00c0 - Reset request mask register */ - u8 res12[4]; /* Reserved: RSTRQMR2 */ - u32 rstrqsr1; /* 0xe00c8 - Reset request status register */ - u8 res13[4]; /* Reserved: RSTRQSR2 */ - u8 res14[4]; /* Reserved: RSTRQWDTMRU */ - u32 rstrqwdtmrl; /* 0xe00d4 - Reset request WDT mask register */ - u8 res15[4]; /* Reserved: RSTRQWDTSRU */ - u32 rstrqwdtsrl; /* 0xe00dc - Reset request WDT status register */ - u8 res16[4]; /* Reserved: BRRU max total of 2 for up to 64 cores */ - u32 brrl; /* 0xe00e4 Boot release register */ + u32 rstrqmr1; /* Reset request mask */ + u8 res12[4]; + u32 rstrqsr1; /* Reset request status */ + u8 res13[4]; + u8 res14[4]; + u32 rstrqwdtmrl; /* Reset request WDT mask */ + u8 res15[4]; + u32 rstrqwdtsrl; /* Reset request WDT status */ + u8 res16[4]; + u32 brrl; /* Boot release */ u8 res17[24]; - u32 rcwsr[16]; /* 0xe0100 - 0xe013c: Reset control word status register */ + u32 rcwsr[16]; /* Reset control word status */ #define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000 #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00008000 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 15 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000 #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000 - u8 res18[192]; /* Reserved: RCWSRn (max total of 64)*/ - u32 scratchrw[4]; /* 0xe0200 - 0xe020c: Scratch Read/Write register */ - u8 res19[240]; /* Reserved: SCRATCHRWn (max total of 64)*/ - u32 scratchw1r[4]; /* 0xe0300 - 0xe030c: Scratch Read register (Write once) */ - u8 res20[240]; /* Reserved: SCRATCHW1Rn (max total of 64)*/ - u32 scrtsr[8]; /* 0xe0400 - 0xe041c: Core reset status register */ - u8 res21[224]; /* Reserved: CRSTSRn (max total of 64 for up to 64 cores)*/ - u32 pex1liodnr; /* 0xe0500 PCI Express 1 Logical I/O Device Number register*/ - u32 pex2liodnr; /* 0xe0504 PCI Express 2 Logical I/O Device Number register*/ - u32 pex3liodnr; /* 0xe0508 PCI Express 3 Logical I/O Device Number register*/ - u32 pex4liodnr; /* 0xe050c PCI Express 4 Logical I/O Device Number register*/ - u32 rio1liodnr; /* 0xe0510 RIO 1 Logical I/O Device Number register*/ - u32 rio2liodnr; /* 0xe0514 RIO 2 Logical I/O Device Number register*/ - u32 rio3liodnr; /* 0xe0518 RIO 3 Logical I/O Device Number register*/ - u32 rio4liodnr; /* 0xe051c RIO 4 Logical I/O Device Number register*/ - u32 usb1liodnr; /* 0xe0520 USB 1 Logical I/O Device Number register*/ - u32 usb2liodnr; /* 0xe0524 USB 2 Logical I/O Device Number register*/ - u32 usb3liodnr; /* 0xe0528 USB 3 Logical I/O Device Number register*/ - u32 usb4liodnr; /* 0xe052c USB 4 Logical I/O Device Number register*/ - u32 sdmmc1liodnr; /* 0xe0530 SD/MMC 1 Logical I/O Device Number register*/ - u32 sdmmc2liodnr; /* 0xe0534 SD/MMC 2 Logical I/O Device Number register*/ - u32 sdmmc3liodnr; /* 0xe0538 SD/MMC 3 Logical I/O Device Number register*/ - u32 sdmmc4liodnr; /* 0xe053c SD/MMC 4 Logical I/O Device Number register*/ - u32 rmuliodnr; /* 0xe0540 RIO Message Unit Logical I/O Device Number register*/ - u32 rduliodnr; /* 0xe0544 RIO Doorbell Unit Logical I/O Device Number register*/ - u32 rpwuliodnr; /* 0xe0548 RIO Port Write Unit Logical I/O Device Number register*/ - u8 res22[52]; /* Reserved: for future LIODN register expansion */ - u32 dma1liodnr; /* 0xe0580 DMA 1 Logical I/O Device Number register*/ - u32 dma2liodnr; /* 0xe0584 DMA 2 Logical I/O Device Number register*/ - u32 dma3liodnr; /* 0xe0588 DMA 3 Logical I/O Device Number register*/ - u32 dma4liodnr; /* 0xe058c DMA 4 Logical I/O Device Number register*/ - u8 res23[48]; /* Reserved: for future LIODN register expansion */ - u8 res24[64]; /* Reserved */ - u32 pblsr; /* 0xe0600 Preboot loader status register*/ - u32 pamubypenr; /* 0xe0604 PAMU bypass enable register*/ - u32 dmacr1; /* 0xe0608 DMA control register*/ - u8 res25[4]; /* Reserved: DMACR2 (max total of 2)*/ - u32 gensr1; /* 0xe0610 General status register*/ - u8 res26[12]; /* Reserved: GENSRn (max total of 4)*/ - u32 gencr1; /* 0xe0620 General control register*/ - u8 res27[12]; /* Reserved: GENCRn (max total of 4)*/ - u8 res28[4]; /* Reserved: CGENSRU (upper portion for support of 64 cores) */ - u32 cgensrl; /* 0xe0634 Core general status register*/ - u8 res29[8]; /* Reserved */ - u8 res30[4]; /* Reserved: CGENCRU (upper portion for support of 64 cores) */ - u32 cgencrl; /* 0xe0634 Core general control register*/ - u8 res31[184]; /* Reserved 0xe0648 - 0xe06fc */ - u32 sriopstecr; /* 0xe0700 SRIO prescaler timer enable control register*/ - u8 res32[2300]; /* Reserved 0xe0704 - 0xe0ffc */ + u8 res18[192]; + u32 scratchrw[4]; /* Scratch Read/Write */ + u8 res19[240]; + u32 scratchw1r[4]; /* Scratch Read (Write once) */ + u8 res20[240]; + u32 scrtsr[8]; /* Core reset status */ + u8 res21[224]; + u32 pex1liodnr; /* PCI Express 1 LIODN */ + u32 pex2liodnr; /* PCI Express 2 LIODN */ + u32 pex3liodnr; /* PCI Express 3 LIODN */ + u32 pex4liodnr; /* PCI Express 4 LIODN */ + u32 rio1liodnr; /* RIO 1 LIODN */ + u32 rio2liodnr; /* RIO 2 LIODN */ + u32 rio3liodnr; /* RIO 3 LIODN */ + u32 rio4liodnr; /* RIO 4 LIODN */ + u32 usb1liodnr; /* USB 1 LIODN */ + u32 usb2liodnr; /* USB 2 LIODN */ + u32 usb3liodnr; /* USB 3 LIODN */ + u32 usb4liodnr; /* USB 4 LIODN */ + u32 sdmmc1liodnr; /* SD/MMC 1 LIODN */ + u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */ + u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */ + u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */ + u32 rmuliodnr; /* RIO Message Unit LIODN */ + u32 rduliodnr; /* RIO Doorbell Unit LIODN */ + u32 rpwuliodnr; /* RIO Port Write Unit LIODN */ + u8 res22[52]; + u32 dma1liodnr; /* DMA 1 LIODN */ + u32 dma2liodnr; /* DMA 2 LIODN */ + u32 dma3liodnr; /* DMA 3 LIODN */ + u32 dma4liodnr; /* DMA 4 LIODN */ + u8 res23[48]; + u8 res24[64]; + u32 pblsr; /* Preboot loader status */ + u32 pamubypenr; /* PAMU bypass enable */ + u32 dmacr1; /* DMA control */ + u8 res25[4]; + u32 gensr1; /* General status */ + u8 res26[12]; + u32 gencr1; /* General control */ + u8 res27[12]; + u8 res28[4]; + u32 cgensrl; /* Core general status */ + u8 res29[8]; + u8 res30[4]; + u32 cgencrl; /* Core general control */ + u8 res31[184]; + u32 sriopstecr; /* SRIO prescaler timer enable control */ + u8 res32[2300]; } ccsr_gur_t; typedef struct ccsr_clk { - u32 clkc0csr; /* 0xe1000 - Core 0 Clock control/status register */ - u8 res1[0x1c]; - u32 clkc1csr; /* 0xe1020 - Core 1 Clock control/status register */ - u8 res2[0x1c]; - u32 clkc2csr; /* 0xe1040 - Core 2 Clock control/status register */ - u8 res3[0x1c]; - u32 clkc3csr; /* 0xe1060 - Core 3 Clock control/status register */ - u8 res4[0x1c]; - u32 clkc4csr; /* 0xe1080 - Core 4 Clock control/status register */ - u8 res5[0x1c]; - u32 clkc5csr; /* 0xe10a0 - Core 5 Clock control/status register */ - u8 res6[0x1c]; - u32 clkc6csr; /* 0xe10c0 - Core 6 Clock control/status register */ - u8 res7[0x1c]; - u32 clkc7csr; /* 0xe10e0 - Core 7 Clock control/status register */ - u8 res8[0x71c]; - u32 pllc1gsr; /* 0xe1800 - Cluster PLL 1 General Status Register */ - u8 res10[0x1c]; - u32 pllc2gsr; /* 0xe1820 - Cluster PLL 2 General Status Register */ - u8 res11[0x1c]; - u32 pllc3gsr; /* 0xe1840 - Cluster PLL 3 General Status Register */ - u8 res12[0x1c]; - u32 pllc4gsr; /* 0xe1860 - Cluster PLL 4 General Status Register */ - u8 res13[0x39c]; - u32 pllpgsr; /* 0xe1c00 - Platform PLL General Status Register */ - u8 res14[0x1c]; - u32 plldgsr; /* 0xe1c20 - DDR PLL General Status Register */ - u8 res15[0x3dc]; + u32 clkc0csr; /* Core 0 Clock control/status */ + u8 res1[0x1c]; + u32 clkc1csr; /* Core 1 Clock control/status */ + u8 res2[0x1c]; + u32 clkc2csr; /* Core 2 Clock control/status */ + u8 res3[0x1c]; + u32 clkc3csr; /* Core 3 Clock control/status */ + u8 res4[0x1c]; + u32 clkc4csr; /* Core 4 Clock control/status */ + u8 res5[0x1c]; + u32 clkc5csr; /* Core 5 Clock control/status */ + u8 res6[0x1c]; + u32 clkc6csr; /* Core 6 Clock control/status */ + u8 res7[0x1c]; + u32 clkc7csr; /* Core 7 Clock control/status */ + u8 res8[0x71c]; + u32 pllc1gsr; /* Cluster PLL 1 General Status */ + u8 res10[0x1c]; + u32 pllc2gsr; /* Cluster PLL 2 General Status */ + u8 res11[0x1c]; + u32 pllc3gsr; /* Cluster PLL 3 General Status */ + u8 res12[0x1c]; + u32 pllc4gsr; /* Cluster PLL 4 General Status */ + u8 res13[0x39c]; + u32 pllpgsr; /* Platform PLL General Status */ + u8 res14[0x1c]; + u32 plldgsr; /* DDR PLL General Status */ + u8 res15[0x3dc]; } ccsr_clk_t; typedef struct ccsr_rcpm { - u8 res1[4]; /* 0xe2000 - Reserved */ - u32 cdozsrl; /* 0xe2004 - Core Doze Status Register */ - u8 res2[4]; /* 0xe2008 - Reserved */ - u32 cdozcrl; /* 0xe200c - Core Doze Control Register */ - u8 res3[4]; /* 0xe2010 - Reserved */ - u32 cnapsrl; /* 0xe2014 - Core Nap Status Register */ - u8 res4[4]; /* 0xe2018 - Reserved */ - u32 cnapcrl; /* 0xe201c - Core Nap Control Register */ - u8 res5[4]; /* 0xe2020 - Reserved */ - u32 cdozpsrl; /* 0xe2024 - Core Doze Previous Status Register */ - u8 res6[4]; /* 0xe2028 - Reserved */ - u32 cdozpcrl; /* 0xe202c - Core Doze Previous Control Register */ - u8 res7[4]; /* 0xe2030 - Reserved */ - u32 cwaitsrl; /* 0xe2034 - Core Wait Status Register */ - u8 res8[8]; /* Reserved */ - u32 powmgtcsr; /* 0xe2040 - Power Mangement Control & Status Register */ - u8 res9[12]; /* Reserved */ - u32 ippdexpcr0; /* 0xe2050 - IP Powerdown Exception Control Register 0 */ - u8 res10[12]; /* Reserved */ - u8 res11[4]; /* Reserved */ - u32 cpmimrl; /* 0xe2064 - Core Power Management Interrupt Masking Register */ - u8 res12[4]; /* Reserved */ - u32 cpmcimrl; /* 0xe206c - Core Power Management Critical Interrupt Masking Register */ - u8 res13[4]; /* Reserved */ - u32 cpmmcimrl; /* 0xe2074 - Core Power Management Machine Check Interrupt Masking Register */ - u8 res14[4]; /* Reserved */ - u32 cpmnmimrl; /* 0xe207c - Core Power Management NMI Masking Register */ - u8 res15[4]; /* Reserved */ - u32 ctbenrl; /* 0xe2084 - Core Time Base Enable Register */ - u8 res16[4]; /* Reserved */ - u32 ctbclkselrl; /* 0xe208c - Core Time Base Clock Select Register */ - u8 res17[4]; /* Reserved */ - u32 ctbhltcrl; /* 0xe2094 - Core Time Base Halt Control Register */ + u8 res1[4]; + u32 cdozsrl; /* Core Doze Status */ + u8 res2[4]; + u32 cdozcrl; /* Core Doze Control */ + u8 res3[4]; + u32 cnapsrl; /* Core Nap Status */ + u8 res4[4]; + u32 cnapcrl; /* Core Nap Control */ + u8 res5[4]; + u32 cdozpsrl; /* Core Doze Previous Status */ + u8 res6[4]; + u32 cdozpcrl; /* Core Doze Previous Control */ + u8 res7[4]; + u32 cwaitsrl; /* Core Wait Status */ + u8 res8[8]; + u32 powmgtcsr; /* Power Mangement Control & Status */ + u8 res9[12]; + u32 ippdexpcr0; /* IP Powerdown Exception Control 0 */ + u8 res10[12]; + u8 res11[4]; + u32 cpmimrl; /* Core PM IRQ Masking */ + u8 res12[4]; + u32 cpmcimrl; /* Core PM Critical IRQ Masking */ + u8 res13[4]; + u32 cpmmcimrl; /* Core PM Machine Check IRQ Masking */ + u8 res14[4]; + u32 cpmnmimrl; /* Core PM NMI Masking */ + u8 res15[4]; + u32 ctbenrl; /* Core Time Base Enable */ + u8 res16[4]; + u32 ctbclkselrl; /* Core Time Base Clock Select */ + u8 res17[4]; + u32 ctbhltcrl; /* Core Time Base Halt Control */ u8 res18[0xf68]; } ccsr_rcpm_t; #else typedef struct ccsr_gur { - uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ + u32 porpllsr; /* POR PLL ratio status */ #ifdef CONFIG_MPC8536 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 @@ -1767,17 +1745,17 @@ typedef struct ccsr_gur { #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000 #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25 #define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e -#define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1 - uint porbmsr; /* 0xe0004 - POR boot mode status register */ +#define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1 + u32 porbmsr; /* POR boot mode status */ #define MPC85xx_PORBMSR_HA 0x00070000 #define MPC85xx_PORBMSR_HA_SHIFT 16 - uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ - uint pordevsr; /* 0xe000c - POR I/O device status regsiter */ + u32 porimpscr; /* POR I/O impedance status & control */ + u32 pordevsr; /* POR I/O device status regsiter */ #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000 #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 -#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 +#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 #define MPC85xx_PORDEVSR_PCI1 0x00800000 #define MPC85xx_PORDEVSR_IO_SEL 0x00780000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 @@ -1789,36 +1767,32 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060 #define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008 #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 - uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ - uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */ + u32 pordbgmsr; /* POR debug mode status */ + u32 pordevsr2; /* POR I/O device status 2 */ /* The 8544 RM says this is bit 26, but it's really bit 24 */ #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 - char res1[8]; - uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ - char res2[12]; - uint gpiocr; /* 0xe0030 - GPIO control register */ - char res3[12]; + u8 res1[8]; + u32 gpporcr; /* General-purpose POR configuration */ + u8 res2[12]; + u32 gpiocr; /* GPIO control */ + u8 res3[12]; #if defined(CONFIG_MPC8569) - uint plppar1; - /* 0xe0040 - Platform port pin assignment register 1 */ - uint plppar2; - /* 0xe0044 - Platform port pin assignment register 2 */ - uint plpdir1; - /* 0xe0048 - Platform port pin direction register 1 */ - uint plpdir2; - /* 0xe004c - Platform port pin direction register 2 */ + u32 plppar1; /* Platform port pin assignment 1 */ + u32 plppar2; /* Platform port pin assignment 2 */ + u32 plpdir1; /* Platform port pin direction 1 */ + u32 plpdir2; /* Platform port pin direction 2 */ #else - uint gpoutdr; /* 0xe0040 - General-purpose output data register */ - char res4[12]; + u32 gpoutdr; /* General-purpose output data */ + u8 res4[12]; #endif - uint gpindr; /* 0xe0050 - General-purpose input data register */ - char res5[12]; - uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ + u32 gpindr; /* General-purpose input data */ + u8 res5[12]; + u32 pmuxcr; /* Alt. function signal multiplex control */ #define MPC85xx_PMUXCR_SD_DATA 0x80000000 #define MPC85xx_PMUXCR_SDHC_CD 0x40000000 #define MPC85xx_PMUXCR_SDHC_WP 0x20000000 - char res6[12]; - uint devdisr; /* 0xe0070 - Device disable control */ + u8 res6[12]; + u32 devdisr; /* Device disable control */ #define MPC85xx_DEVDISR_PCI1 0x80000000 #define MPC85xx_DEVDISR_PCI2 0x40000000 #define MPC85xx_DEVDISR_PCIE 0x20000000 @@ -1842,34 +1816,34 @@ typedef struct ccsr_gur { #define MPC85xx_DEVDISR_TSEC4 0x00000010 #define MPC85xx_DEVDISR_I2C 0x00000004 #define MPC85xx_DEVDISR_DUART 0x00000002 - char res7[12]; - uint powmgtcsr; /* 0xe0080 - Power management status and control register */ - char res8[12]; - uint mcpsumr; /* 0xe0090 - Machine check summary register */ - char res9[12]; - uint pvr; /* 0xe00a0 - Processor version register */ - uint svr; /* 0xe00a4 - System version register */ - char res10a[8]; - uint rstcr; /* 0xe00b0 - Reset control register */ + u8 res7[12]; + u32 powmgtcsr; /* Power management status & control */ + u8 res8[12]; + u32 mcpsumr; /* Machine check summary */ + u8 res9[12]; + u32 pvr; /* Processor version */ + u32 svr; /* System version */ + u8 res10a[8]; + u32 rstcr; /* Reset control */ #if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569) - char res10b[76]; - par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */ - char res10c[3136]; + u8 res10b[76]; + par_io_t qe_par_io[7]; + u8 res10c[3136]; #else - char res10b[3404]; + u8 res10b[3404]; #endif - uint clkocr; /* 0xe0e00 - Clock out select register */ - char res11[12]; - uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */ - char res12[12]; - uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */ - char res13[248]; - uint lbiuiplldcr0; /* 0xe0f1c -- LBIU PLL Debug Reg 0 */ - uint lbiuiplldcr1; /* 0xe0f20 -- LBIU PLL Debug Reg 1 */ - uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */ - uint tsec12ioovcr; /* 0xe0f28 - eTSEC 1/2 IO override control */ - uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */ - char res15[61648]; /* 0xe0f30 to 0xefffff */ + u32 clkocr; /* Clock out select */ + u8 res11[12]; + u32 ddrdllcr; /* DDR DLL control */ + u8 res12[12]; + u32 lbcdllcr; /* LBC DLL control */ + u8 res13[248]; + u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */ + u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */ + u32 ddrioovcr; /* DDR IO Override Control */ + u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */ + u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */ + u8 res15[61648]; } ccsr_gur_t; #endif @@ -1884,8 +1858,8 @@ typedef struct ccsr_gur { #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 -#define CONFIG_SYS_MPC85xx_QMAN_OFFSET 0x318000 -#define CONFIG_SYS_MPC85xx_BMAN_OFFSET 0x31a000 +#define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000 +#define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000 #else #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000 @@ -1899,6 +1873,7 @@ typedef struct ccsr_gur { #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000 #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 +#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 @@ -1908,31 +1883,53 @@ typedef struct ccsr_gur { #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 -#define CONFIG_SYS_MPC85xx_QMAN_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_QMAN_OFFSET) -#define CONFIG_SYS_MPC85xx_BMAN_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_BMAN_OFFSET) -#define CONFIG_SYS_MPC85xx_GUTS_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) -#define CONFIG_SYS_FSL_CORENET_CCM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET) -#define CONFIG_SYS_FSL_CORENET_CLK_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET) -#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET) -#define CONFIG_SYS_MPC85xx_ECM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) -#define CONFIG_SYS_MPC85xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET) -#define CONFIG_SYS_MPC85xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) -#define CONFIG_SYS_MPC85xx_LBC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) -#define CONFIG_SYS_MPC85xx_ESPI_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) -#define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) -#define CONFIG_SYS_MPC85xx_PCIX2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) -#define CONFIG_SYS_MPC85xx_GPIO_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET) -#define CONFIG_SYS_MPC85xx_SATA1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) -#define CONFIG_SYS_MPC85xx_SATA2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET) -#define CONFIG_SYS_MPC85xx_L2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET) -#define CONFIG_SYS_MPC85xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) -#define CONFIG_SYS_MPC85xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) -#define CONFIG_SYS_MPC85xx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) -#define CONFIG_SYS_MPC85xx_CPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) -#define CONFIG_SYS_MPC85xx_SERDES1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) -#define CONFIG_SYS_MPC85xx_SERDES2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) -#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000 +#define CONFIG_SYS_FSL_CORENET_QMAN_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET) +#define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET) +#define CONFIG_SYS_MPC85xx_GUTS_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) +#define CONFIG_SYS_FSL_CORENET_CCM_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET) +#define CONFIG_SYS_FSL_CORENET_CLK_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET) +#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET) +#define CONFIG_SYS_MPC85xx_ECM_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) +#define CONFIG_SYS_MPC85xx_DDR_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET) +#define CONFIG_SYS_MPC85xx_DDR2_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) +#define CONFIG_SYS_MPC85xx_LBC_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) +#define CONFIG_SYS_MPC85xx_ESPI_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) +#define CONFIG_SYS_MPC85xx_PCIX_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) +#define CONFIG_SYS_MPC85xx_PCIX2_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) +#define CONFIG_SYS_MPC85xx_GPIO_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET) +#define CONFIG_SYS_MPC85xx_SATA1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) +#define CONFIG_SYS_MPC85xx_SATA2_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET) +#define CONFIG_SYS_MPC85xx_L2_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET) +#define CONFIG_SYS_MPC85xx_DMA_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) +#define CONFIG_SYS_MPC85xx_ESDHC_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) +#define CONFIG_SYS_MPC85xx_PIC_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) +#define CONFIG_SYS_MPC85xx_CPM_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) +#define CONFIG_SYS_MPC85xx_SERDES1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) +#define CONFIG_SYS_MPC85xx_SERDES2_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) #define CONFIG_SYS_MPC85xx_USB_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) #endif /*__IMMAP_85xx__*/ From dd9ca98f2600000e5c2744735040100b770650e7 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 25 Sep 2009 11:14:11 -0400 Subject: [PATCH 203/208] sbc8548: reclaim wasted sector in boot flash By nature of being based off the MPC8548CDS board, this board inherited an ENV_SIZE setting of 256k. But since it has a smaller flash device (8MB soldered on), it has a native sector size of 128k, and hence the ENV_SIZE was causing 2 sectors to be used for the environment. By removing the unused sector, we can push TEXT_BASE up closer to the end of address space and reclaim that sector for any other application. This also fixes the mismatch between TEXT_BASE and MONITOR_LEN reported by Kumar earlier. Since this board also supports the ability to boot off the 64MB SODIMM flash, this change is forward looking with that in mind; i.e. the settings for MONITOR_LEN and ENV_SIZE will work when the 512k sectors of the SODIMM flash are used for alternate boot in the future. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/config.mk | 2 +- doc/README.sbc8548 | 24 ++++++++++++++++++++++++ include/configs/sbc8548.h | 20 +++++++++++++++++--- 3 files changed, 42 insertions(+), 4 deletions(-) diff --git a/board/sbc8548/config.mk b/board/sbc8548/config.mk index 440d6502ab1..b2013d66791 100644 --- a/board/sbc8548/config.mk +++ b/board/sbc8548/config.mk @@ -24,5 +24,5 @@ # sbc8548 board # ifndef TEXT_BASE -TEXT_BASE = 0xfff80000 +TEXT_BASE = 0xfffa0000 endif diff --git a/doc/README.sbc8548 b/doc/README.sbc8548 index d72d97d027e..6cbe12f1f58 100644 --- a/doc/README.sbc8548 +++ b/doc/README.sbc8548 @@ -63,6 +63,30 @@ a 33MHz PCI configuration is currently untested.) => +Updating U-boot with U-boot: +============================ + +Note that versions of u-boot up to and including 2009.08 had u-boot stored +at 0xfff8_0000 -> 0xffff_ffff (512k). Currently it is being stored from +0xfffa_0000 -> 0xffff_ffff (384k). If you use an old macro/script to +update u-boot with u-boot and it uses the old address, you will render +your board inoperable, and you will require JTAG recovery. + +The following steps list how to update with the current address: + + tftp u-boot.bin + md 200000 10 + protect off all + erase fffa0000 ffffffff + cp.b 200000 fffa0000 60000 + md fffa0000 10 + protect on all + +The "md" steps in the above are just a precautionary step that allow +you to confirm the u-boot version that was downloaded, and then confirm +that it was copied to flash. + + Hardware Reference: =================== diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index d10792a22da..aeac2dea3e4 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -330,7 +330,14 @@ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +/* + * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and + * one for env+bootpg (TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM + * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg + * (TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right + * thing for MONITOR_LEN in both cases. + */ +#define CONFIG_SYS_MONITOR_LEN (~TEXT_BASE + 1) #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ @@ -448,9 +455,16 @@ * Environment */ #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ #define CONFIG_ENV_SIZE 0x2000 +#if TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000) +#define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */ +#elif TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#else +#warning undefined environment size/location. +#endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ From 07355700523203c5f72018712cf0d93683f255c8 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Wed, 23 Sep 2009 15:19:32 +0800 Subject: [PATCH 204/208] mpc8536: fix board config file line length Signed-off-by: Mingkai Hu Signed-off-by: Kumar Gala --- include/configs/MPC8536DS.h | 141 +++++++++++++++++++----------------- 1 file changed, 76 insertions(+), 65 deletions(-) diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index faca8059a1f..9d45648605b 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -86,8 +86,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ #endif -#define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ -#define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ +#define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ +#define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* @@ -97,16 +97,16 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ +#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ #else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR #endif -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000) +#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) +#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000) /* DDR Setup */ #define CONFIG_VERY_BIG_RAM @@ -131,9 +131,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_SPD_BUS_NUM 1 /* These are used when DDR doesn't use SPD. */ -#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ +#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ #define CONFIG_SYS_DDR_TIMING_3 0x00000000 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 @@ -145,7 +145,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ +#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ #define CONFIG_SYS_DDR_CONTROL2 0x04400010 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d @@ -190,21 +190,26 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE #endif -#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) +#define CONFIG_SYS_BR0_PRELIM \ + (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ + | BR_PS_16 | BR_V) #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 -#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) +#define CONFIG_SYS_BR1_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ + | BR_PS_16 | BR_V) #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ + CONFIG_SYS_FLASH_BASE_PHYS } #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ #undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ @@ -224,7 +229,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #endif #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ +#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ #define PIXIS_ID 0x0 /* Board ID at offset 0 */ #define PIXIS_VER 0x1 /* Board version at offset 1 */ @@ -270,11 +275,12 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ #define CONFIG_SYS_NAND_BASE 0xffa00000 #ifdef CONFIG_PHYS_64BIT @@ -293,42 +299,46 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) /* NAND flash config */ -#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | (2< " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) @@ -625,9 +635,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #else #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* @@ -635,7 +646,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * have to be in the first 16 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ /* * Internal Definitions @@ -671,7 +682,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_HOSTNAME unknown #define CONFIG_ROOTPATH /opt/nfsroot #define CONFIG_BOOTFILE uImage -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ #define CONFIG_SERVERIP 192.168.1.1 #define CONFIG_GATEWAYIP 192.168.1.1 From 9a1a0aedbbd56f901bfbc124f18ec6d9dcefe282 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Wed, 23 Sep 2009 15:20:37 +0800 Subject: [PATCH 205/208] NAND boot: MPC8536DS support MPC8536E can support booting from NAND flash which uses the image u-boot-nand.bin. This image contains two parts: a 4K NAND loader and a main U-Boot image. The former is appended to the latter to produce u-boot-nand.bin. The 4K NAND loader includes the corresponding nand_spl directory, along with the code twisted by CONFIG_NAND_SPL. The main U-Boot image just like a general U-Boot image except the parts that included by CONFIG_SYS_RAMBOOT. When power on, eLBC will automatically load from bank 0 the 4K NAND loader into the FCM buffer RAM where CPU can execute the boot code directly. In the first stage, the NAND loader copies itself to RAM or L2SRAM to free up the FCM buffer RAM, then loads the main image from NAND flash to RAM or L2SRAM and boot from it. This patch implements the NAND loader to load the main image into L2SRAM, so the main image can configure the RAM by using SPD EEPROM. In the first stage, the NAND loader copies itself to the second to last 4K address space, and uses the last 4K address space as the initial RAM for stack. Obviously, the size of L2SRAM shouldn't be less than the size of the image used. If so, the workaround is to generate another image that includes the code to configure the RAM by SPD and load it to L2SRAM first, then relocate the main image to RAM to boot up. Signed-off-by: Mingkai Hu Signed-off-by: Kumar Gala --- MAKEALL | 1 + Makefile | 1 + board/freescale/mpc8536ds/config.mk | 7 + board/freescale/mpc8536ds/tlb.c | 11 ++ include/configs/MPC8536DS.h | 97 ++++++++++--- nand_spl/board/freescale/mpc8536ds/Makefile | 127 ++++++++++++++++++ .../board/freescale/mpc8536ds/nand_boot.c | 83 ++++++++++++ 7 files changed, 308 insertions(+), 19 deletions(-) create mode 100644 nand_spl/board/freescale/mpc8536ds/Makefile create mode 100644 nand_spl/board/freescale/mpc8536ds/nand_boot.c diff --git a/MAKEALL b/MAKEALL index 776f9688108..0249058bfcd 100755 --- a/MAKEALL +++ b/MAKEALL @@ -387,6 +387,7 @@ LIST_83xx=" \ LIST_85xx=" \ ATUM8548 \ MPC8536DS \ + MPC8536DS_NAND \ MPC8540ADS \ MPC8540EVAL \ MPC8541CDS \ diff --git a/Makefile b/Makefile index 9c5b2a5c9a3..781db22aaec 100644 --- a/Makefile +++ b/Makefile @@ -2446,6 +2446,7 @@ vme8349_config: unconfig ATUM8548_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548 +MPC8536DS_NAND_config \ MPC8536DS_36BIT_config \ MPC8536DS_config: unconfig @$(MKCONFIG) -t $(@:_config=) MPC8536DS ppc mpc85xx mpc8536ds freescale diff --git a/board/freescale/mpc8536ds/config.mk b/board/freescale/mpc8536ds/config.mk index c1d0525678e..d6490b59ca3 100644 --- a/board/freescale/mpc8536ds/config.mk +++ b/board/freescale/mpc8536ds/config.mk @@ -23,6 +23,13 @@ # # mpc8536ds board # +ifndef NAND_SPL +ifeq ($(CONFIG_MK_NAND), y) +TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds +endif +endif + ifndef TEXT_BASE TEXT_BASE = 0xeff80000 endif diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c index 35a13d44996..dc52d7f9d44 100644 --- a/board/freescale/mpc8536ds/tlb.c +++ b/board/freescale/mpc8536ds/tlb.c @@ -71,6 +71,17 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_1M, 1), + +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + /* *I*G - L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256K, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 9d45648605b..af369867b95 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -31,6 +31,12 @@ #define CONFIG_PHYS_64BIT 1 #endif +#ifdef CONFIG_MK_NAND +#define CONFIG_NAND_U_BOOT 1 +#define CONFIG_RAMBOOT_NAND 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000 +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ @@ -90,11 +96,22 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ #define CONFIG_PANIC_HANG /* do not reset board on panic */ +/* + * Config the L2 Cache as L2 SRAM + */ +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull +#else +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#endif +#define CONFIG_SYS_L2_SIZE (512 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) + /* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ @@ -103,6 +120,12 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #endif #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) +#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR +#else +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#endif + #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) @@ -190,10 +213,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE #endif -#define CONFIG_SYS_BR0_PRELIM \ +#define CONFIG_FLASH_BR_PRELIM \ (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 +#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 #define CONFIG_SYS_BR1_PRELIM \ (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ @@ -213,6 +236,12 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO @@ -265,6 +294,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define PIXIS_VWATCH 0x24 /* Watchdog Register */ #define PIXIS_LED 0x25 /* LED Register */ +#define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ + /* old pixis referenced names */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ @@ -282,12 +313,21 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ +#ifndef CONFIG_NAND_SPL #define CONFIG_SYS_NAND_BASE 0xffa00000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull #else #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #endif +#else +#define CONFIG_SYS_NAND_BASE 0xfff00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif +#endif #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ CONFIG_SYS_NAND_BASE + 0x40000, \ CONFIG_SYS_NAND_BASE + 0x80000, \ @@ -298,6 +338,16 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +/* NAND boot: 4K NAND loader config */ +#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) +#define CONFIG_SYS_NAND_U_BOOT_START \ + (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) +#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) + /* NAND flash config */ #define CONFIG_NAND_BR_PRELIM \ (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ @@ -314,8 +364,17 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); | OR_FCM_TRLX \ | OR_FCM_EHTR) +#ifdef CONFIG_RAMBOOT_NAND +#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ +#else +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#endif #define CONFIG_SYS_BR4_PRELIM \ (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \ @@ -536,15 +595,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_CMD_EXT2 #endif -/* - * USB - */ -#define CONFIG_CMD_USB -#define CONFIG_USB_STORAGE -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI @@ -579,14 +629,23 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* * Environment */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) + +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE + #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#endif +#else + #define CONFIG_ENV_IS_IN_FLASH 1 + #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 + #define CONFIG_ENV_ADDR 0xfff80000 + #else + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) + #endif + #define CONFIG_ENV_SIZE 0x2000 + #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ diff --git a/nand_spl/board/freescale/mpc8536ds/Makefile b/nand_spl/board/freescale/mpc8536ds/Makefile new file mode 100644 index 00000000000..1d5e3198358 --- /dev/null +++ b/nand_spl/board/freescale/mpc8536ds/Makefile @@ -0,0 +1,127 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# Copyright 2009 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +NAND_SPL := y +TEXT_BASE := 0xfff00000 +PAD_TO := 0xfff01000 + +include $(TOPDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/cpu/$(CPU)/u-boot-nand_spl.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = start.o resetvec.o +COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ + nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +# create symbolic links for common files + +$(obj)cache.c: + @rm -f $(obj)cache.c + ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c + +$(obj)cpu_init_early.c: + @rm -f $(obj)cpu_init_early.c + ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c + +$(obj)cpu_init_nand.c: + @rm -f $(obj)cpu_init_nand.c + ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c + +$(obj)fsl_law.c: + @rm -f $(obj)fsl_law.c + ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c + +$(obj)law.c: + @rm -f $(obj)law.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c + +$(obj)nand_boot_fsl_elbc.c: + @rm -f $(obj)nand_boot_fsl_elbc.c + ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ + $(obj)nand_boot_fsl_elbc.c + +$(obj)ns16550.c: + @rm -f $(obj)ns16550.c + ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c + +$(obj)resetvec.S: + @rm -f $(obj)resetvec.S + ln -s $(SRCTREE)/cpu/$(CPU)/resetvec.S $(obj)resetvec.S + +$(obj)fixed_ivor.S: + @rm -f $(obj)fixed_ivor.S + ln -sf $(SRCTREE)/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S + +$(obj)start.S: $(obj)fixed_ivor.S + @rm -f $(obj)start.S + ln -sf $(SRCTREE)/cpu/mpc85xx/start.S $(obj)start.S + +$(obj)tlb.c: + @rm -f $(obj)tlb.c + ln -sf $(SRCTREE)/cpu/mpc85xx/tlb.c $(obj)tlb.c + +$(obj)tlb_table.c: + @rm -f $(obj)tlb_table.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/freescale/mpc8536ds/nand_boot.c b/nand_spl/board/freescale/mpc8536ds/nand_boot.c new file mode 100644 index 00000000000..af29dc278fb --- /dev/null +++ b/nand_spl/board/freescale/mpc8536ds/nand_boot.c @@ -0,0 +1,83 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include + +u32 sysclk_tbl[] = { + 33333000, 39999600, 49999500, 66666000, + 83332500, 99999000, 133332000, 166665000 +}; + +void board_init_f(ulong bootflag) +{ + int px_spd; + u32 plat_ratio, bus_clk, sys_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + ccsr_lbc_t *lbc = (void *)CONFIG_SYS_MPC85xx_LBC_ADDR; + +#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) + /* for FPGA */ + out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM); + out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM); +#else +#error CONFIG_SYS_BR3_PRELIM, CONFIG_SYS_OR3_PRELIM must be defined +#endif + + /* initialize selected port with appropriate baud rate */ + px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD)); + sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK]; + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + bus_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + bus_clk / 16 / CONFIG_BAUDRATE); + + puts("\nNAND boot... "); + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, + CONFIG_SYS_NAND_U_BOOT_RELOC); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} + +void putc(char c) +{ + if (c == '\n') + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); + + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} From e40ac4870c6e72302044e98338322f45c34435bd Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Wed, 23 Sep 2009 15:20:38 +0800 Subject: [PATCH 206/208] On-chip ROM boot: MPC8536DS support The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC and boot from eSPI. When power on, the porcessor excutes the ROM code to initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from the memory device that interfaced to the controller, such as the SDCard or SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it. The memory device should contain a specific data structure with control word and config word at the fixed address. The config word direct the process how to config the memory device, and the control word direct the processor where to find the image on the memory device, or where copy the main image to. The user can use any method to store the data structure to the memory device, only if store it on the assigned address. The on-chip ROM code will map the whole 4GB address space by setting entry0 in the TLB1, so the main image need to switch to Address space 1 to disable this mapping and map the address space again. This patch implements loading the mian U-Boot image into L2SRAM, so the image can configure the system memory by using SPD EEPROM. Signed-off-by: Mingkai Hu Signed-off-by: Kumar Gala --- MAKEALL | 2 ++ Makefile | 2 ++ board/freescale/mpc8536ds/config.mk | 12 ++++++++++++ include/configs/MPC8536DS.h | 17 ++++++++++++++++- 4 files changed, 32 insertions(+), 1 deletion(-) diff --git a/MAKEALL b/MAKEALL index 0249058bfcd..8ff6987a2c1 100755 --- a/MAKEALL +++ b/MAKEALL @@ -388,6 +388,8 @@ LIST_85xx=" \ ATUM8548 \ MPC8536DS \ MPC8536DS_NAND \ + MPC8536DS_SDCARD \ + MPC8536DS_SPIFLASH \ MPC8540ADS \ MPC8540EVAL \ MPC8541CDS \ diff --git a/Makefile b/Makefile index 781db22aaec..c8a883cf086 100644 --- a/Makefile +++ b/Makefile @@ -2447,6 +2447,8 @@ ATUM8548_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548 MPC8536DS_NAND_config \ +MPC8536DS_SDCARD_config \ +MPC8536DS_SPIFLASH_config \ MPC8536DS_36BIT_config \ MPC8536DS_config: unconfig @$(MKCONFIG) -t $(@:_config=) MPC8536DS ppc mpc85xx mpc8536ds freescale diff --git a/board/freescale/mpc8536ds/config.mk b/board/freescale/mpc8536ds/config.mk index d6490b59ca3..e38af731bed 100644 --- a/board/freescale/mpc8536ds/config.mk +++ b/board/freescale/mpc8536ds/config.mk @@ -30,8 +30,20 @@ LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds endif endif +ifeq ($(CONFIG_MK_SDCARD), y) +TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +RESET_VECTOR_ADDRESS = 0xf8fffffc +endif + +ifeq ($(CONFIG_MK_SPIFLASH), y) +TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +RESET_VECTOR_ADDRESS = 0xf8fffffc +endif + ifndef TEXT_BASE TEXT_BASE = 0xeff80000 endif +ifndef RESET_VECTOR_ADDRESS RESET_VECTOR_ADDRESS = 0xeffffffc +endif diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index af369867b95..a8472754622 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -37,6 +37,16 @@ #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000 #endif +#ifdef CONFIG_MK_SDCARD +#define CONFIG_RAMBOOT_SDCARD 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000 +#endif + +#ifdef CONFIG_MK_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000 +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ @@ -236,7 +246,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ -#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) +#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \ + || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) #define CONFIG_SYS_RAMBOOT #else #undef CONFIG_SYS_RAMBOOT @@ -635,6 +646,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) + #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) + #define CONFIG_ENV_SIZE 0x2000 #endif #else #define CONFIG_ENV_IS_IN_FLASH 1 From 693a048d8ac191181f5b9adbff642d3f1bbd479f Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Wed, 23 Sep 2009 15:20:39 +0800 Subject: [PATCH 207/208] Add README.mpc8536ds Add boot from NAND/eSDHC/eSPI description Signed-off-by: Mingkai Hu Signed-off-by: Kumar Gala --- doc/README.mpc8536ds | 127 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 127 insertions(+) create mode 100644 doc/README.mpc8536ds diff --git a/doc/README.mpc8536ds b/doc/README.mpc8536ds new file mode 100644 index 00000000000..4d0bee042f1 --- /dev/null +++ b/doc/README.mpc8536ds @@ -0,0 +1,127 @@ +Overview: +========= + +The MPC8536E integrates a PowerPC processor core with system logic +required for imaging, networking, and communications applications. + +Boot from NAND: +=============== + +The MPC8536E is capable of booting from NAND flash which uses the image +u-boot-nand.bin. This image contains two parts: a first stage image(also +call 4K NAND loader and a second stage image. The former is appended to +the latter to produce u-boot-nand.bin. + +The bootup process can be divided into two stages: the first stage will +configure the L2SRAM, then copy the second stage image to L2SRAM and jump +to it. The second stage image is to configure all the hardware and boot up +to U-Boot command line. + +The 4K NAND loader's code comes from the corresponding nand_spl directory, +along with the code twisted by CONFIG_NAND_SPL. The macro CONFIG_NAND_SPL +is mainly used to shrink the code size to the 4K size limitation. + +The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the +second stage image. It's set in the board config file when boot from NAND +is selected. + +Build and boot steps +-------------------- + +1. Building image + make MPC8536DS_NAND_config + make CROSS_COMPILE=powerpc-none-linux-gnuspe- all + +2. Change dip-switch + SW2[5-8] = 1011 + SW9[1-3] = 101 + Note: 1 stands for 'on', 0 stands for 'off' + +3. Flash image + tftp 1000000 u-boot-nand.bin + nand erase 0 a0000 + nand write 1000000 0 a0000 + +Boot from On-chip ROM: +====================== + +The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC +and boot from eSPI. When power on, the porcessor excutes the ROM code to +initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from +the memory device that interfaced to the controller, such as the SDCard or +SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it. + +The memory device should contain a specific data structure with control word +and config word at the fixed address. The config word direct the process how +to config the memory device, and the control word direct the processor where +to find the image on the memory device, or where copy the main image to. The +user can use any method to store the data structure to the memory device, only +if store it on the assigned address. + +Build and boot steps +-------------------- + +For boot from eSDHC: +1. Build image + make MPC8536DS_SDCARD_config + make CROSS_COMPILE=powerpc-none-linux-gnuspe- all + +2. Change dip-switch + SW2[5-8] = 0111 + SW3[1] = 0 + SW8[7] = 0 - The on-board SD/MMC slot is active + SW8[7] = 1 - The externel SD/MMC slot is active + +3. Put image to SDCard + Put the follwing info at the assigned address on the SDCard: + + Offset | Data | Description + -------------------------------------------------------- + | 0x40-0x43 | 0x424F4F54 | BOOT signature | + -------------------------------------------------------- + | 0x48-0x4B | 0x00080000 | u-boot.bin's size | + -------------------------------------------------------- + | 0x50-0x53 | 0x???????? | u-boot.bin's Addr on SDCard | + -------------------------------------------------------- + | 0x58-0x5B | 0xF8F80000 | Target Address | + ------------------------------------------------------- + | 0x60-0x63 | 0xF8FFF000 | Execution Starting Address | + -------------------------------------------------------- + | 0x68-0x6B | 0x6 | Number of Config Addr/Data | + -------------------------------------------------------- + | 0x80-0x83 | 0xFF720100 | Config Addr 1 | + | 0x84-0x87 | 0xF8F80000 | Config Data 1 | + -------------------------------------------------------- + | 0x88-0x8b | 0xFF720e44 | Config Addr 2 | + | 0x8c-0x8f | 0x0000000C | Config Data 2 | + -------------------------------------------------------- + | 0x90-0x93 | 0xFF720000 | Config Addr 3 | + | 0x94-0x97 | 0x80010000 | Config Data 3 | + -------------------------------------------------------- + | 0x98-0x9b | 0xFF72e40e | Config Addr 4 | + | 0x9c-0x9f | 0x00000040 | Config Data 4 | + -------------------------------------------------------- + | 0xa0-0xa3 | 0x40000001 | Config Addr 5 | + | 0xa4-0xa7 | 0x00000100 | Config Data 5 | + -------------------------------------------------------- + | 0xa8-0xab | 0x80000001 | Config Addr 6 | + | 0xac-0xaf | 0x80000001 | Config Data 6 | + -------------------------------------------------------- + | ...... | + -------------------------------------------------------- + | 0x???????? | u-boot.bin | + -------------------------------------------------------- + + then insert the SDCard to the active slot to boot up. + +For boot from eSPI: +1. Build image + make MPC8536DS_SPIFLASH_config + make CROSS_COMPILE=powerpc-none-linux-gnuspe- all + +2. Change dip-switch + SW2[5-8] = 0110 + +3. Put image to SPI flash + Put the info in the above table onto the SPI flash, then + boot up. From 24b17d8a3c3a4b9ceaf6363ebe0021011b0b8bd8 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 30 Sep 2009 08:39:44 -0500 Subject: [PATCH 208/208] ppc/85xx: get_law_entry isn't used in CONFIG_NAND_SPL Don't include get_law_entry as part of the NAND_SPL build since the code isnt used. Signed-off-by: Kumar Gala --- drivers/misc/fsl_law.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index 425eb181bf0..287e5559005 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -79,6 +79,7 @@ void disable_law(u8 idx) return; } +#ifndef CONFIG_NAND_SPL static int get_law_entry(u8 i, struct law_entry *e) { volatile ccsr_local_t *ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); @@ -96,6 +97,7 @@ static int get_law_entry(u8 i, struct law_entry *e) return 1; } +#endif #else void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { @@ -130,6 +132,7 @@ void disable_law(u8 idx) return; } +#ifndef CONFIG_NAND_SPL static int get_law_entry(u8 i, struct law_entry *e) { volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08); @@ -149,6 +152,7 @@ static int get_law_entry(u8 i, struct law_entry *e) return 1; } #endif +#endif int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) {