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arm: dts: am625_sk: Switch to OF_UPSTREAM
Enable OF_UPSTREAM for am625-sk board. Remove DT files that are now available in dts/upstream. Update the appended files based on version of latest OF_UPSTREAM sync point (v6.10-rc1). Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Dhruva Gole <d-gole@ti.com>
This commit is contained in:
Nishanth Menon
Tom Rini
parent
e9bffedf3a
commit
4d0adab959
@ -1198,8 +1198,7 @@ dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-r5-evm.dtb \
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k3-am642-r5-sk.dtb \
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k3-am642-r5-phycore-som-2gb.dtb
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dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
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k3-am625-r5-sk.dtb \
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dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-r5-sk.dtb \
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k3-am625-r5-beagleplay.dtb \
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k3-am625-verdin-r5.dtb \
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k3-am625-r5-phycore-som-2gb.dtb
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File diff suppressed because it is too large
Load Diff
@ -1,176 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/*
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* Device Tree Source for AM625 SoC Family MCU Domain peripherals
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*
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* Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_mcu {
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mcu_pmx0: pinctrl@4084000 {
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bootph-all;
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compatible = "pinctrl-single";
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reg = <0x00 0x04084000 0x00 0x88>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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mcu_esm: esm@4100000 {
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bootph-pre-ram;
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compatible = "ti,j721e-esm";
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reg = <0x00 0x4100000 0x00 0x1000>;
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ti,esm-pins = <0>, <1>, <2>, <85>;
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};
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/*
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* The MCU domain timer interrupts are routed only to the ESM module,
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* and not currently available for Linux. The MCU domain timers are
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* of limited use without interrupts, and likely reserved by the ESM.
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*/
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mcu_timer0: timer@4800000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x4800000 0x00 0x400>;
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clocks = <&k3_clks 35 2>;
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clock-names = "fck";
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power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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status = "reserved";
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};
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mcu_timer1: timer@4810000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x4810000 0x00 0x400>;
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clocks = <&k3_clks 48 2>;
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clock-names = "fck";
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power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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status = "reserved";
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};
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mcu_timer2: timer@4820000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x4820000 0x00 0x400>;
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clocks = <&k3_clks 49 2>;
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clock-names = "fck";
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power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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status = "reserved";
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};
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mcu_timer3: timer@4830000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x4830000 0x00 0x400>;
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clocks = <&k3_clks 50 2>;
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clock-names = "fck";
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power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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status = "reserved";
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};
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mcu_uart0: serial@4a00000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x04a00000 0x00 0x100>;
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interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 149 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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mcu_i2c0: i2c@4900000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x00 0x04900000 0x00 0x100>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 106 2>;
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clock-names = "fck";
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status = "disabled";
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};
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mcu_spi0: spi@4b00000 {
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compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
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reg = <0x00 0x04b00000 0x00 0x400>;
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 147 0>;
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status = "disabled";
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};
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mcu_spi1: spi@4b10000 {
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compatible = "ti,am654-mcspi","ti,omap4-mcspi";
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reg = <0x00 0x04b10000 0x00 0x400>;
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interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 148 0>;
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status = "disabled";
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};
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mcu_gpio_intr: interrupt-controller@4210000 {
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compatible = "ti,sci-intr";
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reg = <0x00 0x04210000 0x00 0x200>;
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ti,intr-trigger-type = <1>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
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#interrupt-cells = <1>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <5>;
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ti,interrupt-ranges = <0 104 4>;
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};
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mcu_gpio0: gpio@4201000 {
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compatible = "ti,am64-gpio", "ti,keystone-gpio";
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reg = <0x00 0x4201000 0x00 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&mcu_gpio_intr>;
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interrupts = <30>, <31>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <24>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 79 0>;
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clock-names = "gpio";
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};
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mcu_rti0: watchdog@4880000 {
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compatible = "ti,j7-rti-wdt";
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reg = <0x00 0x04880000 0x00 0x100>;
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clocks = <&k3_clks 131 0>;
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power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>;
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assigned-clocks = <&k3_clks 131 0>;
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assigned-clock-parents = <&k3_clks 131 2>;
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/* Tightly coupled to M4F */
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status = "reserved";
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};
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mcu_mcan0: can@4e08000 {
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compatible = "bosch,m_can";
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reg = <0x00 0x4e08000 0x00 0x200>,
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<0x00 0x4e00000 0x00 0x8000>;
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reg-names = "m_can", "message_ram";
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power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 188 6>, <&k3_clks 188 1>;
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clock-names = "hclk", "cclk";
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bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
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status = "disabled";
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};
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mcu_mcan1: can@4e18000 {
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compatible = "bosch,m_can";
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reg = <0x00 0x4e18000 0x00 0x200>,
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<0x00 0x4e10000 0x00 0x8000>;
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reg-names = "m_can", "message_ram";
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power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 189 6>, <&k3_clks 189 1>;
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clock-names = "hclk", "cclk";
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bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
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status = "disabled";
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};
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};
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@ -1,36 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/*
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* Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <dt-bindings/thermal/thermal.h>
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thermal_zones: thermal-zones {
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main0_thermal: main0-thermal {
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polling-delay-passive = <250>; /* milliSeconds */
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polling-delay = <500>; /* milliSeconds */
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thermal-sensors = <&wkup_vtm0 0>;
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trips {
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main0_crit: main0-crit {
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temperature = <105000>; /* milliCelsius */
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hysteresis = <2000>; /* milliCelsius */
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type = "critical";
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};
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};
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};
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main1_thermal: main1-thermal {
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polling-delay-passive = <250>; /* milliSeconds */
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polling-delay = <500>; /* milliSeconds */
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thermal-sensors = <&wkup_vtm0 1>;
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trips {
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main1_crit: main1-crit {
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temperature = <105000>; /* milliCelsius */
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hysteresis = <2000>; /* milliCelsius */
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type = "critical";
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};
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};
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};
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};
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@ -1,96 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/*
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* Device Tree Source for AM625 SoC Family Wakeup Domain peripherals
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*
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* Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <dt-bindings/bus/ti-sysc.h>
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&cbass_wakeup {
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wkup_conf: syscon@43000000 {
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bootph-all;
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compatible = "syscon", "simple-mfd";
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reg = <0x00 0x43000000 0x00 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x00 0x43000000 0x20000>;
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chipid: chipid@14 {
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bootph-all;
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compatible = "ti,am654-chipid";
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reg = <0x14 0x4>;
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};
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};
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target-module@2b300050 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x00 0x2b300050 0x00 0x4>,
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<0x00 0x2b300054 0x00 0x4>,
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<0x00 0x2b300058 0x00 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
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SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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ti,syss-mask = <1>;
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ti,no-reset-on-init;
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power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 114 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x00 0x2b300000 0x100000>;
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wkup_uart0: serial@0 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x0 0x100>;
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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};
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wkup_i2c0: i2c@2b200000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x00 0x2b200000 0x00 0x100>;
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interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 107 4>;
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clock-names = "fck";
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status = "disabled";
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};
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wkup_rtc0: rtc@2b1f0000 {
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compatible = "ti,am62-rtc";
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reg = <0x00 0x2b1f0000 0x00 0x100>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 117 6> , <&k3_clks 117 0>;
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clock-names = "vbus", "osc32k";
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power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
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wakeup-source;
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};
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wkup_rti0: watchdog@2b000000 {
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compatible = "ti,j7-rti-wdt";
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reg = <0x00 0x2b000000 0x00 0x100>;
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clocks = <&k3_clks 132 0>;
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power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>;
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assigned-clocks = <&k3_clks 132 0>;
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assigned-clock-parents = <&k3_clks 132 2>;
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/* Used by DM firmware */
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status = "reserved";
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};
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wkup_vtm0: temperature-sensor@b00000 {
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compatible = "ti,j7200-vtm";
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reg = <0x00 0xb00000 0x00 0x400>,
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<0x00 0xb01000 0x00 0x400>;
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power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
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#thermal-sensor-cells = <1>;
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};
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};
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@ -1,122 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/*
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* Device Tree Source for AM62 SoC Family
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*
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* Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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#include "k3-pinctrl.h"
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/ {
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model = "Texas Instruments K3 AM625 SoC";
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compatible = "ti,am625";
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interrupt-parent = <&gic500>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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psci: psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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};
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a53_timer0: timer-cl0-cpu0 {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
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};
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pmu: pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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cbass_main: bus@f0000 {
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bootph-all;
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
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<0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
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<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
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<0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
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<0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
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<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
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<0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
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<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
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<0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
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<0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
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<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
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<0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
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<0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
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<0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
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<0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
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<0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
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<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
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<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
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||||
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
|
||||
<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
|
||||
<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
|
||||
<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
|
||||
<0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
|
||||
|
||||
/* MCU Domain Range */
|
||||
<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
|
||||
|
||||
/* Wakeup Domain Range */
|
||||
<0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
|
||||
<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
|
||||
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
|
||||
|
||||
cbass_mcu: bus@4000000 {
|
||||
bootph-all;
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
|
||||
};
|
||||
|
||||
cbass_wakeup: bus@b00000 {
|
||||
bootph-all;
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
|
||||
<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
|
||||
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
|
||||
};
|
||||
};
|
||||
|
||||
dss_vp1_clk: clock-divider-oldi {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&k3_clks 186 0>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <7>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
|
||||
#include "k3-am62-thermal.dtsi"
|
||||
};
|
||||
|
||||
/* Now include the peripherals for each bus segments */
|
||||
#include "k3-am62-main.dtsi"
|
||||
#include "k3-am62-mcu.dtsi"
|
||||
#include "k3-am62-wakeup.dtsi"
|
||||
@ -141,7 +141,7 @@
|
||||
|
||||
#ifdef CONFIG_TARGET_AM625_A53_EVM
|
||||
|
||||
#define SPL_AM625_SK_DTB "spl/dts/k3-am625-sk.dtb"
|
||||
#define SPL_AM625_SK_DTB "spl/dts/ti/k3-am625-sk.dtb"
|
||||
#define AM625_SK_DTB "u-boot.dtb"
|
||||
|
||||
&binman {
|
||||
|
||||
@ -1,299 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* AM625 SK: https://www.ti.com/lit/zip/sprr448
|
||||
*
|
||||
* Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am62x-sk-common.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am625-sk", "ti,am625";
|
||||
model = "Texas Instruments AM625 SK";
|
||||
|
||||
opp-table {
|
||||
/* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */
|
||||
opp-1400000000 {
|
||||
opp-hz = /bits/ 64 <1400000000>;
|
||||
opp-supported-hw = <0x01 0x0004>;
|
||||
clock-latency-ns = <6000000>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 2G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
|
||||
};
|
||||
|
||||
vmain_pd: regulator-0 {
|
||||
/* TPS65988 PD CONTROLLER OUTPUT */
|
||||
bootph-all;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmain_pd";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_5v0: regulator-1 {
|
||||
/* Output of LM34936 */
|
||||
bootph-all;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vmain_pd>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_3v3_sys: regulator-2 {
|
||||
/* output of LM61460-Q1 */
|
||||
bootph-all;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_3v3_sys";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vmain_pd>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_mmc1: regulator-3 {
|
||||
/* TPS22918DBVR */
|
||||
bootph-all;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_mmc1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
vin-supply = <&vcc_3v3_sys>;
|
||||
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
vdd_sd_dv: regulator-4 {
|
||||
/* Output of TLV71033 */
|
||||
bootph-all;
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "tlv71033";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vdd_sd_dv_pins_default>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc_5v0>;
|
||||
gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 0x0>,
|
||||
<3300000 0x1>;
|
||||
};
|
||||
|
||||
vcc_1v8: regulator-5 {
|
||||
/* output of TPS6282518DMQ */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc_3v3_sys>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_rgmii2_pins_default: main-rgmii2-default-pins {
|
||||
bootph-all;
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
|
||||
AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
|
||||
AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
|
||||
AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
|
||||
AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
|
||||
AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
|
||||
AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
|
||||
AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
|
||||
AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
|
||||
AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
|
||||
AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
|
||||
AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
ospi0_pins_default: ospi0-default-pins {
|
||||
bootph-all;
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
|
||||
AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
|
||||
AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
|
||||
AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
|
||||
AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
|
||||
AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
|
||||
AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
|
||||
AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
|
||||
AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
|
||||
AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
|
||||
AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
|
||||
>;
|
||||
};
|
||||
|
||||
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
|
||||
bootph-all;
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
|
||||
bootph-all;
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_gpio0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_gpio1 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_i2c1 {
|
||||
bootph-all;
|
||||
exp1: gpio@22 {
|
||||
bootph-all;
|
||||
compatible = "ti,tca6424";
|
||||
reg = <0x22>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
|
||||
"PRU_DETECT", "MMC1_SD_EN",
|
||||
"VPP_LDO_EN", "EXP_PS_3V3_En",
|
||||
"EXP_PS_5V0_En", "EXP_HAT_DETECT",
|
||||
"GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
|
||||
"UART1_FET_BUF_EN", "WL_LT_EN",
|
||||
"GPIO_HDMI_RSTn", "CSI_GPIO1",
|
||||
"CSI_GPIO2", "PRU_3V3_EN",
|
||||
"HDMI_INTn", "PD_I2C_IRQ",
|
||||
"MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
|
||||
"MCASP1_FET_SEL", "UART1_FET_SEL",
|
||||
"TSINT#", "IO_EXP_TEST_LED";
|
||||
|
||||
interrupt-parent = <&main_gpio1>;
|
||||
interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
vmmc-supply = <&vdd_mmc1>;
|
||||
vqmmc-supply = <&vdd_sd_dv>;
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy1>;
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
cpsw3g_phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
ti,min-output-impedance;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
mbox_m4_0: mbox-m4-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&fss {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
|
||||
flash@0 {
|
||||
bootph-all;
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-max-frequency = <25000000>;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <4>;
|
||||
|
||||
partitions {
|
||||
bootph-all;
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "ospi.tiboot3";
|
||||
reg = <0x0 0x80000>;
|
||||
};
|
||||
|
||||
partition@80000 {
|
||||
label = "ospi.tispl";
|
||||
reg = <0x80000 0x200000>;
|
||||
};
|
||||
|
||||
partition@280000 {
|
||||
label = "ospi.u-boot";
|
||||
reg = <0x280000 0x400000>;
|
||||
};
|
||||
|
||||
partition@680000 {
|
||||
label = "ospi.env";
|
||||
reg = <0x680000 0x40000>;
|
||||
};
|
||||
|
||||
partition@6c0000 {
|
||||
label = "ospi.env.backup";
|
||||
reg = <0x6c0000 0x40000>;
|
||||
};
|
||||
|
||||
partition@800000 {
|
||||
label = "ospi.rootfs";
|
||||
reg = <0x800000 0x37c0000>;
|
||||
};
|
||||
|
||||
partition@3fc0000 {
|
||||
bootph-pre-ram;
|
||||
label = "ospi.phypattern";
|
||||
reg = <0x3fc0000 0x40000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlv320aic3106 {
|
||||
DVDD-supply = <&vcc_1v8>;
|
||||
};
|
||||
@ -1,155 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Device Tree Source for AM625 SoC family in Quad core configuration
|
||||
*
|
||||
* TRM: https://www.ti.com/lit/pdf/spruiv7
|
||||
*
|
||||
* Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am62.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0: cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&cpu2>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&cpu3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x000>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
clocks = <&k3_clks 135 0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x001>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
clocks = <&k3_clks 136 0>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x002>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
clocks = <&k3_clks 137 0>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x003>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
clocks = <&k3_clks 138 0>;
|
||||
};
|
||||
};
|
||||
|
||||
a53_opp_table: opp-table {
|
||||
compatible = "operating-points-v2-ti-cpu";
|
||||
opp-shared;
|
||||
syscon = <&wkup_conf>;
|
||||
|
||||
opp-200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
opp-supported-hw = <0x01 0x0007>;
|
||||
clock-latency-ns = <6000000>;
|
||||
};
|
||||
|
||||
opp-400000000 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
opp-supported-hw = <0x01 0x0007>;
|
||||
clock-latency-ns = <6000000>;
|
||||
};
|
||||
|
||||
opp-600000000 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-supported-hw = <0x01 0x0007>;
|
||||
clock-latency-ns = <6000000>;
|
||||
};
|
||||
|
||||
opp-800000000 {
|
||||
opp-hz = /bits/ 64 <800000000>;
|
||||
opp-supported-hw = <0x01 0x0007>;
|
||||
clock-latency-ns = <6000000>;
|
||||
};
|
||||
|
||||
opp-1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-supported-hw = <0x01 0x0006>;
|
||||
clock-latency-ns = <6000000>;
|
||||
};
|
||||
|
||||
opp-1250000000 {
|
||||
opp-hz = /bits/ 64 <1250000000>;
|
||||
opp-supported-hw = <0x01 0x0004>;
|
||||
clock-latency-ns = <6000000>;
|
||||
opp-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
cache-size = <0x80000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
};
|
||||
};
|
||||
@ -1,535 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Common dtsi for AM62x SK and derivatives
|
||||
*
|
||||
* Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include "k3-am625.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial2 = &main_uart0;
|
||||
mmc0 = &sdhci0;
|
||||
mmc1 = &sdhci1;
|
||||
mmc2 = &sdhci2;
|
||||
spi0 = &ospi0;
|
||||
ethernet0 = &cpsw_port1;
|
||||
ethernet1 = &cpsw_port2;
|
||||
usb0 = &usb0;
|
||||
usb1 = &usb1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
bootph-pre-ram;
|
||||
device_type = "memory";
|
||||
/* 2G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
ramoops@9ca00000 {
|
||||
compatible = "ramoops";
|
||||
reg = <0x00 0x9ca00000 0x00 0x00100000>;
|
||||
record-size = <0x8000>;
|
||||
console-size = <0x8000>;
|
||||
ftrace-size = <0x00>;
|
||||
pmsg-size = <0x8000>;
|
||||
};
|
||||
|
||||
secure_tfa_ddr: tfa@9e780000 {
|
||||
reg = <0x00 0x9e780000 0x00 0x80000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9db00000 0x00 0xc00000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usr_led_pins_default>;
|
||||
|
||||
led-0 {
|
||||
label = "am62-sk:green:heartbeat";
|
||||
gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
tlv320_mclk: clk-0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <12288000>;
|
||||
};
|
||||
|
||||
codec_audio: sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "AM62x-SKEVM";
|
||||
simple-audio-card,widgets =
|
||||
"Headphone", "Headphone Jack",
|
||||
"Line", "Line In",
|
||||
"Microphone", "Microphone Jack";
|
||||
simple-audio-card,routing =
|
||||
"Headphone Jack", "HPLOUT",
|
||||
"Headphone Jack", "HPROUT",
|
||||
"LINE1L", "Line In",
|
||||
"LINE1R", "Line In",
|
||||
"MIC3R", "Microphone Jack",
|
||||
"Microphone Jack", "Mic Bias";
|
||||
simple-audio-card,format = "dsp_b";
|
||||
simple-audio-card,bitclock-master = <&sound_master>;
|
||||
simple-audio-card,frame-master = <&sound_master>;
|
||||
simple-audio-card,bitclock-inversion;
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&mcasp1>;
|
||||
};
|
||||
|
||||
sound_master: simple-audio-card,codec {
|
||||
sound-dai = <&tlv320aic3106>;
|
||||
clocks = <&tlv320_mclk>;
|
||||
};
|
||||
};
|
||||
|
||||
hdmi0: connector-hdmi {
|
||||
compatible = "hdmi-connector";
|
||||
label = "hdmi";
|
||||
type = "a";
|
||||
port {
|
||||
hdmi_connector_in: endpoint {
|
||||
remote-endpoint = <&sii9022_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
/* First pad number is ALW package and second is AMC package */
|
||||
main_uart0_pins_default: main-uart0-default-pins {
|
||||
bootph-all;
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14/A13) UART0_RXD */
|
||||
AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_uart1_pins_default: main-uart1-default-pins {
|
||||
bootph-pre-ram;
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19/B18) MCASP0_AXR3.UART1_CTSn */
|
||||
AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19/B17) MCASP0_AXR2.UART1_RTSn */
|
||||
AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19/D15) MCASP0_AFSR.UART1_RXD */
|
||||
AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20/D16) MCASP0_ACLKR.UART1_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c0_pins_default: main-i2c0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16/E12) I2C0_SCL */
|
||||
AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16/D14) I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c1_pins_default: main-i2c1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17/A17) I2C1_SCL */
|
||||
AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17/A16) I2C1_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c2_pins_default: main-i2c2-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22/H18) GPMC0_CSn2.I2C2_SCL */
|
||||
AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24/H19) GPMC0_CSn3.I2C2_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mmc0_pins_default: main-mmc0-default-pins {
|
||||
bootph-all;
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3/V3) MMC0_CMD */
|
||||
AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1/Y1) MMC0_CLK */
|
||||
AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2/V2) MMC0_DAT0 */
|
||||
AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1/V1) MMC0_DAT1 */
|
||||
AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3/W2) MMC0_DAT2 */
|
||||
AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4/W1) MMC0_DAT3 */
|
||||
AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2/Y2) MMC0_DAT4 */
|
||||
AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1/W3) MMC0_DAT5 */
|
||||
AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2/W4) MMC0_DAT6 */
|
||||
AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2/V4) MMC0_DAT7 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mmc1_pins_default: main-mmc1-default-pins {
|
||||
bootph-all;
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21/C18) MMC1_CMD */
|
||||
AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22/A20) MMC1_CLK */
|
||||
AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22/A19) MMC1_DAT0 */
|
||||
AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21/B19) MMC1_DAT1 */
|
||||
AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21/B20) MMC1_DAT2 */
|
||||
AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22/C19) MMC1_DAT3 */
|
||||
AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17/C15) MMC1_SDCD */
|
||||
>;
|
||||
};
|
||||
|
||||
usr_led_pins_default: usr-led-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17/B15) MMC1_SDWP.GPIO1_49 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mdio1_pins_default: main-mdio1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24/V17) MDIO0_MDC */
|
||||
AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22/U16) MDIO0_MDIO */
|
||||
>;
|
||||
};
|
||||
|
||||
main_rgmii1_pins_default: main-rgmii1-default-pins {
|
||||
bootph-all;
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17/W15) RGMII1_RD0 */
|
||||
AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17/Y16) RGMII1_RD1 */
|
||||
AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16/AA17) RGMII1_RD2 */
|
||||
AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15/Y15) RGMII1_RD3 */
|
||||
AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17/AA16) RGMII1_RXC */
|
||||
AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17/W14) RGMII1_RX_CTL */
|
||||
AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20/U14) RGMII1_TD0 */
|
||||
AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20/AA19) RGMII1_TD1 */
|
||||
AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18/Y17) RGMII1_TD2 */
|
||||
AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18/AA18) RGMII1_TD3 */
|
||||
AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19/W16) RGMII1_TXC */
|
||||
AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19/V15) RGMII1_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
main_usb1_pins_default: main-usb1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mcasp1_pins_default: main-mcasp1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x090, PIN_INPUT, 2) /* (M24/K17) GPMC0_BE0N_CLE.MCASP1_ACLKX */
|
||||
AM62X_IOPAD(0x098, PIN_INPUT, 2) /* (U23/P21) GPMC0_WAIT0.MCASP1_AFSX */
|
||||
AM62X_IOPAD(0x08c, PIN_OUTPUT, 2) /* (L25/J17) GPMC0_WEN.MCASP1_AXR0 */
|
||||
AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23/K20) GPMC0_ADVN_ALE.MCASP1_AXR2 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_dss0_pins_default: main-dss0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */
|
||||
AM62X_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */
|
||||
AM62X_IOPAD(0x104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */
|
||||
AM62X_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */
|
||||
AM62X_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */
|
||||
AM62X_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */
|
||||
AM62X_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */
|
||||
AM62X_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */
|
||||
AM62X_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */
|
||||
AM62X_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */
|
||||
AM62X_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */
|
||||
AM62X_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */
|
||||
AM62X_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */
|
||||
AM62X_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */
|
||||
AM62X_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */
|
||||
AM62X_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */
|
||||
AM62X_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */
|
||||
AM62X_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */
|
||||
AM62X_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */
|
||||
AM62X_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */
|
||||
AM62X_IOPAD(0x05c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */
|
||||
AM62X_IOPAD(0x060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */
|
||||
AM62X_IOPAD(0x064, PIN_OUTPUT, 1) /* (T25) GPMC0_AD10.VOUT0_DATA18 */
|
||||
AM62X_IOPAD(0x068, PIN_OUTPUT, 1) /* (R21) GPMC0_AD11.VOUT0_DATA19 */
|
||||
AM62X_IOPAD(0x06c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */
|
||||
AM62X_IOPAD(0x070, PIN_OUTPUT, 1) /* (T24) GPMC0_AD13.VOUT0_DATA21 */
|
||||
AM62X_IOPAD(0x074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */
|
||||
AM62X_IOPAD(0x078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_pmx0 {
|
||||
wkup_uart0_pins_default: wkup-uart0-default-pins {
|
||||
bootph-pre-ram;
|
||||
pinctrl-single,pins = <
|
||||
AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6/A7) WKUP_UART0_CTSn */
|
||||
AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4/B4) WKUP_UART0_RTSn */
|
||||
AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4/B5) WKUP_UART0_RXD */
|
||||
AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5/C6) WKUP_UART0_TXD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_uart0 {
|
||||
/* WKUP UART0 is used by DM firmware */
|
||||
bootph-pre-ram;
|
||||
status = "reserved";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wkup_uart0_pins_default>;
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
/* Main UART1 is used by TIFS firmware */
|
||||
bootph-pre-ram;
|
||||
status = "reserved";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart1_pins_default>;
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
eeprom@51 {
|
||||
/* AT24C512C-MAHM-T or M24512-DFMC6TG */
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
typec_pd0: tps6598x@3f {
|
||||
compatible = "ti,tps6598x";
|
||||
reg = <0x3f>;
|
||||
|
||||
connector {
|
||||
compatible = "usb-c-connector";
|
||||
label = "USB-C";
|
||||
self-powered;
|
||||
data-role = "dual";
|
||||
power-role = "sink";
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
usb_con_hs: endpoint {
|
||||
remote-endpoint = <&usb0_hs_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c1_pins_default>;
|
||||
clock-frequency = <100000>;
|
||||
|
||||
tlv320aic3106: audio-codec@1b {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "ti,tlv320aic3106";
|
||||
reg = <0x1b>;
|
||||
ai3x-micbias-vg = <1>; /* 2.0V */
|
||||
|
||||
/* Regulators */
|
||||
AVDD-supply = <&vcc_3v3_sys>;
|
||||
IOVDD-supply = <&vcc_3v3_sys>;
|
||||
DRVDD-supply = <&vcc_3v3_sys>;
|
||||
};
|
||||
|
||||
sii9022: bridge-hdmi@3b {
|
||||
compatible = "sil,sii9022";
|
||||
reg = <0x3b>;
|
||||
interrupt-parent = <&exp1>;
|
||||
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
|
||||
#sound-dai-cells = <0>;
|
||||
sil,i2s-data-lanes = < 0 >;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
sii9022_in: endpoint {
|
||||
remote-endpoint = <&dpi1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
sii9022_out: endpoint {
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c2 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c2_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc0_pins_default>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
/* SD/MMC */
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
bootph-all;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_rgmii1_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw_port1 {
|
||||
bootph-all;
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy0>;
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mdio1_pins_default>;
|
||||
|
||||
cpsw3g_phy0: ethernet-phy@0 {
|
||||
bootph-all;
|
||||
reg = <0>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
ti,min-output-impedance;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
mbox_m4_0: mbox-m4-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
ti,vbus-divider;
|
||||
};
|
||||
|
||||
&usbss1 {
|
||||
status = "okay";
|
||||
ti,vbus-divider;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
bootph-all;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
usb-role-switch;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
usb0_hs_ep: endpoint {
|
||||
remote-endpoint = <&usb_con_hs>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "host";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_usb1_pins_default>;
|
||||
};
|
||||
|
||||
&mcasp1 {
|
||||
status = "okay";
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcasp1_pins_default>;
|
||||
|
||||
op-mode = <0>; /* MCASP_IIS_MODE */
|
||||
tdm-slots = <2>;
|
||||
|
||||
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
|
||||
1 0 2 0
|
||||
0 0 0 0
|
||||
0 0 0 0
|
||||
0 0 0 0
|
||||
>;
|
||||
tx-num-evt = <32>;
|
||||
rx-num-evt = <32>;
|
||||
};
|
||||
|
||||
&dss {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_dss0_pins_default>;
|
||||
};
|
||||
|
||||
&dss_ports {
|
||||
/* VP2: DPI Output */
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
dpi1_out: endpoint {
|
||||
remote-endpoint = <&sii9022_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
|
||||
&mcu_gpio0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&mcu_gpio_intr {
|
||||
status = "reserved";
|
||||
};
|
||||
@ -10,7 +10,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000
|
||||
CONFIG_SF_DEFAULT_SPEED=25000000
|
||||
CONFIG_SPL_DM_SPI=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="k3-am625-sk"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am625-sk"
|
||||
CONFIG_SPL_TEXT_BASE=0x80080000
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_DM_RESET=y
|
||||
@ -56,6 +56,7 @@ CONFIG_CMD_EFIDEBUG=y
|
||||
CONFIG_MMC_SPEED_MODE_SET=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_UPSTREAM=y
|
||||
CONFIG_MULTI_DTB_FIT=y
|
||||
CONFIG_SPL_MULTI_DTB_FIT=y
|
||||
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user