mirrors/u-boot
1
0
Fork 0
mirror of https://source.denx.de/u-boot/u-boot.git synced 2025-09-21 13:51:29 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity

Merge patch series "arm: dts: k3-am625-verdin: Enable LPDDR4 WDQS control"

Browse Source 
Emanuele Ghidoli <emanuele.ghidoli@toradex.com> says:

Manually, since SysConfig tool do not have the relevant option,
set PHY_LP4_WDQS_OE_EXTEND to 1.
Since WDQS control mode is required on our modules LPDDR4,
this enables WDQS control mode 1.
This commit is contained in:
Tom Rini 2024-06-07 13:58:25 -06:00
commit 48639c7050
1 changed files with 6 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
View File

@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: GPL-2.0+
/* /*
* This file was generated with the * This file was generated with the
* AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.10 * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.10.01
* Mon Dec 11 2023 17:07:35 GMT+0100 (Central European Standard Time) * Tue May 14 2024 12:55:28 GMT+0200 (Central European Summer Time)
* DDR Type: LPDDR4 * DDR Type: LPDDR4
* F0 = 50MHz F1 = NA F2 = 800MHz * F0 = 50MHz F1 = NA F2 = 800MHz
* Density (per channel): 16Gb * Density (per channel): 16Gb
@ -10,9 +10,11 @@
* Number of Ranks: 1 * Number of Ranks: 1
*/ */
#define DDRSS_PLL_FHS_CNT 3 #define DDRSS_PLL_FHS_CNT 3
#define DDRSS_PLL_FREQUENCY_1 400000000 #define DDRSS_PLL_FREQUENCY_1 400000000
#define DDRSS_PLL_FREQUENCY_2 400000000 #define DDRSS_PLL_FREQUENCY_2 400000000
#define DDRSS_SDRAM_IDX 15
#define DDRSS_CTL_0_DATA 0x00000B00 #define DDRSS_CTL_0_DATA 0x00000B00
@ -848,7 +850,7 @@
#define DDRSS_PHY_62_DATA 0x00000000 #define DDRSS_PHY_62_DATA 0x00000000
#define DDRSS_PHY_63_DATA 0x00000000 #define DDRSS_PHY_63_DATA 0x00000000
#define DDRSS_PHY_64_DATA 0x00000000 #define DDRSS_PHY_64_DATA 0x00000000
#define DDRSS_PHY_65_DATA 0x00000004 #define DDRSS_PHY_65_DATA 0x00000104
#define DDRSS_PHY_66_DATA 0x00000000 #define DDRSS_PHY_66_DATA 0x00000000
#define DDRSS_PHY_67_DATA 0x00000000 #define DDRSS_PHY_67_DATA 0x00000000
#define DDRSS_PHY_68_DATA 0x00000000 #define DDRSS_PHY_68_DATA 0x00000000
@ -1104,7 +1106,7 @@
#define DDRSS_PHY_318_DATA 0x00000000 #define DDRSS_PHY_318_DATA 0x00000000
#define DDRSS_PHY_319_DATA 0x00000000 #define DDRSS_PHY_319_DATA 0x00000000
#define DDRSS_PHY_320_DATA 0x00000000 #define DDRSS_PHY_320_DATA 0x00000000
#define DDRSS_PHY_321_DATA 0x00000004 #define DDRSS_PHY_321_DATA 0x00000104
#define DDRSS_PHY_322_DATA 0x00000000 #define DDRSS_PHY_322_DATA 0x00000000
#define DDRSS_PHY_323_DATA 0x00000000 #define DDRSS_PHY_323_DATA 0x00000000
#define DDRSS_PHY_324_DATA 0x00000000 #define DDRSS_PHY_324_DATA 0x00000000