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Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv

Browse Source 
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/25312

- Fix warning
- Fix incorrect return value
This commit is contained in:
Tom Rini 2025-03-25 11:55:05 -06:00
commit 47f433d577
2 changed files with 4 additions and 3 deletions
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1
board/openpiton/riscv64/Kconfig
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@ -35,6 +35,5 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply SPL_SMP
imply SPL_MMC
imply SMP
imply SPL_RISCV_MMODE
endif

6
drivers/clk/sophgo/clk-common.h
View File

@ -45,12 +45,14 @@ static inline u32 cv1800b_clk_getbit(void *base, struct cv1800b_clk_regbit *bit)
static inline u32 cv1800b_clk_setbit(void *base, struct cv1800b_clk_regbit *bit)
{
return setbits_le32(base + bit->offset, BIT(bit->shift));
setbits_le32(base + bit->offset, BIT(bit->shift));
return 0;
}
static inline u32 cv1800b_clk_clrbit(void *base, struct cv1800b_clk_regbit *bit)
{
return clrbits_le32(base + bit->offset, BIT(bit->shift));
clrbits_le32(base + bit->offset, BIT(bit->shift));
return 0;
}
static inline u32 cv1800b_clk_getfield(void *base,