clk: rockchip: rk3568: add stubs for CLK_PCIEPHY_REF clocks

Device tree contains assigned-clock-rates property for these,
but default value will work just fine

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>

drivers/clk/rockchip/clk_rk3568.c

@@ -425,6 +425,9 @@ static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong rate)
 	case PCLK_PMU:
 		ret = rk3568_pmu_set_pmuclk(priv, rate);
 		break;
+	case CLK_PCIEPHY0_REF:
+	case CLK_PCIEPHY1_REF:
+		return 0;
 	default:
 		return -ENOENT;
 	}