From 95052b4b4001647ac0edd3216f92737cc06b1622 Mon Sep 17 00:00:00 2001 From: Thomas Hebb Date: Fri, 20 Dec 2019 12:28:15 -0800 Subject: [PATCH 01/25] ram: rk3399: don't assume phy_io_config() uses real regs In the RK3399 DRAM driver, the function set_ds_odt() supports operating in two different modes, selected by the ctl_phy_reg argument: when true, the function reads and writes directly from the DRAM registers, accessed through "chan->pctl->denali_*"; when false, the function reads and writes from an array, accessed through "params->pctl_regs.denali_*", which is written to DRAM registers at a later time. However, phy_config_io(), which is called by set_ds_odt() to do a subset of its register operations, operates directly on DRAM registers at all times. This means that it reads incorrect values (and writes new values prematurely) when ctl_phy_reg in set_ds_odt() is false. Fix this by passing in the address of the registers to work with. This prevents an "Invalid DRV value" error in the SPL debug log and (presumably) results in a more correct end state. See the following logs from a RK3399 NanoPi M4 board (4GB LPDDR3): Before: sdram_init() Starting SDRAM initialization... phy_io_config() Invalid DRV value. phy_io_config() Invalid DRV value. sdram_init() sdram_init: data trained for rank 2, ch 0 phy_io_config() Invalid DRV value. phy_io_config() Invalid DRV value. sdram_init() sdram_init: data trained for rank 2, ch 1 Channel 0: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride 256B stride sdram_init() Finish SDRAM initialization... After: sdram_init() Starting SDRAM initialization... sdram_init() sdram_init: data trained for rank 2, ch 0 sdram_init() sdram_init: data trained for rank 2, ch 1 Channel 0: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride 256B stride sdram_init() Finish SDRAM initialization... Signed-off-by: Thomas Hebb Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 7b2bba03fe0..9c276e13b29 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -337,11 +337,9 @@ static void set_memory_map(const struct chan_info *chan, u32 channel, writel(0x2EC7FFFF, &denali_pi[34]); } -static int phy_io_config(const struct chan_info *chan, +static int phy_io_config(u32 *denali_phy, u32 *denali_ctl, const struct rk3399_sdram_params *params, u32 mr5) { - u32 *denali_phy = chan->publ->denali_phy; - u32 *denali_ctl = chan->pctl->denali_ctl; u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac; u32 mode_sel; u32 speed; @@ -780,7 +778,7 @@ static void set_ds_odt(const struct chan_info *chan, /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */ clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value); - phy_io_config(chan, params, mr5); + phy_io_config(denali_phy, denali_ctl, params, mr5); } static void pctl_start(struct dram_info *dram, From 7c5f6d0aa4126ba74c0c8f95f916063418a2a130 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 21 Dec 2019 13:24:34 +0530 Subject: [PATCH 02/25] rk3399: Check MMC env while defining it rk3399 do support SPI flash as well, so there is a possibility of using flash environment for those usecases. So define env device for MMC only when it is used by specific configuration. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- include/configs/evb_rk3399.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h index b9c4d683f47..c0b03588938 100644 --- a/include/configs/evb_rk3399.h +++ b/include/configs/evb_rk3399.h @@ -8,7 +8,9 @@ #include -#define CONFIG_SYS_MMC_ENV_DEV 0 +#if defined(CONFIG_ENV_IS_IN_MMC) +# define CONFIG_SYS_MMC_ENV_DEV 0 +#endif #define SDRAM_BANK_SIZE (2UL << 30) From d7b433e40b037733f47b83b8e2f385f91035924b Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 21 Dec 2019 13:24:35 +0530 Subject: [PATCH 03/25] env: kconfig: Restrict rockchip env for MMC Rockchip do support SPI flash as well, so there is a possibility of using flash environment for those use cases. So, restrict the current env offset, size for MMC. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- env/Kconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/env/Kconfig b/env/Kconfig index 4661082f0e1..ac7b8f7e4e5 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -491,7 +491,7 @@ config ENV_OFFSET hex "Environment offset" depends on ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \ ENV_IS_IN_SPI_FLASH - default 0x3f8000 if ARCH_ROCKCHIP + default 0x3f8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC default 0x88000 if ARCH_SUNXI default 0xE0000 if ARCH_ZYNQ default 0x1E00000 if ARCH_ZYNQMP @@ -514,7 +514,8 @@ config ENV_SIZE hex "Environment Size" default 0x40000 if ENV_IS_IN_SPI_FLASH && ARCH_ZYNQMP default 0x20000 if ARCH_SUNXI || ARCH_ZYNQ || ARCH_OMAP2PLUS || ARCH_AT91 - default 0x8000 if ARCH_ROCKCHIP || ARCH_ZYNQMP || ARCH_VERSAL + default 0x8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC + default 0x8000 if ARCH_ZYNQMP || ARCH_VERSAL default 0x4000 if ARC default 0x1f000 help From 54b85a94e56e26dcc01846b6d38478ae06d87183 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 21 Dec 2019 13:24:36 +0530 Subject: [PATCH 04/25] env: Enable SPI flash env for rockchip Most of the SPI flash devices in rockchip are 16MiB size. So, keeping U-Boot proper offset start from 128MiB with 1MiB size and then start env of 8KiB would be a compatible location between all variants of flash sizes. This patch add env start from 0x14000 with a size of 8KiB. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- env/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/env/Kconfig b/env/Kconfig index ac7b8f7e4e5..0d6f559b39d 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -492,6 +492,7 @@ config ENV_OFFSET depends on ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \ ENV_IS_IN_SPI_FLASH default 0x3f8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC + default 0x140000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH default 0x88000 if ARCH_SUNXI default 0xE0000 if ARCH_ZYNQ default 0x1E00000 if ARCH_ZYNQMP @@ -515,6 +516,7 @@ config ENV_SIZE default 0x40000 if ENV_IS_IN_SPI_FLASH && ARCH_ZYNQMP default 0x20000 if ARCH_SUNXI || ARCH_ZYNQ || ARCH_OMAP2PLUS || ARCH_AT91 default 0x8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC + default 0x2000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH default 0x8000 if ARCH_ZYNQMP || ARCH_VERSAL default 0x4000 if ARC default 0x1f000 @@ -524,6 +526,7 @@ config ENV_SIZE config ENV_SECT_SIZE hex "Environment Sector-Size" depends on ENV_IS_IN_FLASH || ENV_IS_IN_SPI_FLASH + default 0x2000 if ARCH_ROCKCHIP default 0x40000 if ARCH_ZYNQMP || ARCH_VERSAL default 0x20000 if ARCH_ZYNQ || ARCH_OMAP2PLUS || ARCH_AT91 help From c8b1684a8cd80a0c52837c1c09e58937fa82f26c Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 21 Dec 2019 13:24:37 +0530 Subject: [PATCH 05/25] rockchip: dts: Sync ROC-RK3399-PC changes from Linux Sync the ROC-RK3399-PC device tree changes from Linux with below commit details: commit ("arm64: dts: rockchip: Enable MTD Flash on rk3399-roc-pc") Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-roc-pc.dts | 673 +------------------------- arch/arm/dts/rk3399-roc-pc.dtsi | 813 ++++++++++++++++++++++++++++++++ 2 files changed, 816 insertions(+), 670 deletions(-) create mode 100644 arch/arm/dts/rk3399-roc-pc.dtsi diff --git a/arch/arm/dts/rk3399-roc-pc.dts b/arch/arm/dts/rk3399-roc-pc.dts index 257543d069d..6a909e4eefd 100644 --- a/arch/arm/dts/rk3399-roc-pc.dts +++ b/arch/arm/dts/rk3399-roc-pc.dts @@ -4,677 +4,10 @@ */ /dts-v1/; -#include -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" +#include "rk3399-roc-pc.dtsi" / { model = "Firefly ROC-RK3399-PC Board"; - compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm0 0 25000 0>; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - - vcc_vbus_typec0: vcc-vbus-typec0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_vbus_typec0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - /* - * should be placed inside mp8859, but not until mp8859 has - * its own dt-binding. - */ - dc_12v: mp8859-dcdc1 { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <&vcc_vbus_typec0>; - }; - - /* switched by pmic_sleep */ - vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_1v8>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_sys>; - }; - - /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en &hub_rst>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc_vbus_typec1: vcc-vbus-typec1 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_vbus_typec1_en>; - regulator-name = "vcc_vbus_typec1"; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - vin-supply = <&vcc_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc_sys>; - vcc10-supply = <&vcc_sys>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc1v8_pmu>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_codec: LDO_REG1 { - regulator-name = "vcca1v8_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_hdmi: LDO_REG2 { - regulator-name = "vcc1v8_hdmi"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_pmu: LDO_REG3 { - regulator-name = "vcc1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sdio: LDO_REG4 { - regulator-name = "vcc_sdio"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-name = "vcca3v0_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca0v9_hdmi: LDO_REG7 { - regulator-name = "vcca0v9_hdmi"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: vcc_lan: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel1_gpio>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel2_gpio>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - i2c-scl-rising-time-ns = <300>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c4 { - i2c-scl-rising-time-ns = <600>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - fusb1: usb-typec@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio1>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&fusb1_int>; - vbus-supply = <&vcc_vbus_typec1>; - status = "okay"; - }; -}; - -&i2c7 { - i2c-scl-rising-time-ns = <600>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - fusb0: usb-typec@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio1>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&fusb0_int>; - vbus-supply = <&vcc_vbus_typec0>; - status = "okay"; - }; -}; - -&i2s0 { - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; - status = "okay"; -}; - -&i2s1 { - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - audio-supply = <&vcca1v8_codec>; - bt656-supply = <&vcc_3v0>; - gpio1830-supply = <&vcc_3v0>; - sdmmc-supply = <&vcc_sdio>; - status = "okay"; -}; - -&pmu_io_domains { - pmu1830-supply = <&vcc_3v0>; - status = "okay"; -}; - -&pinctrl { - lcd-panel { - lcd_panel_reset: lcd-panel-reset { - rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - vsel1_gpio: vsel1-gpio { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_gpio: vsel2-gpio { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - hub_rst: hub-rst { - rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - usb-typec { - vcc_vbus_typec1_en: vcc-vbus-typec1-en { - rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - fusb30x { - fusb0_int: fusb0-int { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - fusb1_int: fusb1-int { - rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca1v8_s3>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - phy-supply = <&vcc_vbus_typec0>; - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - phy-supply = <&vcc_vbus_typec1>; - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; + compatible = "libretech,roc-rk3399-pc", "firefly,roc-rk3399-pc", + "rockchip,rk3399"; }; diff --git a/arch/arm/dts/rk3399-roc-pc.dtsi b/arch/arm/dts/rk3399-roc-pc.dtsi new file mode 100644 index 00000000000..9a1ce3a4ae1 --- /dev/null +++ b/arch/arm/dts/rk3399-roc-pc.dtsi @@ -0,0 +1,813 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd + */ + +/dts-v1/; +#include +#include +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Firefly ROC-RK3399-PC Board"; + compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1500000>; + poll-interval = <100>; + + recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <18000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key_l>; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>, <&yellow_led_gpio>; + + work-led { + label = "green:work"; + gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + diy-led { + label = "red:diy"; + gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc1"; + }; + + yellow-led { + label = "yellow:yellow-led"; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + vcc_vbus_typec0: vcc-vbus-typec0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_vbus_typec0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + /* + * should be placed inside mp8859, but not until mp8859 has + * its own dt-binding. + */ + dc_12v: mp8859-dcdc1 { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <&vcc_vbus_typec0>; + }; + + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8>; + }; + + vcc3v0_sd: vcc3v0-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v0_sd_en>; + regulator-name = "vcc3v0_sd"; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcca_0v9: vcca-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vcca_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en &hub_rst>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc_vbus_typec1: vcc-vbus-typec1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_vbus_typec1_en>; + regulator-name = "vcc_vbus_typec1"; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_sys_en>; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1400000>; + pwm-supply = <&vcc3v3_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vcc13-supply = <&vcc3v3_sys>; + vcc14-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_3v0>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_codec: LDO_REG1 { + regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_hdmi: LDO_REG2 { + regulator-name = "vcc1v8_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-name = "vcc1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca0v9_hdmi: LDO_REG7 { + regulator-name = "vcca0v9_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: vcc_lan: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_gpio>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + fusb1: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb1_int>; + vbus-supply = <&vcc_vbus_typec1>; + status = "okay"; + }; +}; + +&i2c7 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + fusb0: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-supply = <&vcc_vbus_typec0>; + status = "okay"; + }; +}; + +&i2s0 { + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + status = "okay"; +}; + +&i2s1 { + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + audio-supply = <&vcca1v8_codec>; + bt656-supply = <&vcc_3v0>; + gpio1830-supply = <&vcc_3v0>; + sdmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pinctrl { + buttons { + pwr_key_l: pwr-key-l { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd-panel { + lcd_panel_reset: lcd-panel-reset { + rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + diy_led_gpio: diy_led-gpio { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + work_led_gpio: work_led-gpio { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + yellow_led_gpio: yellow_led-gpio { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + vsel1_gpio: vsel1-gpio { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + vcc3v0_sd_en: vcc3v0-sd-en { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc_sys_en: vcc-sys-en { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hub_rst: hub-rst { + rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + usb-typec { + vcc_vbus_typec1_en: vcc-vbus-typec1-en { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + fusb30x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + fusb1_int: fusb1-int { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v0_sd>; + vqmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&spi1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + phy-supply = <&vcc_vbus_typec0>; + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + phy-supply = <&vcc_vbus_typec1>; + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; From 3d11196c802da6bb91562c9a105e401aa68b6629 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 21 Dec 2019 13:24:38 +0530 Subject: [PATCH 06/25] roc-pc-rk3399: Enable SPI Flash Enable winbond SPI flash for ROC-PC-RK3399 board. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 4 ++++ configs/roc-pc-rk3399_defconfig | 2 ++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi index 77d5cf5d3cd..57464429811 100644 --- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi +++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi @@ -7,6 +7,10 @@ #include "rk3399-sdram-lpddr4-100.dtsi" / { + aliases { + spi0 = &spi1; + }; + chosen { u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; }; diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 39c3e18ab26..e51197c80c0 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -42,6 +42,8 @@ CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_ROCKCHIP_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y From 1c37f60c286cd4a0ff592cad64d1dcfec1adb6ae Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 21 Dec 2019 13:24:39 +0530 Subject: [PATCH 07/25] rockpro-rk3399: Enable SPI Flash Enable winbond SPI flash for ROC-PC-RK3399 board. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 4 ++++ configs/rockpro64-rk3399_defconfig | 2 ++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi index 4648513ea9b..deaa3efd39c 100644 --- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi @@ -6,6 +6,10 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi" / { + aliases { + spi0 = &spi1; + }; + chosen { u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; }; diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 201b826e34b..70b4e4d1861 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -46,6 +46,8 @@ CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_ROCKCHIP_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y From 2952f39269cab842769d0ff9a8ad5d7dcfb9a26c Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 9 Jan 2020 14:22:15 +0530 Subject: [PATCH 08/25] rockchip: Add cpu-info Add cpu information for rockchip soc. This would help to print the SoC family number, with associated temparature, clock and reason for reset etc. Reviewed-by: Kever Yang Signed-off-by: Jagan Teki --- arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/cpu-info.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) create mode 100644 arch/arm/mach-rockchip/cpu-info.c diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index a728acda24a..5b38526fe05 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -22,6 +22,7 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) # we can have the preprocessor correctly recognise both 0x0 and 0 # meaning "turn it off". obj-y += boot_mode.o +obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o obj-$(CONFIG_MISC_INIT_R) += misc.o endif diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c new file mode 100644 index 00000000000..9bccbd4f68d --- /dev/null +++ b/arch/arm/mach-rockchip/cpu-info.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * (C) Copyright 2019 Amarula Solutions(India) + * Author: Jagan Teki + */ + +#include + +int print_cpuinfo(void) +{ + printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC); + + /* TODO print operating temparature and clock */ + + return 0; +} From d49d8aa272718303324b5b12df99211f80ee37d8 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 9 Jan 2020 14:22:16 +0530 Subject: [PATCH 09/25] rockchip: rk3399: Enable DISPLAY_CPUINFO RK3288, RK3399 are now support cpu-info, so enable DISPLAY_CPUINFO by default. Reviewed-by: Kever Yang Signed-off-by: Jagan Teki --- configs/evb-rk3288_defconfig | 1 - configs/evb-rk3399_defconfig | 1 - configs/ficus-rk3399_defconfig | 1 - configs/firefly-rk3288_defconfig | 1 - configs/firefly-rk3399_defconfig | 1 - configs/khadas-edge-captain-rk3399_defconfig | 1 - configs/khadas-edge-rk3399_defconfig | 1 - configs/khadas-edge-v-rk3399_defconfig | 1 - configs/leez-rk3399_defconfig | 1 - configs/miqi-rk3288_defconfig | 1 - configs/nanopc-t4-rk3399_defconfig | 1 - configs/nanopi-m4-rk3399_defconfig | 1 - configs/nanopi-neo4-rk3399_defconfig | 1 - configs/orangepi-rk3399_defconfig | 1 - configs/phycore-rk3288_defconfig | 1 - configs/popmetal-rk3288_defconfig | 1 - configs/puma-rk3399_defconfig | 1 - configs/roc-pc-rk3399_defconfig | 1 - configs/rock-pi-4-rk3399_defconfig | 1 - configs/rock960-rk3399_defconfig | 1 - configs/rockpro64-rk3399_defconfig | 1 - configs/tinker-rk3288_defconfig | 1 - configs/tinker-s-rk3288_defconfig | 1 - configs/vyasa-rk3288_defconfig | 1 - 24 files changed, 24 deletions(-) diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index c881a29546e..178f67b4dd4 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -18,7 +18,6 @@ CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/fit_spl_optee.sh" CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 42e52e67777..14da0c56e9f 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index b96c2266371..dd7bd384bcc 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_SPL_TEXT_BASE=0xff8c2000 -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index dc3e2e4e3c1..2c730efd296 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -14,7 +14,6 @@ CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index a6390cdd653..0d95a5ff49c 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index a2318dc9929..defe2cf3452 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtbi" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index 2cd3bac67d4..e5a652388a0 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index 8eb9e310b58..0735152d4b8 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtbi" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig index 70732d0ea60..8672f0a1d4d 100644 --- a/configs/leez-rk3399_defconfig +++ b/configs/leez-rk3399_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-leez-p710.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index 4931138dfa3..de6f01f2cc3 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -15,7 +15,6 @@ CONFIG_SPL_TEXT_BASE=0xff704000 CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-miqi.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index a559cd03c5c..efcd9399d35 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index d8180631bdd..60d447e9848 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index c73a5403c3a..e318288f11b 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index a8c0125efb6..0a83b4a7992 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index fb57ba4f918..c8345013c74 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -16,7 +16,6 @@ CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y CONFIG_DEFAULT_FDT_FILE="rk3288-phycore-rdk.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index dc9d9075db3..01d3603f1e1 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -16,7 +16,6 @@ CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y CONFIG_DEFAULT_FDT_FILE="rk3288-popmetal.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 02c95ccbb6c..a76e0e44699 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -16,7 +16,6 @@ CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_SPL_FIT_GENERATOR="board/theobroma-systems/puma_rk3399/fit_spl_atf.sh" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" CONFIG_MISC_INIT_R=y -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index e51197c80c0..8204e002534 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 50ff1ccbbed..eac8dd920ae 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4.dtb" CONFIG_MISC_INIT_R=y -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index f0a92d182c1..ba4226e1735 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 70b4e4d1861..de0cf5d6a2e 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -10,7 +10,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" CONFIG_MISC_INIT_R=y -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 85b181d1072..fb7d1065dcf 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -16,7 +16,6 @@ CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig index 4925b148210..6215aa2d619 100644 --- a/configs/tinker-s-rk3288_defconfig +++ b/configs/tinker-s-rk3288_defconfig @@ -15,7 +15,6 @@ CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-tinker-s.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x300000 diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig index e1566ee30a6..acf02078588 100644 --- a/configs/vyasa-rk3288_defconfig +++ b/configs/vyasa-rk3288_defconfig @@ -14,7 +14,6 @@ CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-vyasa.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 From b52a199e323e68ff5cbda4feb03731cb0d39587a Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 9 Jan 2020 14:22:17 +0530 Subject: [PATCH 10/25] arm: rockchip: Add common cru.h Few of the rockchip family SoC atleast rk3288, rk3399 are sharing some cru register bits so adding common code between these SoC families would require to include both cru include files that indeed resulting function declarations error. So, create a common cru include as cru.h then include the rk3399 arch cru include file and move the common cru register bit definitions into it. The rest of rockchip cru files will add it in future. Reviewed-by: Kever Yang Signed-off-by: Jagan Teki --- arch/arm/include/asm/arch-rockchip/clock.h | 4 +- arch/arm/include/asm/arch-rockchip/cru.h | 18 ++++++++ .../include/asm/arch-rockchip/cru_rk3288.h | 6 +-- .../include/asm/arch-rockchip/cru_rk3399.h | 11 +++-- arch/arm/mach-rockchip/rk3288/clk_rk3288.c | 2 +- arch/arm/mach-rockchip/rk3288/rk3288.c | 4 +- arch/arm/mach-rockchip/rk3399/clk_rk3399.c | 2 +- arch/arm/mach-rockchip/rk3399/rk3399.c | 2 +- drivers/clk/rockchip/clk_rk3288.c | 42 +++++++++---------- drivers/clk/rockchip/clk_rk3399.c | 36 ++++++++-------- drivers/ram/rockchip/sdram_rk3288.c | 10 ++--- drivers/ram/rockchip/sdram_rk3399.c | 10 ++--- drivers/video/rockchip/rk3288_mipi.c | 2 +- drivers/video/rockchip/rk3399_mipi.c | 2 +- drivers/video/rockchip/rk_mipi.c | 2 +- 15 files changed, 85 insertions(+), 68 deletions(-) create mode 100644 arch/arm/include/asm/arch-rockchip/cru.h diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 8f7fc86a9eb..22de0aef8dc 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -153,10 +153,10 @@ void *rockchip_get_cru(void); */ void *rockchip_get_pmucru(void); -struct rk3288_cru; +struct rockchip_cru; struct rk3288_grf; -void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf); +void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf); int rockchip_get_clk(struct udevice **devp); diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h new file mode 100644 index 00000000000..475d772fb64 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * (C) Copyright 2019 Amarula Solutions. + * Author: Jagan Teki + */ + +#ifndef _ROCKCHIP_CLOCK_H +#define _ROCKCHIP_CLOCK_H + +#if defined(CONFIG_ROCKCHIP_RK3288) +# include +#elif defined(CONFIG_ROCKCHIP_RK3399) +# include +#endif + +#define MHz 1000000 + +#endif /* _ROCKCHIP_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h index e891f20b373..7aa6efe46c5 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h @@ -27,11 +27,11 @@ /* Private data for the clock driver - used by rockchip_get_cru() */ struct rk3288_clk_priv { struct rk3288_grf *grf; - struct rk3288_cru *cru; + struct rockchip_cru *cru; ulong rate; }; -struct rk3288_cru { +struct rockchip_cru { struct rk3288_pll { u32 con0; u32 con1; @@ -58,7 +58,7 @@ struct rk3288_cru { u32 cru_sdio1_con[2]; u32 cru_emmc_con[2]; }; -check_member(rk3288_cru, cru_emmc_con[1], 0x021c); +check_member(rockchip_cru, cru_emmc_con[1], 0x021c); /* CRU_CLKSEL11_CON */ enum { diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h index 15eeb9c4407..789ca6aa28f 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h @@ -10,7 +10,7 @@ /* Private data for the clock driver - used by rockchip_get_cru() */ struct rk3399_clk_priv { - struct rk3399_cru *cru; + struct rockchip_cru *cru; }; struct rk3399_pmuclk_priv { @@ -33,7 +33,7 @@ struct rk3399_pmucru { }; check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134); -struct rk3399_cru { +struct rockchip_cru { u32 apll_l_con[6]; u32 reserved[2]; u32 apll_b_con[6]; @@ -65,8 +65,7 @@ struct rk3399_cru { u32 sdio0_con[2]; u32 sdio1_con[2]; }; -check_member(rk3399_cru, sdio1_con[1], 0x594); -#define MHz 1000000 +check_member(rockchip_cru, sdio1_con[1], 0x594); #define KHz 1000 #define OSC_HZ (24*MHz) #define LPLL_HZ (600*MHz) @@ -107,9 +106,9 @@ enum apll_b_frequencies { APLL_B_600_MHZ, }; -void rk3399_configure_cpu_l(struct rk3399_cru *cru, +void rk3399_configure_cpu_l(struct rockchip_cru *cru, enum apll_l_frequencies apll_l_freq); -void rk3399_configure_cpu_b(struct rk3399_cru *cru, +void rk3399_configure_cpu_b(struct rockchip_cru *cru, enum apll_b_frequencies apll_b_freq); #endif /* __ASM_ARCH_CRU_RK3399_H_ */ diff --git a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c index e64ee86f081..1730f124439 100644 --- a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include int rockchip_get_clk(struct udevice **devp) { diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index 9572f7ea9c5..47ee5d440b3 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include @@ -104,7 +104,7 @@ void board_debug_uart_init(void) static void rk3288_detect_reset_reason(void) { - struct rk3288_cru *cru = rockchip_get_cru(); + struct rockchip_cru *cru = rockchip_get_cru(); const char *reason; if (IS_ERR(cru)) diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c index f0411c0a21e..a80a46f1dbc 100644 --- a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include static int rockchip_get_cruclk(struct udevice **devp) { diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 863024d0710..dafa142824c 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -240,7 +240,7 @@ static void rk3399_force_power_on_reset(void) void spl_board_init(void) { #if defined(SPL_GPIO_SUPPORT) - struct rk3399_cru *cru = rockchip_get_cru(); + struct rockchip_cru *cru = rockchip_get_cru(); /* * The RK3399 resets only 'almost all logic' (see also in the TRM diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 85d1b67e431..cc1c1e81e95 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include @@ -141,7 +141,7 @@ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1); static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); -static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, +static int rkclk_set_pll(struct rockchip_cru *cru, enum rk_clk_id clk_id, const struct pll_div *div) { int pll_id = rk_pll_id(clk_id); @@ -172,7 +172,7 @@ static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, return 0; } -static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf, +static int rkclk_configure_ddr(struct rockchip_cru *cru, struct rk3288_grf *grf, unsigned int hz) { static const struct pll_div dpll_cfg[] = { @@ -295,7 +295,7 @@ static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div) return 0; } -static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq) +static int rockchip_mac_set_clk(struct rockchip_cru *cru, uint freq) { ulong ret; @@ -333,7 +333,7 @@ static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq) return ret; } -static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf, +static int rockchip_vop_set_clk(struct rockchip_cru *cru, struct rk3288_grf *grf, int periph, unsigned int rate_hz) { struct pll_div npll_config = {0}; @@ -384,7 +384,7 @@ static u32 rockchip_clk_gcd(u32 a, u32 b) return a; } -static ulong rockchip_i2s_get_clk(struct rk3288_cru *cru, uint gclk_rate) +static ulong rockchip_i2s_get_clk(struct rockchip_cru *cru, uint gclk_rate) { unsigned long long rate; uint val; @@ -400,7 +400,7 @@ static ulong rockchip_i2s_get_clk(struct rk3288_cru *cru, uint gclk_rate) return (ulong)rate; } -static ulong rockchip_i2s_set_clk(struct rk3288_cru *cru, uint gclk_rate, +static ulong rockchip_i2s_set_clk(struct rockchip_cru *cru, uint gclk_rate, uint freq) { int n, d; @@ -418,7 +418,7 @@ static ulong rockchip_i2s_set_clk(struct rk3288_cru *cru, uint gclk_rate, } #endif /* CONFIG_SPL_BUILD */ -static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) +static void rkclk_init(struct rockchip_cru *cru, struct rk3288_grf *grf) { u32 aclk_div; u32 hclk_div; @@ -492,7 +492,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); } -void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) +void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf) { /* pll enter slow-mode */ rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, @@ -534,7 +534,7 @@ void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) } /* Get pll rate by id */ -static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru, +static uint32_t rkclk_pll_get_rate(struct rockchip_cru *cru, enum rk_clk_id clk_id) { uint32_t nr, no, nf; @@ -567,7 +567,7 @@ static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru, } } -static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate, +static ulong rockchip_mmc_get_clk(struct rockchip_cru *cru, uint gclk_rate, int periph) { uint src_rate; @@ -601,7 +601,7 @@ static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate, return DIV_TO_RATE(src_rate, div); } -static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate, +static ulong rockchip_mmc_set_clk(struct rockchip_cru *cru, uint gclk_rate, int periph, uint freq) { int src_clk_div; @@ -651,7 +651,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate, return rockchip_mmc_get_clk(cru, gclk_rate, periph); } -static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate, +static ulong rockchip_spi_get_clk(struct rockchip_cru *cru, uint gclk_rate, int periph) { uint div, mux; @@ -681,7 +681,7 @@ static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate, return DIV_TO_RATE(gclk_rate, div); } -static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate, +static ulong rockchip_spi_set_clk(struct rockchip_cru *cru, uint gclk_rate, int periph, uint freq) { int src_clk_div; @@ -715,7 +715,7 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate, return rockchip_spi_get_clk(cru, gclk_rate, periph); } -static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru) +static ulong rockchip_saradc_get_clk(struct rockchip_cru *cru) { u32 div, val; @@ -726,7 +726,7 @@ static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru) return DIV_TO_RATE(OSC_HZ, div); } -static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz) +static ulong rockchip_saradc_set_clk(struct rockchip_cru *cru, uint hz) { int src_clk_div; @@ -785,7 +785,7 @@ static ulong rk3288_clk_get_rate(struct clk *clk) static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate) { struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); - struct rk3288_cru *cru = priv->cru; + struct rockchip_cru *cru = priv->cru; ulong new_rate, gclk_rate; gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); @@ -892,7 +892,7 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate) static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent) { struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); - struct rk3288_cru *cru = priv->cru; + struct rockchip_cru *cru = priv->cru; const char *clock_output_name; int ret; @@ -1008,15 +1008,15 @@ static int rk3288_clk_bind(struct udevice *dev) debug("Warning: No sysreset driver: ret=%d\n", ret); } else { priv = malloc(sizeof(struct sysreset_reg)); - priv->glb_srst_fst_value = offsetof(struct rk3288_cru, + priv->glb_srst_fst_value = offsetof(struct rockchip_cru, cru_glb_srst_fst_value); - priv->glb_srst_snd_value = offsetof(struct rk3288_cru, + priv->glb_srst_snd_value = offsetof(struct rockchip_cru, cru_glb_srst_snd_value); sys_child->priv = priv; } #if CONFIG_IS_ENABLED(RESET_ROCKCHIP) - ret = offsetof(struct rk3288_cru, cru_softrst_con[0]); + ret = offsetof(struct rockchip_cru, cru_softrst_con[0]); ret = rockchip_reset_bind(dev, ret, 12); if (ret) debug("Warning: software reset driver bind faile\n"); diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 9020a9f202a..37fc142a7a8 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include @@ -418,7 +418,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div) return 0; } -void rk3399_configure_cpu_l(struct rk3399_cru *cru, +void rk3399_configure_cpu_l(struct rockchip_cru *cru, enum apll_l_frequencies apll_l_freq) { u32 aclkm_div; @@ -453,7 +453,7 @@ void rk3399_configure_cpu_l(struct rk3399_cru *cru, atclk_div << ATCLK_CORE_L_DIV_SHIFT); } -void rk3399_configure_cpu_b(struct rk3399_cru *cru, +void rk3399_configure_cpu_b(struct rockchip_cru *cru, enum apll_b_frequencies apll_b_freq) { u32 aclkm_div; @@ -505,7 +505,7 @@ void rk3399_configure_cpu_b(struct rk3399_cru *cru, #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \ ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT) -static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) +static ulong rk3399_i2c_get_clk(struct rockchip_cru *cru, ulong clk_id) { u32 div, con; @@ -542,7 +542,7 @@ static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) return DIV_TO_RATE(GPLL_HZ, div); } -static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) +static ulong rk3399_i2c_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz) { int src_clk_div; @@ -619,7 +619,7 @@ static const struct spi_clkreg spi_clkregs[] = { .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, }, }; -static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id) +static ulong rk3399_spi_get_clk(struct rockchip_cru *cru, ulong clk_id) { const struct spi_clkreg *spiclk = NULL; u32 div, val; @@ -641,7 +641,7 @@ static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id) return DIV_TO_RATE(GPLL_HZ, div); } -static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) +static ulong rk3399_spi_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz) { const struct spi_clkreg *spiclk = NULL; int src_clk_div; @@ -668,7 +668,7 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) return rk3399_spi_get_clk(cru, clk_id); } -static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) +static ulong rk3399_vop_set_clk(struct rockchip_cru *cru, ulong clk_id, u32 hz) { struct pll_div vpll_config = {0}; int aclk_vop = 198 * MHz; @@ -712,7 +712,7 @@ static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) return hz; } -static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id) +static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id) { u32 div, con; @@ -739,7 +739,7 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id) return DIV_TO_RATE(GPLL_HZ, div); } -static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, +static ulong rk3399_mmc_set_clk(struct rockchip_cru *cru, ulong clk_id, ulong set_rate) { int src_clk_div; @@ -792,7 +792,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, return rk3399_mmc_get_clk(cru, clk_id); } -static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate) +static ulong rk3399_gmac_set_clk(struct rockchip_cru *cru, ulong rate) { ulong ret; @@ -817,7 +817,7 @@ static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate) } #define PMUSGRF_DDR_RGN_CON16 0xff330040 -static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, +static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru, ulong set_rate) { struct pll_div dpll_cfg; @@ -863,7 +863,7 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, return set_rate; } -static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru) +static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru) { u32 div, val; @@ -874,7 +874,7 @@ static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru) return DIV_TO_RATE(OSC_HZ, div); } -static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz) +static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz) { int src_clk_div; @@ -1071,7 +1071,7 @@ static struct clk_ops rk3399_clk_ops = { }; #ifdef CONFIG_SPL_BUILD -static void rkclk_init(struct rk3399_cru *cru) +static void rkclk_init(struct rockchip_cru *cru) { u32 aclk_div; u32 hclk_div; @@ -1188,15 +1188,15 @@ static int rk3399_clk_bind(struct udevice *dev) debug("Warning: No sysreset driver: ret=%d\n", ret); } else { priv = malloc(sizeof(struct sysreset_reg)); - priv->glb_srst_fst_value = offsetof(struct rk3399_cru, + priv->glb_srst_fst_value = offsetof(struct rockchip_cru, glb_srst_fst_value); - priv->glb_srst_snd_value = offsetof(struct rk3399_cru, + priv->glb_srst_snd_value = offsetof(struct rockchip_cru, glb_srst_snd_value); sys_child->priv = priv; } #if CONFIG_IS_ENABLED(RESET_ROCKCHIP) - ret = offsetof(struct rk3399_cru, softrst_con[0]); + ret = offsetof(struct rockchip_cru, softrst_con[0]); ret = rockchip_reset_bind(dev, ret, 21); if (ret) debug("Warning: software reset driver bind faile\n"); diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c index 3eb14cdb32c..9f6f5551471 100644 --- a/drivers/ram/rockchip/sdram_rk3288.c +++ b/drivers/ram/rockchip/sdram_rk3288.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include @@ -37,7 +37,7 @@ struct dram_info { struct chan_info chan[2]; struct ram_info info; struct clk ddr_clk; - struct rk3288_cru *cru; + struct rockchip_cru *cru; struct rk3288_grf *grf; struct rk3288_sgrf *sgrf; struct rk3288_pmu *pmu; @@ -93,7 +93,7 @@ static void copy_to_reg(u32 *dest, const u32 *src, u32 n) } } -static void ddr_reset(struct rk3288_cru *cru, u32 ch, u32 ctl, u32 phy) +static void ddr_reset(struct rockchip_cru *cru, u32 ch, u32 ctl, u32 phy) { u32 phy_ctl_srstn_shift = 4 + 5 * ch; u32 ctl_psrstn_shift = 3 + 5 * ch; @@ -110,7 +110,7 @@ static void ddr_reset(struct rk3288_cru *cru, u32 ch, u32 ctl, u32 phy) phy << phy_srstn_shift); } -static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n) +static void ddr_phy_ctl_reset(struct rockchip_cru *cru, u32 ch, u32 n) { u32 phy_ctl_srstn_shift = 4 + 5 * ch; @@ -118,7 +118,7 @@ static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n) 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift); } -static void phy_pctrl_reset(struct rk3288_cru *cru, +static void phy_pctrl_reset(struct rockchip_cru *cru, struct rk3288_ddr_publ *publ, int channel) { diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 9c276e13b29..d69ef01d080 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include @@ -66,7 +66,7 @@ struct dram_info { u32 pwrup_srefresh_exit[2]; struct chan_info chan[2]; struct clk ddr_clk; - struct rk3399_cru *cru; + struct rockchip_cru *cru; struct rk3399_grf_regs *grf; struct rk3399_pmu_regs *pmu; struct rk3399_pmucru *pmucru; @@ -228,7 +228,7 @@ static void *get_ddrc0_con(struct dram_info *dram, u8 channel) return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc1_con0; } -static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl, +static void rkclk_ddr_reset(struct rockchip_cru *cru, u32 channel, u32 ctl, u32 phy) { channel &= 0x1; @@ -239,7 +239,7 @@ static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl, &cru->softrst_con[4]); } -static void phy_pctrl_reset(struct rk3399_cru *cru, u32 channel) +static void phy_pctrl_reset(struct rockchip_cru *cru, u32 channel) { rkclk_ddr_reset(cru, channel, 1, 1); udelay(10); @@ -2943,7 +2943,7 @@ static int sdram_init(struct dram_info *dram, for (channel = 0; channel < 2; channel++) { const struct chan_info *chan = &dram->chan[channel]; - struct rk3399_cru *cru = dram->cru; + struct rockchip_cru *cru = dram->cru; struct rk3399_ddr_publ_regs *publ = chan->publ; phy_pctrl_reset(cru, channel); diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c index 7c4a4cc53b0..65891ce45c2 100644 --- a/drivers/video/rockchip/rk3288_mipi.c +++ b/drivers/video/rockchip/rk3288_mipi.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c index a93b73400be..a5b7ba69a8b 100644 --- a/drivers/video/rockchip/rk3399_mipi.c +++ b/drivers/video/rockchip/rk3399_mipi.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index bcd039b7bc6..f9280e86070 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include From ee6321fa14050e54211acd49e8b6890ee15b2518 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 9 Jan 2020 14:22:18 +0530 Subject: [PATCH 11/25] rockchip: Add common reset cause Add cpu reset cause in common cpu-info file. This would help to print the reset cause for various resets. Right now it support rk3288, rk3399. rest of rockchip platforms doesn't have reset cause support ye but this code is more feasible to extend the same. Reviewed-by: Kever Yang Signed-off-by: Jagan Teki --- arch/arm/include/asm/arch-rockchip/cru.h | 12 +++++ .../include/asm/arch-rockchip/cru_rk3288.h | 14 +----- arch/arm/mach-rockchip/cpu-info.c | 49 +++++++++++++++++++ arch/arm/mach-rockchip/rk3288/rk3288.c | 39 --------------- 4 files changed, 62 insertions(+), 52 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h index 475d772fb64..5cf2aec11a7 100644 --- a/arch/arm/include/asm/arch-rockchip/cru.h +++ b/arch/arm/include/asm/arch-rockchip/cru.h @@ -13,6 +13,18 @@ # include #endif +/* CRU_GLB_RST_ST */ +enum { + GLB_POR_RST, + FST_GLB_RST_ST = BIT(0), + SND_GLB_RST_ST = BIT(1), + FST_GLB_TSADC_RST_ST = BIT(2), + SND_GLB_TSADC_RST_ST = BIT(3), + FST_GLB_WDT_RST_ST = BIT(4), + SND_GLB_WDT_RST_ST = BIT(5), + GLB_RST_ST_MASK = GENMASK(5, 0), +}; + #define MHz 1000000 #endif /* _ROCKCHIP_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h index 7aa6efe46c5..412b73e55fa 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h @@ -51,7 +51,7 @@ struct rockchip_cru { u32 cru_glb_cnt_th; u32 cru_glb_rst_con; u32 reserved3; - u32 cru_glb_rst_st; + u32 glb_rst_st; u32 reserved4; u32 cru_sdmmc_con[2]; u32 cru_sdio0_con[2]; @@ -227,16 +227,4 @@ enum { CLKF_MASK = 0x1fff << CLKF_SHIFT, }; -/* CRU_GLB_RST_ST */ -enum { - GLB_POR_RST, - FST_GLB_RST_ST = BIT(0), - SND_GLB_RST_ST = BIT(1), - FST_GLB_TSADC_RST_ST = BIT(2), - SND_GLB_TSADC_RST_ST = BIT(3), - FST_GLB_WDT_RST_ST = BIT(4), - SND_GLB_WDT_RST_ST = BIT(5), - GLB_RST_ST_MASK = GENMASK(5, 0), -}; - #endif diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c index 9bccbd4f68d..4b0e99299a0 100644 --- a/arch/arm/mach-rockchip/cpu-info.c +++ b/arch/arm/mach-rockchip/cpu-info.c @@ -5,10 +5,59 @@ */ #include +#include +#include +#include +#include +#include + +static char *get_reset_cause(void) +{ + struct rockchip_cru *cru = rockchip_get_cru(); + char *cause = NULL; + + if (IS_ERR(cru)) + return cause; + + switch (cru->glb_rst_st) { + case GLB_POR_RST: + cause = "POR"; + break; + case FST_GLB_RST_ST: + case SND_GLB_RST_ST: + cause = "RST"; + break; + case FST_GLB_TSADC_RST_ST: + case SND_GLB_TSADC_RST_ST: + cause = "THERMAL"; + break; + case FST_GLB_WDT_RST_ST: + case SND_GLB_WDT_RST_ST: + cause = "WDOG"; + break; + default: + cause = "unknown reset"; + } + + /** + * reset_reason env is used by rk3288, due to special use case + * to figure it the boot behavior. so keep this as it is. + */ + env_set("reset_reason", cause); + + /* + * Clear glb_rst_st, so we can determine the last reset cause + * for following resets. + */ + rk_clrreg(&cru->glb_rst_st, GLB_RST_ST_MASK); + + return cause; +} int print_cpuinfo(void) { printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC); + printf("Reset cause: %s\n", get_reset_cause()); /* TODO print operating temparature and clock */ diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index 47ee5d440b3..18ea7f35fbf 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -102,43 +102,6 @@ void board_debug_uart_init(void) } #endif -static void rk3288_detect_reset_reason(void) -{ - struct rockchip_cru *cru = rockchip_get_cru(); - const char *reason; - - if (IS_ERR(cru)) - return; - - switch (cru->cru_glb_rst_st) { - case GLB_POR_RST: - reason = "POR"; - break; - case FST_GLB_RST_ST: - case SND_GLB_RST_ST: - reason = "RST"; - break; - case FST_GLB_TSADC_RST_ST: - case SND_GLB_TSADC_RST_ST: - reason = "THERMAL"; - break; - case FST_GLB_WDT_RST_ST: - case SND_GLB_WDT_RST_ST: - reason = "WDOG"; - break; - default: - reason = "unknown reset"; - } - - env_set("reset_reason", reason); - - /* - * Clear cru_glb_rst_st, so we can determine the last reset cause - * for following resets. - */ - rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK); -} - __weak int rk3288_board_late_init(void) { return 0; @@ -146,8 +109,6 @@ __weak int rk3288_board_late_init(void) int rk_board_late_init(void) { - rk3288_detect_reset_reason(); - return rk3288_board_late_init(); } From efebc8edd6a477fdc160c0f504078488c5618c30 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 9 Jan 2020 14:22:19 +0530 Subject: [PATCH 12/25] rockchip: rk3399: Add bootcount support Add bootcount support for Rockchip rk3399. The bootcount value is preserved in PMU_SYS_REG0 register, this would help to support redundent boot. Once the redundant boot triggers, the altboot command will look for extlinux-rollback.conf on particular bootable partition which supposed to be a recovery partition where redundant boot required. Reviewed-by: Kever Yang Signed-off-by: Jagan Teki --- arch/arm/mach-rockchip/Kconfig | 2 ++ arch/arm/mach-rockchip/rk3399/Kconfig | 10 ++++++++++ include/configs/rk3399_common.h | 5 ++++- 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index b689a420bdb..2f260a5c5f1 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -244,6 +244,8 @@ config ROCKCHIP_RK3399 imply TPL_CLK imply TPL_TINY_MEMSET imply TPL_ROCKCHIP_COMMON_BOARD + imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT + imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 and quad-core Cortex-A53. diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 868e85fc2a0..f9941528035 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -113,6 +113,16 @@ config TPL_TEXT_BASE config SPL_STACK_R_ADDR default 0x04000000 +if BOOTCOUNT_LIMIT + +config BOOTCOUNT_BOOTLIMIT + default 3 + +config SYS_BOOTCOUNT_ADDR + default 0xff3100f0 # PMU_SYS_REG0 + +endif # BOOTCOUNT_LIMIT + source "board/rockchip/evb_rk3399/Kconfig" source "board/theobroma-systems/puma_rk3399/Kconfig" source "board/vamrs/rock960_rk3399/Kconfig" diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 127ca1f09cd..89a8a44bbe2 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -63,7 +63,10 @@ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ ROCKCHIP_DEVICE_SETTINGS \ - BOOTENV + BOOTENV \ + "altbootcmd=" \ + "setenv boot_syslinux_conf extlinux/extlinux-rollback.conf;" \ + "run distro_bootcmd\0" #endif From b1022d5f2963bd5d8250725ebf2f96eaf39a393f Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 10 Jan 2020 00:16:16 +0530 Subject: [PATCH 13/25] Makefile: Add rockchip image type Add rockchip image type support. right now the image type marked with rksd, So create image type variable with required image type like rksd or rkspi. Cc: Matwey V. Kornilov Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- Makefile | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index f4de30b6dfc..7947f346047 100644 --- a/Makefile +++ b/Makefile @@ -1378,7 +1378,15 @@ u-boot-with-spl.bin: $(SPL_IMAGE) $(SPL_PAYLOAD) FORCE $(call if_changed,pad_cat) ifeq ($(CONFIG_ARCH_ROCKCHIP),y) -MKIMAGEFLAGS_u-boot-tpl.img = -n $(CONFIG_SYS_SOC) -T rksd + +# rockchip image type +ifeq ($(CONFIG_SPL_SPI_LOAD),y) +ROCKCHIP_IMG_TYPE := rkspi +else +ROCKCHIP_IMG_TYPE := rksd +endif + +MKIMAGEFLAGS_u-boot-tpl.img = -n $(CONFIG_SYS_SOC) -T $(ROCKCHIP_IMG_TYPE) tpl/u-boot-tpl.img: tpl/u-boot-tpl.bin FORCE $(call if_changed,mkimage) idbloader.img: tpl/u-boot-tpl.img spl/u-boot-spl.bin FORCE From 3029a7bb06f71901bfc9ac7420db8301b3c44e21 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 10 Jan 2020 00:16:17 +0530 Subject: [PATCH 14/25] Makefile: rockchip: Suffix platform type with tpl name Most of the platforms uses the platform type on their boot stage image naming conventions in makefile like, u-boot-x86-start16-tpl.bin - x86 start16 TPL bin u-boot-spl-mtk.bin - Mediatek SPL bin This would help to understand the users to what that particular image belongs to? and less confused. On that note, suffix platform type rockchip for existing u-boot-tpl.img so now it become u-boot-tpl-rockchip.bin Also, bin is more conventional way to include it on tools like binman, pad_cat etc in future patches. Note: usage of platform type doesn't follow consistent order as of now. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index 7947f346047..4eeba6f1360 100644 --- a/Makefile +++ b/Makefile @@ -1386,10 +1386,10 @@ else ROCKCHIP_IMG_TYPE := rksd endif -MKIMAGEFLAGS_u-boot-tpl.img = -n $(CONFIG_SYS_SOC) -T $(ROCKCHIP_IMG_TYPE) -tpl/u-boot-tpl.img: tpl/u-boot-tpl.bin FORCE +MKIMAGEFLAGS_u-boot-tpl-rockchip.bin = -n $(CONFIG_SYS_SOC) -T $(ROCKCHIP_IMG_TYPE) +tpl/u-boot-tpl-rockchip.bin: tpl/u-boot-tpl.bin FORCE $(call if_changed,mkimage) -idbloader.img: tpl/u-boot-tpl.img spl/u-boot-spl.bin FORCE +idbloader.img: tpl/u-boot-tpl-rockchip.bin spl/u-boot-spl.bin FORCE $(call if_changed,cat) endif From 66ffe317871e01db6ee8ba6cb69ec8a025d00c3d Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 10 Jan 2020 00:16:18 +0530 Subject: [PATCH 15/25] Makefile: rockchip: Support SPL-alone mkimage Add SPL-alone mkimage tooling support via Makefile for few platforms or boards used in rockchip family. With this users would get rid of explicitly creating mkimage tool for rockchip rksd or rkspi boot modes. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- Makefile | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 4eeba6f1360..be7292d485e 100644 --- a/Makefile +++ b/Makefile @@ -911,7 +911,7 @@ ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy) ALL-y += u-boot-with-dtb.bin endif -ifeq ($(CONFIG_ARCH_ROCKCHIP)$(CONFIG_SPL)$(CONFIG_TPL),yyy) +ifeq ($(CONFIG_ARCH_ROCKCHIP)$(CONFIG_SPL),yy) ALL-y += idbloader.img endif @@ -1386,11 +1386,19 @@ else ROCKCHIP_IMG_TYPE := rksd endif +# TPL + SPL +ifeq ($(CONFIG_SPL)$(CONFIG_TPL),yy) MKIMAGEFLAGS_u-boot-tpl-rockchip.bin = -n $(CONFIG_SYS_SOC) -T $(ROCKCHIP_IMG_TYPE) tpl/u-boot-tpl-rockchip.bin: tpl/u-boot-tpl.bin FORCE $(call if_changed,mkimage) idbloader.img: tpl/u-boot-tpl-rockchip.bin spl/u-boot-spl.bin FORCE $(call if_changed,cat) +else +MKIMAGEFLAGS_idbloader.img = -n $(CONFIG_SYS_SOC) -T $(ROCKCHIP_IMG_TYPE) +idbloader.img: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) +endif + endif ifeq ($(CONFIG_ARCH_LPC32XX)$(CONFIG_SPL),yy) From f48299a883884f43a7bc5f530b696a44ab675aed Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 10 Jan 2020 00:16:19 +0530 Subject: [PATCH 16/25] arm: dts: rk3036: Add rk3036-u-boot.dtsi Add U-Boot specific dtsi file for rk3036 SoC. This would help to add U-Boot specific dts nodes, properties which are common across rk3036. Right now, the file is empty, will add required changes in future patches. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3036-sdk-u-boot.dtsi | 2 ++ arch/arm/dts/rk3036-u-boot.dtsi | 4 ++++ 2 files changed, 6 insertions(+) create mode 100644 arch/arm/dts/rk3036-u-boot.dtsi diff --git a/arch/arm/dts/rk3036-sdk-u-boot.dtsi b/arch/arm/dts/rk3036-sdk-u-boot.dtsi index 6f15f4a8ec7..754800c6e69 100644 --- a/arch/arm/dts/rk3036-sdk-u-boot.dtsi +++ b/arch/arm/dts/rk3036-sdk-u-boot.dtsi @@ -1,3 +1,5 @@ +#include "rk3036-u-boot.dtsi" + &uart2 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rk3036-u-boot.dtsi b/arch/arm/dts/rk3036-u-boot.dtsi new file mode 100644 index 00000000000..1e7d079315a --- /dev/null +++ b/arch/arm/dts/rk3036-u-boot.dtsi @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ From a1b75cf94141b2dd9806224b95ea21d025ef06a4 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 10 Jan 2020 00:16:20 +0530 Subject: [PATCH 17/25] arm: dts: rk3188: Add rk3188-u-boot.dtsi Add U-Boot specific dtsi file for rk3188 SoC. This would help to add U-Boot specific dts nodes, properties which are common across rk3188. Right now, the file is empty, will add required changes in future patches. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3188-radxarock-u-boot.dtsi | 2 ++ arch/arm/dts/rk3188-u-boot.dtsi | 4 ++++ 2 files changed, 6 insertions(+) create mode 100644 arch/arm/dts/rk3188-u-boot.dtsi diff --git a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi index 1bb5408592e..204bb3a90ee 100644 --- a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi +++ b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. */ +#include "rk3188-u-boot.dtsi" + &cru { u-boot,dm-spl; }; diff --git a/arch/arm/dts/rk3188-u-boot.dtsi b/arch/arm/dts/rk3188-u-boot.dtsi new file mode 100644 index 00000000000..1e7d079315a --- /dev/null +++ b/arch/arm/dts/rk3188-u-boot.dtsi @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ From 79030a486128bdb6888059113711a6ae66ff89c5 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 10 Jan 2020 00:16:21 +0530 Subject: [PATCH 18/25] rockchip: Add Single boot image (with binman, pad_cat) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All rockchip platforms support TPL or SPL-based bootloader in mainline with U-Boot proper as final stage. For each stage we need to burn the image on to flash with respective offsets. This patch creates a single boot image component using - binman, for arm32 rockchip platforms - pad_cat, for arm64 rockchip platforms. This would help users to get rid of burning different boot stage images. The new image called 'u-boot-rockchip.bin' which can burn into flash like: ₹ sudo dd if=u-boot-rockchip.bin of=/dev/sda seek=64 This would support all rockchip platforms, except rk3128 since it doesn't support for SPL yet. Cc: Matwey V. Kornilov Cc: Wadim Egorov Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- Makefile | 14 ++++++++++++-- arch/arm/Kconfig | 1 + arch/arm/dts/rk3036-u-boot.dtsi | 2 ++ arch/arm/dts/rk3188-u-boot.dtsi | 2 ++ arch/arm/dts/rk3288-u-boot.dtsi | 2 ++ arch/arm/dts/rockchip-u-boot.dtsi | 21 +++++++++++++++++++++ configs/phycore-rk3288_defconfig | 2 -- include/configs/rockchip-common.h | 3 +++ 8 files changed, 43 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/rockchip-u-boot.dtsi diff --git a/Makefile b/Makefile index be7292d485e..b21a143e497 100644 --- a/Makefile +++ b/Makefile @@ -912,7 +912,7 @@ ALL-y += u-boot-with-dtb.bin endif ifeq ($(CONFIG_ARCH_ROCKCHIP)$(CONFIG_SPL),yy) -ALL-y += idbloader.img +ALL-y += u-boot-rockchip.bin endif LDFLAGS_u-boot += $(LDFLAGS_FINAL) @@ -1399,7 +1399,17 @@ idbloader.img: spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) endif -endif +ifeq ($(CONFIG_ARM64),) +u-boot-rockchip.bin: idbloader.img u-boot.img FORCE + $(call if_changed,binman) +else +OBJCOPYFLAGS_u-boot-rockchip.bin = -I binary -O binary \ + --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff +u-boot-rockchip.bin: idbloader.img u-boot.itb FORCE + $(call if_changed,pad_cat) +endif # CONFIG_ARM64 + +endif # CONFIG_ARCH_ROCKCHIP ifeq ($(CONFIG_ARCH_LPC32XX)$(CONFIG_SPL),yy) MKIMAGEFLAGS_lpc32xx-spl.img = -T lpc32xximage -a $(CONFIG_SPL_TEXT_BASE) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 12363151688..6353b1bab3f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1625,6 +1625,7 @@ config ARCH_STM32MP config ARCH_ROCKCHIP bool "Support Rockchip SoCs" select BLK + select BINMAN if !ARM64 select DM select DM_GPIO select DM_I2C diff --git a/arch/arm/dts/rk3036-u-boot.dtsi b/arch/arm/dts/rk3036-u-boot.dtsi index 1e7d079315a..41ac054b81e 100644 --- a/arch/arm/dts/rk3036-u-boot.dtsi +++ b/arch/arm/dts/rk3036-u-boot.dtsi @@ -2,3 +2,5 @@ /* * Copyright (C) 2019 Jagan Teki */ + +#include "rockchip-u-boot.dtsi" diff --git a/arch/arm/dts/rk3188-u-boot.dtsi b/arch/arm/dts/rk3188-u-boot.dtsi index 1e7d079315a..41ac054b81e 100644 --- a/arch/arm/dts/rk3188-u-boot.dtsi +++ b/arch/arm/dts/rk3188-u-boot.dtsi @@ -2,3 +2,5 @@ /* * Copyright (C) 2019 Jagan Teki */ + +#include "rockchip-u-boot.dtsi" diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index 3f00a3b6d35..6d31735362d 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2019 Rockchip Electronics Co., Ltd */ +#include "rockchip-u-boot.dtsi" + / { chosen { u-boot,spl-boot-order = \ diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi new file mode 100644 index 00000000000..a2559e2db08 --- /dev/null +++ b/arch/arm/dts/rockchip-u-boot.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +#include + +/ { + binman { + filename = "u-boot-rockchip.bin"; + pad-byte = <0xff>; + + blob { + filename = "idbloader.img"; + }; + + u-boot-img { + offset = ; + }; + }; +}; diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index c8345013c74..8c1bd20deca 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -19,8 +19,6 @@ CONFIG_DEFAULT_FDT_FILE="rk3288-phycore-rdk.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 68e1105a4b1..b55e09a9ca1 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -9,6 +9,9 @@ #define CONFIG_SYS_NS16550_MEM32 +/* ((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512) */ +#define CONFIG_SPL_PAD_TO 8355840 + #ifndef CONFIG_SPL_BUILD /* First try to boot from SD (index 0), then eMMC (index 1) */ From 338b86c9b3058c17c272ac4eb82ddb566e33a023 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 10 Jan 2020 00:16:22 +0530 Subject: [PATCH 19/25] doc: boards: Add rockchip documentation Rockchip has documentation file, doc/README.rockchip but which is not so readable to add or understand the existing contents. Even the format that support is legacy readme in U-Boot. Add rockchip specific documentation file using new rst format, which describes the information about Rockchip supported boards and it's usage steps. Added minimal information about rk3288, rk3328, rk3368 and rk3399 boards and usage. This would indeed updated further based on the requirements and updates. Cc: Kever Yang Cc: Matwey V. Kornilov Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- doc/board/rockchip/index.rst | 10 +++ doc/board/rockchip/rockchip.rst | 130 ++++++++++++++++++++++++++++++++ 2 files changed, 140 insertions(+) create mode 100644 doc/board/rockchip/index.rst create mode 100644 doc/board/rockchip/rockchip.rst diff --git a/doc/board/rockchip/index.rst b/doc/board/rockchip/index.rst new file mode 100644 index 00000000000..0c377e9bbba --- /dev/null +++ b/doc/board/rockchip/index.rst @@ -0,0 +1,10 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright (C) 2019 Jagan Teki + +Rockchip +======== + +.. toctree:: + :maxdepth: 2 + + rockchip diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst new file mode 100644 index 00000000000..cd9c8d6dc47 --- /dev/null +++ b/doc/board/rockchip/rockchip.rst @@ -0,0 +1,130 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright (C) 2019 Jagan Teki + +ROCKCHIP +======== + +About this +---------- + +This document describes the information about Rockchip supported boards +and it's usage steps. + +Rockchip boards +--------------- + +Rockchip is SoC solutions provider for tablets & PCs, streaming media +TV boxes, AI audio & vision, IoT hardware. + +A wide range of Rockchip SoCs with associated boardsare supported in +mainline U-Boot. + +List of mainline supported rockchip boards: + +* rk3288 + - Evb-RK3288 + - Firefly-RK3288 + - mqmaker MiQi + - Phytec RK3288 PCM-947 + - PopMetal-RK3288 + - Radxa Rock 2 Square + - Tinker-RK3288 + - Google Jerry + - Google Mickey + - Google Minnie + - Google Speedy + - Amarula Vyasa-RK3288 +* rk3328 + - Rockchip RK3328 EVB + - Pine64 Rock64 +* rk3368 + - GeekBox + - PX5 EVB + - Rockchip sheep board + - Theobroma Systems RK3368-uQ7 SoM +* rk3399 + - 96boards RK3399 Ficus + - 96boards Rock960 + - Firefly-RK3399 Board + - Firefly ROC-RK3399-PC Board + - FriendlyElec NanoPC-T4 + - FriendlyElec NanoPi M4 + - FriendlyARM NanoPi NEO4 + - Google Bob + - Khadas Edge + - Khadas Edge-Captain + - Khadas Edge-V + - Orange Pi RK3399 Board + - Pine64 RockPro64 + - Radxa ROCK Pi 4 + - Rockchip RK3399 Evaluation Board + - Theobroma Systems RK3399-Q7 SoM + +Building +-------- + +TF-A +^^^^ + +TF-A would require to build for ARM64 Rockchip SoCs platforms. + +To build TF-A:: + + git clone https://github.com/ARM-software/arm-trusted-firmware.git + cd arm-trusted-firmware + make realclean + make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 + +Specify the PLAT= with desired rockchip platform to build TF-A for. + +U-Boot +^^^^^^ + +To build rk3328 boards:: + + export BL31=/path/to/arm-trusted-firmware/to/bl31.elf + make evb-rk3328_defconfig + make + +To build rk3288 boards:: + + make evb-rk3288_defconfig + make + +To build rk3368 boards:: + + export BL31=/path/to/arm-trusted-firmware/to/bl31.elf + make evb-px5_defconfig + make + +To build rk3399 boards:: + + export BL31=/path/to/arm-trusted-firmware/to/bl31.elf + make evb-rk3399_defconfig + make + +Flashing +-------- + +SD Card +^^^^^^^ + +All rockchip platforms, except rk3128 (which doesn't use SPL) are now +supporting single boot image using binman and pad_cat. + +To write an image that boots from an SD card (assumed to be /dev/sda):: + + sudo dd if=u-boot-rockchip.bin of=/dev/sda seek=64 + sync + +TODO +---- + +- Add rockchip idbloader image building +- Add rockchip TPL image building +- Document SPI flash boot +- Describe steps for eMMC flashing +- Add missing SoC's with it boards list + +.. Jagan Teki +.. Fri Jan 10 00:08:40 IST 2020 From 31531f6fdb22ab0e938f465e799d8191733981ae Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 7 Jan 2020 15:15:20 +0800 Subject: [PATCH 20/25] ram: rk3328: only do data traning for cs0 No need to do twice data training for rk3328 ddr sdram, we re-use the setting for both channel. And adjust the sdram_init properly for correct init flow. Signed-off-by: Kever Yang Signed-off-by: YouMin Chen --- drivers/ram/rockchip/sdram_rk3328.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index 69521cef699..8329f4a352f 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -377,16 +377,12 @@ static int sdram_init(struct dram_info *dram, printf("data training error\n"); return -1; } - if (data_training(dram, 1, sdram_params->base.dramtype) != 0) { - printf("data training error\n"); - return -1; - } if (sdram_params->base.dramtype == DDR4) pctl_write_vrefdq(dram->pctl, 0x3, 5670, sdram_params->base.dramtype); - if (pre_init == 0) { + if (pre_init != 0) { rx_deskew_switch_adjust(dram); tx_deskew_switch_adjust(dram); } @@ -482,7 +478,7 @@ static int sdram_init_detect(struct dram_info *dram, memcpy(&sdram_ch, &sdram_params->ch, sizeof(struct rk3328_sdram_channel)); - sdram_init(dram, sdram_params, 1); + sdram_init(dram, sdram_params, 0); dram_detect_cap(dram, sdram_params, 0); /* modify bw, cs related timing */ @@ -495,7 +491,7 @@ static int sdram_init_detect(struct dram_info *dram, sdram_ch.noc_timings.ddrtiming.b.bwratio = 1; /* reinit sdram by real dram cap */ - sdram_init(dram, sdram_params, 0); + sdram_init(dram, sdram_params, 1); /* redetect cs1 row */ sdram_detect_cs1_row(cap_info, sdram_params->base.dramtype); From c7df6483c2484073c6953885886c4aa8aad84890 Mon Sep 17 00:00:00 2001 From: YouMin Chen Date: Tue, 7 Jan 2020 15:15:21 +0800 Subject: [PATCH 21/25] ram: rk3328: add support ddr4 init Add rk3328-sdram-ddr4-666.dtsi for support ddr4 init. Signed-off-by: YouMin Chen Signed-off-by: Kever Yang --- arch/arm/dts/rk3328-sdram-ddr4-666.dtsi | 216 ++++++++++++++++++++++++ 1 file changed, 216 insertions(+) create mode 100644 arch/arm/dts/rk3328-sdram-ddr4-666.dtsi diff --git a/arch/arm/dts/rk3328-sdram-ddr4-666.dtsi b/arch/arm/dts/rk3328-sdram-ddr4-666.dtsi new file mode 100644 index 00000000000..0859649a690 --- /dev/null +++ b/arch/arm/dts/rk3328-sdram-ddr4-666.dtsi @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. + +&dmc { + rockchip,sdram-params = < + 0x1 + 0xA + 0x2 + 0x1 + 0x0 + 0x0 + 0x11 + 0x0 + 0x11 + 0x0 + 0 + + 0x94291288 + 0x00000000 + 0x00000027 + 0x00000462 + 0x00000015 + 0x00000242 + 0x000000ff + + 333 + 0 + 1 + 0 + 0 + + 0x00000000 + 0x43049010 + 0x00000064 + 0x0028003b + 0x000000d0 + 0x00020053 + 0x000000d4 + 0x00220000 + 0x000000d8 + 0x00000100 + 0x000000dc + 0x00040000 + 0x000000e0 + 0x00000000 + 0x000000e4 + 0x00110000 + 0x000000e8 + 0x00000420 + 0x000000ec + 0x00000400 + 0x000000f4 + 0x000f011f + 0x00000100 + 0x09060b06 + 0x00000104 + 0x00020209 + 0x00000108 + 0x0505040a + 0x0000010c + 0x0040400c + 0x00000110 + 0x05030206 + 0x00000114 + 0x03030202 + 0x00000120 + 0x03030b03 + 0x00000124 + 0x00020208 + 0x00000180 + 0x01000040 + 0x00000184 + 0x00000000 + 0x00000190 + 0x07030003 + 0x00000198 + 0x05001100 + 0x000001a0 + 0xc0400003 + 0x00000240 + 0x06000604 + 0x00000244 + 0x00000201 + 0x00000250 + 0x00000f00 + 0x00000490 + 0x00000001 + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + + 0x00000004 + 0x0000000c + 0x00000028 + 0x0000000a + 0x0000002c + 0x00000000 + 0x00000030 + 0x00000009 + 0xffffffff + 0xffffffff + + 0x77 + 0x88 + 0x79 + 0x79 + 0x87 + 0x97 + 0x87 + 0x78 + 0x77 + 0x78 + 0x87 + 0x88 + 0x87 + 0x87 + 0x77 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x79 + 0x9 + >; +}; From 4082a6814235d81a21a1bfe9bfa8ca99c69d8fa8 Mon Sep 17 00:00:00 2001 From: YouMin Chen Date: Tue, 7 Jan 2020 15:15:22 +0800 Subject: [PATCH 22/25] ram: rk3328: update lpddr3 setting update lpddr3 setting for fix init fail about "col error". Signed-off-by: YouMin Chen Signed-off-by: Kever Yang --- arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi b/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi index b9d3b3b9485..df42bb29ce8 100644 --- a/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi +++ b/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi @@ -18,7 +18,7 @@ 0x10 0 - 0x0c48a18a + 0x8c48a18a 0x00000000 0x00000021 0x00000482 @@ -33,7 +33,7 @@ 0 0x00000000 - 0xc3040008 + 0x43041008 0x00000064 0x00140023 0x000000d0 @@ -48,6 +48,8 @@ 0x00010000 0x000000e4 0x00070003 + 0x000000f4 + 0x000f011f 0x00000100 0x06090b07 0x00000104 @@ -90,8 +92,6 @@ 0xffffffff 0xffffffff 0xffffffff - 0xffffffff - 0xffffffff 0x00000004 0x0000000b From 3c176ea7cef3de1e047d2572cd5bcc0171b97338 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 7 Jan 2020 16:59:39 +0800 Subject: [PATCH 23/25] rockchip: px30: remove CONFIG_OPTEE support Rockchip use CONFIG_SPL_OPTEE for OPTEE support, which is load and run before U-Boot, but not use CONFIG_OPTEE which is after U-Boot. Signed-off-by: Kever Yang --- configs/evb-px30_defconfig | 1 - configs/firefly-px30_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index d83cc6f4dbc..912ea95223c 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -90,7 +90,6 @@ CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SOUND=y CONFIG_SYSRESET=y -CONFIG_OPTEE=y CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig index 9564a01c644..5ed60379bfc 100644 --- a/configs/firefly-px30_defconfig +++ b/configs/firefly-px30_defconfig @@ -91,7 +91,6 @@ CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SOUND=y CONFIG_SYSRESET=y -CONFIG_OPTEE=y CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y From a7eb9ae349a3b7d0c44c2afa073e5df14d2a18f6 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Wed, 8 Jan 2020 17:38:48 +0800 Subject: [PATCH 24/25] rockchip: rk3308: add alias for emmc/sdmmc Add alias for mmc/sdmmc so that we can have a fix mmc number for emmc. Signed-off-by: Kever Yang Reviewed-by: Jagan Teki --- arch/arm/dts/rk3308-u-boot.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi index f5a595337e5..4bfad31fbab 100644 --- a/arch/arm/dts/rk3308-u-boot.dtsi +++ b/arch/arm/dts/rk3308-u-boot.dtsi @@ -3,6 +3,13 @@ *(C) Copyright 2019 Rockchip Electronics Co., Ltd */ +/ { + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + }; +}; + &cru { u-boot,dm-pre-reloc; }; From c8343e93220a487f332441cff780a702ca2ce3a9 Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Mon, 13 Jan 2020 11:39:16 +0100 Subject: [PATCH 25/25] configs: firefly-rk3399: Enable CONFIG_MISC_INIT_R and ROCKCHIP_EFUSE This enables readning the cpuid from e-fuse, and deriving a static MAC address from it. Signed-off-by: Mark Kettenis Reviewed-by: Kever Yang --- configs/firefly-rk3399_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 0d95a5ff49c..bc15eae64bd 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -8,6 +8,7 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" +CONFIG_MISC_INIT_R=y CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y @@ -26,6 +27,8 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y