mirrors/u-boot
1
0
Fork 0
mirror of https://source.denx.de/u-boot/u-boot.git synced 2025-11-28 14:11:29 +01:00
Code Issues Actions Packages Projects Releases Wiki Activity

ARM: tegra: enable PLLX only once it's been fully configured

Browse Source 
This programming sequence is correct per Jimmy Zhang, and makes sense
too!

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Stephen Warren 2014-01-24 12:46:09 -07:00 committed by Tom Warren
parent cad38a57d3
commit 41447fb2cf
1 changed files with 9 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
arch/arm/cpu/arm720t/tegra-common/cpu.c
View File

@ -144,18 +144,23 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
reg |= (1 << PLL_DCCON_SHIFT); reg |= (1 << PLL_DCCON_SHIFT);
writel(reg, &pll->pll_misc); writel(reg, &pll->pll_misc);
/* Enable PLLX */
reg = readl(&pll->pll_base);
reg |= PLL_ENABLE_MASK;
/* Disable BYPASS */ /* Disable BYPASS */
reg = readl(&pll->pll_base);
reg &= ~PLL_BYPASS_MASK; reg &= ~PLL_BYPASS_MASK;
writel(reg, &pll->pll_base); writel(reg, &pll->pll_base);
debug("pllx_set_rate: base = 0x%08X\n", reg);
/* Set lock_enable to PLLX_MISC */ /* Set lock_enable to PLLX_MISC */
reg = readl(&pll->pll_misc); reg = readl(&pll->pll_misc);
reg |= PLL_LOCK_ENABLE_MASK; reg |= PLL_LOCK_ENABLE_MASK;
writel(reg, &pll->pll_misc); writel(reg, &pll->pll_misc);
debug("pllx_set_rate: misc = 0x%08X\n", reg);
/* Enable PLLX last, once it's all configured */
reg = readl(&pll->pll_base);
reg |= PLL_ENABLE_MASK;
writel(reg, &pll->pll_base);
debug("pllx_set_rate: base final = 0x%08X\n", reg);
return 0; return 0;
} }