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mtd: nand: Add support for EDO mode 1-5 to IMX6ULL platform

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The clock driver allows to boost the NAND performance
controller. Make changes to let it use the new clock driver

=> time nand read ${loadaddr} kernel

NAND read: device 0 offset 0x500000, size 0x800000
 8388608 bytes read: OK

time: 0.488 seconds

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
This commit is contained in:
Michael Trimarchi 2025-05-30 17:16:45 +02:00 committed by Fabio Estevam
parent 1c513b9edf
commit 404a4c84d8
2 changed files with 11 additions and 1 deletions
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10
drivers/mtd/nand/raw/mxs_nand.c
View File

@ -1507,8 +1507,18 @@ static void mxs_compute_timings(struct nand_chip *chip,
writel(GPMI_CTRL1_CLEAR_MASK, &nand_info->gpmi_regs->hw_gpmi_ctrl1_clr);
writel(ctrl1n, &nand_info->gpmi_regs->hw_gpmi_ctrl1_set);
/* Clock dividers do NOT guarantee a clean clock signal on its output
* during the change of the divide factor on i.MX6Q/UL/SX. On i.MX7/8,
* all clock dividers provide these guarantee.
*/
if (IS_ENABLED(CONFIG_MX6ULL))
clk_disable(nand_info->gpmi_clk);
clk_set_rate(nand_info->gpmi_clk, clk_rate);
if (IS_ENABLED(CONFIG_MX6ULL))
clk_enable(nand_info->gpmi_clk);
/* Wait 64 clock cycles before using the GPMI after enabling the DLL */
dll_wait_time_us = USEC_PER_SEC / clk_rate * 64;
if (!dll_wait_time_us)

2
drivers/mtd/nand/raw/mxs_nand_dt.c
View File

@ -99,7 +99,7 @@ static int mxs_nand_dt_probe(struct udevice *dev)
info->use_minimum_ecc = dev_read_bool(dev, "fsl,use-minimum-ecc");
if (IS_ENABLED(CONFIG_CLK) &&
(IS_ENABLED(CONFIG_IMX8) || IS_ENABLED(CONFIG_IMX8M))) {
(IS_ENABLED(CONFIG_IMX8) || IS_ENABLED(CONFIG_IMX8M) || IS_ENABLED(CONFIG_MX6ULL))) {
struct clk_bulk clk_bulk;
info->gpmi_clk = devm_clk_get(dev, "gpmi_io");