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sunxi: clock: D1/R528: Enable PLL LDO during PLL1 setup

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The D1/R528/T113s SoCs introduce a new "LDO enable" bit in the CPUX_PLL.
Just enable that when we program that PLL.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Andre Przywara 2022-12-02 20:30:40 +00:00
parent b9a91b98e8
commit 39ba474698
2 changed files with 8 additions and 5 deletions
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1
arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
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@ -228,6 +228,7 @@ struct sunxi_ccm_reg {
/* pll1 bit field */ /* pll1 bit field */
#define CCM_PLL1_CTRL_EN BIT(31) #define CCM_PLL1_CTRL_EN BIT(31)
#define CCM_PLL1_LDO_EN BIT(30)
#define CCM_PLL1_LOCK_EN BIT(29) #define CCM_PLL1_LOCK_EN BIT(29)
#define CCM_PLL1_LOCK BIT(28) #define CCM_PLL1_LOCK BIT(28)
#define CCM_PLL1_OUT_EN BIT(27) #define CCM_PLL1_OUT_EN BIT(27)

12
arch/arm/mach-sunxi/clock_sun50i_h6.c
View File

@ -89,11 +89,13 @@ void clock_set_pll1(unsigned int clk)
writel(val, &ccm->cpu_axi_cfg); writel(val, &ccm->cpu_axi_cfg);
/* clk = 24*n/p, p is ignored if clock is >288MHz */ /* clk = 24*n/p, p is ignored if clock is >288MHz */
writel(CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2 | val = CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2;
#ifdef CONFIG_MACH_SUN50I_H616 val |= CCM_PLL1_CTRL_N(clk / 24000000);
CCM_PLL1_OUT_EN | if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
#endif val |= CCM_PLL1_OUT_EN;
CCM_PLL1_CTRL_N(clk / 24000000), &ccm->pll1_cfg); if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
val |= CCM_PLL1_OUT_EN | CCM_PLL1_LDO_EN;
writel(val, &ccm->pll1_cfg);
while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {} while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {}
/* Switch CPU to PLL1 */ /* Switch CPU to PLL1 */