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Prepare v2025.07-rc3

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Merge tag 'v2025.07-rc3' into next

Prepare v2025.07-rc3
This commit is contained in:
Tom Rini 2025-05-26 16:07:19 -06:00
commit 39b815d02d
145 changed files with 4066 additions and 956 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.azure-pipelines.yml
View File

@ -92,7 +92,7 @@ stages:
set -e
python3 -m venv /tmp/venvhtml
. /tmp/venvhtml/bin/activate
pip install -r doc/sphinx/requirements.txt pytest
pip install -r doc/sphinx/requirements.txt -r test/py/requirements.txt
make htmldocs KDOC_WERROR=1
make infodocs

2
.gitlab-ci.yml
View File

@ -164,7 +164,7 @@ docs:
script:
- python3 -m venv /tmp/venvhtml
- . /tmp/venvhtml/bin/activate
- pip install -r doc/sphinx/requirements.txt pytest
- pip install -r doc/sphinx/requirements.txt -r test/py/requirements.txt
- make htmldocs KDOC_WERROR=1
- make infodocs

1
.readthedocs.yml
View File

@ -22,3 +22,4 @@ formats: []
python:
install:
- requirements: doc/sphinx/requirements.txt
- requirements: test/py/requirements.txt

2
Makefile
View File

@ -3,7 +3,7 @@
VERSION = 2025
PATCHLEVEL = 07
SUBLEVEL =
EXTRAVERSION = -rc2
EXTRAVERSION = -rc3
NAME =
# *DOCUMENTATION*

12
README
View File

@ -482,18 +482,6 @@ The following options need to be configured:
for your device
- CONFIG_USBD_PRODUCTID 0xFFFF
- ULPI Layer Support:
The ULPI (UTMI Low Pin (count) Interface) PHYs are supported via
the generic ULPI layer. The generic layer accesses the ULPI PHY
via the platform viewport, so you need both the genric layer and
the viewport enabled. Currently only Chipidea/ARC based
viewport is supported.
To enable the ULPI layer support, define CONFIG_USB_ULPI and
CONFIG_USB_ULPI_VIEWPORT in your board configuration file.
If your ULPI phy needs a different reference clock than the
standard 24 MHz then you have to define CFG_ULPI_REF_CLK to
the appropriate value in Hz.
- MMC Support:
CONFIG_SH_MMCIF
Support for Renesas on-chip MMCIF controller

2
arch/arm/Kconfig
View File

@ -1416,7 +1416,7 @@ config TARGET_TOTAL_COMPUTE
select DM_SERIAL
select DM_GPIO
select MMC
imply OF_HAS_PRIOR_STAGE
imply OF_HAS_PRIOR_STAGE if !BLOBLIST
imply MISC_INIT_R
config TARGET_LS2080A_EMU

3
arch/arm/dts/Makefile
View File

@ -918,8 +918,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-librem5-r4.dtb
dtb-$(CONFIG_ARCH_IMX9) += \
imx93-var-som-symphony.dtb \
imx93-phyboard-segin.dtb
imx93-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1020-evk.dtb \
imxrt1170-evk.dtb \

8
arch/arm/dts/imx6ulz-bsh-smm-m2-u-boot.dtsi
View File

@ -5,8 +5,12 @@
* Author: Michael Trimarchi <michael@amarulasolutions.com>
*/
&{/soc} {
bootph-all;
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
bootph-pre-ram;
};
};
&aips2 {

117
arch/arm/dts/imx93-phyboard-segin.dts
View File

@ -1,117 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de>
* Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
*
* Product homepage:
* phyBOARD-Segin carrier board is reused for the i.MX93 design.
* https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/
*/
/dts-v1/;
#include "imx93-phycore-som.dtsi"
/{
model = "PHYTEC phyBOARD-Segin-i.MX93";
compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som",
"fsl,imx93";
chosen {
stdout-path = &lpuart1;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "VCC_SD";
};
};
/* Console */
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* eMMC */
&usdhc1 {
no-1-8-v;
};
/* SD-Card */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
bus-width = <4>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
no-mmc;
no-sdio;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&iomuxc {
pinctrl_uart1: uart1grp {
fsl,pins = <
MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
MX93_PAD_UART1_TXD__LPUART1_TX 0x30e
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
>;
};
pinctrl_usdhc2_cd: usdhc2cdgrp {
fsl,pins = <
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
>;
};
pinctrl_usdhc2_default: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x178e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
};

126
arch/arm/dts/imx93-phycore-som.dtsi
View File

@ -1,126 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de>
* Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
*
* Product homepage:
* https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/
*/
#include <dt-bindings/leds/common.h>
#include "imx93.dtsi"
/{
model = "PHYTEC phyCORE-i.MX93";
compatible = "phytec,imx93-phycore-som", "fsl,imx93";
reserved-memory {
ranges;
#address-cells = <2>;
#size-cells = <2>;
linux,cma {
compatible = "shared-dma-pool";
reusable;
alloc-ranges = <0 0x80000000 0 0x40000000>;
size = <0 0x10000000>;
linux,cma-default;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
led-0 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_HEARTBEAT;
gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
};
/* Ethernet */
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
fsl,magic-packet;
assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
<&clk IMX93_CLK_ENET_REF>,
<&clk IMX93_CLK_ENET_REF_PHY>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
assigned-clock-rates = <100000000>, <50000000>, <50000000>;
status = "okay";
mdio: mdio {
clock-frequency = <5000000>;
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <8>;
non-removable;
status = "okay";
};
/* Watchdog */
&wdog3 {
status = "okay";
};
&iomuxc {
pinctrl_fec: fecgrp {
fsl,pins = <
MX93_PAD_ENET2_MDC__ENET1_MDC 0x50e
MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x502
MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x5fe
MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x50e
MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x50e
MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x50e
MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x4000050e
>;
};
pinctrl_leds: ledsgrp {
fsl,pins = <
MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e
MX93_PAD_SD1_CMD__USDHC1_CMD 0x1386
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x1386
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x1386
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x1386
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x1386
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x1386
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x1386
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
>;
};
};

28
arch/arm/dts/imxrt1170-evk.dts
View File

@ -234,6 +234,34 @@
(IMX_PAD_SION | 8) /* SEMC_DQS */
>;
};
pinctrl_flexspi1: flexspi1grp {
fsl,pins = <
IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS 0xa
IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B 0xa
IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK 0xa
IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00 0xa
IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01 0xa
IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02 0xa
IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 0xa
>;
};
};
};
&flexspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi1>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <250000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
};
};

13
arch/arm/dts/imxrt1170.dtsi
View File

@ -246,6 +246,19 @@
#interrupt-cells = <2>;
};
flexspi1: spi@400cc000 {
compatible = "nxp,imxrt1170-fspi";
reg = <0x400cc000 0x800>, <0x30000000 0x10000000>;
reg-names = "fspi_base", "fspi_mmap";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <130>;
clocks = <&clks IMXRT1170_CLK_DUMMY>,
<&clks IMXRT1170_CLK_FLEXSPI1>;
clock-names = "fspi_en", "fspi";
status = "disabled";
};
gpt1: gpt1@400ec000 {
compatible = "fsl,imxrt-gpt";
reg = <0x400ec000 0x4000>;

42
arch/arm/mach-imx/imx8m/soc.c
View File

@ -38,7 +38,7 @@
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_IMX_HAB)
#if IS_ENABLED(CONFIG_IMX_HAB)
struct imx_fuse const imx_sec_config_fuse = {
.bank = 1,
.word = 3,
@ -52,7 +52,7 @@ struct imx_fuse const imx_field_return_fuse = {
int timer_init(void)
{
#ifdef CONFIG_XPL_BUILD
#if IS_ENABLED(CONFIG_XPL_BUILD)
struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
unsigned long freq = readl(&sctr->cntfid0);
@ -110,7 +110,7 @@ void set_wdog_reset(struct wdog_regs *wdog)
setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
}
#ifdef CONFIG_ARMV8_PSCI
#if IS_ENABLED(CONFIG_ARMV8_PSCI)
#define PTE_MAP_NS PTE_BLOCK_NS
#else
#define PTE_MAP_NS 0
@ -700,11 +700,11 @@ int arch_cpu_init(void)
return 0;
}
#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
#if IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP)
struct rom_api *g_rom_api = (struct rom_api *)0x980;
#endif
#if defined(CONFIG_IMX8M)
#if IS_ENABLED(CONFIG_IMX8M)
#include <spl.h>
int imx8m_detect_secondary_image_boot(void)
{
@ -790,8 +790,8 @@ int boot_mode_getprisec(void)
}
#endif
#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
#ifdef SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
#if IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP)
#if IS_ENABLED(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION)
#define IMG_CNTN_SET1_OFFSET GENMASK(22, 19)
unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
unsigned long raw_sect)
@ -826,7 +826,7 @@ unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
return raw_sect;
}
#endif /* SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION */
#endif /* CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION */
#endif
bool is_usb_boot(void)
@ -834,7 +834,7 @@ bool is_usb_boot(void)
return get_boot_device() == USB_BOOT;
}
#ifdef CONFIG_OF_SYSTEM_SETUP
#if IS_ENABLED(CONFIG_OF_SYSTEM_SETUP)
bool check_fdt_new_path(void *blob)
{
const char *soc_path = "/soc@0";
@ -880,7 +880,7 @@ add_status:
return 0;
}
#ifdef CONFIG_IMX8MQ
#if IS_ENABLED(CONFIG_IMX8MQ)
bool check_dcss_fused(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
@ -1026,7 +1026,7 @@ int disable_vpu_nodes(void *blob)
return -EPERM;
}
#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
#if IS_ENABLED(CONFIG_IMX8MN_LOW_DRIVE_MODE)
static int low_drive_gpu_freq(void *blob)
{
static const char *nodes_path_8mn[] = {
@ -1311,7 +1311,7 @@ int ft_system_setup(void *blob, struct bd_info *bd)
"/cpus/cpu@3",
};
#ifdef CONFIG_IMX8MQ
#if IS_ENABLED(CONFIG_IMX8MQ)
int i = 0;
int rc;
int nodeoff;
@ -1387,7 +1387,7 @@ usb_modify_speed:
if (is_imx8md())
disable_cpu_nodes(blob, nodes_path, 2, 4);
#elif defined(CONFIG_IMX8MM)
#elif IS_ENABLED(CONFIG_IMX8MM)
if (is_imx8mml() || is_imx8mmdl() || is_imx8mmsl())
disable_vpu_nodes(blob);
@ -1396,10 +1396,10 @@ usb_modify_speed:
else if (is_imx8mms() || is_imx8mmsl())
disable_cpu_nodes(blob, nodes_path, 3, 4);
#elif defined(CONFIG_IMX8MN)
#elif IS_ENABLED(CONFIG_IMX8MN)
if (is_imx8mnl() || is_imx8mndl() || is_imx8mnsl())
disable_gpu_nodes(blob);
#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
#if IS_ENABLED(CONFIG_IMX8MN_LOW_DRIVE_MODE)
else {
int ldm_gpu = low_drive_gpu_freq(blob);
@ -1415,7 +1415,7 @@ usb_modify_speed:
else if (is_imx8mns() || is_imx8mnsl() || is_imx8mnus())
disable_cpu_nodes(blob, nodes_path, 3, 4);
#elif defined(CONFIG_IMX8MP)
#elif IS_ENABLED(CONFIG_IMX8MP)
if (is_imx8mpul()) {
/* Disable GPU */
disable_gpu_nodes(blob);
@ -1471,7 +1471,7 @@ void reset_cpu(void)
}
#endif
#if defined(CONFIG_ARCH_MISC_INIT)
#if IS_ENABLED(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
if (IS_ENABLED(CONFIG_FSL_CAAM)) {
@ -1487,8 +1487,8 @@ int arch_misc_init(void)
}
#endif
#if defined(CONFIG_XPL_BUILD)
#if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
#if IS_ENABLED(CONFIG_XPL_BUILD)
#if IS_ENABLED(CONFIG_IMX8MQ) || IS_ENABLED(CONFIG_IMX8MM) || IS_ENABLED(CONFIG_IMX8MN)
bool serror_need_skip = true;
void do_error(struct pt_regs *pt_regs)
@ -1523,7 +1523,7 @@ void do_error(struct pt_regs *pt_regs)
#endif
#endif
#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
#if IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP)
enum env_location arch_env_get_location(enum env_operation op, int prio)
{
enum boot_device dev = get_boot_device();
@ -1571,7 +1571,7 @@ enum env_location arch_env_get_location(enum env_operation op, int prio)
#endif
#ifdef CONFIG_IMX_BOOTAUX
#if IS_ENABLED(CONFIG_IMX_BOOTAUX)
const struct rproc_att hostmap[] = {
/* aux core , host core, size */
{ 0x00000000, 0x007e0000, 0x00020000 },

1
arch/arm/mach-imx/imx9/Kconfig
View File

@ -73,6 +73,7 @@ config TARGET_PHYCORE_IMX93
bool "phycore_imx93"
select IMX93
select IMX9_LPDDR4X
imply OF_UPSTREAM
select OF_BOARD_FIXUP
select OF_BOARD_SETUP

8
arch/arm/mach-imx/spl_imx_romapi.c
View File

@ -35,12 +35,10 @@ ulong __weak spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev)
{
u32 sector = 0;
/*
* Some boards use this value even though MMC is not enabled in SPL, for
* example imx8mn_bsh_smm_s2
*/
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#if IS_ENABLED(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR)
sector = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
#elif IS_ENABLED(CONFIG_SPL_NAND_RAW_U_BOOT_USE_SECTOR)
sector = CONFIG_SPL_NAND_RAW_U_BOOT_SECTOR;
#endif
return image_offset + sector * 512 - 0x8000;

9
arch/arm/mach-kirkwood/Kconfig
View File

@ -50,11 +50,13 @@ config TARGET_DS109
bool "Synology DS109"
select KW88F6281
select SHEEVA_88SV131
select KIRKWOOD_COMMON
config TARGET_GURUPLUG
bool "GuruPlug Board"
select KW88F6281
select SHEEVA_88SV131
select KIRKWOOD_COMMON
config TARGET_SHEEVAPLUG
bool "SheevaPlug Board"
@ -86,6 +88,7 @@ config TARGET_DNS325
bool "dns325 Board"
select FEROCEON_88FR131
select KW88F6281
select KIRKWOOD_COMMON
config TARGET_ICONNECT
bool "iconnect Board"
@ -103,15 +106,18 @@ config TARGET_NET2BIG_V2
bool "LaCie 2Big Network v2 NAS Board"
select FEROCEON_88FR131
select KW88F6281
select KIRKWOOD_COMMON
config TARGET_NETSPACE_V2
bool "LaCie netspace_v2 Board"
select FEROCEON_88FR131
select KIRKWOOD_COMMON
config TARGET_IB62X0
bool "ib62x0 Board"
select FEROCEON_88FR131
select KW88F6281
select KIRKWOOD_COMMON
config TARGET_DOCKSTAR
bool "Dockstar Board"
@ -129,6 +135,7 @@ config TARGET_NAS220
bool "BlackArmor NAS220"
select FEROCEON_88FR131
select KW88F6192
select KIRKWOOD_COMMON
config TARGET_NSA310S
bool "Zyxel NSA310S"
@ -146,11 +153,13 @@ config TARGET_SBx81LIFKW
bool "Allied Telesis SBx81GS24/SBx81GT40/SBx81XS6/SBx81XS16"
select FEROCEON_88FR131
select KW88F6281
select KIRKWOOD_COMMON
config TARGET_SBx81LIFXCAT
bool "Allied Telesis SBx81GP24/SBx81GT24"
select FEROCEON_88FR131
select KW88F6281
select KIRKWOOD_COMMON
endchoice

9
arch/riscv/Kconfig
View File

@ -77,6 +77,14 @@ config SYS_DCACHE_OFF
help
Do not enable data cache in U-Boot.
config SYS_CACHE_THEAD_CMO
bool "THEAD non-standard cache operations"
depends on !SYS_DCACHE_OFF
default n
help
Support for non-standard cache management operations on SoCs based on
T-Head C906/C910 cores.
config SPL_SYS_DCACHE_OFF
bool "Do not enable dcache in SPL"
depends on SPL
@ -118,6 +126,7 @@ source "arch/riscv/cpu/generic/Kconfig"
source "arch/riscv/cpu/jh7110/Kconfig"
source "arch/riscv/cpu/k1/Kconfig"
source "arch/riscv/cpu/k230/Kconfig"
source "arch/riscv/cpu/th1520/Kconfig"
# architecture-specific options below

6
arch/riscv/cpu/cpu.c
View File

@ -18,6 +18,7 @@
#include <asm/hwcap.h>
#include <asm/cpufeature.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <dm/uclass-internal.h>
#include <linux/bitops.h>
#include <linux/log2.h>
@ -746,3 +747,8 @@ __weak int cleanup_before_linux(void)
return 0;
}
void arch_setup_gd(gd_t *new_gd)
{
set_gd(new_gd);
}

1
arch/riscv/cpu/cv1800b/Kconfig
View File

@ -6,6 +6,7 @@ config SOPHGO_CV1800B
bool
select ARCH_EARLY_INIT_R
select SYS_CACHE_SHIFT_6
select SYS_CACHE_THEAD_CMO
imply CPU
imply CPU_RISCV
imply RISCV_TIMER

1
arch/riscv/cpu/cv1800b/Makefile
View File

@ -4,4 +4,3 @@
obj-y += dram.o
obj-y += cpu.o
obj-y += cache.o

22
arch/riscv/cpu/th1520/Kconfig Normal file
View File

@ -0,0 +1,22 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
# Copyright (C) 2025, Yao Zi <ziyao@disroot.org>
config THEAD_TH1520
bool
select ARCH_EARLY_INIT_R
select SYS_CACHE_SHIFT_6
select SUPPORT_SPL
select BINMAN if SPL
select SYS_CACHE_THEAD_CMO
select CLK_THEAD
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
imply RISCV_ACLINT if RISCV_MMODE
imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE
imply CMD_CPU
imply SPL_CPU
imply SPL_OPENSBI
imply SPL_LOAD_FIT

8
arch/riscv/cpu/th1520/Makefile Normal file
View File

@ -0,0 +1,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2025, Yao Zi <ziyao@disroot.org>
obj-y += cache.o
obj-y += cpu.o
obj-y += dram.o
obj-y += spl.o

32
arch/riscv/cpu/th1520/cache.c Normal file
View File

@ -0,0 +1,32 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2025 Yao Zi <ziyao@disroot.org>
*/
#include <asm/io.h>
#include <cpu_func.h>
#include <linux/bitops.h>
#define CSR_MHCR 0x7c1
#define CSR_MHCR_IE BIT(0)
#define CSR_MHCR_DE BIT(1)
void icache_enable(void)
{
csr_write(CSR_MHCR, csr_read(CSR_MHCR) | CSR_MHCR_IE);
}
void dcache_enable(void)
{
csr_write(CSR_MHCR, csr_read(CSR_MHCR) | CSR_MHCR_DE);
}
int icache_status(void)
{
return (csr_read(CSR_MHCR) & CSR_MHCR_IE) != 0;
}
int dcache_status(void)
{
return (csr_read(CSR_MHCR) & CSR_MHCR_DE) != 0;
}

21
arch/riscv/cpu/th1520/cpu.c Normal file
View File

@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2025 Yao Zi <ziyao@disroot.org>
*
* TH1520 SoC has a set of undocumented customized PMP registers that are
* configured through MMIO operation. It must be disabled before entering
* the DRAM region, or an exception will be raised.
*/
#include <asm/io.h>
#include <cpu_func.h>
#define TH1520_PMP_BASE (void *)0xffdc020000
void th1520_invalidate_pmp(void)
{
/* Invalidate the PMP configuration as in vendor U-Boot code */
writel(0x0, TH1520_PMP_BASE + 0x0);
invalidate_icache_all();
}

21
arch/riscv/cpu/th1520/dram.c Normal file
View File

@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
*/
#include <fdtdec.h>
#include <init.h>
#include <asm/global_data.h>
#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
return fdtdec_setup_mem_size_base();
}
int dram_init_banksize(void)
{
return fdtdec_setup_memory_banksize();
}

96
arch/riscv/cpu/th1520/spl.c Normal file
View File

@ -0,0 +1,96 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
*/
#include <asm/arch/iopmp.h>
#include <asm/io.h>
#include <dm.h>
#include <linux/sizes.h>
#include <log.h>
#include <init.h>
DECLARE_GLOBAL_DATA_PTR;
#define TH1520_SUBSYS_CLK (void __iomem *)(0xffff011000 + 0x220)
#define TH1520_SUBSYS_CLK_VO_EN BIT(2)
#define TH1520_SUBSYS_CLK_VI_EN BIT(1)
#define TH1520_SUBSYS_CLK_DSP_EN BIT(0)
#define TH1520_SUBSYS_RST (void __iomem *)(0xffff015000 + 0x220)
#define TH1520_SUBSYS_RST_VP_N BIT(3)
#define TH1520_SUBSYS_RST_VO_N BIT(2)
#define TH1520_SUBSYS_RST_VI_N BIT(1)
#define TH1520_SUBSYS_RST_DSP_N BIT(0)
int spl_dram_init(void)
{
int ret;
struct udevice *dev;
ret = fdtdec_setup_mem_size_base();
if (ret) {
printf("failed to setup memory size and base: %d\n", ret);
return ret;
}
/* DDR init */
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
printf("DRAM init failed: %d\n", ret);
return ret;
}
return 0;
}
static void __iomem *th1520_iopmp_regs[] = {
TH1520_IOPMP_EMMC,
TH1520_IOPMP_SDIO0,
TH1520_IOPMP_SDIO1,
TH1520_IOPMP_USB0,
TH1520_IOPMP_AO,
TH1520_IOPMP_AUD,
TH1520_IOPMP_CHIP_DBG,
TH1520_IOPMP_EIP120I,
TH1520_IOPMP_EIP120II,
TH1520_IOPMP_EIP120III,
TH1520_IOPMP_ISP0,
TH1520_IOPMP_ISP1,
TH1520_IOPMP_DW200,
TH1520_IOPMP_VIPRE,
TH1520_IOPMP_VENC,
TH1520_IOPMP_VDEC,
TH1520_IOPMP_G2D,
TH1520_IOPMP_FCE,
TH1520_IOPMP_NPU,
TH1520_IOPMP_DPU0,
TH1520_IOPMP_DPU1,
TH1520_IOPMP_GPU,
TH1520_IOPMP_GMAC1,
TH1520_IOPMP_GMAC2,
TH1520_IOPMP_DMAC,
TH1520_IOPMP_TEE_DMAC,
TH1520_IOPMP_DSP0,
TH1520_IOPMP_DSP1,
};
void harts_early_init(void)
{
int i;
/*
* Set IOPMPs to the default attribute, allowing the application
* processor to access various peripherals. Subsystem clocks should be
* enabled and resets should be deasserted ahead of time, or the HART
* will hang when configuring corresponding IOPMP entries.
*/
setbits_le32(TH1520_SUBSYS_CLK, TH1520_SUBSYS_CLK_VO_EN |
TH1520_SUBSYS_CLK_VI_EN |
TH1520_SUBSYS_CLK_DSP_EN);
setbits_le32(TH1520_SUBSYS_RST, TH1520_SUBSYS_RST_VP_N |
TH1520_SUBSYS_RST_VO_N |
TH1520_SUBSYS_RST_VI_N |
TH1520_SUBSYS_RST_DSP_N);
for (i = 0; i < ARRAY_SIZE(th1520_iopmp_regs); i++)
writel(TH1520_IOPMP_DEFAULT_ATTR, th1520_iopmp_regs[i]);
}

15
arch/riscv/dts/binman.dtsi
View File

@ -5,6 +5,12 @@
#include <config.h>
#ifdef CONFIG_64BIT
#define ARCH "riscv64"
#else
#define ARCH "riscv"
#endif
/ {
binman: binman {
multiple-images;
@ -31,12 +37,11 @@
description = "U-Boot";
type = "standalone";
os = "U-Boot";
arch = "riscv";
arch = ARCH;
compression = "none";
load = /bits/ 64 <CONFIG_TEXT_BASE>;
uboot_blob: u-boot-nodtb {
filename = "u-boot-nodtb.bin";
};
};
#else
@ -44,7 +49,7 @@
description = "Linux";
type = "standalone";
os = "Linux";
arch = "riscv";
arch = ARCH;
compression = "none";
load = /bits/ 64 <CONFIG_TEXT_BASE>;
@ -57,7 +62,7 @@
tee {
description = "OP-TEE";
type = "tee";
arch = "riscv";
arch = ARCH;
compression = "none";
os = "tee";
load = /bits/ 64 <CONFIG_SPL_OPTEE_LOAD_ADDR>;
@ -71,7 +76,7 @@
description = "OpenSBI fw_dynamic Firmware";
type = "firmware";
os = "opensbi";
arch = "riscv";
arch = ARCH;
compression = "none";
load = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
entry = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>;

1
arch/riscv/dts/jh7110-common-u-boot.dtsi
View File

@ -27,7 +27,6 @@
bootph-pre-ram;
reg-offset = <0>;
current-speed = <115200>;
clock-frequency = <24000000>;
};
&mmc0 {

73
arch/riscv/dts/jh7110-u-boot.dtsi
View File

@ -6,46 +6,6 @@
#include <dt-bindings/reset/starfive,jh7110-crg.h>
/ {
cpus: cpus {
bootph-pre-ram;
S7_0: cpu@0 {
bootph-pre-ram;
status = "okay";
cpu0_intc: interrupt-controller {
bootph-pre-ram;
};
};
U74_1: cpu@1 {
bootph-pre-ram;
cpu1_intc: interrupt-controller {
bootph-pre-ram;
};
};
U74_2: cpu@2 {
bootph-pre-ram;
cpu2_intc: interrupt-controller {
bootph-pre-ram;
};
};
U74_3: cpu@3 {
bootph-pre-ram;
cpu3_intc: interrupt-controller {
bootph-pre-ram;
};
};
U74_4: cpu@4 {
bootph-pre-ram;
cpu4_intc: interrupt-controller {
bootph-pre-ram;
};
};
};
timer {
compatible = "riscv,timer";
interrupts-extended = <&cpu0_intc 5>,
@ -58,10 +18,6 @@
soc {
bootph-pre-ram;
clint: timer@2000000 {
bootph-pre-ram;
};
dmc: dmc@15700000 {
bootph-pre-ram;
compatible = "starfive,jh7110-dmc";
@ -78,6 +34,34 @@
};
};
&clint {
bootph-pre-ram;
};
&cpu0_intc {
bootph-pre-ram;
};
&cpu1_intc {
bootph-pre-ram;
};
&cpu2_intc {
bootph-pre-ram;
};
&cpu3_intc {
bootph-pre-ram;
};
&cpu4_intc {
bootph-pre-ram;
};
&cpus {
bootph-pre-ram;
};
&osc {
bootph-pre-ram;
};
@ -107,6 +91,7 @@
};
&syscrg {
assigned-clock-rates = <0>; /* cpufreq not implemented, use defaults */
bootph-pre-ram;
};

9
arch/riscv/dts/th1520-lichee-module-4a.dtsi
View File

@ -14,6 +14,7 @@
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x2 0x00000000>;
bootph-pre-ram;
};
};
@ -25,14 +26,6 @@
clock-frequency = <32768>;
};
&apb_clk {
clock-frequency = <62500000>;
};
&uart_sclk {
clock-frequency = <100000000>;
};
&emmc {
bus-width = <8>;
max-frequency = <198000000>;

1
arch/riscv/dts/th1520-lichee-pi-4a.dts
View File

@ -4,6 +4,7 @@
*/
#include "th1520-lichee-module-4a.dtsi"
#include "thead-th1520-binman.dtsi"
/ {
model = "Sipeed Lichee Pi 4A";

91
arch/riscv/dts/th1520.dtsi
View File

@ -4,6 +4,7 @@
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
*/
#include <dt-bindings/clock/thead,th1520-clk-ap.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
@ -14,6 +15,7 @@
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
bootph-pre-ram;
timebase-frequency = <3000000>;
c910_0: cpu@0 {
@ -21,6 +23,7 @@
device_type = "cpu";
riscv,isa = "rv64imafdc";
reg = <0>;
bootph-pre-ram;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@ -42,6 +45,7 @@
device_type = "cpu";
riscv,isa = "rv64imafdc";
reg = <1>;
bootph-pre-ram;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@ -63,6 +67,7 @@
device_type = "cpu";
riscv,isa = "rv64imafdc";
reg = <2>;
bootph-pre-ram;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@ -84,6 +89,7 @@
device_type = "cpu";
riscv,isa = "rv64imafdc";
reg = <3>;
bootph-pre-ram;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@ -122,25 +128,6 @@
#clock-cells = <0>;
};
apb_clk: apb-clk-clock {
compatible = "fixed-clock";
clock-output-names = "apb_clk";
#clock-cells = <0>;
};
uart_sclk: uart-sclk-clock {
compatible = "fixed-clock";
clock-output-names = "uart_sclk";
#clock-cells = <0>;
};
sdhci_clk: sdhci-clock {
compatible = "fixed-clock";
clock-frequency = <198000000>;
clock-output-names = "sdhci_clk";
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
@ -173,8 +160,10 @@
uart0: serial@ffe7014000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xe7014000 0x0 0x100>;
bootph-pre-ram;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_sclk>;
clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>;
clock-names = "buadclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@ -184,7 +173,7 @@
compatible = "thead,th1520-dwcmshc";
reg = <0xff 0xe7080000 0x0 0x10000>;
interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sdhci_clk>;
clocks = <&clk CLK_EMMC_SDIO>;
clock-names = "core";
status = "disabled";
};
@ -193,7 +182,7 @@
compatible = "thead,th1520-dwcmshc";
reg = <0xff 0xe7090000 0x0 0x10000>;
interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sdhci_clk>;
clocks = <&clk CLK_EMMC_SDIO>;
clock-names = "core";
status = "disabled";
};
@ -202,7 +191,7 @@
compatible = "thead,th1520-dwcmshc";
reg = <0xff 0xe70a0000 0x0 0x10000>;
interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sdhci_clk>;
clocks = <&clk CLK_EMMC_SDIO>;
clock-names = "core";
status = "disabled";
};
@ -211,7 +200,8 @@
compatible = "snps,dw-apb-uart";
reg = <0xff 0xe7f00000 0x0 0x100>;
interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_sclk>;
clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>;
clock-names = "buadclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@ -221,7 +211,8 @@
compatible = "snps,dw-apb-uart";
reg = <0xff 0xe7f04000 0x0 0x100>;
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_sclk>;
clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>;
clock-names = "buadclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@ -230,6 +221,8 @@
gpio2: gpio@ffe7f34000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xe7f34000 0x0 0x1000>;
clocks = <&clk CLK_GPIO2>;
clock-names = "bus";
#address-cells = <1>;
#size-cells = <0>;
@ -248,6 +241,8 @@
gpio3: gpio@ffe7f38000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xe7f38000 0x0 0x1000>;
clocks = <&clk CLK_GPIO3>;
clock-names = "bus";
#address-cells = <1>;
#size-cells = <0>;
@ -266,6 +261,8 @@
gpio0: gpio@ffec005000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xec005000 0x0 0x1000>;
clocks = <&clk CLK_GPIO0>;
clock-names = "bus";
#address-cells = <1>;
#size-cells = <0>;
@ -284,6 +281,8 @@
gpio1: gpio@ffec006000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xec006000 0x0 0x1000>;
clocks = <&clk CLK_GPIO1>;
clock-names = "bus";
#address-cells = <1>;
#size-cells = <0>;
@ -303,16 +302,24 @@
compatible = "snps,dw-apb-uart";
reg = <0xff 0xec010000 0x0 0x4000>;
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_sclk>;
clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>;
clock-names = "buadclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
clk: clock-controller@ffef010000 {
compatible = "thead,th1520-clk-ap";
reg = <0xff 0xef010000 0x0 0x1000>;
clocks = <&osc>;
#clock-cells = <1>;
};
timer0: timer@ffefc32000 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xefc32000 0x0 0x14>;
clocks = <&apb_clk>;
clocks = <&clk CLK_PERI_APB_PCLK>;
clock-names = "timer";
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@ -321,7 +328,7 @@
timer1: timer@ffefc32014 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xefc32014 0x0 0x14>;
clocks = <&apb_clk>;
clocks = <&clk CLK_PERI_APB_PCLK>;
clock-names = "timer";
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@ -330,7 +337,7 @@
timer2: timer@ffefc32028 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xefc32028 0x0 0x14>;
clocks = <&apb_clk>;
clocks = <&clk CLK_PERI_APB_PCLK>;
clock-names = "timer";
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@ -339,7 +346,7 @@
timer3: timer@ffefc3203c {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xefc3203c 0x0 0x14>;
clocks = <&apb_clk>;
clocks = <&clk CLK_PERI_APB_PCLK>;
clock-names = "timer";
interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@ -349,7 +356,8 @@
compatible = "snps,dw-apb-uart";
reg = <0xff 0xf7f08000 0x0 0x4000>;
interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_sclk>;
clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>;
clock-names = "buadclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@ -359,16 +367,27 @@
compatible = "snps,dw-apb-uart";
reg = <0xff 0xf7f0c000 0x0 0x4000>;
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_sclk>;
clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>;
clock-names = "buadclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
ddrc: ddrc@fffd000000 {
compatible = "thead,th1520-ddrc";
reg = <0xff 0xfd000000 0x0 0x1000000>,
<0xff 0xfe000000 0x0 0x1000000>,
<0xff 0xff000000 0x0 0x4000>,
<0xff 0xff005000 0x0 0x1000>;
reg-names = "phy-0", "phy-1", "ctrl", "sys";
bootph-pre-ram;
};
timer4: timer@ffffc33000 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xffc33000 0x0 0x14>;
clocks = <&apb_clk>;
clocks = <&clk CLK_PERI_APB_PCLK>;
clock-names = "timer";
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@ -377,7 +396,7 @@
timer5: timer@ffffc33014 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xffc33014 0x0 0x14>;
clocks = <&apb_clk>;
clocks = <&clk CLK_PERI_APB_PCLK>;
clock-names = "timer";
interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@ -386,7 +405,7 @@
timer6: timer@ffffc33028 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xffc33028 0x0 0x14>;
clocks = <&apb_clk>;
clocks = <&clk CLK_PERI_APB_PCLK>;
clock-names = "timer";
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@ -395,7 +414,7 @@
timer7: timer@ffffc3303c {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xffc3303c 0x0 0x14>;
clocks = <&apb_clk>;
clocks = <&clk CLK_PERI_APB_PCLK>;
clock-names = "timer";
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";

55
arch/riscv/dts/thead-th1520-binman.dtsi Normal file
View File

@ -0,0 +1,55 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2025 Yao Zi <ziyao@disroot.org>
*/
#include <config.h>
/ {
binman: binman {
};
};
&binman {
filename = "u-boot-with-spl.bin";
u-boot-spl {
};
ddr-fw {
filename = "th1520-ddr-firmware.bin";
type = "blob-ext";
};
fit {
offset = <CONFIG_SPL_PAD_TO>;
description = "Configuration to load M-mode U-Boot";
#address-cells = <2>;
fit,fdt-list = "of-list";
images {
uboot {
description = "U-Boot";
type = "standalone";
os = "U-boot";
arch = "riscv";
compression = "none";
load = /bits/ 64 <CONFIG_TEXT_BASE>;
uboot_blob: u-boot {
};
};
};
configurations {
default = "conf-th1520-lichee-pi-4a";
conf-th1520-lichee-pi-4a {
description = "th1520-lichee-pi-4a";
loadables = "uboot";
};
};
};
};

9
arch/riscv/include/asm/arch-th1520/cpu.h Normal file
View File

@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2025 Yao Zi <ziyao@disroot.org>
*/
#ifndef _ASM_TH1520_CPU_H_
#define _ASM_TH1520_CPU_H_
void th1520_invalidate_pmp(void);
#endif /* _ASM_TH1520_CPU_H_ */

42
arch/riscv/include/asm/arch-th1520/iopmp.h Normal file
View File

@ -0,0 +1,42 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
*/
#ifndef _ASM_ARCH_TH1520_IOPMP_H_
#define _ASM_ARCH_TH1520_IOPMP_H_
#define TH1520_IOPMP_EMMC (void *)0xfffc0280c0
#define TH1520_IOPMP_SDIO0 (void *)0xfffc0290c0
#define TH1520_IOPMP_SDIO1 (void *)0xfffc02a0c0
#define TH1520_IOPMP_USB0 (void *)0xfffc02e0c0
#define TH1520_IOPMP_AO (void *)0xffffc210c0
#define TH1520_IOPMP_AUD (void *)0xffffc220c0
#define TH1520_IOPMP_CHIP_DBG (void *)0xffffc370c0
#define TH1520_IOPMP_EIP120I (void *)0xffff2200c0
#define TH1520_IOPMP_EIP120II (void *)0xffff2300c0
#define TH1520_IOPMP_EIP120III (void *)0xffff2400c0
#define TH1520_IOPMP_ISP0 (void *)0xfff40800c0
#define TH1520_IOPMP_ISP1 (void *)0xfff40810c0
#define TH1520_IOPMP_DW200 (void *)0xfff40820c0
#define TH1520_IOPMP_VIPRE (void *)0xfff40830c0
#define TH1520_IOPMP_VENC (void *)0xfffcc600c0
#define TH1520_IOPMP_VDEC (void *)0xfffcc610c0
#define TH1520_IOPMP_G2D (void *)0xfffcc620c0
#define TH1520_IOPMP_FCE (void *)0xfffcc630c0
#define TH1520_IOPMP_NPU (void *)0xffff01c0c0
#define TH1520_IOPMP_DPU0 (void *)0xffff5200c0
#define TH1520_IOPMP_DPU1 (void *)0xffff5210c0
#define TH1520_IOPMP_GPU (void *)0xffff5220c0
#define TH1520_IOPMP_GMAC1 (void *)0xfffc0010c0
#define TH1520_IOPMP_GMAC2 (void *)0xfffc0020c0
#define TH1520_IOPMP_DMAC (void *)0xffffc200c0
#define TH1520_IOPMP_TEE_DMAC (void *)0xffff2500c0
#define TH1520_IOPMP_DSP0 (void *)0xffff0580c0
#define TH1520_IOPMP_DSP1 (void *)0xffff0590c0
#define TH1520_IOPMP_AUDIO (void *)0xffffc220c0
#define TH1520_IOPMP_AUDIO0 (void *)0xffcb02e0c0
#define TH1520_IOPMP_AUDIO1 (void *)0xffcb02f0c0
#define TH1520_IOPMP_DEFAULT_ATTR 0xffffffff
#endif // _ASM_ARCH_TH1520_IOPMP_H_

10
arch/riscv/include/asm/arch-th1520/spl.h Normal file
View File

@ -0,0 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
*/
#ifndef _ASM_ARCH_TH1520_SPL_H_
#define _ASM_ARCH_TH1520_SPL_H_
void spl_dram_init(void);
#endif // _ASM_ARCH_TH1520_SPL_H_

19
arch/riscv/include/asm/global_data.h
View File

@ -14,6 +14,7 @@
#include <asm/smp.h>
#include <asm/u-boot.h>
#include <compiler.h>
#include <config.h>
/* Architecture-specific global data */
struct arch_global_data {
@ -47,8 +48,26 @@ struct arch_global_data {
#include <asm-generic/global_data.h>
#if defined(__clang__) || CONFIG_IS_ENABLED(LTO)
#define DECLARE_GLOBAL_DATA_PTR
#define gd get_gd()
static inline gd_t *get_gd(void)
{
gd_t *gd_ptr;
__asm__ volatile ("mv %0, gp\n" : "=r" (gd_ptr));
return gd_ptr;
}
#else
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("gp")
#endif
static inline void set_gd(volatile gd_t *gd_ptr)
{
#ifdef CONFIG_64BIT

6
arch/riscv/include/asm/insn-def.h
View File

@ -5,8 +5,8 @@
* Ported from linux insn-def.h.
*/
#ifndef _ASM_RISCV_BARRIER_H
#define _ASM_RISCV_BARRIER_H
#ifndef _ASM_RISCV_INSN_DEF_H
#define _ASM_RISCV_INSN_DEF_H
#define INSN_I_SIMM12_SHIFT 20
#define INSN_I_RS1_SHIFT 15
@ -36,4 +36,4 @@
__INSN_I(RV_##opcode, RV_##func3, RV_##rd, \
RV_##rs1, RV_##simm12)
#endif /* _ASM_RISCV_BARRIER_H */
#endif /* _ASM_RISCV_INSN_DEF_H */

4
arch/riscv/include/asm/u-boot.h
View File

@ -23,6 +23,10 @@
#include <asm/u-boot-riscv.h>
/* For image.h:image_check_target_arch() */
#ifdef CONFIG_64BIT
#define IH_ARCH_DEFAULT IH_ARCH_RISCV64
#else
#define IH_ARCH_DEFAULT IH_ARCH_RISCV
#endif
#endif /* _U_BOOT_H_ */

1
arch/riscv/lib/Makefile
View File

@ -11,6 +11,7 @@ obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
obj-$(CONFIG_CMD_GO) += boot.o
obj-y += cache.o
obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
obj-$(CONFIG_SYS_CACHE_THEAD_CMO) += thead_cmo.o
ifeq ($(CONFIG_$(PHASE_)RISCV_MMODE),y)
obj-$(CONFIG_$(PHASE_)RISCV_ACLINT) += aclint_ipi.o
obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o

4
arch/riscv/lib/bootm.c
View File

@ -90,6 +90,10 @@ static void boot_jump_linux(struct bootm_headers *images, int flag)
announce_and_cleanup(fake);
if (!fake) {
if (images->os.arch != IH_ARCH_DEFAULT) {
printf("Image arch not compatible with host arch.\n");
hang();
}
if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
#ifdef CONFIG_SMP
ret = smp_call_function(images->ep,

0
arch/riscv/cpu/cv1800b/cache.c → arch/riscv/lib/thead_cmo.c
View File

2
arch/x86/lib/tables.c
View File

@ -126,6 +126,8 @@ int write_tables(void)
use_high = true;
if (!gd->arch.table_start_high)
gd->arch.table_start_high = rom_addr;
if (table->tag == BLOBLISTT_SMBIOS_TABLES)
gd_set_smbios_start(rom_addr);
}
rom_table_end = table->write(rom_addr);
if (!rom_table_end) {

18
board/Synology/ds109/ds109.c
View File

@ -97,24 +97,6 @@ int board_init(void)
return 0;
}
/* Synology reset uses UART */
#include <ns16550.h>
#define SOFTWARE_SHUTDOWN 0x31
#define SOFTWARE_REBOOT 0x43
#define CFG_SYS_NS16550_COM2 KW_UART1_BASE
void reset_misc(void)
{
int b_d;
printf("Synology reset...");
udelay(50000);
b_d = ns16550_calc_divisor((struct ns16550 *)CFG_SYS_NS16550_COM2,
CFG_SYS_NS16550_CLK, 9600);
ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM2, b_d);
ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM2,
SOFTWARE_REBOOT);
}
#ifdef CONFIG_RESET_PHY_R
/* Configure and enable MV88E1116 PHY */
void reset_phy(void)

2
board/armltd/total_compute/Makefile
View File

@ -4,4 +4,4 @@
# Usama Arif <usama.arif@arm.com>
obj-y := total_compute.o
obj-y += lowlevel_init.o
obj-$(CONFIG_OF_HAS_PRIOR_STAGE) += lowlevel_init.o

5
board/armltd/total_compute/total_compute.c
View File

@ -31,6 +31,7 @@ static struct mm_region total_compute_mem_map[TC_MEM_MAP_MAX] = {
struct mm_region *mem_map = total_compute_mem_map;
#ifdef CONFIG_OF_HAS_PRIOR_STAGE
/*
* Push the variable into the .data section so that it
* does not get cleared later.
@ -45,14 +46,16 @@ int board_fdt_blob_setup(void **fdtp)
*fdtp = (void *)fw_dtb_pointer;
return 0;
}
#endif
int misc_init_r(void)
{
size_t base;
#ifdef CONFIG_OF_HAS_PRIOR_STAGE
if (!env_get("fdt_addr_r"))
env_set_hex("fdt_addr_r", fw_dtb_pointer);
#endif
if (!env_get("kernel_addr_r")) {
/*
* The kernel has to be 2M aligned and the first 64K at the

6
board/armltd/total_compute/total_compute.env
View File

@ -11,6 +11,12 @@ bootcmd=
blk_dev=mmc;
fi;
echo block device is ${blk_dev};
if test -n "${fdt_addr_r}"; then
echo "Custom FDT at ${fdt_addr_r}";
else;
setenv fdt_addr_r ${fdtcontroladdr};
echo "FDT address is now set to ${fdt_addr_r}";
fi;
if part number ${blk_dev} 0 vbmeta is_avb; then
echo '${blk_dev} with vbmeta partition detected.';
echo 'Starting Android Verified boot...';

3
board/bsh/imx6ulz_smm_m2/Makefile
View File

@ -2,5 +2,4 @@
# (C) Copyright 2021 Amarula Solutions B.V.
obj-y := imx6ulz_smm_m2.o
obj-$(CONFIG_XPL_BUILD) += spl.o
obj-$(CONFIG_XPL_BUILD) += spl.o ddr3l_timing_512m.o ddr3l_timing_256m.o ddr3l_timing_128m.o

169
board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m.c Normal file
View File

@ -0,0 +1,169 @@
// SPDX-License-Identifier: GPL-2.0+
#include "spl_mtypes.h"
static const struct dram_cfg_param ddr_ddrc_cfg_128mb[] = {
/* IOMUX */
/* DDR IO Type: */
{0x020e04b4, 0x000C0000}, /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
{0x020e04ac, 0x00000000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
/* Clock: */
{0x020e027c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
/* Address: */
{0x020e0250, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
{0x020e024c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
{0x020e0490, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
/* Control: */
{0x020e0288, 0x000C0028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
{0x020e0270, 0x00000000}, /*
* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured
* using Group Control Register IOMUXC_SW_PAD_CTL_GRP_CTLDS
*/
{0x020e0260, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */
{0x020e0264, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */
{0x020e04a0, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
/* Data Strobes: */
{0x020e0494, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
{0x020e0280, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */
{0x020e0284, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
/* Data: */
{0x020e04b0, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
{0x020e0498, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
{0x020e04a4, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
{0x020e0244, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
{0x020e0248, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
/*
* =============================================================================
* DDR Controller Registers
* =============================================================================
* Manufacturer:ISSI
* Device Part Number:IS43TR16640BL-125JBLI
* Clock Freq.: 400MHz
* Density per CS in Gb: 1
* Chip Selects used:1
* Number of Banks:8
* Row address: 13
* Column address: 10
* Data bus width16
* =============================================================================
*/
{0x021b001c, 0x00008000}, /*
* MMDC0_MDSCR, set the Configuration request bit
* during MMDC set up
*/
/*
* =============================================================================
* Calibration setup.
* =============================================================================
*/
{0x021b0800, 0xA1390003}, /*
* DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic
* HW ZQ calibration.
*/
/*
* For target board, may need to run write leveling calibration to fine tune
* these settings.
*/
{0x021b080c, 0x00000000},
/* Read DQS Gating calibration */
{0x021b083c, 0x41480148}, /* MPDGCTRL0 PHY0 */
/* Read calibration */
{0x021b0848, 0x40403A3E}, /* MPRDDLCTL PHY0 */
/* Write calibration */
{0x021b0850, 0x4040362E}, /* MPWRDLCTL PHY0 */
/*
* Read data bit delay: 3 is the recommended default value, although out of reset
* value is 0.
*/
{0x021b081c, 0x33333333}, /* MMDC_MPRDDQBY0DL */
{0x021b0820, 0x33333333}, /* MMDC_MPRDDQBY1DL */
/* Write data bit delay: */
{0x021b082c, 0xF3333333}, /* MMDC_MPWRDQBY0DL */
{0x021b0830, 0xF3333333}, /* MMDC_MPWRDQBY1DL */
/* DQS&CLK Duty Cycle */
{0x021b08c0, 0x00944009}, /* [MMDC_MPDCCR] MMDC Duty Cycle Control Register */
/* Complete calibration by forced measurement: */
{0x021b08b8, 0x00000800}, /* DDR_PHY_P0_MPMUR0, frc_msr */
/*
* =============================================================================
* Calibration setup end
* =============================================================================
*/
/* MMDC init: */
{0x021b0004, 0x0002002D}, /* MMDC0_MDPDC */
{0x021b0008, 0x1B333030}, /* MMDC0_MDOTC */
{0x021b000c, 0x2B2F52F3}, /* MMDC0_MDCFG0 */
{0x021b0010, 0xB66D0B63}, /* MMDC0_MDCFG1 */
{0x021b0014, 0x01FF00DB}, /* MMDC0_MDCFG2 */
/*
* MDMISC: RALAT kept to the high level of 5.
* MDMISC: consider reducing RALAT if your 528MHz board design allow that.
* Lower RALAT benefits:
* a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
* b. Small performance improvement
*/
{0x021b0018, 0x00211740}, /* MMDC0_MDMISC */
{0x021b001c, 0x00008000}, /*
* MMDC0_MDSCR, set the Configuration request bit during
* MMDC set up
*/
{0x021b002c, 0x000026D2}, /* MMDC0_MDRWD */
{0x021b0030, 0x002F1023}, /* MMDC0_MDOR */
{0x021b0040, 0x00000043}, /* Chan0 CS0_END */
{0x021b0000, 0x82180000}, /* MMDC0_MDCTL */
{0x021b0890, 0x00400000}, /* MPPDCMPR2 */
/* Mode register writes */
{0x021b001c, 0x02808032}, /* MMDC0_MDSCR, MR2 write, CS0 */
{0x021b001c, 0x00008033}, /* MMDC0_MDSCR, MR3 write, CS0 */
{0x021b001c, 0x00048031}, /* MMDC0_MDSCR, MR1 write, CS0 */
{0x021b001c, 0x15208030}, /* MMDC0_MDSCR, MR0write, CS0 */
{0x021b001c, 0x04008040}, /*
* MMDC0_MDSCR, ZQ calibration command sent to device
* on CS0
*/
{0x021b0020, 0x00007800}, /* MMDC0_MDREF */
{0x021b0818, 0x00000227}, /* DDR_PHY_P0_MPODTCTRL */
{0x021b0004, 0x0002552D}, /* MMDC0_MDPDC now SDCTL power down enabled */
{0x021b0404, 0x00011006}, /*
* MMDC0_MAPSR ADOPT power down enabled,
* MMDC will enter automatically to self-refresh
* while the number of idle cycle reached.
*/
{0x021b001c, 0x00000000}, /*
* MMDC0_MDSCR, clear this register (especially the
* configuration bit as initialization is complete)
*/
};
struct dram_timing_info bsh_dram_timing_128mb = {
.ddrc_cfg = ddr_ddrc_cfg_128mb,
.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_128mb),
};

168
board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m.c Normal file
View File

@ -0,0 +1,168 @@
// SPDX-License-Identifier: GPL-2.0+
#include "spl_mtypes.h"
static const struct dram_cfg_param ddr_ddrc_cfg_256mb[] = {
/* IOMUX */
/* DDR IO Type: */
{0x020e04b4, 0x000C0000}, /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
{0x020e04ac, 0x00000000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
/* Clock: */
{0x020e027c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
/* Address: */
{0x020e0250, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
{0x020e024c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
{0x020e0490, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
/* Control: */
{0x020e0288, 0x000C0028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
{0x020e0270, 0x00000000}, /*
* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured
* using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
*/
{0x020e0260, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */
{0x020e0264, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */
{0x020e04a0, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
/* Data Strobes: */
{0x020e0494, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
{0x020e0280, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */
{0x020e0284, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
/* Data: */
{0x020e04b0, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
{0x020e0498, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
{0x020e04a4, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
{0x020e0244, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
{0x020e0248, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
/*
* =============================================================================
* DDR Controller Registers
* =============================================================================
* Manufacturer:ISSI
* Device Part Number:IS43TR16640BL-125JBLI
* Clock Freq.: 400MHz
* Density per CS in Gb: 2
* Chip Selects used:1
* Number of Banks:8
* Row address: 14
* Column address: 10
* Data bus width16
* =============================================================================
*/
{0x021b001c, 0x00008000}, /*
* MMDC0_MDSCR, set the Configuration request bit during
* MMDC set up
*/
/*
* =============================================================================
* Calibration setup.
* =============================================================================
*/
{0x021b0800, 0xA1390003}, /*
* DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic
* HW ZQ calibration
*/
/*
* For target board, may need to run write leveling calibration to fine tune these settings
*/
{0x021b080c, 0x00050005},
/* Read DQS Gating calibration */
{0x021b083c, 0x01480144}, /* MPDGCTRL0 PHY0 */
/* Read calibration */
{0x021b0848, 0x4040363A}, /* MPRDDLCTL PHY0 */
/* Write calibration */
{0x021b0850, 0x40402E2C}, /* MPWRDLCTL PHY0 */
/*
* Read data bit delay: 3 is the reccommended default value, although out of reset value
* is 0
*/
{0x021b081c, 0x33333333}, /* MMDC_MPRDDQBY0DL */
{0x021b0820, 0x33333333}, /* MMDC_MPRDDQBY1DL */
/* Write data bit delay: */
{0x021b082c, 0xF3333333}, /* MMDC_MPWRDQBY0DL */
{0x021b0830, 0xF3333333}, /* MMDC_MPWRDQBY1DL */
/* DQS&CLK Duty Cycle */
{0x021b08c0, 0x00944009}, /* [MMDC_MPDCCR] MMDC Duty Cycle Control Register */
/* Complete calibration by forced measurement: */
{0x021b08b8, 0x00000800}, /* DDR_PHY_P0_MPMUR0, frc_msr */
/*
* =============================================================================
* Calibration setup end
* =============================================================================
*/
/* MMDC init: */
{0x021b0004, 0x0002002D}, /* MMDC0_MDPDC */
{0x021b0008, 0x1B333030}, /* MMDC0_MDOTC */
{0x021b000c, 0x3F435333}, /* MMDC0_MDCFG0 */
{0x021b0010, 0xB68E0B63}, /* MMDC0_MDCFG1 */
{0x021b0014, 0x01FF00DB}, /* MMDC0_MDCFG2 */
/*
* MDMISC: RALAT kept to the high level of 5.
* MDMISC: consider reducing RALAT if your 528MHz board design allow that.
* Lower RALAT benefits:
* a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
* b. Small performence improvment
*/
{0x021b0018, 0x00211740}, /* MMDC0_MDMISC */
{0x021b001c, 0x00008000}, /*
* MMDC0_MDSCR, set the Configuration request bit during
* MMDC set up
*/
{0x021b002c, 0x000026D2}, /* MMDC0_MDRWD */
{0x021b0030, 0x00431023}, /* MMDC0_MDOR */
{0x021b0040, 0x00000047}, /* Chan0 CS0_END */
{0x021b0000, 0x83180000}, /* MMDC0_MDCTL */
{0x021b0890, 0x00400000}, /* MPPDCMPR2 */
/* Mode register writes */
{0x021b001c, 0x02808032}, /* MMDC0_MDSCR, MR2 write, CS0 */
{0x021b001c, 0x00008033}, /* MMDC0_MDSCR, MR3 write, CS0 */
{0x021b001c, 0x00048031}, /* MMDC0_MDSCR, MR1 write, CS0 */
{0x021b001c, 0x15208030}, /* MMDC0_MDSCR, MR0write, CS0 */
{0x021b001c, 0x04008040}, /*
* MMDC0_MDSCR, ZQ calibration command sent to device
* on CS0
*/
{0x021b0020, 0x00007800}, /* MMDC0_MDREF */
{0x021b0818, 0x00000227}, /* DDR_PHY_P0_MPODTCTRL */
{0x021b0004, 0x0002552D}, /* MMDC0_MDPDC now SDCTL power down enabled */
{0x021b0404, 0x00011006}, /*
* MMDC0_MAPSR ADOPT power down enabled, MMDC will enter
* automatically to self-refresh while the number of idle
* cycle reached
*/
{0x021b001c, 0x00000000}, /*
* MMDC0_MDSCR, clear this register (especially the
* configuration bit as initialization is complete)
*/
};
struct dram_timing_info bsh_dram_timing_256mb = {
.ddrc_cfg = ddr_ddrc_cfg_256mb,
.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_256mb),
};

168
board/bsh/imx6ulz_smm_m2/ddr3l_timing_512m.c Normal file
View File

@ -0,0 +1,168 @@
// SPDX-License-Identifier: GPL-2.0+
#include "spl_mtypes.h"
static const struct dram_cfg_param ddr_ddrc_cfg_512mb[] = {
/*
* =============================================================================
* IOMUX
* =============================================================================
*/
/* DDR IO Type: */
{0x020e04b4, 0x000C0000}, /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
{0x020e04ac, 0x00000000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
/* Clock: */
{0x020e027c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
/* Address: */
{0x020e0250, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
{0x020e024c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
{0x020e0490, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
/* Control: */
{0x020e0288, 0x000C0028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
{0x020e0270, 0x00000000}, /*
* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using
* Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
*/
{0x020e0260, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */
{0x020e0264, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */
{0x020e04a0, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
/* Data Strobes: */
{0x020e0494, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
{0x020e0280, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */
{0x020e0284, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
/* Data: */
{0x020e04b0, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
{0x020e0498, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
{0x020e04a4, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
{0x020e0244, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
{0x020e0248, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
/*
* =============================================================================
* DDR Controller Registers
* =============================================================================
* Manufacturer:ISSI
* Device Part Number:IS43TR16640BL-125JBLI
* Clock Freq.: 400MHz
* Density per CS in Gb: 2
* Chip Selects used:1
* Number of Banks:8
* Row address: 14
* Column address: 10
* Data bus width16
* =============================================================================
*/
{0x021b001c, 0x00008000}, /*
* MMDC0_MDSCR, set the Configuration request bit during
* MMDC set up
*/
/*
* =============================================================================
* Calibration setup.
* =============================================================================
*/
{0x021b0800, 0xA1390003}, /*
* DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic
* HW ZQ calibration
*/
/*
* For target board may need to run write leveling calibration to fine tune these settings
*/
{0x021b080c, 0x00000000},
/* Read DQS Gating calibration */
{0x021b083c, 0x01440140}, /* MPDGCTRL0 PHY0 */
/* Read calibration */
{0x021b0848, 0x40403A3E}, /* MPRDDLCTL PHY0 */
/* Write calibration */
{0x021b0850, 0x4040322A}, /* MPWRDLCTL PHY0 */
/*
* Read data bit delay: 3 is the reccommended default value, although out of reset value
* is 0
*/
{0x021b081c, 0x33333333}, /* MMDC_MPRDDQBY0DL */
{0x021b0820, 0x33333333}, /* MMDC_MPRDDQBY1DL */
/* Write data bit delay: */
{0x021b082c, 0xF3333333}, /* MMDC_MPWRDQBY0DL */
{0x021b0830, 0xF3333333}, /* MMDC_MPWRDQBY1DL */
/* DQS&CLK Duty Cycle */
{0x021b08c0, 0x00944009}, /* [MMDC_MPDCCR] MMDC Duty Cycle Control Register */
/* Complete calibration by forced measurement: */
{0x021b08b8, 0x00000800}, /* DDR_PHY_P0_MPMUR0, frc_msr */
/*
* =============================================================================
* Calibration setup end
* =============================================================================
*/
/* MMDC init: */
{0x021b0004, 0x0002002D}, /* MMDC0_MDPDC */
{0x021b0008, 0x1B333030}, /* MMDC0_MDOTC */
{0x021b000c, 0x3F435333}, /* MMDC0_MDCFG0 */
{0x021b0010, 0xB68E0B63}, /* MMDC0_MDCFG1 */
{0x021b0014, 0x01FF00DB}, /* MMDC0_MDCFG2 */
/*
* MDMISC: RALAT kept to the high level of 5.
* MDMISC: consider reducing RALAT if your 528MHz board design allow that.
* Lower RALAT benefits:
* a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
* b. Small performence improvment
*/
{0x021b0018, 0x00211740}, /* MMDC0_MDMISC */
{0x021b001c, 0x00008000}, /*
* MMDC0_MDSCR set the Configuration request bit during
* MMDC set up
*/
{0x021b002c, 0x000026D2}, /* MMDC0_MDRWD */
{0x021b0030, 0x00431023}, /* MMDC0_MDOR */
{0x021b0040, 0x0000004F}, /* Chan0 CS0_END */
{0x021b0000, 0x84180000}, /* MMDC0_MDCTL */
{0x021b0890, 0x00400000}, /* MPPDCMPR2 */
/* Mode register writes */
{0x021b001c, 0x02808032}, /* MMDC0_MDSCR, MR2 write, CS0 */
{0x021b001c, 0x00008033}, /* MMDC0_MDSCR, MR3 write, CS0 */
{0x021b001c, 0x00048031}, /* MMDC0_MDSCR, MR1 write, CS0 */
{0x021b001c, 0x15208030}, /* MMDC0_MDSCR, MR0write, CS0 */
{0x021b001c, 0x04008040}, /* MMDC0_MDSCR, ZQ calibration command sent to device on CS0 */
{0x021b0020, 0x00007800}, /* MMDC0_MDREF */
{0x021b0818, 0x00000227}, /* DDR_PHY_P0_MPODTCTRL */
{0x021b0004, 0x0002552D}, /* MMDC0_MDPDC now SDCTL power down enabled */
{0x021b0404, 0x00011006}, /*
* MMDC0_MAPSR ADOPT power down enabled, MMDC will enter
* automatically to self-refresh while the number of idle
* cycle reached
*/
{0x021b001c, 0x00000000}, /*
* MMDC0_MDSCR, clear this register (especially the configuration
* bit as initialization is complete)
*/
};
struct dram_timing_info bsh_dram_timing_512mb = {
.ddrc_cfg = ddr_ddrc_cfg_512mb,
.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_512mb),
};

111
board/bsh/imx6ulz_smm_m2/spl.c
View File

@ -13,10 +13,13 @@
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
#include "spl_mtypes.h"
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
@ -31,69 +34,48 @@ static void setup_iomux_uart(void)
imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
}
static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
.grp_addds = 0x00000028,
.grp_ddrmode_ctl = 0x00020000,
.grp_b0ds = 0x00000028,
.grp_ctlds = 0x00000028,
.grp_b1ds = 0x00000028,
.grp_ddrpke = 0x00000000,
.grp_ddrmode = 0x00020000,
.grp_ddr_type = 0x000c0000,
};
static void ddr_cfg_write(const struct dram_timing_info *dram_timing_info)
{
int i;
const struct dram_cfg_param *ddrc_cfg = dram_timing_info->ddrc_cfg;
const int ddrc_cfg_num = dram_timing_info->ddrc_cfg_num;
struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_dqm0 = 0x00000028,
.dram_dqm1 = 0x00000028,
.dram_ras = 0x00000028,
.dram_cas = 0x00000028,
.dram_odt0 = 0x00000028,
.dram_odt1 = 0x00000028,
.dram_sdba2 = 0x00000000,
.dram_sdclk_0 = 0x00000028,
.dram_sdqs0 = 0x00000028,
.dram_sdqs1 = 0x00000028,
.dram_reset = 0x000c0028,
};
clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */
clrbits_le32(&mmdc0->mdctl, 1 << 30); /* clear SDE_1 */
static struct mx6_mmdc_calibration mx6_mmcd_calib = {
.p0_mpwldectrl0 = 0x00000000,
.p0_mpwldectrl1 = 0x00100010,
.p0_mpdgctrl0 = 0x414c014c,
.p0_mpdgctrl1 = 0x00000000,
.p0_mprddlctl = 0x40403a42,
.p0_mpwrdlctl = 0x4040342e,
};
for (i = 0; i < ddrc_cfg_num; i++) {
debug("Writing 0x%x to register 0x%x\n", ddrc_cfg->val,
ddrc_cfg->reg);
writel(ddrc_cfg->val, ddrc_cfg->reg);
ddrc_cfg++;
}
}
static struct mx6_ddr_sysinfo ddr_sysinfo = {
.dsize = 0,
.cs1_mirror = 0,
.cs_density = 32,
.ncs = 1,
.bi_on = 1,
.rtt_nom = 1,
.rtt_wr = 0,
.ralat = 5,
.walat = 1,
.mif3_mode = 3,
.rst_to_cke = 0x23, /* 33 cycles (JEDEC value for DDR3) - total of 500 us */
.sde_to_rst = 0x10, /* 14 cycles (JEDEC value for DDR3) - total of 200 us */
.refsel = 1,
.refr = 3,
};
static void spl_dram_init(void)
{
/* Configure memory to maximum supported size for detection */
ddr_cfg_write(&bsh_dram_timing_512mb);
static struct mx6_ddr3_cfg mem_ddr = {
.mem_speed = 1333,
.density = 2,
.width = 16,
.banks = 8,
.rowaddr = 13,
.coladdr = 10,
.pagesz = 2,
.trcd = 1350,
.trcmin = 4950,
.trasmin = 3600,
};
/* Detect memory physically present */
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_512M);
/* Reconfigure memory for actual detected size */
switch (gd->ram_size) {
case SZ_512M:
/* Already configured, nothing to do */
break;
case SZ_256M:
udelay(1);
ddr_cfg_write(&bsh_dram_timing_256mb);
break;
case SZ_128M:
default:
udelay(1);
ddr_cfg_write(&bsh_dram_timing_128mb);
break;
}
}
static void ccgr_init(void)
{
@ -108,20 +90,17 @@ static void ccgr_init(void)
writel(0xFFFFFFFF, &ccm->CCGR6);
}
static void imx6ul_spl_dram_cfg(void)
{
mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
}
void board_init_f(ulong dummy)
{
ccgr_init();
/* DDR initialization */
spl_dram_init();
arch_cpu_init();
timer_init();
setup_iomux_uart();
preloader_console_init();
imx6ul_spl_dram_cfg();
}
void reset_cpu(void)

27
board/bsh/imx6ulz_smm_m2/spl_mtypes.h Normal file
View File

@ -0,0 +1,27 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2025 BSH Hausgeraete GmbH
*
* Written by: Simon Holesch <simon.holesch@bshg.com>
*/
#ifndef SPL_MTYPES_H
#define SPL_MTYPES_H
#include <spl.h>
struct dram_cfg_param {
unsigned int reg;
unsigned int val;
};
struct dram_timing_info {
const struct dram_cfg_param *ddrc_cfg;
unsigned int ddrc_cfg_num;
};
extern struct dram_timing_info bsh_dram_timing_128mb;
extern struct dram_timing_info bsh_dram_timing_256mb;
extern struct dram_timing_info bsh_dram_timing_512mb;
#endif /* SPL_MTYPES_H */

2
board/bsh/imx8mn_smm_s2/spl.c
View File

@ -43,8 +43,6 @@ void spl_board_init(void)
int board_early_init_f(void)
{
init_uart_clk(3);
if (IS_ENABLED(CONFIG_NAND_MXS)) {
init_nand_clk();
}

1
board/emulation/qemu-x86/Kconfig
View File

@ -23,5 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply VIRTIO_PCI
imply VIRTIO_NET
imply VIRTIO_BLK
imply CMD_SMBIOS
endif

2
board/freescale/imx8mn_evk/spl.c
View File

@ -115,8 +115,6 @@ void board_init_f(ulong dummy)
arch_cpu_init();
init_uart_clk(1);
timer_init();
/* Clear the BSS. */

2
board/phytec/phycore_imx93/MAINTAINERS
View File

@ -3,8 +3,6 @@ M: Mathieu Othacehe <m.othacehe@gmail.com>
R: Christoph Stoidner <c.stoidner@phytec.de>
W: https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/
S: Maintained
F: arch/arm/dts/imx93-phyboard-segin.dts
F: arch/arm/dts/imx93-phycore-som.dtsi
F: arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
F: board/phytec/phycore_imx93/
F: board/phytec/common/imx93_som_detection.c

5
board/thead/th1520_lpi4a/Kconfig
View File

@ -11,7 +11,7 @@ config SYS_VENDOR
default "thead"
config SYS_CPU
default "generic"
default "th1520"
config SYS_CONFIG_NAME
default "th1520_lpi4a"
@ -22,7 +22,7 @@ config TEXT_BASE
default 0x01c00000 if RISCV_SMODE
config SPL_TEXT_BASE
default 0x08000000
default 0xffe0000000
config SPL_OPENSBI_LOAD_ADDR
default 0x80000000
@ -30,6 +30,7 @@ config SPL_OPENSBI_LOAD_ADDR
config BOARD_SPECIFIC_OPTIONS
def_bool y
select ARCH_EARLY_INIT_R
select THEAD_TH1520
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if RISCV_SMODE

1
board/thead/th1520_lpi4a/Makefile
View File

@ -3,3 +3,4 @@
# Copyright (c) 2023, Yixun Lan <dlan@gentoo.org>
obj-y += board.o
obj-$(CONFIG_XPL_BUILD) += spl.o

48
board/thead/th1520_lpi4a/spl.c Normal file
View File

@ -0,0 +1,48 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2025, Yao Zi <ziyao@disroot.org>
*/
#include <asm/io.h>
#include <asm/spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/spl.h>
#include <cpu_func.h>
#include <dm.h>
#include <hang.h>
#include <spl.h>
u32 spl_boot_device(void)
{
/*
* We don't bother to load proper U-Boot from an external device as
* it fits in the integrated SRAM nicely.
*/
return BOOT_DEVICE_RAM;
}
void board_init_f(ulong dummy)
{
int ret = spl_early_init();
struct udevice *dev;
if (ret)
panic("spl_early_init() failed %d\n", ret);
preloader_console_init();
/*
* Manually bind CPU ahead of time to make sure in-core timers are
* available in SPL.
*/
ret = uclass_get_device(UCLASS_CPU, 0, &dev);
if (ret)
panic("failed to bind CPU: %d\n", ret);
spl_dram_init();
icache_enable();
dcache_enable();
th1520_invalidate_pmp();
}

3
boot/image.c
View File

@ -92,7 +92,8 @@ static const table_entry_t uimage_arch[] = {
{ IH_ARCH_ARC, "arc", "ARC", },
{ IH_ARCH_X86_64, "x86_64", "AMD x86_64", },
{ IH_ARCH_XTENSA, "xtensa", "Xtensa", },
{ IH_ARCH_RISCV, "riscv", "RISC-V", },
{ IH_ARCH_RISCV, "riscv", "RISC-V 32 Bit",},
{ IH_ARCH_RISCV64, "riscv64", "RISC-V 64 Bit",},
{ -1, "", "", },
};

1
cmd/bootefi.c
View File

@ -9,6 +9,7 @@
#include <command.h>
#include <efi.h>
#include <efi_device_path.h>
#include <efi_loader.h>
#include <exports.h>
#include <log.h>

7
cmd/booti.c
View File

@ -130,8 +130,11 @@ int do_booti(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
bootm_disable_interrupts();
images.os.os = IH_OS_LINUX;
if (IS_ENABLED(CONFIG_RISCV_SMODE))
images.os.arch = IH_ARCH_RISCV;
if (IS_ENABLED(CONFIG_RISCV))
if (IS_ENABLED(CONFIG_64BIT))
images.os.arch = IH_ARCH_RISCV64;
else
images.os.arch = IH_ARCH_RISCV;
else if (IS_ENABLED(CONFIG_ARM64))
images.os.arch = IH_ARCH_ARM64;

5
cmd/eficonfig.c
View File

@ -8,6 +8,7 @@
#include <ansi.h>
#include <cli.h>
#include <charset.h>
#include <efi_device_path.h>
#include <efi_loader.h>
#include <efi_load_initrd.h>
#include <efi_config.h>
@ -514,7 +515,7 @@ struct efi_device_path *eficonfig_create_device_path(struct efi_device_path *dp_
struct efi_device_path_file_path *fp;
fp_size = sizeof(struct efi_device_path) + u16_strsize(current_path);
buf = calloc(1, fp_size + sizeof(END));
buf = calloc(1, fp_size + sizeof(EFI_DP_END));
if (!buf)
return NULL;
@ -526,7 +527,7 @@ struct efi_device_path *eficonfig_create_device_path(struct efi_device_path *dp_
p = buf;
p += fp_size;
*((struct efi_device_path *)p) = END;
*((struct efi_device_path *)p) = EFI_DP_END;
dp = efi_dp_shorten(dp_volume);
if (!dp)

7
cmd/efidebug.c
View File

@ -8,6 +8,7 @@
#include <charset.h>
#include <command.h>
#include <dm/device.h>
#include <efi_device_path.h>
#include <efi_dt_fixup.h>
#include <efi_load_initrd.h>
#include <efi_loader.h>
@ -812,7 +813,7 @@ static int efi_boot_add_uri(int argc, char *const argv[], u16 *var_name16,
lo->label = label;
uridp_len = sizeof(struct efi_device_path) + strlen(argv[3]) + 1;
uridp = efi_alloc(uridp_len + sizeof(END));
uridp = efi_alloc(uridp_len + sizeof(EFI_DP_END));
if (!uridp) {
log_err("Out of memory\n");
return CMD_RET_FAILURE;
@ -822,10 +823,10 @@ static int efi_boot_add_uri(int argc, char *const argv[], u16 *var_name16,
uridp->dp.length = uridp_len;
strcpy(uridp->uri, argv[3]);
pos = (char *)uridp + uridp_len;
memcpy(pos, &END, sizeof(END));
memcpy(pos, &EFI_DP_END, sizeof(EFI_DP_END));
*file_path = &uridp->dp;
*fp_size += uridp_len + sizeof(END);
*fp_size += uridp_len + sizeof(EFI_DP_END);
return CMD_RET_SUCCESS;
}

1
cmd/tlv_eeprom.c
View File

@ -476,6 +476,7 @@ int do_tlv_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
printf("EEPROM data loaded from device to memory.\n");
has_been_read = 1;
return 0;
}
// Subsequent commands require that the EEPROM has already been read.

4
common/board_r.c
View File

@ -814,7 +814,9 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
if (CONFIG_IS_ENABLED(X86_64) && !IS_ENABLED(CONFIG_EFI_APP))
arch_setup_gd(new_gd);
#if !defined(CONFIG_X86) && !defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
#if defined(CONFIG_RISCV)
set_gd(new_gd);
#elif !defined(CONFIG_X86) && !defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
gd = new_gd;
#endif
gd->flags &= ~GD_FLG_LOG_READY;

17
common/cyclic.c
View File

@ -28,9 +28,23 @@ struct hlist_head *cyclic_get_list(void)
return (struct hlist_head *)&gd->cyclic_list;
}
static bool cyclic_is_registered(const struct cyclic_info *cyclic)
{
const struct cyclic_info *c;
hlist_for_each_entry(c, cyclic_get_list(), list) {
if (c == cyclic)
return true;
}
return false;
}
void cyclic_register(struct cyclic_info *cyclic, cyclic_func_t func,
uint64_t delay_us, const char *name)
{
cyclic_unregister(cyclic);
memset(cyclic, 0, sizeof(*cyclic));
/* Store values in struct */
@ -43,6 +57,9 @@ void cyclic_register(struct cyclic_info *cyclic, cyclic_func_t func,
void cyclic_unregister(struct cyclic_info *cyclic)
{
if (!cyclic_is_registered(cyclic))
return;
hlist_del(&cyclic->list);
}

7
common/init/board_init.c
View File

@ -13,8 +13,11 @@
DECLARE_GLOBAL_DATA_PTR;
/* Unfortunately x86 or ARM can't compile this code as gd cannot be assigned */
#if !defined(CONFIG_X86) && !defined(CONFIG_ARM)
/*
* Unfortunately x86, ARM and RISC-V can't compile this code as gd is defined
* as macro and cannot be assigned.
*/
#if !defined(CONFIG_X86) && !defined(CONFIG_ARM) && !defined(CONFIG_RISCV)
__weak void arch_setup_gd(struct global_data *gd_ptr)
{
gd = gd_ptr;

15
common/spl/Kconfig
View File

@ -974,6 +974,21 @@ config SPL_NAND_SUPPORT
This enables the drivers in drivers/mtd/nand/raw as part of an SPL
build.
config SPL_NAND_RAW_U_BOOT_USE_SECTOR
bool "NAND raw mode: by sector"
depends on SPL_NAND_SUPPORT
select SPL_LOAD_BLOCK
help
Use sector number for specifying U-Boot location on NAND in
raw mode.
config SPL_NAND_RAW_U_BOOT_SECTOR
hex "Address on the NAND to load U-Boot from"
depends on SPL_NAND_RAW_U_BOOT_USE_SECTOR
help
Address on the NAND to load U-Boot from, when the NAND is being used
in raw mode. Units: NAND disk sectors (1 sector = 512 bytes).
config SPL_NAND_RAW_ONLY
bool "Support to boot only raw u-boot.bin images"
depends on SPL_NAND_SUPPORT

2
configs/ds109_defconfig
View File

@ -54,8 +54,6 @@ CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_DM_RTC=y
CONFIG_RTC_MV=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SYS_NS16550_REG_SIZE=-4
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y

3
configs/imx6ulz_smm_m2_defconfig
View File

@ -64,6 +64,8 @@ CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_SPL_USB_HOST=y
@ -75,3 +77,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_SDP_LOADADDR=0x877fffc0
CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_IMX_WATCHDOG=y

3
configs/imx8mn_bsh_smm_s2_defconfig
View File

@ -15,7 +15,6 @@ CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK=0x980000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x950000
@ -47,6 +46,8 @@ CONFIG_SPL_DMA=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_RAW_U_BOOT_USE_SECTOR=y
CONFIG_SPL_NAND_RAW_U_BOOT_SECTOR=0x300
CONFIG_SPL_NAND_BASE=y
CONFIG_SPL_NAND_IDENT=y
CONFIG_SPL_POWER=y

1
configs/imx8mn_bsh_smm_s2pro_defconfig
View File

@ -16,7 +16,6 @@ CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK=0x980000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x950000

2
configs/imx93-phycore_defconfig
View File

@ -12,7 +12,7 @@ CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x700000
CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx93-phyboard-segin"
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx93-phyboard-segin"
CONFIG_AHAB_BOOT=y
CONFIG_TARGET_PHYCORE_IMX93=y
CONFIG_OF_LIBFDT_OVERLAY=y

1
configs/imx95_19x19_evk_defconfig
View File

@ -41,6 +41,7 @@ CONFIG_SYS_PBSIZE=2074
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_PCI_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_LOAD_IMX_CONTAINER=y

15
configs/imxrt1170-evk_defconfig
View File

@ -37,6 +37,8 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
CONFIG_CMD_MTD=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_MII is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
@ -58,6 +60,15 @@ CONFIG_CLK_IMXRT1170=y
CONFIG_MXC_GPIO=y
# CONFIG_INPUT is not set
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_CFI_FLASH=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMXRT=y
@ -65,6 +76,10 @@ CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_IMXRT_SDRAM=y
CONFIG_FSL_LPUART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPI_DIRMAP=y
CONFIG_NXP_FSPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_IMX_GPT_TIMER=y

2
configs/mvebu_espressobin_ultra-88f3720_defconfig
View File

@ -97,3 +97,5 @@ CONFIG_USB_EHCI_HCD=y
# CONFIG_WATCHDOG_AUTOSTART is not set
CONFIG_WDT=y
CONFIG_WDT_ARMADA_37XX=y
CONFIG_DM_RNG=y
CONFIG_RNG_TURRIS_RWTM=y

18
configs/th1520_lpi4a_defconfig
View File

@ -90,3 +90,21 @@ CONFIG_ZLIB_UNCOMPRESS=y
CONFIG_BZIP2=y
CONFIG_ZSTD=y
CONFIG_LIB_RATIONAL=y
CONFIG_SPL=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_LOAD_FIT_ADDRESS=0xffe0040000
CONFIG_SPL_HAVE_INIT_STACK=y
CONFIG_SPL_STACK=0xffe0170000
CONFIG_SPL_BSS_START_ADDR=0xffe0160000
CONFIG_SPL_BSS_MAX_SIZE=0x10000
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_RAM_DEVICE=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_SPL_THEAD_TH1520_DDR=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_MMC_y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x10000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x400000

3
configs/total_compute_defconfig
View File

@ -55,3 +55,6 @@ CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_SECT=256
# CONFIG_RANDOM_UUID is not set
CONFIG_LIBAVB=y
CONFIG_BLOBLIST=y
CONFIG_BLOBLIST_PASSAGE_MANDATORY=y
CONFIG_BLOBLIST_SIZE_RELOC=0x10000

27
doc/README.omap-ulpi-viewport
View File

@ -1,27 +0,0 @@
Reference code ""drivers/usb/ulpi/omap-ulpi-viewport.c"
Contains the ulpi read write api's to perform
any ulpi phy port access on omap platform.
On omap ehci reg map contains INSNREG05_ULPI
register which offers the ulpi phy access so
any ulpi phy commands should be passsed using this
register.
omap-ulpi-viewport.c is a low level function
implementation of "drivers/usb/ulpi/ulpi.c"
To enable and use omap-ulpi-viewport.c
we require CONFIG_USB_ULPI_VIEWPORT_OMAP and
CONFIG_USB_ULPI be enabled in config file.
Any ulpi ops request can be done with ulpi.c
and soc specific binding and usage is done with
omap-ulpi-viewport implementation.
Ex: scenario:
omap-ehci driver code requests for ulpi phy reset if
ehci is used in phy mode, which will call ulpi phy reset
the ulpi phy reset does ulpi_read/write from viewport
implementation which will do ulpi reset using the
INSNREG05_ULPI register.

6
doc/api/efi.rst
View File

@ -178,6 +178,12 @@ Driver binding protocol
.. kernel-doc:: include/efi_driver.h
:internal:
Device paths
------------
.. kernel-doc:: include/efi_device_path.h
:internal:
Unit testing
------------

58
doc/board/thead/lpi4a.rst
View File

@ -32,6 +32,8 @@ Mainline support
The support for following drivers are already enabled:
1. ns16550 UART Driver.
2. eMMC and SD card
Building
~~~~~~~~
@ -43,15 +45,32 @@ Building
export CROSS_COMPILE=<riscv64 toolchain prefix>
The U-Boot is capable of running in M-Mode, so we can directly build it.
3. Build DDR firmware
DDR driver requires a firmware to function, to build it:
.. code-block:: bash
git clone --depth 1 https://github.com/ziyao233/th1520-firmware
cd th1520-firmware
lua5.4 ddr-generate.lua src/<CONFIGURATION_NAME>.lua th1520-ddr-firmware.bin
4. Build U-Boot images
The U-Boot is capable of running in M-Mode, so we can directly build it without
OpenSBI. The DDR firmware should be copied to U-Boot source directory before
building.
.. code-block:: console
cd <U-Boot-dir>
cp <path-to-ddr-firmware> th1520-ddr-firmware.bin
make th1520_lpi4a_defconfig
make
This will generate u-boot-dtb.bin
This will generate u-boot-dtb.bin and u-boot-with-spl.bin. The former contains
only proper U-Boot and is for chainloading; the later contains also SPL and
DDR firmware and is ready for booting by BROM directly.
Booting
~~~~~~~
@ -61,7 +80,7 @@ and chain load the mainline u-boot image either via tftp or emmc storage,
then bootup from it.
Sample boot log from Lichee PI 4A board via tftp
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
.. code-block:: none
@ -127,3 +146,36 @@ Sample boot log from Lichee PI 4A board via tftp
Err: serial@ffe7014000
Model: Sipeed Lichee Pi 4A
LPI4A=>
SPL support is still in an early stage and not all of the functionalities are
available when booting from mainline SPL. When using mainline SPL,
u-boot-with-spl.bin should be loaded to SRAM through fastboot.
Sample boot log from Lichee PI 4A board via fastboot and mainline SPL
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
.. code-block:: none
brom_ver 8
[APP][E] protocol_connect failed, exit.
Starting download of 636588 bytes
downloading of 636588 bytes finished
U-Boot SPL 2025.04-rc2-00049-geaa9fc99d4cd-dirty (Apr 26 2025 - 13:31:41 +0000)
Trying to boot from RAM
U-Boot 2025.04-rc2-00049-geaa9fc99d4cd-dirty (Apr 26 2025 - 13:31:41 +0000)
CPU: thead,c910
Model: Sipeed Lichee Pi 4A
DRAM: 8 GiB
Core: 30 devices, 9 uclasses, devicetree: separate
MMC: mmc@ffe7080000: 0, mmc@ffe7090000: 1
Loading Environment from <NULL>... OK
In: serial@ffe7014000
Out: serial@ffe7014000
Err: serial@ffe7014000
Model: Sipeed Lichee Pi 4A
LPI4A=>

13
doc/develop/cyclic.rst
View File

@ -54,3 +54,16 @@ responsible for calling all registered cyclic functions, into the
common schedule() function. This guarantees that cyclic_run() is
executed very often, which is necessary for the cyclic functions to
get scheduled and executed at their configured periods.
Idempotence
-----------
Both the cyclic_register() and cyclic_unregister() functions are safe
to call on any struct cyclic_info, regardless of whether that instance
is already registered or not.
More specifically, calling cyclic_unregister() with a cyclic_info
which is not currently registered is a no-op, while calling
cyclic_register() with a cyclic_info which is currently registered
results in it being automatically unregistered, and then registered
with the new callback function and timeout parameters.

10
doc/develop/pytest/index.rst
View File

@ -16,12 +16,6 @@ Individual tests
.. toctree::
:maxdepth: 1
:glob:
test_000_version
test_bind
test_bootmenu
test_bootstage
test_button
test_efi_loader
test_net
test_net_boot
test_*

24
doc/develop/pytest/usage.rst
View File

@ -522,3 +522,27 @@ of the `ubman.config` object, for example
Build configuration values (from `.config`) may be accessed via the dictionary
`ubman.config.buildconfig`, with keys equal to the Kconfig variable
names.
A required configuration setting can be defined via a buildconfigspec()
annotation. The name of the configuration option is specified in lower case. The
following annotation for a test requires CONFIG_EFI_LOADER=y:
.. code-block:: python
@pytest.mark.buildconfigspec('efi_loader')
Sometimes multiple configuration option supply the same functionality. If
multiple arguments are passed to buildconfigspec(), only one of the
configuration options needs to be set. The following annotation requires that
either of CONFIG_NET or CONFIG_NET_LWIP is set:
.. code-block:: python
@pytest.mark.buildconfigspec('net', 'net lwip')
The notbuildconfigspec() annotation can be used to require a configuration
option not to be set. The following annotation requires CONFIG_RISCV=n:
.. code-block:: python
@pytest.mark.notbuildconfigspec('riscv')

2
doc/develop/release_cycle.rst
View File

@ -75,7 +75,7 @@ For the next scheduled release, release candidates were made on::
* U-Boot |next_ver|-rc2 was released on Mon 12 May 2025.
.. * U-Boot |next_ver|-rc3 was released on Mon 26 May 2025.
* U-Boot |next_ver|-rc3 was released on Mon 26 May 2025.
.. * U-Boot |next_ver|-rc4 was released on Mon 09 June 2025.

2
doc/usage/cmd/wget.rst
View File

@ -141,9 +141,9 @@ https://cacerts.digicert.com/DigiCertTLSRSA4096RootG5.crt.
Bytes transferred = 1864 (748 hex)
# Another server not signed against Digicert will fail
=> wget https://www.google.com/
Certificate verification failed
HTTP client error 4
Certificate verification failed
# Disable authentication to allow the command to proceed anyways
=> wget cacert none
=> wget https://www.google.com/

1
drivers/clk/Kconfig
View File

@ -271,6 +271,7 @@ source "drivers/clk/starfive/Kconfig"
source "drivers/clk/stm32/Kconfig"
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/ti/Kconfig"
source "drivers/clk/thead/Kconfig"
source "drivers/clk/uniphier/Kconfig"
endmenu

1
drivers/clk/Makefile
View File

@ -20,6 +20,7 @@ obj-y += imx/
obj-$(CONFIG_CLK_JH7110) += starfive/
obj-y += tegra/
obj-y += ti/
obj-$(CONFIG_CLK_THEAD) += thead/
obj-$(CONFIG_$(PHASE_)CLK_INTEL) += intel/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/

9
drivers/clk/imx/clk-imxrt1170.c
View File

@ -105,6 +105,8 @@ static const char * const usdhc1_sels[] = {"rcosc48M_div2", "osc", "rcosc400M",
"pll2_pfd2", "pll2_pfd0", "pll1_div5", "pll_arm"};
static const char * const semc_sels[] = {"rcosc48M_div2", "osc", "rcosc400M", "rcosc16M",
"pll1_div5", "pll2_sys", "pll2_pfd2", "pll3_pfd0"};
static const char * const flexspi1_sels[] = {"rcosc48M_div2", "osc", "rcosc400M", "rcosc16M",
"pll3_pdf0", "pll2_clk", "pll2_pfd2", "pll3_clk"};
static int imxrt1170_clk_probe(struct udevice *dev)
{
@ -163,6 +165,13 @@ static int imxrt1170_clk_probe(struct udevice *dev)
imx_clk_divider(dev, "lpuart1", "lpuart1_sel",
base + (25 * 0x80), 0, 8));
clk_dm(IMXRT1170_CLK_FLEXSPI1_SEL,
imx_clk_mux(dev, "flexspi1_sel", base + (20 * 0x80), 8, 3,
flexspi1_sels, ARRAY_SIZE(flexspi1_sels)));
clk_dm(IMXRT1170_CLK_FLEXSPI1,
imx_clk_divider(dev, "flexspi1", "flexspi1_sel",
base + (20 * 0x80), 0, 8));
clk_dm(IMXRT1170_CLK_USDHC1_SEL,
imx_clk_mux(dev, "usdhc1_sel", base + (58 * 0x80), 8, 3,
usdhc1_sels, ARRAY_SIZE(usdhc1_sels)));

19
drivers/clk/thead/Kconfig Normal file
View File

@ -0,0 +1,19 @@
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Copyright (c) 2025, Yao Zi <ziyao@disroot.org>
config CLK_THEAD
bool "Clock support for T-Head SoCs"
depends on CLK
if CLK_THEAD
config CLK_THEAD_TH1520_AP
bool "T-Head TH1520 AP clock support"
select CLK_CCF
default THEAD_TH1520
help
This enables support clock driver for T-Head TH1520 Application
processor.
endif

5
drivers/clk/thead/Makefile Normal file
View File

@ -0,0 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
obj-$(CONFIG_CLK_THEAD_TH1520_AP) += clk-th1520-ap.o

1031
drivers/clk/thead/clk-th1520-ap.c Normal file
View File

File diff suppressed because it is too large Load Diff

25
drivers/crypto/fsl/jr.c
View File

@ -217,13 +217,6 @@ static int jr_enqueue(uint32_t *desc_addr,
jr->head = (head + 1) & (jr->size - 1);
/* Invalidate output ring */
start = (unsigned long)jr->output_ring &
~(ARCH_DMA_MINALIGN - 1);
end = ALIGN((unsigned long)jr->output_ring + jr->op_size,
ARCH_DMA_MINALIGN);
invalidate_dcache_range(start, end);
sec_out32(&regs->irja, 1);
return 0;
@ -243,6 +236,7 @@ static int jr_dequeue(int sec_idx, struct caam_regs *caam)
#else
uint32_t *addr;
#endif
unsigned long start, end;
while (sec_in32(&regs->orsf) && CIRC_CNT(jr->head, jr->tail,
jr->size)) {
@ -250,6 +244,11 @@ static int jr_dequeue(int sec_idx, struct caam_regs *caam)
found = 0;
caam_dma_addr_t op_desc;
/* Invalidate output ring */
start = (unsigned long)jr->output_ring & ~(ARCH_DMA_MINALIGN - 1);
end = ALIGN((unsigned long)jr->output_ring + jr->op_size, ARCH_DMA_MINALIGN);
invalidate_dcache_range(start, end);
#ifdef CONFIG_CAAM_64BIT
/* Read the 64 bit Descriptor address from Output Ring.
* The 32 bit hign and low part of the address will
@ -283,8 +282,13 @@ static int jr_dequeue(int sec_idx, struct caam_regs *caam)
}
/* Error condition if match not found */
if (!found)
if (!found) {
int slots_full = sec_in32(&regs->orsf);
jr->tail = (jr->tail + slots_full) & (jr->size - 1);
sec_out32(&regs->orjr, slots_full);
return -1;
}
jr->info[idx].op_done = 1;
callback = (void *)jr->info[idx].callback;
@ -296,14 +300,14 @@ static int jr_dequeue(int sec_idx, struct caam_regs *caam)
*/
if (idx == tail)
do {
jr->info[tail].op_done = 0;
tail = (tail + 1) & (jr->size - 1);
} while (jr->info[tail].op_done);
jr->tail = tail;
jr->read_idx = (jr->read_idx + 1) & (jr->size - 1);
sec_out32(&regs->orjr, 1);
jr->info[idx].op_done = 0;
callback(status, arg);
}
@ -378,7 +382,6 @@ static int jr_sw_cleanup(uint8_t sec_idx, struct caam_regs *caam)
jr->head = 0;
jr->tail = 0;
jr->read_idx = 0;
jr->write_idx = 0;
memset(jr->info, 0, sizeof(jr->info));
memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));

4
drivers/crypto/fsl/jr.h
View File

@ -83,10 +83,6 @@ struct jobring {
* in-order job completion
*/
int tail;
/* Read index of the output ring. It may not match with tail in case
* of out of order completetion
*/
int read_idx;
/* Write index to input ring. Would be always equal to head */
int write_idx;
/* Size of the rings. */

4
drivers/mmc/cv1800b_sdhci.c
View File

@ -31,6 +31,7 @@ static void cv1800b_sdhci_reset(struct sdhci_host *host, u8 mask)
udelay(10);
}
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
static int cv1800b_execute_tuning(struct mmc *mmc, u8 opcode)
{
struct sdhci_host *host = dev_get_priv(mmc->dev);
@ -61,9 +62,12 @@ static int cv1800b_execute_tuning(struct mmc *mmc, u8 opcode)
return 0;
}
#endif
const struct sdhci_ops cv1800b_sdhci_sd_ops = {
#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
.platform_execute_tuning = cv1800b_execute_tuning,
#endif
};
static int cv1800b_sdhci_bind(struct udevice *dev)

4
drivers/net/fsl_enetc.c
View File

@ -473,13 +473,15 @@ static int enetc_init_sxgmii(struct udevice *dev)
/* Apply protocol specific configuration to MAC, serdes as needed */
static void enetc_start_pcs(struct udevice *dev)
{
struct enetc_data *data = (struct enetc_data *)dev_get_driver_data(dev);
struct enetc_priv *priv = dev_get_priv(dev);
/* register internal MDIO for debug purposes */
if (enetc_read_pcapr_mdio(dev)) {
priv->imdio.read = enetc_mdio_read;
priv->imdio.write = enetc_mdio_write;
priv->imdio.priv = priv->port_regs + ENETC_PM_IMDIO_BASE;
priv->imdio.priv = priv->port_regs + data->reg_offset_mac +
ENETC_PM_IMDIO_BASE;
strlcpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
if (!miiphy_get_dev_by_name(priv->imdio.name))
mdio_register(&priv->imdio);

1
drivers/ram/Kconfig
View File

@ -135,3 +135,4 @@ source "drivers/ram/sifive/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
source "drivers/ram/starfive/Kconfig"
source "drivers/ram/sunxi/Kconfig"
source "drivers/ram/thead/Kconfig"

4
drivers/ram/Makefile
View File

@ -30,3 +30,7 @@ obj-$(CONFIG_ARCH_OCTEON) += octeon/
obj-$(CONFIG_ARCH_RENESAS) += renesas/
obj-$(CONFIG_CADENCE_DDR_CTRL) += cadence/
ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_SPL_THEAD_TH1520_DDR) += thead/
endif

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