mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-09-01 12:02:28 +02:00
arm64: dts: rockchip: Fix ordering of nodes on rk3588s
Fix the ordering of the main nodes by sorting them alphabetically and then the ones with a memory address sequentially by that address. Signed-off-by: Diederik de Haas <didi.debian@cknow.org> Link: https://lore.kernel.org/r/20240406172821.34173-1-didi.debian@cknow.org Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: cbb97fe18e299ece1c0074924c630de6a19b320f ] (cherry picked from commit bbf7c16f2f1208b96349f6f6648b69cfaa1a482b) Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Diederik de Haas
Kever Yang
parent
9545163b1c
commit
376b0d0515
@ -347,6 +347,11 @@
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};
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};
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};
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};
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display_subsystem: display-subsystem {
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compatible = "rockchip,display-subsystem";
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ports = <&vop_out>;
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};
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firmware {
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firmware {
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optee: optee {
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optee: optee {
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compatible = "linaro,optee-tz";
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compatible = "linaro,optee-tz";
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@ -394,11 +399,6 @@
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#clock-cells = <0>;
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#clock-cells = <0>;
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};
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};
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display_subsystem: display-subsystem {
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compatible = "rockchip,display-subsystem";
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ports = <&vop_out>;
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};
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timer {
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timer {
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compatible = "arm,armv8-timer";
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
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@ -436,6 +436,62 @@
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};
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};
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};
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};
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gpu: gpu@fb000000 {
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compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
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reg = <0x0 0xfb000000 0x0 0x200000>;
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#cooling-cells = <2>;
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assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
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assigned-clock-rates = <200000000>;
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clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
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<&cru CLK_GPU_STACKS>;
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clock-names = "core", "coregroup", "stacks";
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dynamic-power-coefficient = <2982>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "job", "mmu", "gpu";
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operating-points-v2 = <&gpu_opp_table>;
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power-domains = <&power RK3588_PD_GPU>;
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status = "disabled";
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gpu_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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opp-microvolt = <675000 675000 850000>;
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};
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opp-400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-microvolt = <675000 675000 850000>;
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};
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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opp-microvolt = <675000 675000 850000>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <675000 675000 850000>;
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};
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opp-700000000 {
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opp-hz = /bits/ 64 <700000000>;
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opp-microvolt = <700000 700000 850000>;
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};
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opp-800000000 {
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opp-hz = /bits/ 64 <800000000>;
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opp-microvolt = <750000 750000 850000>;
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};
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opp-900000000 {
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opp-hz = /bits/ 64 <900000000>;
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opp-microvolt = <800000 800000 850000>;
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};
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <850000 850000 850000>;
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};
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};
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};
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usb_host0_ehci: usb@fc800000 {
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usb_host0_ehci: usb@fc800000 {
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compatible = "rockchip,rk3588-ehci", "generic-ehci";
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compatible = "rockchip,rk3588-ehci", "generic-ehci";
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reg = <0x0 0xfc800000 0x0 0x40000>;
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reg = <0x0 0xfc800000 0x0 0x40000>;
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@ -501,62 +557,6 @@
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status = "disabled";
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status = "disabled";
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};
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};
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gpu: gpu@fb000000 {
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compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
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reg = <0x0 0xfb000000 0x0 0x200000>;
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#cooling-cells = <2>;
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assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
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assigned-clock-rates = <200000000>;
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clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
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<&cru CLK_GPU_STACKS>;
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clock-names = "core", "coregroup", "stacks";
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dynamic-power-coefficient = <2982>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "job", "mmu", "gpu";
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operating-points-v2 = <&gpu_opp_table>;
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power-domains = <&power RK3588_PD_GPU>;
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status = "disabled";
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gpu_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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opp-microvolt = <675000 675000 850000>;
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};
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opp-400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-microvolt = <675000 675000 850000>;
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};
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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opp-microvolt = <675000 675000 850000>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <675000 675000 850000>;
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};
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opp-700000000 {
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opp-hz = /bits/ 64 <700000000>;
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opp-microvolt = <700000 700000 850000>;
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};
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opp-800000000 {
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opp-hz = /bits/ 64 <800000000>;
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opp-microvolt = <750000 750000 850000>;
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};
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opp-900000000 {
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opp-hz = /bits/ 64 <900000000>;
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opp-microvolt = <800000 800000 850000>;
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};
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <850000 850000 850000>;
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};
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};
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};
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pmu1grf: syscon@fd58a000 {
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pmu1grf: syscon@fd58a000 {
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compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
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compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
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reg = <0x0 0xfd58a000 0x0 0x10000>;
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reg = <0x0 0xfd58a000 0x0 0x10000>;
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@ -702,74 +702,6 @@
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status = "disabled";
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status = "disabled";
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};
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};
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vop: vop@fdd90000 {
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compatible = "rockchip,rk3588-vop";
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reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
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reg-names = "vop", "gamma-lut";
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interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru ACLK_VOP>,
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<&cru HCLK_VOP>,
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<&cru DCLK_VOP0>,
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<&cru DCLK_VOP1>,
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<&cru DCLK_VOP2>,
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<&cru DCLK_VOP3>,
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<&cru PCLK_VOP_ROOT>;
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clock-names = "aclk",
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"hclk",
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"dclk_vp0",
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"dclk_vp1",
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"dclk_vp2",
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"dclk_vp3",
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"pclk_vop";
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iommus = <&vop_mmu>;
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power-domains = <&power RK3588_PD_VOP>;
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rockchip,grf = <&sys_grf>;
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rockchip,vop-grf = <&vop_grf>;
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rockchip,vo1-grf = <&vo1_grf>;
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rockchip,pmu = <&pmu>;
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status = "disabled";
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vop_out: ports {
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#address-cells = <1>;
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#size-cells = <0>;
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vp0: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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vp1: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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vp2: port@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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};
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vp3: port@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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};
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};
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};
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vop_mmu: iommu@fdd97e00 {
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compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
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reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
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interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
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clock-names = "aclk", "iface";
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#iommu-cells = <0>;
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power-domains = <&power RK3588_PD_VOP>;
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status = "disabled";
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};
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uart0: serial@fd890000 {
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uart0: serial@fd890000 {
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compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
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compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
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reg = <0x0 0xfd890000 0x0 0x100>;
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reg = <0x0 0xfd890000 0x0 0x100>;
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@ -1140,6 +1072,87 @@
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};
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};
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};
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};
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av1d: video-codec@fdc70000 {
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compatible = "rockchip,rk3588-av1-vpu";
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reg = <0x0 0xfdc70000 0x0 0x800>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "vdpu";
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assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
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assigned-clock-rates = <400000000>, <400000000>;
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clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
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clock-names = "aclk", "hclk";
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power-domains = <&power RK3588_PD_AV1>;
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resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
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};
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vop: vop@fdd90000 {
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compatible = "rockchip,rk3588-vop";
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reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
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reg-names = "vop", "gamma-lut";
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interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru ACLK_VOP>,
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<&cru HCLK_VOP>,
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<&cru DCLK_VOP0>,
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<&cru DCLK_VOP1>,
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<&cru DCLK_VOP2>,
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<&cru DCLK_VOP3>,
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<&cru PCLK_VOP_ROOT>;
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clock-names = "aclk",
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"hclk",
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"dclk_vp0",
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"dclk_vp1",
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"dclk_vp2",
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"dclk_vp3",
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"pclk_vop";
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iommus = <&vop_mmu>;
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power-domains = <&power RK3588_PD_VOP>;
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rockchip,grf = <&sys_grf>;
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rockchip,vop-grf = <&vop_grf>;
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rockchip,vo1-grf = <&vo1_grf>;
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rockchip,pmu = <&pmu>;
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status = "disabled";
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vop_out: ports {
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#address-cells = <1>;
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#size-cells = <0>;
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vp0: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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vp1: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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vp2: port@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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};
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vp3: port@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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};
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};
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};
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vop_mmu: iommu@fdd97e00 {
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compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
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reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
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interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
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clock-names = "aclk", "iface";
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#iommu-cells = <0>;
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power-domains = <&power RK3588_PD_VOP>;
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status = "disabled";
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};
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i2s4_8ch: i2s@fddc0000 {
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i2s4_8ch: i2s@fddc0000 {
|
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compatible = "rockchip,rk3588-i2s-tdm";
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfddc0000 0x0 0x1000>;
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reg = <0x0 0xfddc0000 0x0 0x1000>;
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@ -1431,6 +1444,16 @@
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reg = <0x0 0xfdf82200 0x0 0x20>;
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reg = <0x0 0xfdf82200 0x0 0x20>;
|
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};
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};
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dfi: dfi@fe060000 {
|
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reg = <0x00 0xfe060000 0x00 0x10000>;
|
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compatible = "rockchip,rk3588-dfi";
|
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
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rockchip,pmu = <&pmu1grf>;
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};
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pcie2x1l1: pcie@fe180000 {
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pcie2x1l1: pcie@fe180000 {
|
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compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
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compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
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bus-range = <0x30 0x3f>;
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bus-range = <0x30 0x3f>;
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@ -1533,16 +1556,6 @@
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};
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};
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};
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};
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dfi: dfi@fe060000 {
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|
||||||
reg = <0x00 0xfe060000 0x00 0x10000>;
|
|
||||||
compatible = "rockchip,rk3588-dfi";
|
|
||||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
||||||
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
||||||
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
||||||
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
||||||
rockchip,pmu = <&pmu1grf>;
|
|
||||||
};
|
|
||||||
|
|
||||||
gmac1: ethernet@fe1c0000 {
|
gmac1: ethernet@fe1c0000 {
|
||||||
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
|
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
|
||||||
reg = <0x0 0xfe1c0000 0x0 0x10000>;
|
reg = <0x0 0xfe1c0000 0x0 0x10000>;
|
||||||
@ -2543,19 +2556,6 @@
|
|||||||
#interrupt-cells = <2>;
|
#interrupt-cells = <2>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
av1d: video-codec@fdc70000 {
|
|
||||||
compatible = "rockchip,rk3588-av1-vpu";
|
|
||||||
reg = <0x0 0xfdc70000 0x0 0x800>;
|
|
||||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
||||||
interrupt-names = "vdpu";
|
|
||||||
assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
|
|
||||||
assigned-clock-rates = <400000000>, <400000000>;
|
|
||||||
clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
|
|
||||||
clock-names = "aclk", "hclk";
|
|
||||||
power-domains = <&power RK3588_PD_AV1>;
|
|
||||||
resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
|
|
||||||
};
|
|
||||||
};
|
};
|
||||||
|
|
||||||
#include "rk3588s-pinctrl.dtsi"
|
#include "rk3588s-pinctrl.dtsi"
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user