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Merge patch series "arm: mediatek: clean up some redundant board init"

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David Lechner <dlechner@baylibre.com> says:

Before adding more targets, we take a moment to clean up some some
redundant code in existing Mediatek SoC support.

The first three patches are removing no-op functions. The last patch
generalizes the mem_map code so that it can be shared between all
Mediatek ARMv8 SoCs.

Link: https://lore.kernel.org/r/20260209-mtk-mach-clean-up-duplicates-v2-0-e3b22282c74d@baylibre.com
This commit is contained in:
Tom Rini 2026-02-18 11:57:24 -06:00
commit 339a55865a
25 changed files with 64 additions and 299 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
arch/arm/mach-mediatek/Kconfig
View File

@ -130,6 +130,33 @@ config TARGET_MT8518
endchoice
if ARM64
config MTK_MEM_MAP_DDR_BASE_PHY
hex "DDR physical base address"
default 0x40000000
help
Target-specific DDR physical base address.
config MTK_MEM_MAP_DDR_SIZE
hex "DDR .size in mem_map"
default 0x200000000 if TARGET_MT7987 || TARGET_MT7988 || TARGET_MT8188
default 0xc0000000 if TARGET_MT8365
default 0x80000000 if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT8183
default 0x40000000 if TARGET_MT7622 || TARGET_MT8512
default 0x20000000
help
Target-specific DDR region size in mem_map.
config MTK_MEM_MAP_MMIO_SIZE
hex "MMIO .size in mem_map"
default 0x40000000 if TARGET_MT7622 || TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7987 || TARGET_MT7988 || TARGET_MT8512
default 0x20000000
help
Target-specific MMIO region size in mem_map.
endif
config SYS_BOARD
string "Board name"
default "mt7622" if TARGET_MT7622

1
arch/arm/mach-mediatek/Makefile
View File

@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_ARM64) += armv8-mem-map.o
obj-y += cpu.o
obj-$(CONFIG_MTK_TZ_MOVABLE) += tzcfg.o
obj-$(CONFIG_XPL_BUILD) += spl.o

24
arch/arm/mach-mediatek/armv8-mem-map.c Normal file
View File

@ -0,0 +1,24 @@
// SPDX-License-Identifier: GPL-2.0-only
#include <asm/armv8/mmu.h>
static struct mm_region mediatek_mem_map[] = {
{
/* DDR */
.virt = CONFIG_MTK_MEM_MAP_DDR_BASE_PHY,
.phys = CONFIG_MTK_MEM_MAP_DDR_BASE_PHY,
.size = CONFIG_MTK_MEM_MAP_DDR_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = CONFIG_MTK_MEM_MAP_MMIO_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
}
};
struct mm_region *mem_map = mediatek_mem_map;

11
arch/arm/mach-mediatek/init.h
View File

@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 MediaTek Inc.
*/
#ifndef __MEDIATEK_INIT_H_
#define __MEDIATEK_INIT_H_
extern int mtk_soc_early_init(void);
#endif /* __MEDIATEK_INIT_H_ */

20
arch/arm/mach-mediatek/mt7622/init.c
View File

@ -36,23 +36,3 @@ void reset_cpu(void)
{
psci_system_reset();
}
static struct mm_region mt7622_mem_map[] = {
{
/* DDR */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x40000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 0x40000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
0,
}
};
struct mm_region *mem_map = mt7622_mem_map;

5
arch/arm/mach-mediatek/mt7623/init.c
View File

@ -16,11 +16,6 @@ DECLARE_GLOBAL_DATA_PTR;
struct boot_argument *preloader_param;
int mtk_soc_early_init(void)
{
return 0;
}
int dram_init(void)
{
u32 i;

2
arch/arm/mach-mediatek/mt7629/init.c
View File

@ -27,7 +27,7 @@
DECLARE_GLOBAL_DATA_PTR;
int mtk_pll_early_init(void)
static int mtk_pll_early_init(void)
{
unsigned long pll_rates[] = {
[CLK_APMIXED_ARMPLL] = 1250000000,

21
arch/arm/mach-mediatek/mt7981/init.c
View File

@ -30,24 +30,3 @@ void reset_cpu(void)
{
psci_system_reset();
}
static struct mm_region mt7981_mem_map[] = {
{
/* DDR */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 0x40000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
0,
}
};
struct mm_region *mem_map = mt7981_mem_map;

21
arch/arm/mach-mediatek/mt7986/init.c
View File

@ -30,24 +30,3 @@ void reset_cpu(void)
{
psci_system_reset();
}
static struct mm_region mt7986_mem_map[] = {
{
/* DDR */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 0x40000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
0,
}
};
struct mm_region *mem_map = mt7986_mem_map;

21
arch/arm/mach-mediatek/mt7987/init.c
View File

@ -39,24 +39,3 @@ void reset_cpu(ulong addr)
{
psci_system_reset();
}
static struct mm_region mt7987_mem_map[] = {
{
/* DDR */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x200000000ULL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 0x40000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
0,
}
};
struct mm_region *mem_map = mt7987_mem_map;

21
arch/arm/mach-mediatek/mt7988/init.c
View File

@ -38,24 +38,3 @@ void reset_cpu(ulong addr)
{
psci_system_reset();
}
static struct mm_region mt7988_mem_map[] = {
{
/* DDR */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x200000000ULL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 0x40000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
0,
}
};
struct mm_region *mem_map = mt7988_mem_map;

30
arch/arm/mach-mediatek/mt8183/init.c
View File

@ -37,16 +37,6 @@ int dram_init_banksize(void)
return 0;
}
int mtk_pll_early_init(void)
{
return 0;
}
int mtk_soc_early_init(void)
{
return 0;
}
void reset_cpu(void)
{
psci_system_reset();
@ -57,23 +47,3 @@ int print_cpuinfo(void)
printf("CPU: MediaTek MT8183\n");
return 0;
}
static struct mm_region mt8183_mem_map[] = {
{
/* DDR */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
0,
}
};
struct mm_region *mem_map = mt8183_mem_map;

5
arch/arm/mach-mediatek/mt8188/init.c
View File

@ -45,11 +45,6 @@ int dram_init_banksize(void)
return 0;
}
int mtk_soc_early_init(void)
{
return 0;
}
void reset_cpu(void)
{
struct udevice *wdt;

5
arch/arm/mach-mediatek/mt8365/init.c
View File

@ -26,11 +26,6 @@ int dram_init_banksize(void)
return 0;
}
int mtk_soc_early_init(void)
{
return 0;
}
void reset_cpu(void)
{
struct udevice *wdt;

21
arch/arm/mach-mediatek/mt8512/init.c
View File

@ -59,24 +59,3 @@ int print_cpuinfo(void)
debug("CPU: MediaTek MT8512\n");
return 0;
}
static struct mm_region mt8512_mem_map[] = {
{
/* DDR */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x40000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 0x40000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
0,
}
};
struct mm_region *mem_map = mt8512_mem_map;

22
arch/arm/mach-mediatek/mt8516/init.c
View File

@ -40,7 +40,7 @@ int dram_init_banksize(void)
return 0;
}
int mtk_pll_early_init(void)
static int mtk_pll_early_init(void)
{
unsigned long pll_rates[] = {
[CLK_APMIXED_ARMPLL] = 1300000000,
@ -94,23 +94,3 @@ int print_cpuinfo(void)
printf("CPU: MediaTek MT8516\n");
return 0;
}
static struct mm_region mt8516_mem_map[] = {
{
/* DDR */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
0,
}
};
struct mm_region *mem_map = mt8516_mem_map;

21
arch/arm/mach-mediatek/mt8518/init.c
View File

@ -51,24 +51,3 @@ int print_cpuinfo(void)
printf("CPU: MediaTek MT8518\n");
return 0;
}
static struct mm_region mt8518_mem_map[] = {
{
/* DDR */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
0,
}
};
struct mm_region *mem_map = mt8518_mem_map;

5
arch/arm/mach-mediatek/spl.c
View File

@ -9,7 +9,10 @@
#include <init.h>
#include <spl.h>
#include "init.h"
__weak int mtk_soc_early_init(void)
{
return 0;
}
void board_init_f(ulong dummy)
{

6
board/mediatek/mt8390_evk/MAINTAINERS → board/mediatek/MAINTAINERS
View File

@ -1,6 +1,10 @@
MT8365 EVK
M: Julien Masson <jmasson@baylibre.com>
S: Maintained
F: configs/mt8365_evk_defconfig
MT8390 EVK
M: Julien Masson <jmasson@baylibre.com>
M: Macpaul Lin <Macpaul.Lin@mediatek.com>
S: Maintained
F: board/mediatek/mt8390_evk/
F: configs/mt8390_evk_defconfig

5
board/mediatek/mt8365_evk/MAINTAINERS
View File

@ -1,5 +0,0 @@
MT8365 EVK
M: Julien Masson <jmasson@baylibre.com>
S: Maintained
F: board/mediatek/mt8365_evk/
F: configs/mt8365_evk_defconfig

3
board/mediatek/mt8365_evk/Makefile
View File

@ -1,3 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
obj-y += mt8365_evk.o

28
board/mediatek/mt8365_evk/mt8365_evk.c
View File

@ -1,28 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2023 BayLibre SAS
* Author: Julien Masson <jmasson@baylibre.com>
*/
#include <asm/armv8/mmu.h>
static struct mm_region mt8365_evk_mem_map[] = {
{
/* DDR */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0xc0000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
0,
}
};
struct mm_region *mem_map = mt8365_evk_mem_map;

3
board/mediatek/mt8390_evk/Makefile
View File

@ -1,3 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
obj-y += mt8390_evk.o

34
board/mediatek/mt8390_evk/mt8390_evk.c
View File

@ -1,34 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2026 BayLibre SAS
* Author: Julien Masson <jmasson@baylibre.com>
*/
#include <linux/types.h>
#include <asm/armv8/mmu.h>
int board_init(void)
{
return 0;
}
static struct mm_region mt8390_evk_mem_map[] = {
{
/* DDR */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x200000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
0,
}
};
struct mm_region *mem_map = mt8390_evk_mem_map;

1
configs/mt8390_evk_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="mediatek/mt8390-genio-700-evk"
CONFIG_TARGET_MT8188=y
CONFIG_SYS_LOAD_ADDR=0x4c000000
CONFIG_IDENT_STRING="mt8390-evk"
# CONFIG_BOARD_INIT is not set
CONFIG_CMD_CLK=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y