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spi: cadence_ospi: Add device reset via OSPI controller

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Add support for flash device reset via OSPI controller
instead of using GPIO, as OSPI IP has device reset
feature on Versal Gen2 platform. Also add compatible
string for Versal Gen2 platform.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250311041317.2992862-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
Venkatesh Yadav Abbarapu 2025-03-11 09:43:17 +05:30 committed by Michal Simek
parent 5ffab6ee12
commit 3243f71b64
3 changed files with 31 additions and 0 deletions
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19
drivers/spi/cadence_ospi_versal.c
View File

@ -204,3 +204,22 @@ void cadence_qspi_apb_enable_linear_mode(bool enable)
~VERSAL_OSPI_LINEAR_MODE, VERSAL_AXI_MUX_SEL); ~VERSAL_OSPI_LINEAR_MODE, VERSAL_AXI_MUX_SEL);
} }
} }
int cadence_device_reset(struct udevice *bus)
{
struct cadence_spi_priv *priv = dev_get_priv(bus);
u32 reg;
reg = readl(priv->regbase + CQSPI_REG_CONFIG);
reg |= CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK;
writel(reg, priv->regbase + CQSPI_REG_CONFIG);
writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, priv->regbase + CQSPI_REG_CONFIG);
udelay(5);
writel(reg | CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, priv->regbase + CQSPI_REG_CONFIG);
udelay(150);
writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, priv->regbase + CQSPI_REG_CONFIG);
udelay(1200);
return 0;
}

9
drivers/spi/cadence_qspi.c
View File

@ -33,6 +33,11 @@ __weak int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
return 0; return 0;
} }
__weak int cadence_device_reset(struct udevice *dev)
{
return 0;
}
__weak int cadence_qspi_flash_reset(struct udevice *dev) __weak int cadence_qspi_flash_reset(struct udevice *dev)
{ {
return 0; return 0;
@ -251,6 +256,9 @@ static int cadence_spi_probe(struct udevice *bus)
priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz); priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz);
if (device_is_compatible(bus, "amd,versal2-ospi"))
return cadence_device_reset(bus);
/* Reset ospi flash device */ /* Reset ospi flash device */
return cadence_qspi_flash_reset(bus); return cadence_qspi_flash_reset(bus);
@ -452,6 +460,7 @@ static const struct dm_spi_ops cadence_spi_ops = {
static const struct udevice_id cadence_spi_ids[] = { static const struct udevice_id cadence_spi_ids[] = {
{ .compatible = "cdns,qspi-nor" }, { .compatible = "cdns,qspi-nor" },
{ .compatible = "ti,am654-ospi" }, { .compatible = "ti,am654-ospi" },
{ .compatible = "amd,versal2-ospi" },
{ } { }
}; };

3
drivers/spi/cadence_qspi.h
View File

@ -45,6 +45,8 @@
#define CQSPI_REG_CONFIG_CLK_POL BIT(1) #define CQSPI_REG_CONFIG_CLK_POL BIT(1)
#define CQSPI_REG_CONFIG_CLK_PHA BIT(2) #define CQSPI_REG_CONFIG_CLK_PHA BIT(2)
#define CQSPI_REG_CONFIG_PHY_ENABLE_MASK BIT(3) #define CQSPI_REG_CONFIG_PHY_ENABLE_MASK BIT(3)
#define CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK BIT(5)
#define CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK BIT(6)
#define CQSPI_REG_CONFIG_DIRECT BIT(7) #define CQSPI_REG_CONFIG_DIRECT BIT(7)
#define CQSPI_REG_CONFIG_DECODE BIT(9) #define CQSPI_REG_CONFIG_DECODE BIT(9)
#define CQSPI_REG_CONFIG_ENBL_DMA BIT(15) #define CQSPI_REG_CONFIG_ENBL_DMA BIT(15)
@ -310,5 +312,6 @@ int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg);
int cadence_qspi_flash_reset(struct udevice *dev); int cadence_qspi_flash_reset(struct udevice *dev);
ofnode cadence_qspi_get_subnode(struct udevice *dev); ofnode cadence_qspi_get_subnode(struct udevice *dev);
void cadence_qspi_apb_enable_linear_mode(bool enable); void cadence_qspi_apb_enable_linear_mode(bool enable);
int cadence_device_reset(struct udevice *dev);
#endif /* __CADENCE_QSPI_H__ */ #endif /* __CADENCE_QSPI_H__ */