From 488c396e711aa3821896242ae5742195a535fe2f Mon Sep 17 00:00:00 2001 From: David Lechner Date: Wed, 7 Jan 2026 10:21:07 -0600 Subject: [PATCH 1/9] mt8365_evk_defconfig: enable clk command Enable CONFIG_CMD_CLK in the mt8365_evk_defconfig to allow using the clk dump command for debugging clock configurations. Reviewed-by: Macpaul Lin Signed-off-by: David Lechner --- configs/mt8365_evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/mt8365_evk_defconfig b/configs/mt8365_evk_defconfig index 7b411453e00..a9f7a24bcba 100644 --- a/configs/mt8365_evk_defconfig +++ b/configs/mt8365_evk_defconfig @@ -11,6 +11,7 @@ CONFIG_SYS_LOAD_ADDR=0x4c000000 CONFIG_IDENT_STRING=" mt8365-evk" CONFIG_DEFAULT_FDT_FILE="mt8365-evk" # CONFIG_BOARD_INIT is not set +CONFIG_CMD_CLK=y CONFIG_OF_UPSTREAM=y CONFIG_CLK=y CONFIG_MMC_MTK=y From 32087f61adae56e9e23d80f82567dbb6ce3e8e54 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Wed, 7 Jan 2026 10:21:08 -0600 Subject: [PATCH 2/9] clk: mediatek: mt8365: fix missing and out of order clocks Fix a few missing clocks and even more clocks in the incorrect order. Since the clocks are looked up by index, having them out of order or skipping an ID will lead to incorrect clocks being used. Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8365.c | 32 ++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index c88545fc7cf..b6332b14aea 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -80,7 +80,7 @@ static const struct mtk_fixed_clk top_fixed_clks[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) static const struct mtk_fixed_factor top_divs[] = { - PLL_FACTOR(CLK_TOP_SYS_26M_D2, "sys_26m_d2", CLK_XTAL, 1, 2), + PLL_FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", CLK_APMIXED_MFGPLL, 1, 1), PLL_FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", CLK_APMIXED_MAINPLL, 1, 2), PLL_FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", CLK_APMIXED_MAINPLL, 1, 4), PLL_FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", CLK_APMIXED_MAINPLL, 1, 8), @@ -110,7 +110,6 @@ static const struct mtk_fixed_factor top_divs[] = { PLL_FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", CLK_APMIXED_UNIVPLL, 1, 20), PLL_FACTOR(CLK_TOP_MMPLL, "mmpll_ck", CLK_APMIXED_MMPLL, 1, 1), PLL_FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", CLK_APMIXED_MMPLL, 1, 2), - PLL_FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", CLK_APMIXED_MFGPLL, 1, 1), PLL_FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", CLK_APMIXED_LVDSPLL, 1, 2), PLL_FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", CLK_APMIXED_LVDSPLL, 1, 4), PLL_FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", CLK_APMIXED_LVDSPLL, 1, 8), @@ -128,6 +127,7 @@ static const struct mtk_fixed_factor top_divs[] = { PLL_FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", CLK_APMIXED_APLL2, 1, 2), PLL_FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", CLK_APMIXED_APLL2, 1, 4), PLL_FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", CLK_APMIXED_APLL2, 1, 8), + PLL_FACTOR(CLK_TOP_SYS_26M_D2, "sys_26m_d2", CLK_XTAL, 1, 2), PLL_FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", CLK_APMIXED_MSDCPLL, 1, 1), PLL_FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", CLK_APMIXED_MSDCPLL, 1, 2), PLL_FACTOR(CLK_TOP_DSPPLL, "dsppll_ck", CLK_APMIXED_DSPPLL, 1, 1), @@ -484,7 +484,7 @@ static const struct mtk_composite top_muxes[] = { static const struct mtk_clk_tree mt8365_clk_tree = { .xtal_rate = 26 * MHZ, .xtal2_rate = 26 * MHZ, - .fdivs_offs = CLK_TOP_SYSPLL_D2, + .fdivs_offs = CLK_TOP_MFGPLL, .muxes_offs = CLK_TOP_AXI_SEL, .plls = apmixed_plls, .fclks = top_fixed_clks, @@ -540,16 +540,6 @@ static const struct mtk_gate_regs top2_cg_regs = { } static const struct mtk_gate top_clk_gates[] = { - GATE_TOP0(CLK_TOP_CONN_32K, CLK_TOP_CLK32K, 10), - GATE_TOP0(CLK_TOP_CONN_26M, CLK_TOP_CLK26M, 11), - GATE_TOP0(CLK_TOP_DSP_32K, CLK_TOP_CLK32K, 16), - GATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17), - GATE_TOP1(CLK_TOP_USB20_48M_EN, CLK_TOP_USB20_192M_D4, 8), - GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, CLK_TOP_USB20_192M_D4, 9), - GATE_TOP1(CLK_TOP_LVDSTX_CLKDIG_EN, CLK_TOP_LVDSTX_CLKDIG_CTS, 20), - GATE_TOP1(CLK_TOP_VPLL_DPIX_EN, CLK_TOP_VPLL_DPIX, 21), - GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, CLK_TOP_CLK_NULL, 22), - GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, CLK_TOP_CLK_NULL, 23), GATE_TOP2(CLK_TOP_AUD_I2S0_M, CLK_TOP_APLL12_CK_DIV0, 0), GATE_TOP2(CLK_TOP_AUD_I2S1_M, CLK_TOP_APLL12_CK_DIV1, 1), GATE_TOP2(CLK_TOP_AUD_I2S2_M, CLK_TOP_APLL12_CK_DIV2, 2), @@ -559,6 +549,16 @@ static const struct mtk_gate top_clk_gates[] = { GATE_TOP2(CLK_TOP_AUD_TDMIN_M, CLK_TOP_APLL12_CK_DIV5, 6), GATE_TOP2(CLK_TOP_AUD_TDMIN_B, CLK_TOP_APLL12_CK_DIV5B, 7), GATE_TOP2(CLK_TOP_AUD_SPDIF_M, CLK_TOP_APLL12_CK_DIV6, 8), + GATE_TOP1(CLK_TOP_USB20_48M_EN, CLK_TOP_USB20_192M_D4, 8), + GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, CLK_TOP_USB20_192M_D4, 9), + GATE_TOP1(CLK_TOP_LVDSTX_CLKDIG_EN, CLK_TOP_LVDSTX_CLKDIG_CTS, 20), + GATE_TOP1(CLK_TOP_VPLL_DPIX_EN, CLK_TOP_VPLL_DPIX, 21), + GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, CLK_TOP_CLK_NULL, 22), + GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, CLK_TOP_CLK_NULL, 23), + GATE_TOP0(CLK_TOP_CONN_32K, CLK_TOP_CLK32K, 10), + GATE_TOP0(CLK_TOP_CONN_26M, CLK_TOP_CLK26M, 11), + GATE_TOP0(CLK_TOP_DSP_32K, CLK_TOP_CLK32K, 16), + GATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17), }; /* infracfg */ @@ -648,6 +648,7 @@ static const struct mtk_gate ifr_clks[] = { GATE_IFR3(CLK_IFR_GCPU, CLK_TOP_AXI_SEL, 8), GATE_IFR3(CLK_IFR_TRNG, CLK_TOP_AXI_SEL, 9), GATE_IFR3(CLK_IFR_AUXADC, CLK_TOP_CLK26M, 10), + GATE_IFR3(CLK_IFR_CPUM, CLK_TOP_AXI_SEL, 11), GATE_IFR3(CLK_IFR_AUXADC_MD, CLK_TOP_CLK26M, 14), GATE_IFR3(CLK_IFR_AP_DMA, CLK_TOP_AXI_SEL, 18), GATE_IFR3(CLK_IFR_DEBUGSYS, CLK_TOP_AXI_SEL, 24), @@ -669,6 +670,7 @@ static const struct mtk_gate ifr_clks[] = { GATE_IFR5(CLK_IFR_PWRAP_TMR, CLK_TOP_CLK26M, 12), GATE_IFR5(CLK_IFR_PWRAP_SPI, CLK_TOP_CLK26M, 13), GATE_IFR5(CLK_IFR_PWRAP_SYS, CLK_TOP_CLK26M, 14), + GATE_IFR5(CLK_IFR_MCU_PM_BK, CLK_TOP_AXI_SEL, 16), GATE_IFR5(CLK_IFR_IRRX_26M, CLK_TOP_CLK26M, 22), GATE_IFR5(CLK_IFR_IRRX_32K, CLK_TOP_CLK32K, 23), GATE_IFR5(CLK_IFR_I2C0_AXI, CLK_TOP_I2C_SEL, 24), @@ -680,8 +682,8 @@ static const struct mtk_gate ifr_clks[] = { GATE_IFR5(CLK_IFR_APU_AXI, CLK_TOP_AXI_SEL, 30), /* IFR6 */ GATE_IFR6(CLK_IFR_NFIECC, CLK_TOP_NFIECC_SEL, 0), - GATE_IFR6(CLK_IFR_NFI1X_BK, CLK_TOP_NFI2X_SEL, 1), - GATE_IFR6(CLK_IFR_NFIECC_BK, CLK_TOP_NFI2X_SEL, 2), + GATE_IFR6(CLK_IFR_NFIECC_BK, CLK_TOP_NFI2X_SEL, 1), + GATE_IFR6(CLK_IFR_NFI1X_BK, CLK_TOP_NFI2X_SEL, 2), GATE_IFR6(CLK_IFR_NFI_BK, CLK_TOP_AXI_SEL, 3), GATE_IFR6(CLK_IFR_MSDC2_AP_BK, CLK_TOP_AXI_SEL, 4), GATE_IFR6(CLK_IFR_MSDC2_MD_BK, CLK_TOP_AXI_SEL, 5), From a694df199a4246036497447479bc08c6c4c09534 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Wed, 7 Jan 2026 10:21:09 -0600 Subject: [PATCH 3/9] clk: mediatek: add separate gates_offs for cg gates Add a gates_offs field to struct mtk_cg_priv and use that instead of struct mtk_clk_tree.gates_offs. Prior to this change, struct mtk_clk_tree.gates_offs could be the offset of struct mtk_clk_tree.gates or struct mtk_cg_priv.gates depending on the context. This was confusing and error-prone. For example, in mt8365 there is one set of gates that needs an offset and one that does not that share the same struct mtk_clk_tree. This is fixed in this patch by giving the correct offset for each gate separately. Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt7622.c | 8 ++++---- drivers/clk/mediatek/clk-mt7623.c | 8 +++----- drivers/clk/mediatek/clk-mt7629.c | 11 +++++------ drivers/clk/mediatek/clk-mt7981.c | 6 +++--- drivers/clk/mediatek/clk-mt7986.c | 2 +- drivers/clk/mediatek/clk-mt7987.c | 2 +- drivers/clk/mediatek/clk-mt7988.c | 8 ++++---- drivers/clk/mediatek/clk-mt8183.c | 2 +- drivers/clk/mediatek/clk-mt8188.c | 22 +++++++--------------- drivers/clk/mediatek/clk-mt8365.c | 5 +++-- drivers/clk/mediatek/clk-mt8512.c | 4 ++-- drivers/clk/mediatek/clk-mt8516.c | 2 +- drivers/clk/mediatek/clk-mt8518.c | 2 +- drivers/clk/mediatek/clk-mtk.c | 24 +++++++++++++----------- drivers/clk/mediatek/clk-mtk.h | 4 +++- 15 files changed, 52 insertions(+), 58 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 16c6f024e72..9621d5efe11 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -693,7 +693,7 @@ static int mt7622_pericfg_probe(struct udevice *dev) static int mt7622_pciesys_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, pcie_cgs, - ARRAY_SIZE(pcie_cgs)); + ARRAY_SIZE(pcie_cgs), 0); } static int mt7622_pciesys_bind(struct udevice *dev) @@ -712,7 +712,7 @@ static int mt7622_pciesys_bind(struct udevice *dev) static int mt7622_ethsys_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs, - ARRAY_SIZE(eth_cgs)); + ARRAY_SIZE(eth_cgs), 0); } static int mt7622_ethsys_bind(struct udevice *dev) @@ -731,13 +731,13 @@ static int mt7622_ethsys_bind(struct udevice *dev) static int mt7622_sgmiisys_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs, - ARRAY_SIZE(sgmii_cgs)); + ARRAY_SIZE(sgmii_cgs), 0); } static int mt7622_ssusbsys_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, ssusb_cgs, - ARRAY_SIZE(ssusb_cgs)); + ARRAY_SIZE(ssusb_cgs), 0); } static const struct udevice_id mt7622_apmixed_compat[] = { diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c index 6ce1d729736..3509ea67e7d 100644 --- a/drivers/clk/mediatek/clk-mt7623.c +++ b/drivers/clk/mediatek/clk-mt7623.c @@ -1055,15 +1055,13 @@ static int mt7623_topckgen_probe(struct udevice *dev) } static const struct mtk_clk_tree mt7623_clk_gate_tree = { - /* Each CLK ID for gates clock starts at index 1 */ - .gates_offs = 1, .xtal_rate = 26 * MHZ, }; static int mt7623_infracfg_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree, infra_cgs, - ARRAY_SIZE(infra_cgs)); + ARRAY_SIZE(infra_cgs), 1); } static const struct mtk_clk_tree mt7623_clk_peri_tree = { @@ -1086,13 +1084,13 @@ static int mt7623_pericfg_probe(struct udevice *dev) static int mt7623_hifsys_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree, hif_cgs, - ARRAY_SIZE(hif_cgs)); + ARRAY_SIZE(hif_cgs), 1); } static int mt7623_ethsys_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree, eth_cgs, - ARRAY_SIZE(eth_cgs)); + ARRAY_SIZE(eth_cgs), 1); } static int mt7623_ethsys_hifsys_bind(struct udevice *dev) diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index e4132f6195f..5bbac309e9d 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -581,7 +581,6 @@ static const struct mtk_clk_tree mt7629_clk_tree = { static const struct mtk_clk_tree mt7629_peri_clk_tree = { .xtal_rate = 40 * MHZ, .xtal2_rate = 20 * MHZ, - .gates_offs = CLK_PERI_PWM1_PD, .fdivs_offs = CLK_TOP_TO_USB3_SYS, .muxes_offs = CLK_TOP_AXI_SEL, .plls = apmixed_plls, @@ -635,19 +634,19 @@ static int mt7629_topckgen_probe(struct udevice *dev) static int mt7629_infracfg_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, infra_cgs, - ARRAY_SIZE(infra_cgs)); + ARRAY_SIZE(infra_cgs), 0); } static int mt7629_pericfg_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7629_peri_clk_tree, peri_cgs, - ARRAY_SIZE(peri_cgs)); + ARRAY_SIZE(peri_cgs), CLK_PERI_PWM1_PD); } static int mt7629_ethsys_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, eth_cgs, - ARRAY_SIZE(eth_cgs)); + ARRAY_SIZE(eth_cgs), 0); } static int mt7629_ethsys_bind(struct udevice *dev) @@ -666,13 +665,13 @@ static int mt7629_ethsys_bind(struct udevice *dev) static int mt7629_sgmiisys_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, sgmii_cgs, - ARRAY_SIZE(sgmii_cgs)); + ARRAY_SIZE(sgmii_cgs), 0); } static int mt7629_ssusbsys_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, ssusb_cgs, - ARRAY_SIZE(ssusb_cgs)); + ARRAY_SIZE(ssusb_cgs), 0); } static const struct udevice_id mt7629_apmixed_compat[] = { diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c index c8090688df0..3f96d25db04 100644 --- a/drivers/clk/mediatek/clk-mt7981.c +++ b/drivers/clk/mediatek/clk-mt7981.c @@ -631,7 +631,7 @@ static const struct mtk_gate sgmii0_cgs[] = { static int mt7981_sgmii0sys_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7981_topckgen_clk_tree, - sgmii0_cgs, ARRAY_SIZE(sgmii0_cgs)); + sgmii0_cgs, ARRAY_SIZE(sgmii0_cgs), 0); } static const struct udevice_id mt7981_sgmii0sys_compat[] = { @@ -658,7 +658,7 @@ static const struct mtk_gate sgmii1_cgs[] = { static int mt7981_sgmii1sys_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7981_topckgen_clk_tree, - sgmii1_cgs, ARRAY_SIZE(sgmii1_cgs)); + sgmii1_cgs, ARRAY_SIZE(sgmii1_cgs), 0); } static const struct udevice_id mt7981_sgmii1sys_compat[] = { @@ -699,7 +699,7 @@ static const struct mtk_gate eth_cgs[] = { static int mt7981_ethsys_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7981_topckgen_clk_tree, - eth_cgs, ARRAY_SIZE(eth_cgs)); + eth_cgs, ARRAY_SIZE(eth_cgs), 0); } static int mt7981_ethsys_bind(struct udevice *dev) diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c index 735e824c874..a8f39a3beb6 100644 --- a/drivers/clk/mediatek/clk-mt7986.c +++ b/drivers/clk/mediatek/clk-mt7986.c @@ -637,7 +637,7 @@ static const struct mtk_gate eth_cgs[] = { static int mt7986_ethsys_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7986_topckgen_clk_tree, eth_cgs, - ARRAY_SIZE(eth_cgs)); + ARRAY_SIZE(eth_cgs), 0); } static int mt7986_ethsys_bind(struct udevice *dev) diff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c index 99ff57c5dc5..818f45ef6bb 100644 --- a/drivers/clk/mediatek/clk-mt7987.c +++ b/drivers/clk/mediatek/clk-mt7987.c @@ -819,7 +819,7 @@ static const struct mtk_gate eth_cgs[] = { static int mt7987_ethsys_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7987_topckgen_clk_tree, eth_cgs, - ARRAY_SIZE(eth_cgs)); + ARRAY_SIZE(eth_cgs), 0); } static int mt7987_ethsys_bind(struct udevice *dev) diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c index da1d2e89d61..6da7c62c585 100644 --- a/drivers/clk/mediatek/clk-mt7988.c +++ b/drivers/clk/mediatek/clk-mt7988.c @@ -893,7 +893,7 @@ static int mt7988_ethdma_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree, ethdma_mtk_gate, - ARRAY_SIZE(ethdma_mtk_gate)); + ARRAY_SIZE(ethdma_mtk_gate), 0); } static int mt7988_ethdma_bind(struct udevice *dev) @@ -952,7 +952,7 @@ static int mt7988_sgmiisys_0_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree, sgmiisys_0_mtk_gate, - ARRAY_SIZE(sgmiisys_0_mtk_gate)); + ARRAY_SIZE(sgmiisys_0_mtk_gate), 0); } static const struct udevice_id mt7988_sgmiisys_0_compat[] = { @@ -997,7 +997,7 @@ static int mt7988_sgmiisys_1_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree, sgmiisys_1_mtk_gate, - ARRAY_SIZE(sgmiisys_1_mtk_gate)); + ARRAY_SIZE(sgmiisys_1_mtk_gate), 0); } static const struct udevice_id mt7988_sgmiisys_1_compat[] = { @@ -1044,7 +1044,7 @@ static int mt7988_ethwarp_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree, ethwarp_mtk_gate, - ARRAY_SIZE(ethwarp_mtk_gate)); + ARRAY_SIZE(ethwarp_mtk_gate), 0); } static int mt7988_ethwarp_bind(struct udevice *dev) diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 5b41cf4b88c..5a353e82f3f 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -778,7 +778,7 @@ static int mt8183_topckgen_probe(struct udevice *dev) static int mt8183_infracfg_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt8183_clk_tree, infra_clks, - ARRAY_SIZE(infra_clks)); + ARRAY_SIZE(infra_clks), 0); } static const struct udevice_id mt8183_apmixed_compat[] = { diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c index a4cbb3213e3..d967a915fac 100644 --- a/drivers/clk/mediatek/clk-mt8188.c +++ b/drivers/clk/mediatek/clk-mt8188.c @@ -1535,7 +1535,6 @@ static const struct mtk_gate infracfg_ao_clks[] = { static const struct mtk_clk_tree mt8188_infracfg_ao_clk_tree = { .xtal_rate = 26 * MHZ, .xtal2_rate = 26 * MHZ, - .gates_offs = 0, /* CLK_INFRA_AO_PMIC_TMR */ }; static const struct mtk_gate_regs peri_ao_cg_regs = { @@ -1570,7 +1569,6 @@ static const struct mtk_gate pericfg_ao_clks[] = { static const struct mtk_clk_tree mt8188_pericfg_ao_clk_tree = { .xtal_rate = 26 * MHZ, .xtal2_rate = 26 * MHZ, - .gates_offs = 0, /* CLK_PERI_AO_ETHERNET */ }; static const struct mtk_gate_regs top0_cg_regs = { @@ -1629,7 +1627,6 @@ static const struct mtk_gate topckgen_cg_clks[] = { static const struct mtk_clk_tree mt8188_topckgen_cg_clk_tree = { .xtal_rate = 26 * MHZ, .xtal2_rate = 26 * MHZ, - .gates_offs = 185, /* CLK_TOP_CFGREG_CLOCK_EN_VPP0 */ }; static const struct mtk_gate_regs imp_iic_wrap_cg_regs = { @@ -1665,22 +1662,16 @@ static const struct mtk_gate imp_iic_wrap_en_clks[] = { const struct mtk_clk_tree mt8188_imp_iic_wrap_c_clk_tree = { .xtal_rate = 26 * MHZ, .xtal2_rate = 26 * MHZ, - /* CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0 */ - .gates_offs = 0, }; const struct mtk_clk_tree mt8188_imp_iic_wrap_w_clk_tree = { .xtal_rate = 26 * MHZ, .xtal2_rate = 26 * MHZ, - /* CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C1 */ - .gates_offs = 0, }; const struct mtk_clk_tree mt8188_imp_iic_wrap_en_clk_tree = { .xtal_rate = 26 * MHZ, .xtal2_rate = 26 * MHZ, - /* imp_iic_wrap_en: CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5 */ - .gates_offs = 0, }; static int mt8188_apmixedsys_probe(struct udevice *dev) @@ -1697,42 +1688,43 @@ static int mt8188_topckgen_cg_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt8188_topckgen_cg_clk_tree, topckgen_cg_clks, - ARRAY_SIZE(topckgen_cg_clks)); + ARRAY_SIZE(topckgen_cg_clks), + CLK_TOP_CFGREG_CLOCK_EN_VPP0); } static int mt8188_infracfg_ao_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt8188_infracfg_ao_clk_tree, infracfg_ao_clks, - ARRAY_SIZE(infracfg_ao_clks)); + ARRAY_SIZE(infracfg_ao_clks), 0); } static int mt8188_pericfg_ao_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt8188_pericfg_ao_clk_tree, pericfg_ao_clks, - ARRAY_SIZE(pericfg_ao_clks)); + ARRAY_SIZE(pericfg_ao_clks), 0); } static int mt8188_imp_iic_wrap_c_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt8188_imp_iic_wrap_c_clk_tree, imp_iic_wrap_c_clks, - ARRAY_SIZE(imp_iic_wrap_c_clks)); + ARRAY_SIZE(imp_iic_wrap_c_clks), 0); } static int mt8188_imp_iic_wrap_w_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt8188_imp_iic_wrap_w_clk_tree, imp_iic_wrap_w_clks, - ARRAY_SIZE(imp_iic_wrap_w_clks)); + ARRAY_SIZE(imp_iic_wrap_w_clks), 0); } static int mt8188_imp_iic_wrap_en_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt8188_imp_iic_wrap_en_clk_tree, imp_iic_wrap_en_clks, - ARRAY_SIZE(imp_iic_wrap_en_clks)); + ARRAY_SIZE(imp_iic_wrap_en_clks), 0); } static const struct udevice_id mt8188_apmixed_compat[] = { diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index b6332b14aea..02d30ab12d8 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -708,13 +708,14 @@ static int mt8365_topckgen_probe(struct udevice *dev) static int mt8365_topckgen_cg_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt8365_clk_tree, top_clk_gates, - ARRAY_SIZE(top_clk_gates)); + ARRAY_SIZE(top_clk_gates), + CLK_TOP_AUD_I2S0_M); } static int mt8365_infracfg_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt8365_clk_tree, ifr_clks, - ARRAY_SIZE(ifr_clks)); + ARRAY_SIZE(ifr_clks), 0); } static const struct udevice_id mt8365_apmixed_compat[] = { diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c index d4f6604c160..bad8c62601d 100644 --- a/drivers/clk/mediatek/clk-mt8512.c +++ b/drivers/clk/mediatek/clk-mt8512.c @@ -809,13 +809,13 @@ static int mt8512_topckgen_probe(struct udevice *dev) static int mt8512_topckgen_cg_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt8512_clk_tree, top_clks, - ARRAY_SIZE(top_clks)); + ARRAY_SIZE(top_clks), 0); } static int mt8512_infracfg_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt8512_clk_tree, infra_clks, - ARRAY_SIZE(infra_clks)); + ARRAY_SIZE(infra_clks), 0); } static const struct udevice_id mt8512_apmixed_compat[] = { diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c index d5f922886a3..a84a5f360f5 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -758,7 +758,7 @@ static int mt8516_topckgen_probe(struct udevice *dev) static int mt8516_topckgen_cg_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt8516_clk_tree, top_clks, - ARRAY_SIZE(top_clks)); + ARRAY_SIZE(top_clks), 0); } static const struct udevice_id mt8516_apmixed_compat[] = { diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c index 92730f3f06c..43a06217d33 100644 --- a/drivers/clk/mediatek/clk-mt8518.c +++ b/drivers/clk/mediatek/clk-mt8518.c @@ -1514,7 +1514,7 @@ static int mt8518_topckgen_probe(struct udevice *dev) static int mt8518_topckgen_cg_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt8518_clk_tree, top_clks, - ARRAY_SIZE(top_clks)); + ARRAY_SIZE(top_clks), 0); } static const struct udevice_id mt8518_apmixed_compat[] = { diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index a3dd18363f6..6ba2fabfd08 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -1018,8 +1018,8 @@ static const int mtk_clk_gate_of_xlate(struct clk *clk, if (ret) return ret; - if (clk->id >= tree->gates_offs && - clk->id < tree->gates_offs + priv->num_gates) + if (clk->id >= priv->gates_offs && + clk->id < priv->gates_offs + priv->num_gates) return 0; return -ENOENT; @@ -1030,10 +1030,10 @@ static int mtk_clk_gate_enable(struct clk *clk) struct mtk_cg_priv *priv = dev_get_priv(clk->dev); const struct mtk_gate *gate; - if (clk->id < priv->tree->gates_offs) + if (clk->id < priv->gates_offs) return -EINVAL; - gate = &priv->gates[clk->id - priv->tree->gates_offs]; + gate = &priv->gates[clk->id - priv->gates_offs]; return mtk_gate_enable(priv->base, gate); } @@ -1042,10 +1042,10 @@ static int mtk_clk_gate_disable(struct clk *clk) struct mtk_cg_priv *priv = dev_get_priv(clk->dev); const struct mtk_gate *gate; - if (clk->id < priv->tree->gates_offs) + if (clk->id < priv->gates_offs) return -EINVAL; - gate = &priv->gates[clk->id - priv->tree->gates_offs]; + gate = &priv->gates[clk->id - priv->gates_offs]; return mtk_gate_disable(priv->base, gate); } @@ -1055,10 +1055,10 @@ static ulong mtk_clk_gate_get_rate(struct clk *clk) struct udevice *parent = priv->parent; const struct mtk_gate *gate; - if (clk->id < priv->tree->gates_offs) + if (clk->id < priv->gates_offs) return -EINVAL; - gate = &priv->gates[clk->id - priv->tree->gates_offs]; + gate = &priv->gates[clk->id - priv->gates_offs]; /* * With requesting a TOPCKGEN parent, make sure the dev parent * is actually topckgen. This might not be the case for an @@ -1094,8 +1094,8 @@ static void mtk_clk_gate_dump(struct udevice *dev) const struct mtk_gate *gate = &priv->gates[i]; printf("[GATE%u] DT: %u", i, gate->id); - mtk_clk_print_mapped_id(gate->id, i + tree->gates_offs, tree->id_offs_map); - mtk_clk_print_rate(dev, i + tree->gates_offs); + mtk_clk_print_mapped_id(gate->id, i + priv->gates_offs, tree->id_offs_map); + mtk_clk_print_rate(dev, i + priv->gates_offs); mtk_clk_print_single_parent(gate->parent, gate->flags); printf("\n"); } @@ -1196,7 +1196,8 @@ int mtk_common_clk_infrasys_init(struct udevice *dev, int mtk_common_clk_gate_init(struct udevice *dev, const struct mtk_clk_tree *tree, - const struct mtk_gate *gates, int num_gates) + const struct mtk_gate *gates, int num_gates, + int gates_offs) { struct mtk_cg_priv *priv = dev_get_priv(dev); struct udevice *parent; @@ -1218,6 +1219,7 @@ int mtk_common_clk_gate_init(struct udevice *dev, priv->tree = tree; priv->gates = gates; priv->num_gates = num_gates; + priv->gates_offs = gates_offs; return 0; } diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index bd8899193c9..068240b123e 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -285,6 +285,7 @@ struct mtk_cg_priv { const struct mtk_clk_tree *tree; const struct mtk_gate *gates; int num_gates; + int gates_offs; }; extern const struct clk_ops mtk_clk_apmixedsys_ops; @@ -299,6 +300,7 @@ int mtk_common_clk_infrasys_init(struct udevice *dev, const struct mtk_clk_tree *tree); int mtk_common_clk_gate_init(struct udevice *dev, const struct mtk_clk_tree *tree, - const struct mtk_gate *gates, int num_gates); + const struct mtk_gate *gates, int num_gates, + int gates_offs); #endif /* __DRV_CLK_MTK_H */ From 9e84e145e37ec64f5e2aecefe40ab977f10ba8a0 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Wed, 7 Jan 2026 10:21:10 -0600 Subject: [PATCH 4/9] clk: mediatek: fix fixed clock parents Add a flags field to struct mtk_fixed_clk to allow properly resolving the parent clock. All chip-specific clocks are updated to populate this field correctly. The parent is currently only used for printing debug information, so there are no functional bugs being fixed. Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt7622.c | 23 +++++++++++---------- drivers/clk/mediatek/clk-mt7623.c | 33 +++++++++++++++++-------------- drivers/clk/mediatek/clk-mt7629.c | 23 +++++++++++---------- drivers/clk/mediatek/clk-mt7981.c | 21 +++++++++++--------- drivers/clk/mediatek/clk-mt7986.c | 21 +++++++++++--------- drivers/clk/mediatek/clk-mt7987.c | 19 ++++++++++-------- drivers/clk/mediatek/clk-mt7988.c | 29 +++++++++++++++------------ drivers/clk/mediatek/clk-mt8183.c | 12 ++++++++--- drivers/clk/mediatek/clk-mt8188.c | 19 ++++++++++-------- drivers/clk/mediatek/clk-mt8365.c | 16 ++++++++++----- drivers/clk/mediatek/clk-mt8512.c | 7 +++++-- drivers/clk/mediatek/clk-mt8516.c | 12 ++++++++--- drivers/clk/mediatek/clk-mt8518.c | 14 +++++++++---- drivers/clk/mediatek/clk-mtk.c | 3 +-- drivers/clk/mediatek/clk-mtk.h | 4 +++- 15 files changed, 154 insertions(+), 102 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 9621d5efe11..782eb14e9c5 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -85,6 +85,9 @@ static const struct mtk_gate apmixed_cgs[] = { }; /* topckgen */ +#define FIXED_CLK0(_id, _rate) \ + FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -95,16 +98,16 @@ static const struct mtk_gate apmixed_cgs[] = { FACTOR(_id, _parent, _mult, _div, 0) static const struct mtk_fixed_clk top_fixed_clks[] = { - FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000), - FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000), - FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000), - FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000), - FIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000), - FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000), - FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333), - FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000), - FIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000), - FIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000), + FIXED_CLK0(CLK_TOP_TO_U2_PHY, 31250000), + FIXED_CLK0(CLK_TOP_TO_U2_PHY_1P, 31250000), + FIXED_CLK0(CLK_TOP_PCIE0_PIPE_EN, 125000000), + FIXED_CLK0(CLK_TOP_PCIE1_PIPE_EN, 125000000), + FIXED_CLK0(CLK_TOP_SSUSB_TX250M, 250000000), + FIXED_CLK0(CLK_TOP_SSUSB_EQ_RX250M, 250000000), + FIXED_CLK0(CLK_TOP_SSUSB_CDR_REF, 33333333), + FIXED_CLK0(CLK_TOP_SSUSB_CDR_FB, 50000000), + FIXED_CLK0(CLK_TOP_SATA_ASIC, 50000000), + FIXED_CLK0(CLK_TOP_SATA_RBC, 50000000), }; static const struct mtk_fixed_factor top_fixed_divs[] = { diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c index 3509ea67e7d..071c4cf8a84 100644 --- a/drivers/clk/mediatek/clk-mt7623.c +++ b/drivers/clk/mediatek/clk-mt7623.c @@ -259,6 +259,9 @@ static const int top_id_offs_map[CLK_TOP_NR + 1] = { [CLK_TOP_AUD_I2S6_MCLK] = 158, }; +#define FIXED_CLK0(_id, _rate) \ + FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -269,21 +272,21 @@ static const int top_id_offs_map[CLK_TOP_NR + 1] = { FACTOR(_id, _parent, _mult, _div, 0) static const struct mtk_fixed_clk top_fixed_clks[] = { - FIXED_CLK(CLK_TOP_DPI, CLK_XTAL, 108 * MHZ), - FIXED_CLK(CLK_TOP_DMPLL, CLK_XTAL, 400 * MHZ), - FIXED_CLK(CLK_TOP_VENCPLL, CLK_XTAL, 295.75 * MHZ), - FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, CLK_XTAL, 340 * MHZ), - FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, CLK_XTAL, 340 * MHZ), - FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, CLK_XTAL, 340 * MHZ), - FIXED_CLK(CLK_TOP_HADDS2_FB, CLK_XTAL, 27 * MHZ), - FIXED_CLK(CLK_TOP_WBG_DIG_416M, CLK_XTAL, 416 * MHZ), - FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, CLK_XTAL, 143 * MHZ), - FIXED_CLK(CLK_TOP_HDMI_SCL_RX, CLK_XTAL, 27 * MHZ), - FIXED_CLK(CLK_TOP_32K_EXTERNAL, CLK_XTAL, 32000), - FIXED_CLK(CLK_TOP_HDMITX_CLKDIG_CTS, CLK_XTAL, 300 * MHZ), - FIXED_CLK(CLK_TOP_AUD_EXT1, CLK_XTAL, 0), - FIXED_CLK(CLK_TOP_AUD_EXT2, CLK_XTAL, 0), - FIXED_CLK(CLK_TOP_NFI1X_PAD, CLK_XTAL, 0), + FIXED_CLK0(CLK_TOP_DPI, 108 * MHZ), + FIXED_CLK0(CLK_TOP_DMPLL, 400 * MHZ), + FIXED_CLK0(CLK_TOP_VENCPLL, 295.75 * MHZ), + FIXED_CLK0(CLK_TOP_HDMI_0_PIX340M, 340 * MHZ), + FIXED_CLK0(CLK_TOP_HDMI_0_DEEP340M, 340 * MHZ), + FIXED_CLK0(CLK_TOP_HDMI_0_PLL340M, 340 * MHZ), + FIXED_CLK0(CLK_TOP_HADDS2_FB, 27 * MHZ), + FIXED_CLK0(CLK_TOP_WBG_DIG_416M, 416 * MHZ), + FIXED_CLK0(CLK_TOP_DSI0_LNTC_DSI, 143 * MHZ), + FIXED_CLK0(CLK_TOP_HDMI_SCL_RX, 27 * MHZ), + FIXED_CLK0(CLK_TOP_32K_EXTERNAL, 32000), + FIXED_CLK0(CLK_TOP_HDMITX_CLKDIG_CTS, 300 * MHZ), + FIXED_CLK0(CLK_TOP_AUD_EXT1, 0), + FIXED_CLK0(CLK_TOP_AUD_EXT2, 0), + FIXED_CLK0(CLK_TOP_NFI1X_PAD, 0), }; static const struct mtk_fixed_factor top_fixed_divs[] = { diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index 5bbac309e9d..582394f594b 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -61,6 +61,9 @@ static const struct mtk_pll_data apmixed_plls[] = { }; /* topckgen */ +#define FIXED_CLK0(_id, _rate) \ + FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -71,16 +74,16 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, 0) static const struct mtk_fixed_clk top_fixed_clks[] = { - FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000), - FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000), - FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000), - FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000), - FIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000), - FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000), - FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333), - FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000), - FIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000), - FIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000), + FIXED_CLK0(CLK_TOP_TO_U2_PHY, 31250000), + FIXED_CLK0(CLK_TOP_TO_U2_PHY_1P, 31250000), + FIXED_CLK0(CLK_TOP_PCIE0_PIPE_EN, 125000000), + FIXED_CLK0(CLK_TOP_PCIE1_PIPE_EN, 125000000), + FIXED_CLK0(CLK_TOP_SSUSB_TX250M, 250000000), + FIXED_CLK0(CLK_TOP_SSUSB_EQ_RX250M, 250000000), + FIXED_CLK0(CLK_TOP_SSUSB_CDR_REF, 33333333), + FIXED_CLK0(CLK_TOP_SSUSB_CDR_FB, 50000000), + FIXED_CLK0(CLK_TOP_SATA_ASIC, 50000000), + FIXED_CLK0(CLK_TOP_SATA_RBC, 50000000), }; static const struct mtk_fixed_factor top_fixed_divs[] = { diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c index 3f96d25db04..09ed4d8a97f 100644 --- a/drivers/clk/mediatek/clk-mt7981.c +++ b/drivers/clk/mediatek/clk-mt7981.c @@ -18,6 +18,9 @@ #define MT7981_CLK_PDN 0x250 #define MT7981_CLK_PDN_EN_WRITE BIT(31) +#define FIXED_CLK0(_id, _rate) \ + FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -29,19 +32,19 @@ /* FIXED PLLS */ static const struct mtk_fixed_clk fixed_pll_clks[] = { - FIXED_CLK(CLK_APMIXED_ARMPLL, CLK_XTAL, 1300000000), - FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000), - FIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 720000000), - FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000), - FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000), - FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000), - FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000), - FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000), + FIXED_CLK0(CLK_APMIXED_ARMPLL, 1300000000), + FIXED_CLK0(CLK_APMIXED_NET2PLL, 800000000), + FIXED_CLK0(CLK_APMIXED_MMPLL, 720000000), + FIXED_CLK0(CLK_APMIXED_SGMPLL, 325000000), + FIXED_CLK0(CLK_APMIXED_WEDMCUPLL, 208000000), + FIXED_CLK0(CLK_APMIXED_NET1PLL, 2500000000), + FIXED_CLK0(CLK_APMIXED_MPLL, 416000000), + FIXED_CLK0(CLK_APMIXED_APLL2, 196608000), }; /* TOPCKGEN FIXED CLK */ static const struct mtk_fixed_clk top_fixed_clks[] = { - FIXED_CLK(CLK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000), + FIXED_CLK0(CLK_TOP_CB_CKSQ_40M, 40000000), }; /* TOPCKGEN FIXED DIV */ diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c index a8f39a3beb6..79efbf43bc4 100644 --- a/drivers/clk/mediatek/clk-mt7986.c +++ b/drivers/clk/mediatek/clk-mt7986.c @@ -23,6 +23,9 @@ #define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) #define VOID_PARENT PARENT(-1, 0) +#define FIXED_CLK0(_id, _rate) \ + FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -34,19 +37,19 @@ /* FIXED PLLS */ static const struct mtk_fixed_clk fixed_pll_clks[] = { - FIXED_CLK(CLK_APMIXED_ARMPLL, CLK_XTAL, 2000000000), - FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000), - FIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 1440000000), - FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000), - FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 760000000), - FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000), - FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000), - FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000), + FIXED_CLK0(CLK_APMIXED_ARMPLL, 2000000000), + FIXED_CLK0(CLK_APMIXED_NET2PLL, 800000000), + FIXED_CLK0(CLK_APMIXED_MMPLL, 1440000000), + FIXED_CLK0(CLK_APMIXED_SGMPLL, 325000000), + FIXED_CLK0(CLK_APMIXED_WEDMCUPLL, 760000000), + FIXED_CLK0(CLK_APMIXED_NET1PLL, 2500000000), + FIXED_CLK0(CLK_APMIXED_MPLL, 416000000), + FIXED_CLK0(CLK_APMIXED_APLL2, 196608000), }; /* TOPCKGEN FIXED CLK */ static const struct mtk_fixed_clk top_fixed_clks[] = { - FIXED_CLK(CLK_TOP_XTAL, CLK_XTAL, 40000000), + FIXED_CLK0(CLK_TOP_XTAL, 40000000), }; /* TOPCKGEN FIXED DIV */ diff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c index 818f45ef6bb..959b1c9cff6 100644 --- a/drivers/clk/mediatek/clk-mt7987.c +++ b/drivers/clk/mediatek/clk-mt7987.c @@ -19,6 +19,9 @@ #define MT7987_CLK_PDN 0x250 #define MT7987_CLK_PDN_EN_WRITE BIT(31) +#define FIXED_CLK0(_id, _rate) \ + FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + #define XTAL_FACTOR(_id, _name, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) @@ -33,14 +36,14 @@ /* FIXED PLLS */ static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = { - FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000), - FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000), - FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000), - FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000), - FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000), - FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000), - FIXED_CLK(CLK_APMIXED_ARM_LL, CLK_XTAL, 2000000000), - FIXED_CLK(CLK_APMIXED_MSDCPLL, CLK_XTAL, 384000000), + FIXED_CLK0(CLK_APMIXED_MPLL, 416000000), + FIXED_CLK0(CLK_APMIXED_APLL2, 196608000), + FIXED_CLK0(CLK_APMIXED_NET1PLL, 2500000000), + FIXED_CLK0(CLK_APMIXED_NET2PLL, 800000000), + FIXED_CLK0(CLK_APMIXED_WEDMCUPLL, 208000000), + FIXED_CLK0(CLK_APMIXED_SGMPLL, 325000000), + FIXED_CLK0(CLK_APMIXED_ARM_LL, 2000000000), + FIXED_CLK0(CLK_APMIXED_MSDCPLL, 384000000), }; static const struct mtk_clk_tree mt7987_fixed_pll_clk_tree = { diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c index 6da7c62c585..cd8726852d7 100644 --- a/drivers/clk/mediatek/clk-mt7988.c +++ b/drivers/clk/mediatek/clk-mt7988.c @@ -21,6 +21,9 @@ #define MT7988_ETHDMA_RST_CTRL_OFS 0x34 #define MT7988_ETHWARP_RST_CTRL_OFS 0x8 +#define FIXED_CLK0(_id, _rate) \ + FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + #define XTAL_FACTOR(_id, _name, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) @@ -35,23 +38,23 @@ /* FIXED PLLS */ static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = { - FIXED_CLK(CLK_APMIXED_NETSYSPLL, CLK_XTAL, 850000000), - FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000), - FIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 720000000), - FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000), - FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000), - FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000), - FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000), - FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000), - FIXED_CLK(CLK_APMIXED_ARM_B, CLK_XTAL, 1500000000), - FIXED_CLK(CLK_APMIXED_CCIPLL2_B, CLK_XTAL, 960000000), - FIXED_CLK(CLK_APMIXED_USXGMIIPLL, CLK_XTAL, 644533000), - FIXED_CLK(CLK_APMIXED_MSDCPLL, CLK_XTAL, 400000000), + FIXED_CLK0(CLK_APMIXED_NETSYSPLL, 850000000), + FIXED_CLK0(CLK_APMIXED_MPLL, 416000000), + FIXED_CLK0(CLK_APMIXED_MMPLL, 720000000), + FIXED_CLK0(CLK_APMIXED_APLL2, 196608000), + FIXED_CLK0(CLK_APMIXED_NET1PLL, 2500000000), + FIXED_CLK0(CLK_APMIXED_NET2PLL, 800000000), + FIXED_CLK0(CLK_APMIXED_WEDMCUPLL, 208000000), + FIXED_CLK0(CLK_APMIXED_SGMPLL, 325000000), + FIXED_CLK0(CLK_APMIXED_ARM_B, 1500000000), + FIXED_CLK0(CLK_APMIXED_CCIPLL2_B, 960000000), + FIXED_CLK0(CLK_APMIXED_USXGMIIPLL, 644533000), + FIXED_CLK0(CLK_APMIXED_MSDCPLL, 400000000), }; /* TOPCKGEN FIXED CLK */ static const struct mtk_fixed_clk topckgen_mtk_fixed_clks[] = { - FIXED_CLK(CLK_TOP_XTAL, CLK_XTAL, 40000000), + FIXED_CLK0(CLK_TOP_XTAL, 40000000), }; /* TOPCKGEN FIXED DIV */ diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 5a353e82f3f..9d9d00622db 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -67,10 +67,16 @@ static const struct mtk_pll_data apmixed_plls[] = { 0, 0, 32, 8, 0x02B4, 1, 0x02B8, 0), }; +#define FIXED_CLK0(_id, _rate) \ + FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + +#define FIXED_CLK1(_id, _rate) \ + FIXED_CLK(_id, CLK_TOP_UNIVPLL, CLK_PARENT_TOPCKGEN, _rate) + static const struct mtk_fixed_clk top_fixed_clks[] = { - FIXED_CLK(CLK_TOP_CLK26M, CLK_XTAL, 26000000), - FIXED_CLK(CLK_TOP_ULPOSC, CLK_XTAL, 250000), - FIXED_CLK(CLK_TOP_UNIVP_192M, CLK_TOP_UNIVPLL, 192000000), + FIXED_CLK0(CLK_TOP_CLK26M, 26000000), + FIXED_CLK0(CLK_TOP_ULPOSC, 250000), + FIXED_CLK1(CLK_TOP_UNIVP_192M, 192000000), }; static const struct mtk_fixed_factor top_fixed_divs[] = { diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c index d967a915fac..64aeaa5949f 100644 --- a/drivers/clk/mediatek/clk-mt8188.c +++ b/drivers/clk/mediatek/clk-mt8188.c @@ -88,15 +88,18 @@ static const struct mtk_clk_tree mt8188_apmixedsys_clk_tree = { .num_plls = ARRAY_SIZE(apmixed_plls), }; +#define FIXED_CLK0(_id, _rate) \ + FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + static const struct mtk_fixed_clk top_fixed_clks[] = { - FIXED_CLK(CLK_TOP_ULPOSC1, CLK_XTAL, 260000000), - FIXED_CLK(CLK_TOP_MPHONE_SLAVE_BCK, CLK_XTAL, 49152000), - FIXED_CLK(CLK_TOP_PAD_FPC, CLK_XTAL, 50000000), - FIXED_CLK(CLK_TOP_466M_FMEM, CLK_XTAL, 533000000), - FIXED_CLK(CLK_TOP_PEXTP_PIPE, CLK_XTAL, 250000000), - FIXED_CLK(CLK_TOP_DSI_PHY, CLK_XTAL, 500000000), - FIXED_CLK(CLK_TOP_CLK26M, CLK_XTAL, 260000000), - FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000), + FIXED_CLK0(CLK_TOP_ULPOSC1, 260000000), + FIXED_CLK0(CLK_TOP_MPHONE_SLAVE_BCK, 49152000), + FIXED_CLK0(CLK_TOP_PAD_FPC, 50000000), + FIXED_CLK0(CLK_TOP_466M_FMEM, 533000000), + FIXED_CLK0(CLK_TOP_PEXTP_PIPE, 250000000), + FIXED_CLK0(CLK_TOP_DSI_PHY, 500000000), + FIXED_CLK0(CLK_TOP_CLK26M, 260000000), + FIXED_CLK0(CLK_TOP_CLK32K, 32000), }; #define FACTOR0(_id, _parent, _mult, _div) \ diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index 02d30ab12d8..13f63d04ad0 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -68,12 +68,18 @@ static const struct mtk_pll_data apmixed_plls[] = { }; /* topckgen */ +#define FIXED_CLK0(_id, _rate) \ + FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + +#define FIXED_CLK1(_id, _rate) \ + FIXED_CLK(_id, CLK_TOP_CLK26M, CLK_PARENT_TOPCKGEN, _rate) + static const struct mtk_fixed_clk top_fixed_clks[] = { - FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 0), - FIXED_CLK(CLK_TOP_I2S0_BCK, CLK_XTAL, 26000000), - FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, CLK_TOP_CLK26M, 75000000), - FIXED_CLK(CLK_TOP_VPLL_DPIX, CLK_TOP_CLK26M, 75000000), - FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, CLK_TOP_CLK26M, 52500000), + FIXED_CLK0(CLK_TOP_CLK_NULL, 0), + FIXED_CLK0(CLK_TOP_I2S0_BCK, 26000000), + FIXED_CLK1(CLK_TOP_DSI0_LNTC_DSICK, 75000000), + FIXED_CLK1(CLK_TOP_VPLL_DPIX, 75000000), + FIXED_CLK1(CLK_TOP_LVDSTX_CLKDIG_CTS, 52500000), }; #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c index bad8c62601d..e6ced91fd06 100644 --- a/drivers/clk/mediatek/clk-mt8512.c +++ b/drivers/clk/mediatek/clk-mt8512.c @@ -59,6 +59,9 @@ static const struct mtk_pll_data apmixed_plls[] = { }; /* topckgen */ +#define FIXED_CLK0(_id, _rate) \ + FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -69,8 +72,8 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, 0) static const struct mtk_fixed_clk top_fixed_clks[] = { - FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000), - FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000), + FIXED_CLK0(CLK_TOP_CLK_NULL, 26000000), + FIXED_CLK0(CLK_TOP_CLK32K, 32000), }; static const struct mtk_fixed_factor top_fixed_divs[] = { diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c index a84a5f360f5..4985ba3e5ce 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -49,6 +49,12 @@ static const struct mtk_pll_data apmixed_plls[] = { }; /* topckgen */ +#define FIXED_CLK0(_id, _rate) \ + FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + +#define FIXED_CLK1(_id, _parent, _rate) \ + FIXED_CLK(_id, _parent, CLK_PARENT_TOPCKGEN, _rate) + #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -59,9 +65,9 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, 0) static const struct mtk_fixed_clk top_fixed_clks[] = { - FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000), - FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, CLK_TOP_CLK_NULL, 26000000), - FIXED_CLK(CLK_TOP_MEMPLL, CLK_TOP_CLK26M, 800000000), + FIXED_CLK0(CLK_TOP_CLK_NULL, 26000000), + FIXED_CLK1(CLK_TOP_I2S_INFRA_BCK, CLK_TOP_CLK_NULL, 26000000), + FIXED_CLK1(CLK_TOP_MEMPLL, CLK_TOP_CLK26M, 800000000), }; static const struct mtk_fixed_factor top_fixed_divs[] = { diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c index 43a06217d33..2fc492e7170 100644 --- a/drivers/clk/mediatek/clk-mt8518.c +++ b/drivers/clk/mediatek/clk-mt8518.c @@ -51,6 +51,12 @@ static const struct mtk_pll_data apmixed_plls[] = { }; /* topckgen */ +#define FIXED_CLK0(_id, _rate) \ + FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + +#define FIXED_CLK1(_id, _rate) \ + FIXED_CLK(_id, CLK_TOP_CLK_NULL, CLK_PARENT_TOPCKGEN, _rate) + #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -61,10 +67,10 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, 0) static const struct mtk_fixed_clk top_fixed_clks[] = { - FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000), - FIXED_CLK(CLK_TOP_FQ_TRNG_OUT0, CLK_TOP_CLK_NULL, 500000000), - FIXED_CLK(CLK_TOP_FQ_TRNG_OUT1, CLK_TOP_CLK_NULL, 500000000), - FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000), + FIXED_CLK0(CLK_TOP_CLK_NULL, 26000000), + FIXED_CLK1(CLK_TOP_FQ_TRNG_OUT0, 500000000), + FIXED_CLK1(CLK_TOP_FQ_TRNG_OUT1, 500000000), + FIXED_CLK0(CLK_TOP_CLK32K, 32000), }; static const struct mtk_fixed_factor top_fixed_divs[] = { diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 6ba2fabfd08..e370d304c03 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -798,8 +798,7 @@ static void mtk_topckgen_dump(struct udevice *dev) printf("[FCLK%u] DT: %u", i, fclk->id); mtk_clk_print_mapped_id(fclk->id, i, tree->id_offs_map); mtk_clk_print_rate(dev, i); - /* FIXME: fclk needs flags to fully determine parent. */ - mtk_clk_print_single_parent(fclk->parent, 0); + mtk_clk_print_single_parent(fclk->parent, fclk->flags); printf("\n"); } diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 068240b123e..e618e982e8b 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -73,12 +73,14 @@ struct mtk_pll_data { struct mtk_fixed_clk { const int id; const int parent; + const int flags; unsigned long rate; }; -#define FIXED_CLK(_id, _parent, _rate) { \ +#define FIXED_CLK(_id, _parent, _flags, _rate) { \ .id = _id, \ .parent = _parent, \ + .flags = _flags, \ .rate = _rate, \ } From 72f56becc003f9cad9e15c5174ba29fcd793c6bc Mon Sep 17 00:00:00 2001 From: David Lechner Date: Wed, 7 Jan 2026 10:21:11 -0600 Subject: [PATCH 5/9] clk: mediatek: mt8365: fix some clock parents Fix a number of clock parent definitions for MT8365 clocks. Most of these are just informational or don't make a function change. The clocks with the new PLL_FACTOR2 macro and the change in apu_parents are fixing actual bugs. Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8365.c | 48 +++++++++++++++++-------------- 1 file changed, 27 insertions(+), 21 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index 13f63d04ad0..4d0a0487b57 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -72,19 +72,25 @@ static const struct mtk_pll_data apmixed_plls[] = { FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) #define FIXED_CLK1(_id, _rate) \ - FIXED_CLK(_id, CLK_TOP_CLK26M, CLK_PARENT_TOPCKGEN, _rate) + FIXED_CLK(_id, CLK_TOP_CLK_NULL, CLK_PARENT_TOPCKGEN, _rate) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_CLK_NULL, 0), - FIXED_CLK0(CLK_TOP_I2S0_BCK, 26000000), - FIXED_CLK1(CLK_TOP_DSI0_LNTC_DSICK, 75000000), - FIXED_CLK1(CLK_TOP_VPLL_DPIX, 75000000), - FIXED_CLK1(CLK_TOP_LVDSTX_CLKDIG_CTS, 52500000), + FIXED_CLK1(CLK_TOP_I2S0_BCK, 26000000), + FIXED_CLK0(CLK_TOP_DSI0_LNTC_DSICK, 75000000), + FIXED_CLK0(CLK_TOP_VPLL_DPIX, 75000000), + FIXED_CLK0(CLK_TOP_LVDSTX_CLKDIG_CTS, 52500000), }; #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) +#define PLL_FACTOR1(_id, _name, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) + +#define PLL_FACTOR2(_id, _name, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) + static const struct mtk_fixed_factor top_divs[] = { PLL_FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", CLK_APMIXED_MFGPLL, 1, 1), PLL_FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", CLK_APMIXED_MAINPLL, 1, 2), @@ -120,20 +126,20 @@ static const struct mtk_fixed_factor top_divs[] = { PLL_FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", CLK_APMIXED_LVDSPLL, 1, 4), PLL_FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", CLK_APMIXED_LVDSPLL, 1, 8), PLL_FACTOR(CLK_TOP_LVDSPLL_D16, "lvdspll_d16", CLK_APMIXED_LVDSPLL, 1, 16), - PLL_FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck", CLK_APMIXED_USB20_EN, 1, 13), - PLL_FACTOR(CLK_TOP_USB20_192M_D4, "usb20_192m_d4", CLK_TOP_USB20_192M, 1, 4), - PLL_FACTOR(CLK_TOP_USB20_192M_D8, "usb20_192m_d8", CLK_TOP_USB20_192M, 1, 8), - PLL_FACTOR(CLK_TOP_USB20_192M_D16, "usb20_192m_d16", CLK_TOP_USB20_192M, 1, 16), - PLL_FACTOR(CLK_TOP_USB20_192M_D32, "usb20_192m_d32", CLK_TOP_USB20_192M, 1, 32), + PLL_FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck", CLK_APMIXED_UNIVPLL, 1, 13), + PLL_FACTOR1(CLK_TOP_USB20_192M_D4, "usb20_192m_d4", CLK_TOP_USB20_192M, 1, 4), + PLL_FACTOR1(CLK_TOP_USB20_192M_D8, "usb20_192m_d8", CLK_TOP_USB20_192M, 1, 8), + PLL_FACTOR1(CLK_TOP_USB20_192M_D16, "usb20_192m_d16", CLK_TOP_USB20_192M, 1, 16), + PLL_FACTOR1(CLK_TOP_USB20_192M_D32, "usb20_192m_d32", CLK_TOP_USB20_192M, 1, 32), PLL_FACTOR(CLK_TOP_APLL1, "apll1_ck", CLK_APMIXED_APLL1, 1, 1), - PLL_FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", CLK_APMIXED_APLL1, 1, 2), - PLL_FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", CLK_APMIXED_APLL1, 1, 4), - PLL_FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", CLK_APMIXED_APLL1, 1, 8), + PLL_FACTOR1(CLK_TOP_APLL1_D2, "apll1_d2", CLK_TOP_APLL1, 1, 2), + PLL_FACTOR1(CLK_TOP_APLL1_D4, "apll1_d4", CLK_TOP_APLL1, 1, 4), + PLL_FACTOR1(CLK_TOP_APLL1_D8, "apll1_d8", CLK_TOP_APLL1, 1, 8), PLL_FACTOR(CLK_TOP_APLL2, "apll2_ck", CLK_APMIXED_APLL2, 1, 1), - PLL_FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", CLK_APMIXED_APLL2, 1, 2), - PLL_FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", CLK_APMIXED_APLL2, 1, 4), - PLL_FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", CLK_APMIXED_APLL2, 1, 8), - PLL_FACTOR(CLK_TOP_SYS_26M_D2, "sys_26m_d2", CLK_XTAL, 1, 2), + PLL_FACTOR1(CLK_TOP_APLL2_D2, "apll2_d2", CLK_TOP_APLL2, 1, 2), + PLL_FACTOR1(CLK_TOP_APLL2_D4, "apll2_d4", CLK_TOP_APLL2, 1, 4), + PLL_FACTOR1(CLK_TOP_APLL2_D8, "apll2_d8", CLK_TOP_APLL2, 1, 8), + PLL_FACTOR2(CLK_TOP_SYS_26M_D2, "sys_26m_d2", CLK_XTAL, 1, 2), PLL_FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", CLK_APMIXED_MSDCPLL, 1, 1), PLL_FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", CLK_APMIXED_MSDCPLL, 1, 2), PLL_FACTOR(CLK_TOP_DSPPLL, "dsppll_ck", CLK_APMIXED_DSPPLL, 1, 1), @@ -141,7 +147,7 @@ static const struct mtk_fixed_factor top_divs[] = { PLL_FACTOR(CLK_TOP_DSPPLL_D4, "dsppll_d4", CLK_APMIXED_DSPPLL, 1, 4), PLL_FACTOR(CLK_TOP_DSPPLL_D8, "dsppll_d8", CLK_APMIXED_DSPPLL, 1, 8), PLL_FACTOR(CLK_TOP_APUPLL, "apupll_ck", CLK_APMIXED_APUPLL, 1, 1), - PLL_FACTOR(CLK_TOP_CLK26M_D52, "clk26m_d52", CLK_XTAL, 1, 52), + PLL_FACTOR2(CLK_TOP_CLK26M_D52, "clk26m_d52", CLK_XTAL, 1, 52), }; static const int axi_parents[] = { @@ -422,7 +428,7 @@ static const int gcpu_cpm_parents[] = { static const int apu_parents[] = { CLK_TOP_CLK26M, CLK_TOP_UNIVPLL_D2, - CLK_APMIXED_APUPLL, + CLK_TOP_APUPLL, CLK_TOP_MMPLL, CLK_TOP_SYSPLL_D3, CLK_TOP_UNIVPLL1_D2, @@ -647,8 +653,8 @@ static const struct mtk_gate ifr_clks[] = { GATE_IFR2(CLK_IFR_BTIF, CLK_TOP_AXI_SEL, 31), /* IFR3 */ GATE_IFR3(CLK_IFR_SPI0, CLK_TOP_SPI_SEL, 1), - GATE_IFR3(CLK_IFR_MSDC0_HCLK, CLK_TOP_MSDC50_0_HC_SEL, 2), - GATE_IFR3(CLK_IFR_MSDC2_HCLK, CLK_TOP_MSDC2_2_HC_SEL, 3), + GATE_IFR3(CLK_IFR_MSDC0_HCLK, CLK_TOP_AXI_SEL, 2), + GATE_IFR3(CLK_IFR_MSDC2_HCLK, CLK_TOP_AXI_SEL, 3), GATE_IFR3(CLK_IFR_MSDC1_HCLK, CLK_TOP_AXI_SEL, 4), GATE_IFR3(CLK_IFR_DVFSRC, CLK_TOP_CLK26M, 7), GATE_IFR3(CLK_IFR_GCPU, CLK_TOP_AXI_SEL, 8), From 4cc0f1b31857d57a980ac16f626ddb57bc3a5610 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Wed, 7 Jan 2026 10:21:12 -0600 Subject: [PATCH 6/9] clk: mediatek: mt8365: split struct mtk_clk_tree Split the struct mtk_clk_tree for MT8365 into separate structures for the apmixedsys, topckgen and infracfg clock controllers. This is needed to support moving the topckgen gates into the struct mtk_clk_tree. Since apmixedsys can also have gates, we need separate structures. Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8365.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index 4d0a0487b57..eaa5c2cf0dc 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -67,6 +67,13 @@ static const struct mtk_pll_data apmixed_plls[] = { 0x03A4, 0, 0, 0), }; +static const struct mtk_clk_tree mt8365_apmixed_tree = { + .xtal_rate = 26 * MHZ, + .xtal2_rate = 26 * MHZ, + .plls = apmixed_plls, + .num_plls = ARRAY_SIZE(apmixed_plls), +}; + /* topckgen */ #define FIXED_CLK0(_id, _rate) \ FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) @@ -493,16 +500,13 @@ static const struct mtk_composite top_muxes[] = { MUX_GATE(CLK_TOP_APU_IF_SEL, apu_parents, 0x0e0, 24, 3, 31), }; -static const struct mtk_clk_tree mt8365_clk_tree = { +static const struct mtk_clk_tree mt8365_topckgen_tree = { .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, .fdivs_offs = CLK_TOP_MFGPLL, .muxes_offs = CLK_TOP_AXI_SEL, - .plls = apmixed_plls, .fclks = top_fixed_clks, .fdivs = top_divs, .muxes = top_muxes, - .num_plls = ARRAY_SIZE(apmixed_plls), .num_fclks = ARRAY_SIZE(top_fixed_clks), .num_fdivs = ARRAY_SIZE(top_divs), .num_muxes = ARRAY_SIZE(top_muxes), @@ -707,26 +711,30 @@ static const struct mtk_gate ifr_clks[] = { GATE_IFR6(CLK_IFR_SSUSB_XHCI, CLK_TOP_SSUSB_XHCI_SEL, 11), }; +static const struct mtk_clk_tree mt8365_infracfg_tree = { + .xtal_rate = 26 * MHZ, +}; + static int mt8365_apmixedsys_probe(struct udevice *dev) { - return mtk_common_clk_init(dev, &mt8365_clk_tree); + return mtk_common_clk_init(dev, &mt8365_apmixed_tree); } static int mt8365_topckgen_probe(struct udevice *dev) { - return mtk_common_clk_init(dev, &mt8365_clk_tree); + return mtk_common_clk_init(dev, &mt8365_topckgen_tree); } static int mt8365_topckgen_cg_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt8365_clk_tree, top_clk_gates, + return mtk_common_clk_gate_init(dev, &mt8365_topckgen_tree, top_clk_gates, ARRAY_SIZE(top_clk_gates), CLK_TOP_AUD_I2S0_M); } static int mt8365_infracfg_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt8365_clk_tree, ifr_clks, + return mtk_common_clk_gate_init(dev, &mt8365_infracfg_tree, ifr_clks, ARRAY_SIZE(ifr_clks), 0); } From 8aeeeff50d467bb63209ff727823dd1c15caf62c Mon Sep 17 00:00:00 2001 From: David Lechner Date: Wed, 7 Jan 2026 10:21:13 -0600 Subject: [PATCH 7/9] clk: mediatek: allow gates in topckgen drivers Add handling for gates in the topckgen clk drivers. This avoids the need to have separate topckgen-cg drivers and devicetree nodes for the same address space and clock ID range. Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mtk.c | 61 +++++++++++++++++++++++++++++++--- 1 file changed, 57 insertions(+), 4 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index e370d304c03..82306ae285c 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -582,7 +582,7 @@ static const int mtk_topckgen_of_xlate(struct clk *clk, if (ret) return ret; - /* topckgen only uses fclks, fdivs and muxes. */ + /* topckgen only uses fclks, fdivs, muxes and gates. */ if (tree->fclks && clk->id < tree->num_fclks) return 0; @@ -595,6 +595,10 @@ static const int mtk_topckgen_of_xlate(struct clk *clk, clk->id < tree->muxes_offs + tree->num_muxes) return 0; + if (tree->gates && clk->id >= tree->gates_offs && + clk->id < tree->gates_offs + tree->num_gates) + return 0; + return -ENOENT; } @@ -696,6 +700,14 @@ static ulong mtk_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk, static ulong mtk_topckgen_get_rate(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + const struct mtk_clk_tree *tree = priv->tree; + + if (tree->gates && clk->id >= tree->gates_offs && + clk->id < tree->gates_offs + tree->num_gates) { + const struct mtk_gate *gate = &tree->gates[clk->id - tree->gates_offs]; + + return mtk_clk_find_parent_rate(clk, gate->parent, NULL); + } if (clk->id < priv->tree->fdivs_offs) return priv->tree->fclks[clk->id].rate; @@ -740,6 +752,21 @@ static int mtk_clk_mux_enable(struct clk *clk) return 0; } +static int mtk_topckgen_enable(struct clk *clk) +{ + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + const struct mtk_clk_tree *tree = priv->tree; + + if (tree->gates && clk->id >= tree->gates_offs && + clk->id < tree->gates_offs + tree->num_gates) { + const struct mtk_gate *gate = &tree->gates[clk->id - tree->gates_offs]; + + return mtk_gate_enable(priv->base, gate); + } + + return mtk_clk_mux_enable(clk); +} + static int mtk_clk_mux_disable(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); @@ -766,13 +793,29 @@ static int mtk_clk_mux_disable(struct clk *clk) return 0; } +static int mtk_topckgen_disable(struct clk *clk) +{ + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + const struct mtk_clk_tree *tree = priv->tree; + + if (tree->gates && clk->id >= tree->gates_offs && + clk->id < tree->gates_offs + tree->num_gates) { + const struct mtk_gate *gate = &tree->gates[clk->id - tree->gates_offs]; + + return mtk_gate_disable(priv->base, gate); + } + + return mtk_clk_mux_disable(clk); +} + static int mtk_common_clk_set_parent(struct clk *clk, struct clk *parent) { struct mtk_clk_priv *parent_priv = dev_get_priv(parent->dev); struct mtk_clk_priv *priv = dev_get_priv(clk->dev); u32 parent_type; - if (clk->id < priv->tree->muxes_offs) + if (!priv->tree->muxes || clk->id < priv->tree->muxes_offs || + clk->id >= priv->tree->muxes_offs + priv->tree->num_muxes) return 0; if (!parent_priv) @@ -821,6 +864,16 @@ static void mtk_topckgen_dump(struct udevice *dev) mtk_clk_print_mux_parents(priv, mux); printf("\n"); } + + for (i = 0; i < tree->num_gates; i++) { + const struct mtk_gate *gate = &tree->gates[i]; + + printf("[GATE%u] DT: %u", i, gate->id); + mtk_clk_print_mapped_id(gate->id, i + tree->gates_offs, tree->id_offs_map); + mtk_clk_print_rate(dev, i + tree->gates_offs); + mtk_clk_print_single_parent(gate->parent, gate->flags); + printf("\n"); + } } #endif @@ -1124,8 +1177,8 @@ const struct clk_ops mtk_clk_fixed_pll_ops = { const struct clk_ops mtk_clk_topckgen_ops = { .of_xlate = mtk_topckgen_of_xlate, - .enable = mtk_clk_mux_enable, - .disable = mtk_clk_mux_disable, + .enable = mtk_topckgen_enable, + .disable = mtk_topckgen_disable, .get_rate = mtk_topckgen_get_rate, .set_parent = mtk_common_clk_set_parent, #if CONFIG_IS_ENABLED(CMD_CLK) From ba207d7f54f97c447053d634f8da7b66f222af9e Mon Sep 17 00:00:00 2001 From: David Lechner Date: Wed, 7 Jan 2026 10:21:14 -0600 Subject: [PATCH 8/9] clk: mediatek: mt8365: remove separate topckgen-cg driver Remove the separate topckgen-cg driver for handling clock gates in the topckgen address space. The devicetree bindings for this were not acceptable upstream because it was creating a separate clock controller using the same address space as the main topckgen clock controller. The gates are moved to the topckgen tree instead. Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8365.c | 49 ++++++++++--------------------- 1 file changed, 15 insertions(+), 34 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index eaa5c2cf0dc..a28547a0cf8 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -500,18 +500,6 @@ static const struct mtk_composite top_muxes[] = { MUX_GATE(CLK_TOP_APU_IF_SEL, apu_parents, 0x0e0, 24, 3, 31), }; -static const struct mtk_clk_tree mt8365_topckgen_tree = { - .xtal_rate = 26 * MHZ, - .fdivs_offs = CLK_TOP_MFGPLL, - .muxes_offs = CLK_TOP_AXI_SEL, - .fclks = top_fixed_clks, - .fdivs = top_divs, - .muxes = top_muxes, - .num_fclks = ARRAY_SIZE(top_fixed_clks), - .num_fdivs = ARRAY_SIZE(top_divs), - .num_muxes = ARRAY_SIZE(top_muxes), -}; - /* topckgen cg */ static const struct mtk_gate_regs top0_cg_regs = { .set_ofs = 0, @@ -577,6 +565,21 @@ static const struct mtk_gate top_clk_gates[] = { GATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17), }; +static const struct mtk_clk_tree mt8365_topckgen_tree = { + .xtal_rate = 26 * MHZ, + .fdivs_offs = CLK_TOP_MFGPLL, + .muxes_offs = CLK_TOP_AXI_SEL, + .gates_offs = CLK_TOP_AUD_I2S0_M, + .fclks = top_fixed_clks, + .fdivs = top_divs, + .muxes = top_muxes, + .gates = top_clk_gates, + .num_fclks = ARRAY_SIZE(top_fixed_clks), + .num_fdivs = ARRAY_SIZE(top_divs), + .num_muxes = ARRAY_SIZE(top_muxes), + .num_gates = ARRAY_SIZE(top_clk_gates), +}; + /* infracfg */ static const struct mtk_gate_regs ifr2_cg_regs = { .set_ofs = 0x80, @@ -725,13 +728,6 @@ static int mt8365_topckgen_probe(struct udevice *dev) return mtk_common_clk_init(dev, &mt8365_topckgen_tree); } -static int mt8365_topckgen_cg_probe(struct udevice *dev) -{ - return mtk_common_clk_gate_init(dev, &mt8365_topckgen_tree, top_clk_gates, - ARRAY_SIZE(top_clk_gates), - CLK_TOP_AUD_I2S0_M); -} - static int mt8365_infracfg_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt8365_infracfg_tree, ifr_clks, @@ -748,11 +744,6 @@ static const struct udevice_id mt8365_topckgen_compat[] = { { } }; -static const struct udevice_id mt8365_topckgen_cg_compat[] = { - { .compatible = "mediatek,mt8365-topckgen-cg", }, - { } -}; - static const struct udevice_id mt8365_infracfg_compat[] = { { .compatible = "mediatek,mt8365-infracfg", }, { } @@ -778,16 +769,6 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = { .flags = DM_FLAG_PRE_RELOC, }; -U_BOOT_DRIVER(mtk_clk_topckgen_cg) = { - .name = "mt8365-topckgen-cg", - .id = UCLASS_CLK, - .of_match = mt8365_topckgen_cg_compat, - .probe = mt8365_topckgen_cg_probe, - .priv_auto = sizeof(struct mtk_cg_priv), - .ops = &mtk_clk_gate_ops, - .flags = DM_FLAG_PRE_RELOC, -}; - U_BOOT_DRIVER(mtk_clk_infracfg) = { .name = "mt8365-infracfg", .id = UCLASS_CLK, From 682528df206b0fd6a7239815b57cd151bc895695 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Wed, 7 Jan 2026 10:21:15 -0600 Subject: [PATCH 9/9] clk: mediatek: mt8365: fix missing topckgen IDs Use a ID map to add clocks for the missing CLK_TOP_CLK32K and CLK_TOP_CLK26M that were not included in the devicetree definitions. This fixes getting the rate of any clock that had one of these as a parent. CLK_TOP_UNIVPLL does not appear to be a real clock, so it is omitted now since we can do that with the ID map as well. Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8365.c | 151 +++++++++++++++++++++++++++++- 1 file changed, 147 insertions(+), 4 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index a28547a0cf8..6ba464097ae 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -75,6 +75,146 @@ static const struct mtk_clk_tree mt8365_apmixed_tree = { }; /* topckgen */ + +/* + * The devicetree bindings missed a few clocks and can't be changed, so we need + * to provide a mapping to fix the omissions. + */ +static const int mt8365_topckgen_id_map[] = { + [0 ... CLK_TOP_NR_CLK - 1] = -1, + /* FIXED */ + /* Fixed 32K oscillator is not available in devicetree definitions */ + [CLK_TOP_CLK32K] = 0, + [CLK_TOP_CLK_NULL] = 1, + [CLK_TOP_I2S0_BCK] = 2, + [CLK_TOP_DSI0_LNTC_DSICK] = 3, + [CLK_TOP_VPLL_DPIX] = 4, + [CLK_TOP_LVDSTX_CLKDIG_CTS] = 5, + /* FACTOR */ + [CLK_TOP_MFGPLL] = 6, + [CLK_TOP_SYSPLL_D2] = 7, + [CLK_TOP_SYSPLL1_D2] = 8, + [CLK_TOP_SYSPLL1_D4] = 9, + [CLK_TOP_SYSPLL1_D8] = 10, + [CLK_TOP_SYSPLL1_D16] = 11, + [CLK_TOP_SYSPLL_D3] = 12, + [CLK_TOP_SYSPLL2_D2] = 13, + [CLK_TOP_SYSPLL2_D4] = 14, + [CLK_TOP_SYSPLL2_D8] = 15, + [CLK_TOP_SYSPLL_D5] = 16, + [CLK_TOP_SYSPLL3_D2] = 17, + [CLK_TOP_SYSPLL3_D4] = 18, + [CLK_TOP_SYSPLL_D7] = 19, + [CLK_TOP_SYSPLL4_D2] = 20, + [CLK_TOP_SYSPLL4_D4] = 21, + /* Skipping CLK_TOP_UNIVPLL since isn't a real clock. */ + [CLK_TOP_UNIVPLL_D2] = 22, + [CLK_TOP_UNIVPLL1_D2] = 23, + [CLK_TOP_UNIVPLL1_D4] = 24, + [CLK_TOP_UNIVPLL_D3] = 25, + [CLK_TOP_UNIVPLL2_D2] = 26, + [CLK_TOP_UNIVPLL2_D4] = 27, + [CLK_TOP_UNIVPLL2_D8] = 28, + [CLK_TOP_UNIVPLL2_D32] = 29, + [CLK_TOP_UNIVPLL_D5] = 30, + [CLK_TOP_UNIVPLL3_D2] = 31, + [CLK_TOP_UNIVPLL3_D4] = 32, + [CLK_TOP_MMPLL] = 33, + [CLK_TOP_MMPLL_D2] = 34, + [CLK_TOP_LVDSPLL_D2] = 35, + [CLK_TOP_LVDSPLL_D4] = 36, + [CLK_TOP_LVDSPLL_D8] = 37, + [CLK_TOP_LVDSPLL_D16] = 38, + [CLK_TOP_USB20_192M] = 39, + [CLK_TOP_USB20_192M_D4] = 40, + [CLK_TOP_USB20_192M_D8] = 41, + [CLK_TOP_USB20_192M_D16] = 42, + [CLK_TOP_USB20_192M_D32] = 43, + [CLK_TOP_APLL1] = 44, + [CLK_TOP_APLL1_D2] = 45, + [CLK_TOP_APLL1_D4] = 46, + [CLK_TOP_APLL1_D8] = 47, + [CLK_TOP_APLL2] = 48, + [CLK_TOP_APLL2_D2] = 49, + [CLK_TOP_APLL2_D4] = 50, + [CLK_TOP_APLL2_D8] = 51, + /* Fixed 26M oscillator is not available in devicetree definitions */ + [CLK_TOP_CLK26M] = 52, + [CLK_TOP_SYS_26M_D2] = 53, + [CLK_TOP_MSDCPLL] = 54, + [CLK_TOP_MSDCPLL_D2] = 55, + [CLK_TOP_DSPPLL] = 56, + [CLK_TOP_DSPPLL_D2] = 57, + [CLK_TOP_DSPPLL_D4] = 58, + [CLK_TOP_DSPPLL_D8] = 59, + [CLK_TOP_APUPLL] = 60, + [CLK_TOP_CLK26M_D52] = 61, + /* MUX */ + [CLK_TOP_AXI_SEL] = 62, + [CLK_TOP_MEM_SEL] = 63, + [CLK_TOP_MM_SEL] = 64, + [CLK_TOP_SCP_SEL] = 65, + [CLK_TOP_MFG_SEL] = 66, + [CLK_TOP_ATB_SEL] = 67, + [CLK_TOP_CAMTG_SEL] = 68, + [CLK_TOP_CAMTG1_SEL] = 69, + [CLK_TOP_UART_SEL] = 70, + [CLK_TOP_SPI_SEL] = 71, + [CLK_TOP_MSDC50_0_HC_SEL] = 72, + [CLK_TOP_MSDC2_2_HC_SEL] = 73, + [CLK_TOP_MSDC50_0_SEL] = 74, + [CLK_TOP_MSDC50_2_SEL] = 75, + [CLK_TOP_MSDC30_1_SEL] = 76, + [CLK_TOP_AUDIO_SEL] = 77, + [CLK_TOP_AUD_INTBUS_SEL] = 78, + [CLK_TOP_AUD_1_SEL] = 79, + [CLK_TOP_AUD_2_SEL] = 80, + [CLK_TOP_AUD_ENGEN1_SEL] = 81, + [CLK_TOP_AUD_ENGEN2_SEL] = 82, + [CLK_TOP_AUD_SPDIF_SEL] = 83, + [CLK_TOP_DISP_PWM_SEL] = 84, + [CLK_TOP_DXCC_SEL] = 85, + [CLK_TOP_SSUSB_SYS_SEL] = 86, + [CLK_TOP_SSUSB_XHCI_SEL] = 87, + [CLK_TOP_SPM_SEL] = 88, + [CLK_TOP_I2C_SEL] = 89, + [CLK_TOP_PWM_SEL] = 90, + [CLK_TOP_SENIF_SEL] = 91, + [CLK_TOP_AES_FDE_SEL] = 92, + [CLK_TOP_CAMTM_SEL] = 93, + [CLK_TOP_DPI0_SEL] = 94, + [CLK_TOP_DPI1_SEL] = 95, + [CLK_TOP_DSP_SEL] = 96, + [CLK_TOP_NFI2X_SEL] = 97, + [CLK_TOP_NFIECC_SEL] = 98, + [CLK_TOP_ECC_SEL] = 99, + [CLK_TOP_ETH_SEL] = 100, + [CLK_TOP_GCPU_SEL] = 101, + [CLK_TOP_GCPU_CPM_SEL] = 102, + [CLK_TOP_APU_SEL] = 103, + [CLK_TOP_APU_IF_SEL] = 104, + /* GATE */ + [CLK_TOP_AUD_I2S0_M] = 105, + [CLK_TOP_AUD_I2S1_M] = 106, + [CLK_TOP_AUD_I2S2_M] = 107, + [CLK_TOP_AUD_I2S3_M] = 108, + [CLK_TOP_AUD_TDMOUT_M] = 109, + [CLK_TOP_AUD_TDMOUT_B] = 110, + [CLK_TOP_AUD_TDMIN_M] = 111, + [CLK_TOP_AUD_TDMIN_B] = 112, + [CLK_TOP_AUD_SPDIF_M] = 113, + [CLK_TOP_USB20_48M_EN] = 114, + [CLK_TOP_UNIVPLL_48M_EN] = 115, + [CLK_TOP_LVDSTX_CLKDIG_EN] = 116, + [CLK_TOP_VPLL_DPIX_EN] = 117, + [CLK_TOP_SSUSB_TOP_CK_EN] = 118, + [CLK_TOP_SSUSB_PHY_CK_EN] = 119, + [CLK_TOP_CONN_32K] = 120, + [CLK_TOP_CONN_26M] = 121, + [CLK_TOP_DSP_32K] = 122, + [CLK_TOP_DSP_26M] = 123, +}; + #define FIXED_CLK0(_id, _rate) \ FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) @@ -82,6 +222,7 @@ static const struct mtk_clk_tree mt8365_apmixed_tree = { FIXED_CLK(_id, CLK_TOP_CLK_NULL, CLK_PARENT_TOPCKGEN, _rate) static const struct mtk_fixed_clk top_fixed_clks[] = { + FIXED_CLK0(CLK_TOP_CLK32K, 32000), FIXED_CLK0(CLK_TOP_CLK_NULL, 0), FIXED_CLK1(CLK_TOP_I2S0_BCK, 26000000), FIXED_CLK0(CLK_TOP_DSI0_LNTC_DSICK, 75000000), @@ -115,7 +256,6 @@ static const struct mtk_fixed_factor top_divs[] = { PLL_FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", CLK_APMIXED_MAINPLL, 1, 7), PLL_FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", CLK_APMIXED_MAINPLL, 1, 14), PLL_FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", CLK_APMIXED_MAINPLL, 1, 28), - PLL_FACTOR(CLK_TOP_UNIVPLL, "univpll", CLK_APMIXED_UNIV_EN, 1, 2), PLL_FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", CLK_APMIXED_UNIVPLL, 1, 2), PLL_FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", CLK_APMIXED_UNIVPLL, 1, 4), PLL_FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", CLK_APMIXED_UNIVPLL, 1, 8), @@ -146,6 +286,7 @@ static const struct mtk_fixed_factor top_divs[] = { PLL_FACTOR1(CLK_TOP_APLL2_D2, "apll2_d2", CLK_TOP_APLL2, 1, 2), PLL_FACTOR1(CLK_TOP_APLL2_D4, "apll2_d4", CLK_TOP_APLL2, 1, 4), PLL_FACTOR1(CLK_TOP_APLL2_D8, "apll2_d8", CLK_TOP_APLL2, 1, 8), + PLL_FACTOR2(CLK_TOP_CLK26M, "clk26m_ck", CLK_XTAL, 1, 1), PLL_FACTOR2(CLK_TOP_SYS_26M_D2, "sys_26m_d2", CLK_XTAL, 1, 2), PLL_FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", CLK_APMIXED_MSDCPLL, 1, 1), PLL_FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", CLK_APMIXED_MSDCPLL, 1, 2), @@ -567,9 +708,11 @@ static const struct mtk_gate top_clk_gates[] = { static const struct mtk_clk_tree mt8365_topckgen_tree = { .xtal_rate = 26 * MHZ, - .fdivs_offs = CLK_TOP_MFGPLL, - .muxes_offs = CLK_TOP_AXI_SEL, - .gates_offs = CLK_TOP_AUD_I2S0_M, + .id_offs_map = mt8365_topckgen_id_map, + .id_offs_map_size = ARRAY_SIZE(mt8365_topckgen_id_map), + .fdivs_offs = mt8365_topckgen_id_map[CLK_TOP_MFGPLL], + .muxes_offs = mt8365_topckgen_id_map[CLK_TOP_AXI_SEL], + .gates_offs = mt8365_topckgen_id_map[CLK_TOP_AUD_I2S0_M], .fclks = top_fixed_clks, .fdivs = top_divs, .muxes = top_muxes,