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arm64: dts: rockchip: sync px30 DTSI with Linux kernel v6.1

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Sync the px30 dtsi from Linux kernel v6.1.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
This commit is contained in:
Quentin Schulz 2023-01-09 11:36:44 +01:00 committed by Kever Yang
parent 600e0177e7
commit 2c9f077064
1 changed files with 25 additions and 3 deletions
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28
arch/arm/dts/px30.dtsi
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@ -365,6 +365,28 @@
status = "disabled"; status = "disabled";
}; };
i2s0_8ch: i2s@ff060000 {
compatible = "rockchip,px30-i2s-tdm";
reg = <0x0 0xff060000 0x0 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
dmas = <&dmac 16>, <&dmac 17>;
dma-names = "tx", "rx";
rockchip,grf = <&grf>;
resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>;
reset-names = "tx-m", "rx-m";
pinctrl-names = "default";
pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx
&i2s0_8ch_lrcktx &i2s0_8ch_lrckrx
&i2s0_8ch_sdo0 &i2s0_8ch_sdi0
&i2s0_8ch_sdo1 &i2s0_8ch_sdi1
&i2s0_8ch_sdo2 &i2s0_8ch_sdi2
&i2s0_8ch_sdo3 &i2s0_8ch_sdi3>;
#sound-dai-cells = <0>;
status = "disabled";
};
i2s1_2ch: i2s@ff070000 { i2s1_2ch: i2s@ff070000 {
compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff070000 0x0 0x1000>; reg = <0x0 0xff070000 0x0 0x1000>;
@ -528,7 +550,7 @@
i2c0: i2c@ff180000 { i2c0: i2c@ff180000 {
compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0xff180000 0x0 0x1000>; reg = <0x0 0xff180000 0x0 0x1000>;
clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
clock-names = "i2c", "pclk"; clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default"; pinctrl-names = "default";
@ -711,7 +733,7 @@
clock-names = "pclk", "timer"; clock-names = "pclk", "timer";
}; };
dmac: dmac@ff240000 { dmac: dma-controller@ff240000 {
compatible = "arm,pl330", "arm,primecell"; compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xff240000 0x0 0x4000>; reg = <0x0 0xff240000 0x0 0x4000>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
@ -1072,7 +1094,7 @@
}; };
dsi: dsi@ff450000 { dsi: dsi@ff450000 {
compatible = "rockchip,px30-mipi-dsi"; compatible = "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x0 0xff450000 0x0 0x10000>; reg = <0x0 0xff450000 0x0 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_MIPI_DSI>; clocks = <&cru PCLK_MIPI_DSI>;