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crypto/fsl: add invalidate_dcache_range for hash output buffer
HW accelerated hash operations are giving incorrect hash output. so invalidate cache lines to avoid cache overwriting in DDR memory region. caam_hash() -moved address alignment check in the beginning of function. -added invalidate_dcache_range for pout buffer before running descriptor. Fixes: d7af2baa49 (crypto/fsl: Fix HW accelerated hash commands) Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
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2c16bf2d14
@ -168,18 +168,18 @@ int caam_hash(const unsigned char *pbuf, unsigned int buf_len,
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uint32_t *desc;
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unsigned int size;
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desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE);
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if (!desc) {
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debug("Not enough memory for descriptor allocation\n");
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return -ENOMEM;
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}
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if (!IS_ALIGNED((uintptr_t)pbuf, ARCH_DMA_MINALIGN) ||
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!IS_ALIGNED((uintptr_t)pout, ARCH_DMA_MINALIGN)) {
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puts("Error: Address arguments are not aligned\n");
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return -EINVAL;
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}
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desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE);
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if (!desc) {
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debug("Not enough memory for descriptor allocation\n");
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return -ENOMEM;
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}
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size = ALIGN(buf_len, ARCH_DMA_MINALIGN);
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flush_dcache_range((unsigned long)pbuf, (unsigned long)pbuf + size);
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@ -190,6 +190,8 @@ int caam_hash(const unsigned char *pbuf, unsigned int buf_len,
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size = ALIGN(sizeof(int) * MAX_CAAM_DESCSIZE, ARCH_DMA_MINALIGN);
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flush_dcache_range((unsigned long)desc, (unsigned long)desc + size);
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size = ALIGN(driver_hash[algo].digestsize, ARCH_DMA_MINALIGN);
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invalidate_dcache_range((unsigned long)pout, (unsigned long)pout + size);
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ret = run_descriptor_jr(desc);
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